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From: Tudor.Ambarus at microchip.com <Tudor.Ambarus@microchip.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH RFT 3/3] spi-nor: spi-nor-ids: Add entries for newer variants of n25q256* and n25q512*
Date: Tue, 24 Sep 2019 12:24:17 +0000	[thread overview]
Message-ID: <87f177e7-eecf-4c3c-9d9b-ac1a1418e9c0@microchip.com> (raw)
In-Reply-To: <CAAh8qsyVGAfX3Rrp4HcPEym9F+Z+_RAoa8iwBUEetrgbQKQdwQ@mail.gmail.com>

Hi, Simon,

On 09/24/2019 02:47 PM, Simon Goldschmidt wrote:
> External E-Mail
> 
> 
> On Tue, Sep 24, 2019 at 7:55 AM Vignesh Raghavendra <vigneshr@ti.com> wrote:
>>
>> Newer variants of n25q256* and n25q512* flashes support 4 Byte
>> addressing opcodes. Add entries for the same. These flashes Bit 6 set in
>> 5th byte of READ ID response.
>>
>> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
>> ---
>>  drivers/mtd/spi/spi-nor-ids.c | 3 +++
>>  1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
>> index 967537eafb55..0074073b123a 100644
>> --- a/drivers/mtd/spi/spi-nor-ids.c
>> +++ b/drivers/mtd/spi/spi-nor-ids.c
>> @@ -161,11 +161,14 @@ const struct flash_info spi_nor_ids[] = {
>>         { INFO("n25q064a",    0x20bb17, 0, 64 * 1024,  128, SECT_4K | SPI_NOR_QUAD_READ) },
>>         { INFO("n25q128a11",  0x20bb18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
>>         { INFO("n25q128a13",  0x20ba18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
>> +       { INFO6("n25q256a",    0x20ba19, 0x104400, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> 
> From the discussion in the other thread, this should probably be named
> "mt25-something"? Seems like the 0x44 in the 5th byte wouldn't be found in the
> n25q256a?
> 

Probably yes, but the ultimate test would be to dump all the JEDEC ID bytes from
the n25q256a flash, with code similar to that from below. It's not the first
time that we see manufacturers messing with the JEDEC IDs or with the SFDP
tables. It would be really helpful if you can dump the JEDEC ID bytes on a n25q256a.

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 1acff745d1a2..0be3496c5367 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -885,13 +885,16 @@ static const struct flash_info *spi_nor_read_id(struct
spi_nor *nor)
        info = spi_nor_ids;
        for (; info->name; info++) {
                if (info->id_len) {
-                       if (!memcmp(info->id, id, info->id_len))
+                       if (!memcmp(info->id, id, info->id_len)) {
+                               dev_err(nor->dev, "JEDEC id bytes: %*ph\n",
+                                       SPI_NOR_MAX_ID_LEN, id);
                                return info;
+                       }
                }
        }

-       dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
-               id[0], id[1], id[2]);
+        dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n",
+                SPI_NOR_MAX_ID_LEN, id);
        return ERR_PTR(-ENODEV);
 }

  parent reply	other threads:[~2019-09-24 12:24 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-24  5:56 [U-Boot] [PATCH RFT 0/3] spi-nor: spi-nor-ids: Fix 4 Byte addressing for n25q256 and n25q512* Vignesh Raghavendra
2019-09-24  5:56 ` [U-Boot] [PATCH RFT 1/3] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256* Vignesh Raghavendra
2019-09-24  5:56 ` [U-Boot] [PATCH RFT 2/3] spi-nor: spi-nor-ids: Rename mt25qu512a entry Vignesh Raghavendra
2019-09-24  5:56 ` [U-Boot] [PATCH RFT 3/3] spi-nor: spi-nor-ids: Add entries for newer variants of n25q256* and n25q512* Vignesh Raghavendra
2019-09-24 11:47   ` Simon Goldschmidt
2019-09-24 11:49     ` Simon Goldschmidt
2019-09-24 12:24     ` Tudor.Ambarus at microchip.com [this message]
2019-09-25  8:21       ` Vignesh Raghavendra
2019-09-25  8:27         ` Simon Goldschmidt
2019-09-25  9:09           ` Vignesh Raghavendra
2019-09-24  7:02 ` [U-Boot] [PATCH RFT 0/3] spi-nor: spi-nor-ids: Fix 4 Byte addressing for n25q256 " Simon Goldschmidt
2019-09-24  8:00   ` Vignesh Raghavendra
2019-09-24  8:43     ` Simon Goldschmidt
2019-09-24  9:17       ` Vignesh Raghavendra
2019-09-24  9:23         ` Simon Goldschmidt
2019-09-24  9:23   ` Tudor.Ambarus at microchip.com
2019-09-24  9:27     ` Simon Goldschmidt
2019-09-24 17:23 ` Eugeniy Paltsev
2019-09-25  8:11   ` Vignesh Raghavendra
2019-10-07 14:46     ` Eugeniy Paltsev
2019-10-09 11:48       ` Vignesh Raghavendra

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