* [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake @ 2019-10-02 11:26 ` Chris Wilson 0 siblings, 0 replies; 20+ messages in thread From: Chris Wilson @ 2019-10-02 11:26 UTC (permalink / raw) To: intel-gfx; +Cc: igt-dev There's very little variation in non-privileged registers for Tigerlake, so we can mostly inherit the set from gen11. There is no whitelist at present, so we do not need to add any special registers. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- tests/i915/gem_ctx_isolation.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c index df1d655ae..819daafc3 100644 --- a/tests/i915/gem_ctx_isolation.c +++ b/tests/i915/gem_ctx_isolation.c @@ -55,10 +55,11 @@ enum { #define GEN9 (ALL << 9) #define GEN10 (ALL << 10) #define GEN11 (ALL << 11) +#define GEN12 (ALL << 12) #define NOCTX 0 -#define LAST_KNOWN_GEN 11 +#define LAST_KNOWN_GEN 12 static const struct named_register { const char *name; @@ -116,9 +117,9 @@ static const struct named_register { { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true }, { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true }, { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true }, - { "L3_Config", GEN8, RCS0, 0x7034 }, - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff }, - { "TD_CTL2", GEN8, RCS0, 0xe404 }, + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 }, + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff }, + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 }, { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 }, { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 }, { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 }, @@ -852,7 +853,7 @@ igt_main gen = intel_gen(intel_get_drm_devid(fd)); igt_warn_on_f(gen > LAST_KNOWN_GEN, - "GEN not recognized! Test needs to be updated to run."); + "GEN not recognized! Test needs to be updated to run."); igt_skip_on(gen > LAST_KNOWN_GEN); } -- 2.23.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake @ 2019-10-02 11:26 ` Chris Wilson 0 siblings, 0 replies; 20+ messages in thread From: Chris Wilson @ 2019-10-02 11:26 UTC (permalink / raw) To: intel-gfx; +Cc: igt-dev There's very little variation in non-privileged registers for Tigerlake, so we can mostly inherit the set from gen11. There is no whitelist at present, so we do not need to add any special registers. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- tests/i915/gem_ctx_isolation.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c index df1d655ae..819daafc3 100644 --- a/tests/i915/gem_ctx_isolation.c +++ b/tests/i915/gem_ctx_isolation.c @@ -55,10 +55,11 @@ enum { #define GEN9 (ALL << 9) #define GEN10 (ALL << 10) #define GEN11 (ALL << 11) +#define GEN12 (ALL << 12) #define NOCTX 0 -#define LAST_KNOWN_GEN 11 +#define LAST_KNOWN_GEN 12 static const struct named_register { const char *name; @@ -116,9 +117,9 @@ static const struct named_register { { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true }, { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true }, { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true }, - { "L3_Config", GEN8, RCS0, 0x7034 }, - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff }, - { "TD_CTL2", GEN8, RCS0, 0xe404 }, + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 }, + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff }, + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 }, { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 }, { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 }, { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 }, @@ -852,7 +853,7 @@ igt_main gen = intel_gen(intel_get_drm_devid(fd)); igt_warn_on_f(gen > LAST_KNOWN_GEN, - "GEN not recognized! Test needs to be updated to run."); + "GEN not recognized! Test needs to be updated to run."); igt_skip_on(gen > LAST_KNOWN_GEN); } -- 2.23.0 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake 2019-10-02 11:26 ` [igt-dev] " Chris Wilson @ 2019-10-02 11:38 ` Petri Latvala -1 siblings, 0 replies; 20+ messages in thread From: Petri Latvala @ 2019-10-02 11:38 UTC (permalink / raw) To: Chris Wilson; +Cc: igt-dev, intel-gfx On Wed, Oct 02, 2019 at 12:26:48PM +0100, Chris Wilson wrote: > There's very little variation in non-privileged registers for Tigerlake, > so we can mostly inherit the set from gen11. There is no whitelist at > present, so we do not need to add any special registers. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599 > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > --- > tests/i915/gem_ctx_isolation.c | 11 ++++++----- > 1 file changed, 6 insertions(+), 5 deletions(-) > > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c > index df1d655ae..819daafc3 100644 > --- a/tests/i915/gem_ctx_isolation.c > +++ b/tests/i915/gem_ctx_isolation.c > @@ -55,10 +55,11 @@ enum { > #define GEN9 (ALL << 9) > #define GEN10 (ALL << 10) > #define GEN11 (ALL << 11) > +#define GEN12 (ALL << 12) > > #define NOCTX 0 > > -#define LAST_KNOWN_GEN 11 > +#define LAST_KNOWN_GEN 12 > > static const struct named_register { > const char *name; > @@ -116,9 +117,9 @@ static const struct named_register { > { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true }, > { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true }, > { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true }, > - { "L3_Config", GEN8, RCS0, 0x7034 }, > - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff }, > - { "TD_CTL2", GEN8, RCS0, 0xe404 }, > + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 }, > + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff }, > + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 }, > { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 }, > { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 }, > { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 }, > @@ -852,7 +853,7 @@ igt_main > gen = intel_gen(intel_get_drm_devid(fd)); > > igt_warn_on_f(gen > LAST_KNOWN_GEN, > - "GEN not recognized! Test needs to be updated to run."); > + "GEN not recognized! Test needs to be updated to run."); > igt_skip_on(gen > LAST_KNOWN_GEN); Thanks to this editorial change, we're able to see that this string is missing a newline character. -- Petri Latvala _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake @ 2019-10-02 11:38 ` Petri Latvala 0 siblings, 0 replies; 20+ messages in thread From: Petri Latvala @ 2019-10-02 11:38 UTC (permalink / raw) To: Chris Wilson; +Cc: igt-dev, intel-gfx On Wed, Oct 02, 2019 at 12:26:48PM +0100, Chris Wilson wrote: > There's very little variation in non-privileged registers for Tigerlake, > so we can mostly inherit the set from gen11. There is no whitelist at > present, so we do not need to add any special registers. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599 > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > --- > tests/i915/gem_ctx_isolation.c | 11 ++++++----- > 1 file changed, 6 insertions(+), 5 deletions(-) > > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c > index df1d655ae..819daafc3 100644 > --- a/tests/i915/gem_ctx_isolation.c > +++ b/tests/i915/gem_ctx_isolation.c > @@ -55,10 +55,11 @@ enum { > #define GEN9 (ALL << 9) > #define GEN10 (ALL << 10) > #define GEN11 (ALL << 11) > +#define GEN12 (ALL << 12) > > #define NOCTX 0 > > -#define LAST_KNOWN_GEN 11 > +#define LAST_KNOWN_GEN 12 > > static const struct named_register { > const char *name; > @@ -116,9 +117,9 @@ static const struct named_register { > { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true }, > { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true }, > { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true }, > - { "L3_Config", GEN8, RCS0, 0x7034 }, > - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff }, > - { "TD_CTL2", GEN8, RCS0, 0xe404 }, > + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 }, > + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff }, > + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 }, > { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 }, > { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 }, > { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 }, > @@ -852,7 +853,7 @@ igt_main > gen = intel_gen(intel_get_drm_devid(fd)); > > igt_warn_on_f(gen > LAST_KNOWN_GEN, > - "GEN not recognized! Test needs to be updated to run."); > + "GEN not recognized! Test needs to be updated to run."); > igt_skip_on(gen > LAST_KNOWN_GEN); Thanks to this editorial change, we're able to see that this string is missing a newline character. -- Petri Latvala _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake 2019-10-02 11:38 ` [Intel-gfx] " Petri Latvala @ 2019-10-03 23:26 ` Stimson, Dale B -1 siblings, 0 replies; 20+ messages in thread From: Stimson, Dale B @ 2019-10-03 23:26 UTC (permalink / raw) To: Chris Wilson, intel-gfx, igt-dev > On Wed, Oct 02, 2019 at 12:26:48PM +0100, Chris Wilson wrote: > > There's very little variation in non-privileged registers for Tigerlake, > > so we can mostly inherit the set from gen11. There is no whitelist at > > present, so we do not need to add any special registers. > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599 > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > --- > > tests/i915/gem_ctx_isolation.c | 11 ++++++----- > > 1 file changed, 6 insertions(+), 5 deletions(-) > > > > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c > > index df1d655ae..819daafc3 100644 > > --- a/tests/i915/gem_ctx_isolation.c > > +++ b/tests/i915/gem_ctx_isolation.c > > @@ -55,10 +55,11 @@ enum { > > #define GEN9 (ALL << 9) > > #define GEN10 (ALL << 10) > > #define GEN11 (ALL << 11) > > +#define GEN12 (ALL << 12) > > > > #define NOCTX 0 > > > > -#define LAST_KNOWN_GEN 11 > > +#define LAST_KNOWN_GEN 12 > > > > static const struct named_register { > > const char *name; > > @@ -116,9 +117,9 @@ static const struct named_register { > > { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true }, > > { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true }, > > { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true }, > > - { "L3_Config", GEN8, RCS0, 0x7034 }, > > - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff }, > > - { "TD_CTL2", GEN8, RCS0, 0xe404 }, > > + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 }, > > + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff }, > > + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 }, > > { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 }, > > { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 }, > > { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 }, > > @@ -852,7 +853,7 @@ igt_main > > gen = intel_gen(intel_get_drm_devid(fd)); > > > > igt_warn_on_f(gen > LAST_KNOWN_GEN, > > - "GEN not recognized! Test needs to be updated to run."); > > + "GEN not recognized! Test needs to be updated to run."); > > igt_skip_on(gen > LAST_KNOWN_GEN); On 2019-10-02 14:38:31, Petri Latvala wrote: > Thanks to this editorial change, we're able to see that this string is > missing a newline character. Your patch looks good (as does Petri's comment). I had identified the same registers as in the patch, but had one additional register. Should it be included? + { "COMMON_SLICE_CHICKEN2", GEN_RANGE(12, 12), RCS0, 0x7014, .masked = true }, I did some testing on a TGL with your patch. There are two pre-existing issues, both of which I have encountered before. These are that the S3/S4 test never wakes up, and errors reported by nonpriv for vcs'2 registers. See below. Because of the S3/S4 issues, running gem_ctx_isolation for Gen12 will require subsequent reboot. Should gem_ctx_isolation temporarily disable the S3/S4 tests for Gen12 until this problem is resolved? I have been doing some work to address the vcs issue, which I will send to the mailing list soon. The vcs issue is due to confusion between the physical engine really being vcs'2, and the kernel presenting the engine to usermode as vcs1. The test refers to the vcs'2 registers via the mmio_base expected for vcs1 and therefore fails. Planned solution: "MMIO Remapping" for ICL and later. Results for gem_ctx_isolation Never wakes from rcs0-S3 or rcs0-S4. (Probably also true for *-S3 and *-s4). Starting subtest: rcs0-S3 [cmd] rtcwake: assuming RTC uses UTC ... rtcwake: wakeup from "mem" using /dev/rtc0 at Thu Oct 3 17:45:41 2019 <Manually recovered via reboot> The following diagnostic is due to confusion between the physical engine really being vcs'2, and the kernel presenting the engine to usermode as vcs1. The test refers to the registers via the mmio_base expected for vcs1 and therefore fails. Starting subtest: vcs1-nonpriv (gem_ctx_isolation:2152) WARNING: Register 0x1c4600 (VCS1_GPR[0]): A=ffffffff B=00000000 (gem_ctx_isolation:2152) WARNING: Register 0x1c4604 (VCS1_GPR[1]): A=ffffffff B=00000000 ...and so on Tested with: ------------------------------------------------------------- Local kernel branch: Based on git://anongit.freedesktop.org/drm-tip Branch drm-tip fd44976bff7a drm-tip: 2019y-10m-03d-15h-13m-54s UTC integration manifest ------------------------------------------------------------- Local igt branch: Based on https://gitlab.freedesktop.org/drm/igt-gpu-tools.git branch master: 74f55119 (public/master) i915/gem_eio: Relax timeout for forced resets Plus your patch: i915/gem_ctx_isolation: Bump support for Tigerlake Plus a test patch to bypass S3 and S4 tests so other results could be seen: tests/i915/gem_ctx_isolation.c - Suppress suspend/resume tests -Dale _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake @ 2019-10-03 23:26 ` Stimson, Dale B 0 siblings, 0 replies; 20+ messages in thread From: Stimson, Dale B @ 2019-10-03 23:26 UTC (permalink / raw) To: Chris Wilson, intel-gfx, igt-dev > On Wed, Oct 02, 2019 at 12:26:48PM +0100, Chris Wilson wrote: > > There's very little variation in non-privileged registers for Tigerlake, > > so we can mostly inherit the set from gen11. There is no whitelist at > > present, so we do not need to add any special registers. > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599 > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > --- > > tests/i915/gem_ctx_isolation.c | 11 ++++++----- > > 1 file changed, 6 insertions(+), 5 deletions(-) > > > > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c > > index df1d655ae..819daafc3 100644 > > --- a/tests/i915/gem_ctx_isolation.c > > +++ b/tests/i915/gem_ctx_isolation.c > > @@ -55,10 +55,11 @@ enum { > > #define GEN9 (ALL << 9) > > #define GEN10 (ALL << 10) > > #define GEN11 (ALL << 11) > > +#define GEN12 (ALL << 12) > > > > #define NOCTX 0 > > > > -#define LAST_KNOWN_GEN 11 > > +#define LAST_KNOWN_GEN 12 > > > > static const struct named_register { > > const char *name; > > @@ -116,9 +117,9 @@ static const struct named_register { > > { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true }, > > { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true }, > > { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true }, > > - { "L3_Config", GEN8, RCS0, 0x7034 }, > > - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff }, > > - { "TD_CTL2", GEN8, RCS0, 0xe404 }, > > + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 }, > > + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff }, > > + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 }, > > { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 }, > > { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 }, > > { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 }, > > @@ -852,7 +853,7 @@ igt_main > > gen = intel_gen(intel_get_drm_devid(fd)); > > > > igt_warn_on_f(gen > LAST_KNOWN_GEN, > > - "GEN not recognized! Test needs to be updated to run."); > > + "GEN not recognized! Test needs to be updated to run."); > > igt_skip_on(gen > LAST_KNOWN_GEN); On 2019-10-02 14:38:31, Petri Latvala wrote: > Thanks to this editorial change, we're able to see that this string is > missing a newline character. Your patch looks good (as does Petri's comment). I had identified the same registers as in the patch, but had one additional register. Should it be included? + { "COMMON_SLICE_CHICKEN2", GEN_RANGE(12, 12), RCS0, 0x7014, .masked = true }, I did some testing on a TGL with your patch. There are two pre-existing issues, both of which I have encountered before. These are that the S3/S4 test never wakes up, and errors reported by nonpriv for vcs'2 registers. See below. Because of the S3/S4 issues, running gem_ctx_isolation for Gen12 will require subsequent reboot. Should gem_ctx_isolation temporarily disable the S3/S4 tests for Gen12 until this problem is resolved? I have been doing some work to address the vcs issue, which I will send to the mailing list soon. The vcs issue is due to confusion between the physical engine really being vcs'2, and the kernel presenting the engine to usermode as vcs1. The test refers to the vcs'2 registers via the mmio_base expected for vcs1 and therefore fails. Planned solution: "MMIO Remapping" for ICL and later. Results for gem_ctx_isolation Never wakes from rcs0-S3 or rcs0-S4. (Probably also true for *-S3 and *-s4). Starting subtest: rcs0-S3 [cmd] rtcwake: assuming RTC uses UTC ... rtcwake: wakeup from "mem" using /dev/rtc0 at Thu Oct 3 17:45:41 2019 <Manually recovered via reboot> The following diagnostic is due to confusion between the physical engine really being vcs'2, and the kernel presenting the engine to usermode as vcs1. The test refers to the registers via the mmio_base expected for vcs1 and therefore fails. Starting subtest: vcs1-nonpriv (gem_ctx_isolation:2152) WARNING: Register 0x1c4600 (VCS1_GPR[0]): A=ffffffff B=00000000 (gem_ctx_isolation:2152) WARNING: Register 0x1c4604 (VCS1_GPR[1]): A=ffffffff B=00000000 ...and so on Tested with: ------------------------------------------------------------- Local kernel branch: Based on git://anongit.freedesktop.org/drm-tip Branch drm-tip fd44976bff7a drm-tip: 2019y-10m-03d-15h-13m-54s UTC integration manifest ------------------------------------------------------------- Local igt branch: Based on https://gitlab.freedesktop.org/drm/igt-gpu-tools.git branch master: 74f55119 (public/master) i915/gem_eio: Relax timeout for forced resets Plus your patch: i915/gem_ctx_isolation: Bump support for Tigerlake Plus a test patch to bypass S3 and S4 tests so other results could be seen: tests/i915/gem_ctx_isolation.c - Suppress suspend/resume tests -Dale _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake 2019-10-03 23:26 ` [Intel-gfx] " Stimson, Dale B @ 2019-10-04 8:16 ` Chris Wilson -1 siblings, 0 replies; 20+ messages in thread From: Chris Wilson @ 2019-10-04 8:16 UTC (permalink / raw) To: Stimson, Dale B, igt-dev, intel-gfx Quoting Stimson, Dale B (2019-10-04 00:26:24) > > On Wed, Oct 02, 2019 at 12:26:48PM +0100, Chris Wilson wrote: > > > There's very little variation in non-privileged registers for Tigerlake, > > > so we can mostly inherit the set from gen11. There is no whitelist at > > > present, so we do not need to add any special registers. > > > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599 > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > > --- > > > tests/i915/gem_ctx_isolation.c | 11 ++++++----- > > > 1 file changed, 6 insertions(+), 5 deletions(-) > > > > > > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c > > > index df1d655ae..819daafc3 100644 > > > --- a/tests/i915/gem_ctx_isolation.c > > > +++ b/tests/i915/gem_ctx_isolation.c > > > @@ -55,10 +55,11 @@ enum { > > > #define GEN9 (ALL << 9) > > > #define GEN10 (ALL << 10) > > > #define GEN11 (ALL << 11) > > > +#define GEN12 (ALL << 12) > > > > > > #define NOCTX 0 > > > > > > -#define LAST_KNOWN_GEN 11 > > > +#define LAST_KNOWN_GEN 12 > > > > > > static const struct named_register { > > > const char *name; > > > @@ -116,9 +117,9 @@ static const struct named_register { > > > { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true }, > > > { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true }, > > > { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true }, > > > - { "L3_Config", GEN8, RCS0, 0x7034 }, > > > - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff }, > > > - { "TD_CTL2", GEN8, RCS0, 0xe404 }, > > > + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 }, > > > + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff }, > > > + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 }, > > > { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 }, > > > { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 }, > > > { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 }, > > > @@ -852,7 +853,7 @@ igt_main > > > gen = intel_gen(intel_get_drm_devid(fd)); > > > > > > igt_warn_on_f(gen > LAST_KNOWN_GEN, > > > - "GEN not recognized! Test needs to be updated to run."); > > > + "GEN not recognized! Test needs to be updated to run."); > > > igt_skip_on(gen > LAST_KNOWN_GEN); > > On 2019-10-02 14:38:31, Petri Latvala wrote: > > Thanks to this editorial change, we're able to see that this string is > > missing a newline character. > > Your patch looks good (as does Petri's comment). > > I had identified the same registers as in the patch, but had one additional > register. Should it be included? > > + { "COMMON_SLICE_CHICKEN2", GEN_RANGE(12, 12), RCS0, 0x7014, .masked = true }, > > I did some testing on a TGL with your patch. There are two pre-existing > issues, both of which I have encountered before. These are that the S3/S4 test > never wakes up, and errors reported by nonpriv for vcs'2 registers. See below. > > Because of the S3/S4 issues, running gem_ctx_isolation for Gen12 will require > subsequent reboot. Should gem_ctx_isolation temporarily disable the S3/S4 > tests for Gen12 until this problem is resolved? No. Fix the problem; it's to do with the interrupts being fubar. > I have been doing some work to address the vcs issue, which I will send > to the mailing list soon. The vcs issue is due to confusion between the > physical engine really being vcs'2, and the kernel presenting the engine to > usermode as vcs1. The test refers to the vcs'2 registers via the mmio_base > expected for vcs1 and therefore fails. Planned solution: "MMIO Remapping" > for ICL and later. Or see the patches to expose the mmio_base. If push comes to shove, it's already given in debugfs for precisely this purpose. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [igt-dev] [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake @ 2019-10-04 8:16 ` Chris Wilson 0 siblings, 0 replies; 20+ messages in thread From: Chris Wilson @ 2019-10-04 8:16 UTC (permalink / raw) To: Stimson, Dale B, igt-dev, intel-gfx; +Cc: Petri Latvala Quoting Stimson, Dale B (2019-10-04 00:26:24) > > On Wed, Oct 02, 2019 at 12:26:48PM +0100, Chris Wilson wrote: > > > There's very little variation in non-privileged registers for Tigerlake, > > > so we can mostly inherit the set from gen11. There is no whitelist at > > > present, so we do not need to add any special registers. > > > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599 > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > > --- > > > tests/i915/gem_ctx_isolation.c | 11 ++++++----- > > > 1 file changed, 6 insertions(+), 5 deletions(-) > > > > > > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c > > > index df1d655ae..819daafc3 100644 > > > --- a/tests/i915/gem_ctx_isolation.c > > > +++ b/tests/i915/gem_ctx_isolation.c > > > @@ -55,10 +55,11 @@ enum { > > > #define GEN9 (ALL << 9) > > > #define GEN10 (ALL << 10) > > > #define GEN11 (ALL << 11) > > > +#define GEN12 (ALL << 12) > > > > > > #define NOCTX 0 > > > > > > -#define LAST_KNOWN_GEN 11 > > > +#define LAST_KNOWN_GEN 12 > > > > > > static const struct named_register { > > > const char *name; > > > @@ -116,9 +117,9 @@ static const struct named_register { > > > { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true }, > > > { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true }, > > > { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true }, > > > - { "L3_Config", GEN8, RCS0, 0x7034 }, > > > - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff }, > > > - { "TD_CTL2", GEN8, RCS0, 0xe404 }, > > > + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 }, > > > + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff }, > > > + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 }, > > > { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 }, > > > { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 }, > > > { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 }, > > > @@ -852,7 +853,7 @@ igt_main > > > gen = intel_gen(intel_get_drm_devid(fd)); > > > > > > igt_warn_on_f(gen > LAST_KNOWN_GEN, > > > - "GEN not recognized! Test needs to be updated to run."); > > > + "GEN not recognized! Test needs to be updated to run."); > > > igt_skip_on(gen > LAST_KNOWN_GEN); > > On 2019-10-02 14:38:31, Petri Latvala wrote: > > Thanks to this editorial change, we're able to see that this string is > > missing a newline character. > > Your patch looks good (as does Petri's comment). > > I had identified the same registers as in the patch, but had one additional > register. Should it be included? > > + { "COMMON_SLICE_CHICKEN2", GEN_RANGE(12, 12), RCS0, 0x7014, .masked = true }, > > I did some testing on a TGL with your patch. There are two pre-existing > issues, both of which I have encountered before. These are that the S3/S4 test > never wakes up, and errors reported by nonpriv for vcs'2 registers. See below. > > Because of the S3/S4 issues, running gem_ctx_isolation for Gen12 will require > subsequent reboot. Should gem_ctx_isolation temporarily disable the S3/S4 > tests for Gen12 until this problem is resolved? No. Fix the problem; it's to do with the interrupts being fubar. > I have been doing some work to address the vcs issue, which I will send > to the mailing list soon. The vcs issue is due to confusion between the > physical engine really being vcs'2, and the kernel presenting the engine to > usermode as vcs1. The test refers to the vcs'2 registers via the mmio_base > expected for vcs1 and therefore fails. Planned solution: "MMIO Remapping" > for ICL and later. Or see the patches to expose the mmio_base. If push comes to shove, it's already given in debugfs for precisely this purpose. -Chris _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 20+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_ctx_isolation: Bump support for Tigerlake 2019-10-02 11:26 ` [igt-dev] " Chris Wilson (?) (?) @ 2019-10-02 12:58 ` Patchwork -1 siblings, 0 replies; 20+ messages in thread From: Patchwork @ 2019-10-02 12:58 UTC (permalink / raw) To: Chris Wilson; +Cc: igt-dev == Series Details == Series: i915/gem_ctx_isolation: Bump support for Tigerlake URL : https://patchwork.freedesktop.org/series/67484/ State : success == Summary == CI Bug Log - changes from CI_DRM_6988 -> IGTPW_3527 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/index.html Known issues ------------ Here are the changes found in IGTPW_3527 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@prime_vgem@basic-read: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/fi-icl-u3/igt@prime_vgem@basic-read.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/fi-icl-u3/igt@prime_vgem@basic-read.html #### Possible fixes #### * igt@gem_exec_parallel@basic: - {fi-tgl-u2}: [INCOMPLETE][3] -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/fi-tgl-u2/igt@gem_exec_parallel@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/fi-tgl-u2/igt@gem_exec_parallel@basic.html * igt@i915_module_load@reload-with-fault-injection: - {fi-icl-guc}: [DMESG-WARN][5] ([fdo#106107]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/fi-icl-guc/igt@i915_module_load@reload-with-fault-injection.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/fi-icl-guc/igt@i915_module_load@reload-with-fault-injection.html * igt@kms_chamelium@hdmi-edid-read: - {fi-icl-u4}: [FAIL][7] ([fdo#111045]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/fi-icl-u4/igt@kms_chamelium@hdmi-edid-read.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/fi-icl-u4/igt@kms_chamelium@hdmi-edid-read.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: [FAIL][9] ([fdo#109483]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html - fi-kbl-7500u: [FAIL][11] ([fdo#111045] / [fdo#111096]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html - {fi-icl-u4}: [FAIL][13] ([fdo#111045] / [fdo#111096]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/fi-icl-u4/igt@kms_chamelium@hdmi-hpd-fast.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/fi-icl-u4/igt@kms_chamelium@hdmi-hpd-fast.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - {fi-icl-dsi}: [DMESG-WARN][15] ([fdo#106107]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/fi-icl-dsi/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/fi-icl-dsi/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt@prime_self_import@basic-llseek-size: - fi-icl-u3: [DMESG-WARN][17] ([fdo#107724]) -> [PASS][18] +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/fi-icl-u3/igt@prime_self_import@basic-llseek-size.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/fi-icl-u3/igt@prime_self_import@basic-llseek-size.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483 [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600 Participating hosts (49 -> 46) ------------------------------ Additional (4): fi-bdw-gvtdvm fi-tgl-u fi-skl-6260u fi-skl-6600u Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5209 -> IGTPW_3527 CI-20190529: 20190529 CI_DRM_6988: a41f194b3d8797220fd614bfd13df8752507bb27 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_3527: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/index.html IGT_5209: ec639c89860b859fdf4b038c2fa8ad593bd6909e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 20+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for i915/gem_ctx_isolation: Bump support for Tigerlake 2019-10-02 11:26 ` [igt-dev] " Chris Wilson ` (2 preceding siblings ...) (?) @ 2019-10-02 18:48 ` Patchwork -1 siblings, 0 replies; 20+ messages in thread From: Patchwork @ 2019-10-02 18:48 UTC (permalink / raw) To: Chris Wilson; +Cc: igt-dev == Series Details == Series: i915/gem_ctx_isolation: Bump support for Tigerlake URL : https://patchwork.freedesktop.org/series/67484/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6988_full -> IGTPW_3527_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with IGTPW_3527_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_3527_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_3527_full: ### IGT changes ### #### Possible regressions #### * igt@gem_userptr_blits@process-exit-gtt-busy: - shard-iclb: NOTRUN -> [SKIP][1] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-iclb6/igt@gem_userptr_blits@process-exit-gtt-busy.html Known issues ------------ Here are the changes found in IGTPW_3527_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][2] -> [SKIP][3] ([fdo#110854]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-iclb1/igt@gem_exec_balancer@smoke.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-iclb6/igt@gem_exec_balancer@smoke.html * igt@gem_exec_schedule@in-order-bsd: - shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#111325]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-iclb5/igt@gem_exec_schedule@in-order-bsd.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-iclb4/igt@gem_exec_schedule@in-order-bsd.html * igt@gem_exec_schedule@independent-bsd2: - shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#109276]) +13 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-iclb1/igt@gem_exec_schedule@independent-bsd2.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-iclb7/igt@gem_exec_schedule@independent-bsd2.html * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup: - shard-apl: [PASS][8] -> [DMESG-WARN][9] ([fdo#109385] / [fdo#111870]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-apl1/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-apl8/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html - shard-kbl: [PASS][10] -> [DMESG-WARN][11] ([fdo#111870]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-kbl2/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-kbl6/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html - shard-snb: [PASS][12] -> [DMESG-WARN][13] ([fdo#111870]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: - shard-snb: [PASS][14] -> [DMESG-WARN][15] ([fdo#110789] / [fdo#111870]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html - shard-glk: [PASS][16] -> [DMESG-WARN][17] ([fdo#111870]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-glk6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-glk7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html * igt@i915_selftest@mock_fence: - shard-iclb: [PASS][18] -> [INCOMPLETE][19] ([fdo#107713]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-iclb4/igt@i915_selftest@mock_fence.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-iclb7/igt@i915_selftest@mock_fence.html * igt@kms_flip@dpms-vs-vblank-race-interruptible: - shard-glk: [PASS][20] -> [FAIL][21] ([fdo#111609]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-glk9/igt@kms_flip@dpms-vs-vblank-race-interruptible.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-glk7/igt@kms_flip@dpms-vs-vblank-race-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: [PASS][22] -> [FAIL][23] ([fdo#103167]) +2 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [PASS][24] -> [DMESG-WARN][25] ([fdo#108566]) +5 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-apl6/igt@kms_frontbuffer_tracking@fbc-suspend.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-apl2/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-rte: - shard-iclb: [PASS][26] -> [FAIL][27] ([fdo#103167] / [fdo#110378]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html * igt@kms_psr@psr2_basic: - shard-iclb: [PASS][28] -> [SKIP][29] ([fdo#109441]) +2 similar issues [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-iclb2/igt@kms_psr@psr2_basic.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-iclb1/igt@kms_psr@psr2_basic.html #### Possible fixes #### * igt@gem_bad_reloc@negative-reloc-default: - shard-hsw: [INCOMPLETE][30] ([fdo#103540]) -> [PASS][31] [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-hsw1/igt@gem_bad_reloc@negative-reloc-default.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-hsw5/igt@gem_bad_reloc@negative-reloc-default.html * igt@gem_eio@unwedge-stress: - shard-snb: [FAIL][32] ([fdo#109661]) -> [PASS][33] +1 similar issue [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-snb1/igt@gem_eio@unwedge-stress.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-snb5/igt@gem_eio@unwedge-stress.html * igt@gem_exec_basic@gtt-rcs0: - shard-snb: [DMESG-WARN][34] -> [PASS][35] [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-snb6/igt@gem_exec_basic@gtt-rcs0.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-snb1/igt@gem_exec_basic@gtt-rcs0.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [SKIP][36] ([fdo#111325]) -> [PASS][37] +5 similar issues [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-iclb6/igt@gem_exec_schedule@preempt-other-chain-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [SKIP][38] ([fdo#109276]) -> [PASS][39] +18 similar issues [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-iclb3/igt@gem_exec_schedule@preempt-queue-bsd1.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd1.html * igt@gem_userptr_blits@coherency-sync: - shard-hsw: [DMESG-WARN][40] ([fdo#111870]) -> [PASS][41] +4 similar issues [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-hsw6/igt@gem_userptr_blits@coherency-sync.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-hsw2/igt@gem_userptr_blits@coherency-sync.html - shard-snb: [DMESG-WARN][42] ([fdo#110789] / [fdo#111870]) -> [PASS][43] [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-snb2/igt@gem_userptr_blits@coherency-sync.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-snb5/igt@gem_userptr_blits@coherency-sync.html * igt@gem_userptr_blits@dmabuf-unsync: - shard-snb: [DMESG-WARN][44] ([fdo#111870]) -> [PASS][45] [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-snb5/igt@gem_userptr_blits@dmabuf-unsync.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-snb2/igt@gem_userptr_blits@dmabuf-unsync.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: - shard-iclb: [DMESG-WARN][46] ([fdo#111870]) -> [PASS][47] +1 similar issue [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-iclb2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-iclb2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup: - shard-glk: [DMESG-WARN][48] ([fdo#111870]) -> [PASS][49] +1 similar issue [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-glk6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-glk8/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html * igt@gem_userptr_blits@sync-unmap: - shard-kbl: [DMESG-WARN][50] ([fdo#111870]) -> [PASS][51] +1 similar issue [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-kbl2/igt@gem_userptr_blits@sync-unmap.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-kbl3/igt@gem_userptr_blits@sync-unmap.html * {igt@i915_pm_dc@dc5-dpms}: - shard-iclb: [FAIL][52] ([fdo#111795 ]) -> [PASS][53] [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-iclb5/igt@i915_pm_dc@dc5-dpms.html * igt@kms_busy@extended-modeset-hang-newfb-render-c: - shard-iclb: [INCOMPLETE][54] ([fdo#107713]) -> [PASS][55] [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-iclb7/igt@kms_busy@extended-modeset-hang-newfb-render-c.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-iclb4/igt@kms_busy@extended-modeset-hang-newfb-render-c.html * igt@kms_cursor_crc@pipe-a-cursor-dpms: - shard-kbl: [FAIL][56] ([fdo#103232]) -> [PASS][57] [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-dpms.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-dpms.html - shard-apl: [FAIL][58] ([fdo#103232]) -> [PASS][59] [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-dpms.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-dpms.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-apl: [DMESG-WARN][60] ([fdo#108566]) -> [PASS][61] +3 similar issues [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html * igt@kms_cursor_legacy@all-pipes-single-bo: - shard-apl: [INCOMPLETE][62] ([fdo#103927]) -> [PASS][63] +1 similar issue [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-apl3/igt@kms_cursor_legacy@all-pipes-single-bo.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-apl8/igt@kms_cursor_legacy@all-pipes-single-bo.html * igt@kms_flip@2x-flip-vs-panning: - shard-hsw: [DMESG-WARN][64] -> [PASS][65] [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-hsw8/igt@kms_flip@2x-flip-vs-panning.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-hsw6/igt@kms_flip@2x-flip-vs-panning.html * igt@kms_flip@modeset-vs-vblank-race: - shard-apl: [FAIL][66] ([fdo#111609]) -> [PASS][67] [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-apl7/igt@kms_flip@modeset-vs-vblank-race.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-apl7/igt@kms_flip@modeset-vs-vblank-race.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite: - shard-iclb: [FAIL][68] ([fdo#103167]) -> [PASS][69] +5 similar issues [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html * igt@kms_psr2_su@page_flip: - shard-iclb: [SKIP][70] ([fdo#109642] / [fdo#111068]) -> [PASS][71] [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-iclb4/igt@kms_psr2_su@page_flip.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-iclb2/igt@kms_psr2_su@page_flip.html * igt@kms_psr@no_drrs: - shard-iclb: [FAIL][72] ([fdo#108341]) -> [PASS][73] [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-iclb1/igt@kms_psr@no_drrs.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-iclb6/igt@kms_psr@no_drrs.html * igt@kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [SKIP][74] ([fdo#109441]) -> [PASS][75] +1 similar issue [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html * igt@kms_setmode@basic: - shard-apl: [FAIL][76] ([fdo#99912]) -> [PASS][77] [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-apl1/igt@kms_setmode@basic.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-apl3/igt@kms_setmode@basic.html #### Warnings #### * igt@gem_ctx_isolation@vcs1-nonpriv: - shard-iclb: [FAIL][78] ([fdo#111329]) -> [SKIP][79] ([fdo#109276]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-iclb8/igt@gem_ctx_isolation@vcs1-nonpriv.html * igt@gem_mocs_settings@mocs-isolation-bsd2: - shard-iclb: [FAIL][80] ([fdo#111330]) -> [SKIP][81] ([fdo#109276]) +1 similar issue [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6988/shard-iclb2/igt@gem_mocs_settings@mocs-isolation-bsd2.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/shard-iclb6/igt@gem_mocs_settings@mocs-isolation-bsd2.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232 [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109385]: https://bugs.freedesktop.org/show_bug.cgi?id=109385 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661 [fdo#110378]: https://bugs.freedesktop.org/show_bug.cgi?id=110378 [fdo#110548]: https://bugs.freedesktop.org/show_bug.cgi?id=110548 [fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789 [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325 [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329 [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330 [fdo#111609]: https://bugs.freedesktop.org/show_bug.cgi?id=111609 [fdo#111795 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111795 [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870 [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912 Participating hosts (11 -> 6) ------------------------------ Missing (5): shard-skl pig-hsw-4770r pig-glk-j5005 shard-tglb pig-skl-6260u Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5209 -> IGTPW_3527 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_6988: a41f194b3d8797220fd614bfd13df8752507bb27 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_3527: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/index.html IGT_5209: ec639c89860b859fdf4b038c2fa8ad593bd6909e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3527/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake 2019-10-02 11:26 ` [igt-dev] " Chris Wilson @ 2019-10-04 13:51 ` Mika Kuoppala -1 siblings, 0 replies; 20+ messages in thread From: Mika Kuoppala @ 2019-10-04 13:51 UTC (permalink / raw) To: Chris Wilson, intel-gfx; +Cc: igt-dev Chris Wilson <chris@chris-wilson.co.uk> writes: > There's very little variation in non-privileged registers for Tigerlake, > so we can mostly inherit the set from gen11. There is no whitelist at > present, so we do not need to add any special registers. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599 > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > --- > tests/i915/gem_ctx_isolation.c | 11 ++++++----- > 1 file changed, 6 insertions(+), 5 deletions(-) > > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c > index df1d655ae..819daafc3 100644 > --- a/tests/i915/gem_ctx_isolation.c > +++ b/tests/i915/gem_ctx_isolation.c > @@ -55,10 +55,11 @@ enum { > #define GEN9 (ALL << 9) > #define GEN10 (ALL << 10) > #define GEN11 (ALL << 11) > +#define GEN12 (ALL << 12) > > #define NOCTX 0 > > -#define LAST_KNOWN_GEN 11 > +#define LAST_KNOWN_GEN 12 > > static const struct named_register { > const char *name; > @@ -116,9 +117,9 @@ static const struct named_register { > { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true }, > { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true }, > { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true }, > - { "L3_Config", GEN8, RCS0, 0x7034 }, > - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff }, > - { "TD_CTL2", GEN8, RCS0, 0xe404 }, > + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 }, > + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff }, > + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 }, The ignore list needs an update too? -Mika > { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 }, > { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 }, > { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 }, > @@ -852,7 +853,7 @@ igt_main > gen = intel_gen(intel_get_drm_devid(fd)); > > igt_warn_on_f(gen > LAST_KNOWN_GEN, > - "GEN not recognized! Test needs to be updated to run."); > + "GEN not recognized! Test needs to be updated to run."); > igt_skip_on(gen > LAST_KNOWN_GEN); > } > > -- > 2.23.0 > > _______________________________________________ > igt-dev mailing list > igt-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/igt-dev _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake @ 2019-10-04 13:51 ` Mika Kuoppala 0 siblings, 0 replies; 20+ messages in thread From: Mika Kuoppala @ 2019-10-04 13:51 UTC (permalink / raw) To: Chris Wilson, intel-gfx; +Cc: igt-dev Chris Wilson <chris@chris-wilson.co.uk> writes: > There's very little variation in non-privileged registers for Tigerlake, > so we can mostly inherit the set from gen11. There is no whitelist at > present, so we do not need to add any special registers. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599 > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > --- > tests/i915/gem_ctx_isolation.c | 11 ++++++----- > 1 file changed, 6 insertions(+), 5 deletions(-) > > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c > index df1d655ae..819daafc3 100644 > --- a/tests/i915/gem_ctx_isolation.c > +++ b/tests/i915/gem_ctx_isolation.c > @@ -55,10 +55,11 @@ enum { > #define GEN9 (ALL << 9) > #define GEN10 (ALL << 10) > #define GEN11 (ALL << 11) > +#define GEN12 (ALL << 12) > > #define NOCTX 0 > > -#define LAST_KNOWN_GEN 11 > +#define LAST_KNOWN_GEN 12 > > static const struct named_register { > const char *name; > @@ -116,9 +117,9 @@ static const struct named_register { > { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true }, > { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true }, > { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true }, > - { "L3_Config", GEN8, RCS0, 0x7034 }, > - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff }, > - { "TD_CTL2", GEN8, RCS0, 0xe404 }, > + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 }, > + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff }, > + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 }, The ignore list needs an update too? -Mika > { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 }, > { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 }, > { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 }, > @@ -852,7 +853,7 @@ igt_main > gen = intel_gen(intel_get_drm_devid(fd)); > > igt_warn_on_f(gen > LAST_KNOWN_GEN, > - "GEN not recognized! Test needs to be updated to run."); > + "GEN not recognized! Test needs to be updated to run."); > igt_skip_on(gen > LAST_KNOWN_GEN); > } > > -- > 2.23.0 > > _______________________________________________ > igt-dev mailing list > igt-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/igt-dev _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake 2019-10-04 13:51 ` Mika Kuoppala @ 2019-10-04 13:57 ` Chris Wilson -1 siblings, 0 replies; 20+ messages in thread From: Chris Wilson @ 2019-10-04 13:57 UTC (permalink / raw) To: Mika Kuoppala, intel-gfx; +Cc: igt-dev Quoting Mika Kuoppala (2019-10-04 14:51:05) > Chris Wilson <chris@chris-wilson.co.uk> writes: > > > There's very little variation in non-privileged registers for Tigerlake, > > so we can mostly inherit the set from gen11. There is no whitelist at > > present, so we do not need to add any special registers. > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599 > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > --- > > tests/i915/gem_ctx_isolation.c | 11 ++++++----- > > 1 file changed, 6 insertions(+), 5 deletions(-) > > > > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c > > index df1d655ae..819daafc3 100644 > > --- a/tests/i915/gem_ctx_isolation.c > > +++ b/tests/i915/gem_ctx_isolation.c > > @@ -55,10 +55,11 @@ enum { > > #define GEN9 (ALL << 9) > > #define GEN10 (ALL << 10) > > #define GEN11 (ALL << 11) > > +#define GEN12 (ALL << 12) > > > > #define NOCTX 0 > > > > -#define LAST_KNOWN_GEN 11 > > +#define LAST_KNOWN_GEN 12 > > > > static const struct named_register { > > const char *name; > > @@ -116,9 +117,9 @@ static const struct named_register { > > { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true }, > > { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true }, > > { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true }, > > - { "L3_Config", GEN8, RCS0, 0x7034 }, > > - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff }, > > - { "TD_CTL2", GEN8, RCS0, 0xe404 }, > > + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 }, > > + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff }, > > + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 }, > > The ignore list needs an update too? The timestamps? The extra VCS are marked as GEN11+ and we weren't caught out by noticing the counter change -- so I presume it was ok. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake @ 2019-10-04 13:57 ` Chris Wilson 0 siblings, 0 replies; 20+ messages in thread From: Chris Wilson @ 2019-10-04 13:57 UTC (permalink / raw) To: Mika Kuoppala, intel-gfx; +Cc: igt-dev Quoting Mika Kuoppala (2019-10-04 14:51:05) > Chris Wilson <chris@chris-wilson.co.uk> writes: > > > There's very little variation in non-privileged registers for Tigerlake, > > so we can mostly inherit the set from gen11. There is no whitelist at > > present, so we do not need to add any special registers. > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599 > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > --- > > tests/i915/gem_ctx_isolation.c | 11 ++++++----- > > 1 file changed, 6 insertions(+), 5 deletions(-) > > > > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c > > index df1d655ae..819daafc3 100644 > > --- a/tests/i915/gem_ctx_isolation.c > > +++ b/tests/i915/gem_ctx_isolation.c > > @@ -55,10 +55,11 @@ enum { > > #define GEN9 (ALL << 9) > > #define GEN10 (ALL << 10) > > #define GEN11 (ALL << 11) > > +#define GEN12 (ALL << 12) > > > > #define NOCTX 0 > > > > -#define LAST_KNOWN_GEN 11 > > +#define LAST_KNOWN_GEN 12 > > > > static const struct named_register { > > const char *name; > > @@ -116,9 +117,9 @@ static const struct named_register { > > { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true }, > > { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true }, > > { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true }, > > - { "L3_Config", GEN8, RCS0, 0x7034 }, > > - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff }, > > - { "TD_CTL2", GEN8, RCS0, 0xe404 }, > > + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 }, > > + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff }, > > + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 }, > > The ignore list needs an update too? The timestamps? The extra VCS are marked as GEN11+ and we weren't caught out by noticing the counter change -- so I presume it was ok. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake 2019-10-02 11:26 ` [igt-dev] " Chris Wilson @ 2019-10-04 15:17 ` Chris Wilson -1 siblings, 0 replies; 20+ messages in thread From: Chris Wilson @ 2019-10-04 15:17 UTC (permalink / raw) To: intel-gfx; +Cc: igt-dev There's very little variation in non-privileged registers for Tigerlake, so we can mostly inherit the set from gen11. There is no whitelist at present, so we do not need to add any special registers. v2: Add COMMON_SLICE_CHICKEN2, GEN9_SLICE_COMMON_ECO_CHICKEN1 and a variety of huc readonly status registers. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> --- tests/i915/gem_ctx_isolation.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c index df1d655ae..58b824e84 100644 --- a/tests/i915/gem_ctx_isolation.c +++ b/tests/i915/gem_ctx_isolation.c @@ -55,10 +55,11 @@ enum { #define GEN9 (ALL << 9) #define GEN10 (ALL << 10) #define GEN11 (ALL << 11) +#define GEN12 (ALL << 12) #define NOCTX 0 -#define LAST_KNOWN_GEN 11 +#define LAST_KNOWN_GEN 12 static const struct named_register { const char *name; @@ -116,9 +117,9 @@ static const struct named_register { { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true }, { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true }, { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true }, - { "L3_Config", GEN8, RCS0, 0x7034 }, - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff }, - { "TD_CTL2", GEN8, RCS0, 0xe404 }, + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 }, + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff }, + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 }, { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 }, { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 }, { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 }, @@ -142,7 +143,9 @@ static const struct named_register { /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */ { "CTX_PREEMPT", NOCTX /* GEN9 */, RCS0, 0x2248 }, { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true }, + { "COMMON_SLICE_CHICKEN2", GEN9, RCS0, 0x7014, .masked = true }, { "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .masked = true }, + { "SLICE_COMMON_ECO_CHICKEN1", GEN_RANGE(9, 11), 0x731c, .masked = true }, { "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask = ~0x1ffff0 }, { "HALF_SLICE_CHICKEN7", GEN_RANGE(11, 11), RCS0, 0xe194, .masked = true }, { "SAMPLER_MODE", GEN_RANGE(11, 11), RCS0, 0xe18c, .masked = true }, @@ -178,6 +181,23 @@ static const struct named_register { { "VCS3 timestamp", GEN11, ~0u, 0x1d4358 }, { "VECS timestamp", GEN11, ~0u, 0x1c8358 }, + /* huc read only */ + { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x2000 }, + { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x2014 }, + { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x23b0 }, + + { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2000 }, + { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2014 }, + { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x23b0 }, + + { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x2000 }, + { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x2014 }, + { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x23b0 }, + + { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2000 }, + { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2014 }, + { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x23b0 }, + {} }; @@ -852,7 +872,7 @@ igt_main gen = intel_gen(intel_get_drm_devid(fd)); igt_warn_on_f(gen > LAST_KNOWN_GEN, - "GEN not recognized! Test needs to be updated to run."); + "GEN not recognized! Test needs to be updated to run.\n"); igt_skip_on(gen > LAST_KNOWN_GEN); } -- 2.23.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake @ 2019-10-04 15:17 ` Chris Wilson 0 siblings, 0 replies; 20+ messages in thread From: Chris Wilson @ 2019-10-04 15:17 UTC (permalink / raw) To: intel-gfx; +Cc: igt-dev There's very little variation in non-privileged registers for Tigerlake, so we can mostly inherit the set from gen11. There is no whitelist at present, so we do not need to add any special registers. v2: Add COMMON_SLICE_CHICKEN2, GEN9_SLICE_COMMON_ECO_CHICKEN1 and a variety of huc readonly status registers. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> --- tests/i915/gem_ctx_isolation.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c index df1d655ae..58b824e84 100644 --- a/tests/i915/gem_ctx_isolation.c +++ b/tests/i915/gem_ctx_isolation.c @@ -55,10 +55,11 @@ enum { #define GEN9 (ALL << 9) #define GEN10 (ALL << 10) #define GEN11 (ALL << 11) +#define GEN12 (ALL << 12) #define NOCTX 0 -#define LAST_KNOWN_GEN 11 +#define LAST_KNOWN_GEN 12 static const struct named_register { const char *name; @@ -116,9 +117,9 @@ static const struct named_register { { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true }, { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true }, { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true }, - { "L3_Config", GEN8, RCS0, 0x7034 }, - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff }, - { "TD_CTL2", GEN8, RCS0, 0xe404 }, + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 }, + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff }, + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 }, { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 }, { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 }, { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 }, @@ -142,7 +143,9 @@ static const struct named_register { /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */ { "CTX_PREEMPT", NOCTX /* GEN9 */, RCS0, 0x2248 }, { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true }, + { "COMMON_SLICE_CHICKEN2", GEN9, RCS0, 0x7014, .masked = true }, { "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .masked = true }, + { "SLICE_COMMON_ECO_CHICKEN1", GEN_RANGE(9, 11), 0x731c, .masked = true }, { "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask = ~0x1ffff0 }, { "HALF_SLICE_CHICKEN7", GEN_RANGE(11, 11), RCS0, 0xe194, .masked = true }, { "SAMPLER_MODE", GEN_RANGE(11, 11), RCS0, 0xe18c, .masked = true }, @@ -178,6 +181,23 @@ static const struct named_register { { "VCS3 timestamp", GEN11, ~0u, 0x1d4358 }, { "VECS timestamp", GEN11, ~0u, 0x1c8358 }, + /* huc read only */ + { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x2000 }, + { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x2014 }, + { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x23b0 }, + + { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2000 }, + { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2014 }, + { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x23b0 }, + + { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x2000 }, + { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x2014 }, + { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x23b0 }, + + { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2000 }, + { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2014 }, + { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x23b0 }, + {} }; @@ -852,7 +872,7 @@ igt_main gen = intel_gen(intel_get_drm_devid(fd)); igt_warn_on_f(gen > LAST_KNOWN_GEN, - "GEN not recognized! Test needs to be updated to run."); + "GEN not recognized! Test needs to be updated to run.\n"); igt_skip_on(gen > LAST_KNOWN_GEN); } -- 2.23.0 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake 2019-10-04 15:17 ` [igt-dev] " Chris Wilson @ 2019-10-04 15:19 ` Mika Kuoppala -1 siblings, 0 replies; 20+ messages in thread From: Mika Kuoppala @ 2019-10-04 15:19 UTC (permalink / raw) To: Chris Wilson, intel-gfx; +Cc: igt-dev Chris Wilson <chris@chris-wilson.co.uk> writes: > There's very little variation in non-privileged registers for Tigerlake, > so we can mostly inherit the set from gen11. There is no whitelist at > present, so we do not need to add any special registers. > > v2: Add COMMON_SLICE_CHICKEN2, GEN9_SLICE_COMMON_ECO_CHICKEN1 and a > variety of huc readonly status registers. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599 > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > tests/i915/gem_ctx_isolation.c | 30 +++++++++++++++++++++++++----- > 1 file changed, 25 insertions(+), 5 deletions(-) > > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c > index df1d655ae..58b824e84 100644 > --- a/tests/i915/gem_ctx_isolation.c > +++ b/tests/i915/gem_ctx_isolation.c > @@ -55,10 +55,11 @@ enum { > #define GEN9 (ALL << 9) > #define GEN10 (ALL << 10) > #define GEN11 (ALL << 11) > +#define GEN12 (ALL << 12) > > #define NOCTX 0 > > -#define LAST_KNOWN_GEN 11 > +#define LAST_KNOWN_GEN 12 > > static const struct named_register { > const char *name; > @@ -116,9 +117,9 @@ static const struct named_register { > { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true }, > { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true }, > { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true }, > - { "L3_Config", GEN8, RCS0, 0x7034 }, > - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff }, > - { "TD_CTL2", GEN8, RCS0, 0xe404 }, > + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 }, > + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff }, > + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 }, > { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 }, > { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 }, > { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 }, > @@ -142,7 +143,9 @@ static const struct named_register { > /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */ > { "CTX_PREEMPT", NOCTX /* GEN9 */, RCS0, 0x2248 }, > { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true }, > + { "COMMON_SLICE_CHICKEN2", GEN9, RCS0, 0x7014, .masked = true }, > { "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .masked = true }, > + { "SLICE_COMMON_ECO_CHICKEN1", GEN_RANGE(9, 11), 0x731c, .masked = true }, > { "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask = ~0x1ffff0 }, > { "HALF_SLICE_CHICKEN7", GEN_RANGE(11, 11), RCS0, 0xe194, .masked = true }, > { "SAMPLER_MODE", GEN_RANGE(11, 11), RCS0, 0xe18c, .masked = true }, > @@ -178,6 +181,23 @@ static const struct named_register { > { "VCS3 timestamp", GEN11, ~0u, 0x1d4358 }, > { "VECS timestamp", GEN11, ~0u, 0x1c8358 }, > > + /* huc read only */ > + { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x2000 }, > + { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x2014 }, > + { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x23b0 }, > + > + { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2000 }, > + { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2014 }, > + { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x23b0 }, > + > + { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x2000 }, > + { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x2014 }, > + { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x23b0 }, > + > + { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2000 }, > + { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2014 }, > + { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x23b0 }, > + > {} > }; > > @@ -852,7 +872,7 @@ igt_main > gen = intel_gen(intel_get_drm_devid(fd)); > > igt_warn_on_f(gen > LAST_KNOWN_GEN, > - "GEN not recognized! Test needs to be updated to run."); > + "GEN not recognized! Test needs to be updated to run.\n"); > igt_skip_on(gen > LAST_KNOWN_GEN); > } > > -- > 2.23.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake @ 2019-10-04 15:19 ` Mika Kuoppala 0 siblings, 0 replies; 20+ messages in thread From: Mika Kuoppala @ 2019-10-04 15:19 UTC (permalink / raw) To: Chris Wilson, intel-gfx; +Cc: igt-dev Chris Wilson <chris@chris-wilson.co.uk> writes: > There's very little variation in non-privileged registers for Tigerlake, > so we can mostly inherit the set from gen11. There is no whitelist at > present, so we do not need to add any special registers. > > v2: Add COMMON_SLICE_CHICKEN2, GEN9_SLICE_COMMON_ECO_CHICKEN1 and a > variety of huc readonly status registers. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599 > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > tests/i915/gem_ctx_isolation.c | 30 +++++++++++++++++++++++++----- > 1 file changed, 25 insertions(+), 5 deletions(-) > > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c > index df1d655ae..58b824e84 100644 > --- a/tests/i915/gem_ctx_isolation.c > +++ b/tests/i915/gem_ctx_isolation.c > @@ -55,10 +55,11 @@ enum { > #define GEN9 (ALL << 9) > #define GEN10 (ALL << 10) > #define GEN11 (ALL << 11) > +#define GEN12 (ALL << 12) > > #define NOCTX 0 > > -#define LAST_KNOWN_GEN 11 > +#define LAST_KNOWN_GEN 12 > > static const struct named_register { > const char *name; > @@ -116,9 +117,9 @@ static const struct named_register { > { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true }, > { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true }, > { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true }, > - { "L3_Config", GEN8, RCS0, 0x7034 }, > - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff }, > - { "TD_CTL2", GEN8, RCS0, 0xe404 }, > + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 }, > + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff }, > + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 }, > { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 }, > { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 }, > { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 }, > @@ -142,7 +143,9 @@ static const struct named_register { > /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */ > { "CTX_PREEMPT", NOCTX /* GEN9 */, RCS0, 0x2248 }, > { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true }, > + { "COMMON_SLICE_CHICKEN2", GEN9, RCS0, 0x7014, .masked = true }, > { "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .masked = true }, > + { "SLICE_COMMON_ECO_CHICKEN1", GEN_RANGE(9, 11), 0x731c, .masked = true }, > { "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask = ~0x1ffff0 }, > { "HALF_SLICE_CHICKEN7", GEN_RANGE(11, 11), RCS0, 0xe194, .masked = true }, > { "SAMPLER_MODE", GEN_RANGE(11, 11), RCS0, 0xe18c, .masked = true }, > @@ -178,6 +181,23 @@ static const struct named_register { > { "VCS3 timestamp", GEN11, ~0u, 0x1d4358 }, > { "VECS timestamp", GEN11, ~0u, 0x1c8358 }, > > + /* huc read only */ > + { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x2000 }, > + { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x2014 }, > + { "BSD0 0x2000", GEN11, ~0u, 0x1c0000 + 0x23b0 }, > + > + { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2000 }, > + { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2014 }, > + { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x23b0 }, > + > + { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x2000 }, > + { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x2014 }, > + { "BSD2 0x2000", GEN11, ~0u, 0x1d0000 + 0x23b0 }, > + > + { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2000 }, > + { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2014 }, > + { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x23b0 }, > + > {} > }; > > @@ -852,7 +872,7 @@ igt_main > gen = intel_gen(intel_get_drm_devid(fd)); > > igt_warn_on_f(gen > LAST_KNOWN_GEN, > - "GEN not recognized! Test needs to be updated to run."); > + "GEN not recognized! Test needs to be updated to run.\n"); > igt_skip_on(gen > LAST_KNOWN_GEN); > } > > -- > 2.23.0 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 20+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_ctx_isolation: Bump support for Tigerlake (rev2) 2019-10-02 11:26 ` [igt-dev] " Chris Wilson ` (5 preceding siblings ...) (?) @ 2019-10-04 16:14 ` Patchwork -1 siblings, 0 replies; 20+ messages in thread From: Patchwork @ 2019-10-04 16:14 UTC (permalink / raw) To: Chris Wilson; +Cc: igt-dev == Series Details == Series: i915/gem_ctx_isolation: Bump support for Tigerlake (rev2) URL : https://patchwork.freedesktop.org/series/67484/ State : success == Summary == CI Bug Log - changes from CI_DRM_7010 -> IGTPW_3537 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/index.html Known issues ------------ Here are the changes found in IGTPW_3537 that come from known issues: ### IGT changes ### #### Possible fixes #### * igt@core_auth@basic-auth: - fi-icl-u3: [DMESG-WARN][1] ([fdo#107724]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/fi-icl-u3/igt@core_auth@basic-auth.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/fi-icl-u3/igt@core_auth@basic-auth.html * igt@gem_ctx_create@basic-files: - fi-icl-u3: [INCOMPLETE][3] ([fdo#107713] / [fdo#109100]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/fi-icl-u3/igt@gem_ctx_create@basic-files.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/fi-icl-u3/igt@gem_ctx_create@basic-files.html * igt@gem_exec_suspend@basic: - fi-icl-u2: [FAIL][5] ([fdo#111699]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/fi-icl-u2/igt@gem_exec_suspend@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/fi-icl-u2/igt@gem_exec_suspend@basic.html * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [INCOMPLETE][7] ([fdo#107718]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html #### Warnings #### * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][9] ([fdo#111045] / [fdo#111096]) -> [FAIL][10] ([fdo#111407]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [fdo#111699]: https://bugs.freedesktop.org/show_bug.cgi?id=111699 Participating hosts (51 -> 44) ------------------------------ Additional (1): fi-icl-guc Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus fi-kbl-r Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5211 -> IGTPW_3537 CI-20190529: 20190529 CI_DRM_7010: 0d2c0d7bfb5246b27ab8d9601ac1251501afe827 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_3537: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/index.html IGT_5211: 1601e1571eb0f29a06b64494040b3ea7859a650f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 20+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for i915/gem_ctx_isolation: Bump support for Tigerlake (rev2) 2019-10-02 11:26 ` [igt-dev] " Chris Wilson ` (6 preceding siblings ...) (?) @ 2019-10-05 1:40 ` Patchwork -1 siblings, 0 replies; 20+ messages in thread From: Patchwork @ 2019-10-05 1:40 UTC (permalink / raw) To: Chris Wilson; +Cc: igt-dev == Series Details == Series: i915/gem_ctx_isolation: Bump support for Tigerlake (rev2) URL : https://patchwork.freedesktop.org/series/67484/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7010_full -> IGTPW_3537_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with IGTPW_3537_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_3537_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_3537_full: ### IGT changes ### #### Possible regressions #### * igt@gem_ctx_isolation@vcs0-nonpriv: - shard-apl: [PASS][1] -> [FAIL][2] +5 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-apl8/igt@gem_ctx_isolation@vcs0-nonpriv.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-apl8/igt@gem_ctx_isolation@vcs0-nonpriv.html - shard-glk: [PASS][3] -> [FAIL][4] +6 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-glk4/igt@gem_ctx_isolation@vcs0-nonpriv.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-glk8/igt@gem_ctx_isolation@vcs0-nonpriv.html * igt@gem_ctx_isolation@vcs0-reset: - shard-apl: NOTRUN -> [FAIL][5] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-apl4/igt@gem_ctx_isolation@vcs0-reset.html * igt@gem_ctx_isolation@vecs0-nonpriv: - shard-iclb: [PASS][6] -> [FAIL][7] +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-iclb1/igt@gem_ctx_isolation@vecs0-nonpriv.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-iclb2/igt@gem_ctx_isolation@vecs0-nonpriv.html * igt@gem_ctx_isolation@vecs0-reset: - shard-kbl: [PASS][8] -> [FAIL][9] +10 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-kbl6/igt@gem_ctx_isolation@vecs0-reset.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-kbl7/igt@gem_ctx_isolation@vecs0-reset.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt@gem_ctx_isolation@bcs0-nonpriv-switch}: - shard-apl: [PASS][10] -> [FAIL][11] +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-apl3/igt@gem_ctx_isolation@bcs0-nonpriv-switch.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-apl4/igt@gem_ctx_isolation@bcs0-nonpriv-switch.html - shard-glk: [PASS][12] -> [FAIL][13] +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-glk6/igt@gem_ctx_isolation@bcs0-nonpriv-switch.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-glk7/igt@gem_ctx_isolation@bcs0-nonpriv-switch.html * {igt@gem_ctx_isolation@vcs0-nonpriv-switch}: - shard-iclb: [PASS][14] -> [FAIL][15] +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-iclb8/igt@gem_ctx_isolation@vcs0-nonpriv-switch.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-iclb7/igt@gem_ctx_isolation@vcs0-nonpriv-switch.html * igt@gem_ctx_isolation@vcs2-clean: - {shard-tglb}: [SKIP][16] ([fdo#111599]) -> [SKIP][17] +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-tglb5/igt@gem_ctx_isolation@vcs2-clean.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-tglb3/igt@gem_ctx_isolation@vcs2-clean.html * igt@gem_ctx_isolation@vcs2-reset: - {shard-tglb}: NOTRUN -> [SKIP][18] +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-tglb2/igt@gem_ctx_isolation@vcs2-reset.html * {igt@gem_ctx_isolation@vecs0-nonpriv-switch}: - shard-kbl: [PASS][19] -> [FAIL][20] +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-kbl1/igt@gem_ctx_isolation@vecs0-nonpriv-switch.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-kbl3/igt@gem_ctx_isolation@vecs0-nonpriv-switch.html * igt@gem_ctx_isolation@vecs0-s3: - {shard-tglb}: [SKIP][21] ([fdo#111599]) -> [INCOMPLETE][22] +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-tglb6/igt@gem_ctx_isolation@vecs0-s3.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-tglb7/igt@gem_ctx_isolation@vecs0-s3.html * igt@gem_exec_parallel@vecs0-contexts: - {shard-tglb}: [PASS][23] -> [INCOMPLETE][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-tglb4/igt@gem_exec_parallel@vecs0-contexts.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-tglb1/igt@gem_exec_parallel@vecs0-contexts.html * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping: - {shard-tglb}: NOTRUN -> [INCOMPLETE][25] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-tglb3/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html Known issues ------------ Here are the changes found in IGTPW_3537_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][26] -> [SKIP][27] ([fdo#110841]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-iclb6/igt@gem_ctx_shared@exec-single-timeline-bsd.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html * igt@gem_eio@unwedge-stress: - shard-snb: [PASS][28] -> [FAIL][29] ([fdo#109661]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-snb7/igt@gem_eio@unwedge-stress.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-snb1/igt@gem_eio@unwedge-stress.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][30] -> [SKIP][31] ([fdo#110854]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-iclb1/igt@gem_exec_balancer@smoke.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-iclb5/igt@gem_exec_balancer@smoke.html * igt@gem_exec_schedule@preempt-bsd: - shard-iclb: [PASS][32] -> [SKIP][33] ([fdo#111325]) +4 similar issues [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-iclb5/igt@gem_exec_schedule@preempt-bsd.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-iclb1/igt@gem_exec_schedule@preempt-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][34] -> [SKIP][35] ([fdo#109276]) +12 similar issues [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-iclb1/igt@gem_exec_schedule@preempt-queue-bsd1.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-iclb3/igt@gem_exec_schedule@preempt-queue-bsd1.html * igt@gem_userptr_blits@dmabuf-unsync: - shard-hsw: [PASS][36] -> [DMESG-WARN][37] ([fdo#111870]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-hsw8/igt@gem_userptr_blits@dmabuf-unsync.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-hsw8/igt@gem_userptr_blits@dmabuf-unsync.html * igt@gem_userptr_blits@sync-unmap-after-close: - shard-kbl: [PASS][38] -> [DMESG-WARN][39] ([fdo#111870]) +2 similar issues [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-kbl4/igt@gem_userptr_blits@sync-unmap-after-close.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-kbl7/igt@gem_userptr_blits@sync-unmap-after-close.html - shard-apl: [PASS][40] -> [DMESG-WARN][41] ([fdo#109385] / [fdo#111870]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-apl2/igt@gem_userptr_blits@sync-unmap-after-close.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-apl6/igt@gem_userptr_blits@sync-unmap-after-close.html - shard-snb: [PASS][42] -> [DMESG-WARN][43] ([fdo#111870]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-snb5/igt@gem_userptr_blits@sync-unmap-after-close.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-snb6/igt@gem_userptr_blits@sync-unmap-after-close.html * igt@gem_userptr_blits@sync-unmap-cycles: - shard-iclb: [PASS][44] -> [DMESG-WARN][45] ([fdo#111870]) +1 similar issue [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-iclb2/igt@gem_userptr_blits@sync-unmap-cycles.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-iclb3/igt@gem_userptr_blits@sync-unmap-cycles.html * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-kbl: [PASS][46] -> [SKIP][47] ([fdo#109271]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-kbl3/igt@i915_pm_rc6_residency@rc6-accuracy.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-kbl7/igt@i915_pm_rc6_residency@rc6-accuracy.html * igt@i915_pm_rpm@system-suspend-execbuf: - shard-iclb: [PASS][48] -> [INCOMPLETE][49] ([fdo#107713] / [fdo#108840]) +1 similar issue [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-iclb5/igt@i915_pm_rpm@system-suspend-execbuf.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-iclb7/igt@i915_pm_rpm@system-suspend-execbuf.html * igt@i915_suspend@debugfs-reader: - shard-apl: [PASS][50] -> [DMESG-WARN][51] ([fdo#108566]) +2 similar issues [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-apl8/igt@i915_suspend@debugfs-reader.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-apl7/igt@i915_suspend@debugfs-reader.html * igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen: - shard-iclb: [PASS][52] -> [INCOMPLETE][53] ([fdo#107713]) +2 similar issues [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-iclb2/igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-iclb7/igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen.html * igt@kms_flip@2x-flip-vs-suspend-interruptible: - shard-hsw: [PASS][54] -> [INCOMPLETE][55] ([fdo#103540]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-hsw6/igt@kms_flip@2x-flip-vs-suspend-interruptible.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-hsw8/igt@kms_flip@2x-flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: - shard-iclb: [PASS][56] -> [FAIL][57] ([fdo#103167]) +3 similar issues [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][58] -> [SKIP][59] ([fdo#109441]) +1 similar issue [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-iclb1/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_setmode@basic: - shard-hsw: [PASS][60] -> [FAIL][61] ([fdo#99912]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-hsw1/igt@kms_setmode@basic.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-hsw5/igt@kms_setmode@basic.html #### Possible fixes #### * igt@gem_ctx_isolation@bcs0-dirty-create: - {shard-tglb}: [SKIP][62] ([fdo#111599]) -> [PASS][63] +6 similar issues [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-tglb1/igt@gem_ctx_isolation@bcs0-dirty-create.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-tglb5/igt@gem_ctx_isolation@bcs0-dirty-create.html * igt@gem_ctx_shared@q-smoketest-render: - {shard-tglb}: [INCOMPLETE][64] ([fdo# 111852 ]) -> [PASS][65] [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-tglb6/igt@gem_ctx_shared@q-smoketest-render.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-tglb7/igt@gem_ctx_shared@q-smoketest-render.html * igt@gem_exec_schedule@in-order-bsd2: - shard-iclb: [SKIP][66] ([fdo#109276]) -> [PASS][67] +13 similar issues [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-iclb7/igt@gem_exec_schedule@in-order-bsd2.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-iclb2/igt@gem_exec_schedule@in-order-bsd2.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [SKIP][68] ([fdo#111325]) -> [PASS][69] +5 similar issues [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-iclb5/igt@gem_exec_schedule@preemptive-hang-bsd.html * igt@gem_mmap_gtt@hang: - shard-kbl: [DMESG-WARN][70] -> [PASS][71] [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-kbl2/igt@gem_mmap_gtt@hang.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-kbl7/igt@gem_mmap_gtt@hang.html - shard-iclb: [DMESG-WARN][72] -> [PASS][73] [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-iclb8/igt@gem_mmap_gtt@hang.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-iclb2/igt@gem_mmap_gtt@hang.html * igt@gem_userptr_blits@dmabuf-sync: - shard-snb: [DMESG-WARN][74] ([fdo#111870]) -> [PASS][75] +1 similar issue [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-snb5/igt@gem_userptr_blits@dmabuf-sync.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-snb5/igt@gem_userptr_blits@dmabuf-sync.html * igt@gem_userptr_blits@map-fixed-invalidate-busy: - shard-glk: [DMESG-WARN][76] ([fdo#111870]) -> [PASS][77] +1 similar issue [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-glk1/igt@gem_userptr_blits@map-fixed-invalidate-busy.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-glk6/igt@gem_userptr_blits@map-fixed-invalidate-busy.html * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup: - shard-kbl: [DMESG-WARN][78] ([fdo#111870]) -> [PASS][79] [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-kbl4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-kbl1/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: - shard-hsw: [DMESG-WARN][80] ([fdo#111870]) -> [PASS][81] +3 similar issues [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html * igt@gem_workarounds@suspend-resume-fd: - {shard-tglb}: [INCOMPLETE][82] ([fdo#111832]) -> [PASS][83] +1 similar issue [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-tglb5/igt@gem_workarounds@suspend-resume-fd.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-tglb3/igt@gem_workarounds@suspend-resume-fd.html * igt@kms_color@pipe-a-ctm-red-to-blue: - {shard-tglb}: [FAIL][84] ([fdo#111859]) -> [PASS][85] [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-tglb7/igt@kms_color@pipe-a-ctm-red-to-blue.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-tglb2/igt@kms_color@pipe-a-ctm-red-to-blue.html * igt@kms_color@pipe-a-gamma: - {shard-tglb}: [FAIL][86] ([fdo#104782]) -> [PASS][87] [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-tglb7/igt@kms_color@pipe-a-gamma.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-tglb2/igt@kms_color@pipe-a-gamma.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: [FAIL][88] ([fdo#103167]) -> [PASS][89] +1 similar issue [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [DMESG-WARN][90] ([fdo#108566]) -> [PASS][91] +5 similar issues [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-apl1/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu: - {shard-tglb}: [FAIL][92] ([fdo#103167]) -> [PASS][93] +4 similar issues [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu.html * igt@kms_plane_cursor@pipe-a-primary-size-256: - shard-apl: [INCOMPLETE][94] ([fdo#103927]) -> [PASS][95] +3 similar issues [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-apl1/igt@kms_plane_cursor@pipe-a-primary-size-256.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-apl4/igt@kms_plane_cursor@pipe-a-primary-size-256.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [SKIP][96] ([fdo#109441]) -> [PASS][97] +2 similar issues [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-iclb3/igt@kms_psr@psr2_cursor_mmap_cpu.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_setmode@basic: - shard-kbl: [FAIL][98] ([fdo#99912]) -> [PASS][99] [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-kbl7/igt@kms_setmode@basic.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-kbl4/igt@kms_setmode@basic.html * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-kbl: [INCOMPLETE][100] ([fdo#103665]) -> [PASS][101] [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html #### Warnings #### * igt@gem_mocs_settings@mocs-rc6-bsd2: - shard-iclb: [SKIP][102] ([fdo#109276]) -> [FAIL][103] ([fdo#111330]) [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-iclb8/igt@gem_mocs_settings@mocs-rc6-bsd2.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-iclb2/igt@gem_mocs_settings@mocs-rc6-bsd2.html * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup: - shard-snb: [DMESG-WARN][104] ([fdo#111870]) -> [DMESG-WARN][105] ([fdo#110789] / [fdo#111870]) [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7010/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/shard-snb7/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo# 111852 ]: https://bugs.freedesktop.org/show_bug.cgi?id= 111852 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3537/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2019-10-05 1:40 UTC | newest] Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-10-02 11:26 [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake Chris Wilson 2019-10-02 11:26 ` [igt-dev] " Chris Wilson 2019-10-02 11:38 ` Petri Latvala 2019-10-02 11:38 ` [Intel-gfx] " Petri Latvala 2019-10-03 23:26 ` Stimson, Dale B 2019-10-03 23:26 ` [Intel-gfx] " Stimson, Dale B 2019-10-04 8:16 ` Chris Wilson 2019-10-04 8:16 ` [igt-dev] [Intel-gfx] " Chris Wilson 2019-10-02 12:58 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork 2019-10-02 18:48 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork 2019-10-04 13:51 ` [igt-dev] [PATCH i-g-t] " Mika Kuoppala 2019-10-04 13:51 ` Mika Kuoppala 2019-10-04 13:57 ` Chris Wilson 2019-10-04 13:57 ` [Intel-gfx] " Chris Wilson 2019-10-04 15:17 ` Chris Wilson 2019-10-04 15:17 ` [igt-dev] " Chris Wilson 2019-10-04 15:19 ` Mika Kuoppala 2019-10-04 15:19 ` [igt-dev] " Mika Kuoppala 2019-10-04 16:14 ` [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_ctx_isolation: Bump support for Tigerlake (rev2) Patchwork 2019-10-05 1:40 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
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