From: Jonathan Behrens <jonathan@fintelia.io> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>, Jonathan Behrens <jonathan@fintelia.io>, Palmer Dabbelt <palmer@sifive.com>, Alistair Francis <Alistair.Francis@wdc.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Bin Meng <bmeng.cn@gmail.com> Subject: [PATCH v4 1/3] target/riscv: Tell gdbstub the correct number of CSRs Date: Mon, 14 Oct 2019 11:45:27 -0400 [thread overview] Message-ID: <20191014154529.287048-2-jonathan@fintelia.io> (raw) In-Reply-To: <20191014154529.287048-1-jonathan@fintelia.io> If the number of registers reported to the gdbstub code does not match the number in the associated XML file, then the register numbers used by the stub may get out of sync with a remote GDB instance. Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/gdbstub.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index ded140e8d8..cb5bfd3d50 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -384,7 +384,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) } gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 4096, "riscv-32bit-csr.xml", 0); + 240, "riscv-32bit-csr.xml", 0); #elif defined(TARGET_RISCV64) if (env->misa & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, @@ -392,6 +392,6 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) } gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 4096, "riscv-64bit-csr.xml", 0); + 240, "riscv-64bit-csr.xml", 0); #endif } -- 2.23.0
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Behrens <jonathan@fintelia.io> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Jonathan Behrens <jonathan@fintelia.io>, Bin Meng <bmeng.cn@gmail.com>, Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Subject: [PATCH v4 1/3] target/riscv: Tell gdbstub the correct number of CSRs Date: Mon, 14 Oct 2019 11:45:27 -0400 [thread overview] Message-ID: <20191014154529.287048-2-jonathan@fintelia.io> (raw) In-Reply-To: <20191014154529.287048-1-jonathan@fintelia.io> If the number of registers reported to the gdbstub code does not match the number in the associated XML file, then the register numbers used by the stub may get out of sync with a remote GDB instance. Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/gdbstub.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index ded140e8d8..cb5bfd3d50 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -384,7 +384,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) } gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 4096, "riscv-32bit-csr.xml", 0); + 240, "riscv-32bit-csr.xml", 0); #elif defined(TARGET_RISCV64) if (env->misa & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, @@ -392,6 +392,6 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) } gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 4096, "riscv-64bit-csr.xml", 0); + 240, "riscv-64bit-csr.xml", 0); #endif } -- 2.23.0
next prev parent reply other threads:[~2019-10-14 15:52 UTC|newest] Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-10-14 15:45 [PATCH v4 0/3] target/riscv: Expose "priv" register for GDB Jonathan Behrens 2019-10-14 15:45 ` Jonathan Behrens [this message] 2019-10-14 15:45 ` [PATCH v4 1/3] target/riscv: Tell gdbstub the correct number of CSRs Jonathan Behrens 2019-10-14 15:45 ` [PATCH v4 2/3] target/riscv: Expose "priv" register for GDB for reads Jonathan Behrens 2019-10-14 15:45 ` Jonathan Behrens 2019-10-14 18:00 ` Alistair Francis 2019-10-14 18:00 ` Alistair Francis 2019-10-15 8:38 ` Bin Meng 2019-10-15 8:38 ` Bin Meng 2019-10-14 15:45 ` [PATCH v4 3/3] target/riscv: Make the priv register writable by GDB Jonathan Behrens 2019-10-14 15:45 ` Jonathan Behrens 2019-10-18 18:35 ` [PATCH v4 0/3] target/riscv: Expose "priv" register for GDB Palmer Dabbelt 2019-10-18 18:35 ` Palmer Dabbelt
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