From: Jonathan Behrens <jonathan@fintelia.io> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: "Sagar Karandikar" <sagark@eecs.berkeley.edu>, "Jonathan Behrens" <jonathan@fintelia.io>, "Palmer Dabbelt" <palmer@sifive.com>, "Philippe Mathieu-Daudé" <philmd@redhat.com>, "Alistair Francis" <Alistair.Francis@wdc.com>, "Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>, "Alex Bennée" <alex.bennee@linaro.org> Subject: [PATCH v4 2/3] target/riscv: Expose "priv" register for GDB for reads Date: Mon, 14 Oct 2019 11:45:28 -0400 [thread overview] Message-ID: <20191014154529.287048-3-jonathan@fintelia.io> (raw) In-Reply-To: <20191014154529.287048-1-jonathan@fintelia.io> This patch enables a debugger to read the current privilege level via a virtual "priv" register. When compiled with CONFIG_USER_ONLY the register is still visible but always reports the value zero. Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> --- configure | 4 ++-- gdb-xml/riscv-32bit-virtual.xml | 11 +++++++++++ gdb-xml/riscv-64bit-virtual.xml | 11 +++++++++++ target/riscv/gdbstub.c | 23 +++++++++++++++++++++++ 4 files changed, 47 insertions(+), 2 deletions(-) create mode 100644 gdb-xml/riscv-32bit-virtual.xml create mode 100644 gdb-xml/riscv-64bit-virtual.xml diff --git a/configure b/configure index 30544f52e6..6118a6a045 100755 --- a/configure +++ b/configure @@ -7520,13 +7520,13 @@ case "$target_name" in TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes - gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml" + gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml riscv-32bit-virtual.xml" ;; riscv64) TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes - gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml" + gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml" ;; sh4|sh4eb) TARGET_ARCH=sh4 diff --git a/gdb-xml/riscv-32bit-virtual.xml b/gdb-xml/riscv-32bit-virtual.xml new file mode 100644 index 0000000000..905f1c555d --- /dev/null +++ b/gdb-xml/riscv-32bit-virtual.xml @@ -0,0 +1,11 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.riscv.virtual"> + <reg name="priv" bitsize="32"/> +</feature> diff --git a/gdb-xml/riscv-64bit-virtual.xml b/gdb-xml/riscv-64bit-virtual.xml new file mode 100644 index 0000000000..62d86c237b --- /dev/null +++ b/gdb-xml/riscv-64bit-virtual.xml @@ -0,0 +1,11 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.riscv.virtual"> + <reg name="priv" bitsize="64"/> +</feature> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index cb5bfd3d50..1f71604b78 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -373,6 +373,23 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n) return 0; } +static int riscv_gdb_get_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) +{ + if (n == 0) { +#ifdef CONFIG_USER_ONLY + return gdb_get_regl(mem_buf, 0); +#else + return gdb_get_regl(mem_buf, cs->priv); +#endif + } + return 0; +} + +static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) +{ + return 0; +} + void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); @@ -385,6 +402,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 240, "riscv-32bit-csr.xml", 0); + + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, + 1, "riscv-32bit-virtual.xml", 0); #elif defined(TARGET_RISCV64) if (env->misa & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, @@ -393,5 +413,8 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 240, "riscv-64bit-csr.xml", 0); + + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, + 1, "riscv-64bit-virtual.xml", 0); #endif } -- 2.23.0
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Behrens <jonathan@fintelia.io> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: "Jonathan Behrens" <jonathan@fintelia.io>, "Alex Bennée" <alex.bennee@linaro.org>, "Philippe Mathieu-Daudé" <philmd@redhat.com>, "Palmer Dabbelt" <palmer@sifive.com>, "Alistair Francis" <Alistair.Francis@wdc.com>, "Sagar Karandikar" <sagark@eecs.berkeley.edu>, "Bastian Koppelmann" <kbastian@mail.uni-paderborn.de> Subject: [PATCH v4 2/3] target/riscv: Expose "priv" register for GDB for reads Date: Mon, 14 Oct 2019 11:45:28 -0400 [thread overview] Message-ID: <20191014154529.287048-3-jonathan@fintelia.io> (raw) In-Reply-To: <20191014154529.287048-1-jonathan@fintelia.io> This patch enables a debugger to read the current privilege level via a virtual "priv" register. When compiled with CONFIG_USER_ONLY the register is still visible but always reports the value zero. Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> --- configure | 4 ++-- gdb-xml/riscv-32bit-virtual.xml | 11 +++++++++++ gdb-xml/riscv-64bit-virtual.xml | 11 +++++++++++ target/riscv/gdbstub.c | 23 +++++++++++++++++++++++ 4 files changed, 47 insertions(+), 2 deletions(-) create mode 100644 gdb-xml/riscv-32bit-virtual.xml create mode 100644 gdb-xml/riscv-64bit-virtual.xml diff --git a/configure b/configure index 30544f52e6..6118a6a045 100755 --- a/configure +++ b/configure @@ -7520,13 +7520,13 @@ case "$target_name" in TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes - gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml" + gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml riscv-32bit-virtual.xml" ;; riscv64) TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes - gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml" + gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml" ;; sh4|sh4eb) TARGET_ARCH=sh4 diff --git a/gdb-xml/riscv-32bit-virtual.xml b/gdb-xml/riscv-32bit-virtual.xml new file mode 100644 index 0000000000..905f1c555d --- /dev/null +++ b/gdb-xml/riscv-32bit-virtual.xml @@ -0,0 +1,11 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.riscv.virtual"> + <reg name="priv" bitsize="32"/> +</feature> diff --git a/gdb-xml/riscv-64bit-virtual.xml b/gdb-xml/riscv-64bit-virtual.xml new file mode 100644 index 0000000000..62d86c237b --- /dev/null +++ b/gdb-xml/riscv-64bit-virtual.xml @@ -0,0 +1,11 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.riscv.virtual"> + <reg name="priv" bitsize="64"/> +</feature> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index cb5bfd3d50..1f71604b78 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -373,6 +373,23 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n) return 0; } +static int riscv_gdb_get_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) +{ + if (n == 0) { +#ifdef CONFIG_USER_ONLY + return gdb_get_regl(mem_buf, 0); +#else + return gdb_get_regl(mem_buf, cs->priv); +#endif + } + return 0; +} + +static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) +{ + return 0; +} + void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); @@ -385,6 +402,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 240, "riscv-32bit-csr.xml", 0); + + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, + 1, "riscv-32bit-virtual.xml", 0); #elif defined(TARGET_RISCV64) if (env->misa & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, @@ -393,5 +413,8 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 240, "riscv-64bit-csr.xml", 0); + + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, + 1, "riscv-64bit-virtual.xml", 0); #endif } -- 2.23.0
next prev parent reply other threads:[~2019-10-14 15:52 UTC|newest] Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-10-14 15:45 [PATCH v4 0/3] target/riscv: Expose "priv" register for GDB Jonathan Behrens 2019-10-14 15:45 ` [PATCH v4 1/3] target/riscv: Tell gdbstub the correct number of CSRs Jonathan Behrens 2019-10-14 15:45 ` Jonathan Behrens 2019-10-14 15:45 ` Jonathan Behrens [this message] 2019-10-14 15:45 ` [PATCH v4 2/3] target/riscv: Expose "priv" register for GDB for reads Jonathan Behrens 2019-10-14 18:00 ` Alistair Francis 2019-10-14 18:00 ` Alistair Francis 2019-10-15 8:38 ` Bin Meng 2019-10-15 8:38 ` Bin Meng 2019-10-14 15:45 ` [PATCH v4 3/3] target/riscv: Make the priv register writable by GDB Jonathan Behrens 2019-10-14 15:45 ` Jonathan Behrens 2019-10-18 18:35 ` [PATCH v4 0/3] target/riscv: Expose "priv" register for GDB Palmer Dabbelt 2019-10-18 18:35 ` Palmer Dabbelt
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