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* [PATCH 01/14] drm/i915: Rework watermark readout to use plane api
@ 2019-10-17 13:20 Maarten Lankhorst
  2019-10-17 13:20 ` [PATCH 02/14] drm/i915: Introduce intel_atomic_get_plane_state_after_check(), v2 Maarten Lankhorst
                   ` (19 more replies)
  0 siblings, 20 replies; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-17 13:20 UTC (permalink / raw)
  To: intel-gfx

Instead of unconditionally verifying the cursor plane, handle it in the
same way as any other plane, and use our existing api to verify.

While at it, ensure that on gen9+ we verify active_planes mask as well.
This should give the correct results for planar YUV planes too, as we
update active_planes for them.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 83 ++++++--------------
 1 file changed, 23 insertions(+), 60 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 164ded862148..945ab2180614 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12932,7 +12932,8 @@ static void verify_wm_state(struct intel_crtc *crtc,
 	struct skl_pipe_wm *sw_wm;
 	struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
 	const enum pipe pipe = crtc->pipe;
-	int plane, level, max_level = ilk_wm_max_level(dev_priv);
+	int level, max_level = ilk_wm_max_level(dev_priv);
+	struct intel_plane *plane;
 
 	if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->base.active)
 		return;
@@ -12956,63 +12957,25 @@ static void verify_wm_state(struct intel_crtc *crtc,
 			  hw->ddb.enabled_slices);
 
 	/* planes */
-	for_each_universal_plane(dev_priv, pipe, plane) {
+	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
 		struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
+		enum pipe plane_pipe = pipe;
 
-		hw_plane_wm = &hw->wm.planes[plane];
-		sw_plane_wm = &sw_wm->planes[plane];
-
-		/* Watermarks */
-		for (level = 0; level <= max_level; level++) {
-			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
-						&sw_plane_wm->wm[level]))
-				continue;
-
-			DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
-				  pipe_name(pipe), plane + 1, level,
-				  sw_plane_wm->wm[level].plane_en,
-				  sw_plane_wm->wm[level].plane_res_b,
-				  sw_plane_wm->wm[level].plane_res_l,
-				  hw_plane_wm->wm[level].plane_en,
-				  hw_plane_wm->wm[level].plane_res_b,
-				  hw_plane_wm->wm[level].plane_res_l);
-		}
+		hw_plane_wm = &hw->wm.planes[plane->id];
+		sw_plane_wm = &sw_wm->planes[plane->id];
 
-		if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
-					 &sw_plane_wm->trans_wm)) {
-			DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
-				  pipe_name(pipe), plane + 1,
-				  sw_plane_wm->trans_wm.plane_en,
-				  sw_plane_wm->trans_wm.plane_res_b,
-				  sw_plane_wm->trans_wm.plane_res_l,
-				  hw_plane_wm->trans_wm.plane_en,
-				  hw_plane_wm->trans_wm.plane_res_b,
-				  hw_plane_wm->trans_wm.plane_res_l);
-		}
-
-		/* DDB */
-		hw_ddb_entry = &hw->ddb_y[plane];
-		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
-
-		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
-			DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
-				  pipe_name(pipe), plane + 1,
-				  sw_ddb_entry->start, sw_ddb_entry->end,
-				  hw_ddb_entry->start, hw_ddb_entry->end);
+		if (!plane->get_hw_state(plane, &plane_pipe)) {
+			WARN(new_crtc_state->active_planes & BIT(plane->id),
+			     "pipe %c %s should be visible, but isn't\n",
+			     pipe_name(pipe), plane->base.name);
+			continue;
 		}
-	}
 
-	/*
-	 * cursor
-	 * If the cursor plane isn't active, we may not have updated it's ddb
-	 * allocation. In that case since the ddb allocation will be updated
-	 * once the plane becomes visible, we can skip this check
-	 */
-	if (1) {
-		struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
+		WARN_ON(plane_pipe != pipe);
 
-		hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
-		sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
+		WARN(!(new_crtc_state->active_planes & BIT(plane->id)),
+		     "pipe %c %s should be invisible, but visible.\n",
+		     pipe_name(pipe), plane->base.name);
 
 		/* Watermarks */
 		for (level = 0; level <= max_level; level++) {
@@ -13020,8 +12983,8 @@ static void verify_wm_state(struct intel_crtc *crtc,
 						&sw_plane_wm->wm[level]))
 				continue;
 
-			DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
-				  pipe_name(pipe), level,
+			DRM_ERROR("mismatch in WM pipe %c %s level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+				  pipe_name(pipe), plane->base.name, level,
 				  sw_plane_wm->wm[level].plane_en,
 				  sw_plane_wm->wm[level].plane_res_b,
 				  sw_plane_wm->wm[level].plane_res_l,
@@ -13032,8 +12995,8 @@ static void verify_wm_state(struct intel_crtc *crtc,
 
 		if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
 					 &sw_plane_wm->trans_wm)) {
-			DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
-				  pipe_name(pipe),
+			DRM_ERROR("mismatch in trans WM pipe %c %s (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+				  pipe_name(pipe), plane->base.name,
 				  sw_plane_wm->trans_wm.plane_en,
 				  sw_plane_wm->trans_wm.plane_res_b,
 				  sw_plane_wm->trans_wm.plane_res_l,
@@ -13043,12 +13006,12 @@ static void verify_wm_state(struct intel_crtc *crtc,
 		}
 
 		/* DDB */
-		hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
-		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
+		hw_ddb_entry = &hw->ddb_y[plane->id];
+		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id];
 
 		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
-			DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
-				  pipe_name(pipe),
+			DRM_ERROR("mismatch in DDB state pipe %c %s (expected (%u,%u), found (%u,%u))\n",
+				  pipe_name(pipe), plane->base.name,
 				  sw_ddb_entry->start, sw_ddb_entry->end,
 				  hw_ddb_entry->start, hw_ddb_entry->end);
 		}
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH 02/14] drm/i915: Introduce intel_atomic_get_plane_state_after_check(), v2.
  2019-10-17 13:20 [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Maarten Lankhorst
@ 2019-10-17 13:20 ` Maarten Lankhorst
  2019-10-17 13:20 ` [PATCH 03/14] drm/i915: Handle a few more cases for crtc hw/uapi split, v2 Maarten Lankhorst
                   ` (18 subsequent siblings)
  19 siblings, 0 replies; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-17 13:20 UTC (permalink / raw)
  To: intel-gfx

Use this in all the places where we try to acquire planes after the planes
atomic_check().

In case of intel_modeset_all_pipes() this is not yet done after atomic_check,
but seems like it will be in the future. To add some paranoia, add all planes
rather than active planes, because of bigjoiner and planar YUV support having
extra planes outside of the core's view that wouldn't be added otherwise.

Changes since v1:
- Always add all planes, to handle force plane updates to work correctly
  with a disabled cursor plane.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic.c   | 41 +++++++++----------
 .../gpu/drm/i915/display/intel_atomic_plane.c | 15 +++++++
 drivers/gpu/drm/i915/display/intel_cdclk.c    | 15 ++++---
 drivers/gpu/drm/i915/display/intel_color.c    |  7 ++--
 .../drm/i915/display/intel_display_types.h    |  6 +++
 drivers/gpu/drm/i915/intel_pm.c               | 14 ++++---
 6 files changed, 62 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index c5a552a69752..e6cb85d41c8d 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -313,13 +313,10 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
 			       struct intel_crtc *intel_crtc,
 			       struct intel_crtc_state *crtc_state)
 {
-	struct drm_plane *plane = NULL;
-	struct intel_plane *intel_plane;
-	struct intel_plane_state *plane_state = NULL;
 	struct intel_crtc_scaler_state *scaler_state =
 		&crtc_state->scaler_state;
 	struct drm_atomic_state *drm_state = crtc_state->base.state;
-	struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
+	struct intel_atomic_state *state = to_intel_atomic_state(drm_state);
 	int num_scalers_need;
 	int i;
 
@@ -346,6 +343,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
 
 	/* walkthrough scaler_users bits and start assigning scalers */
 	for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
+		struct intel_plane_state *plane_state = NULL;
 		int *scaler_id;
 		const char *name;
 		int idx;
@@ -361,19 +359,16 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
 			/* panel fitter case: assign as a crtc scaler */
 			scaler_id = &scaler_state->scaler_id;
 		} else {
-			name = "PLANE";
+			struct intel_plane *plane;
 
 			/* plane scaler case: assign as a plane scaler */
 			/* find the plane that set the bit as scaler_user */
-			plane = drm_state->planes[i].ptr;
 
 			/*
 			 * to enable/disable hq mode, add planes that are using scaler
 			 * into this transaction
 			 */
-			if (!plane) {
-				struct drm_plane_state *state;
-
+			if (!drm_state->planes[i].ptr) {
 				/*
 				 * GLK+ scalers don't have a HQ mode so it
 				 * isn't necessary to change between HQ and dyn mode
@@ -382,24 +377,28 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
 				if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 					continue;
 
-				plane = drm_plane_from_index(&dev_priv->drm, i);
-				state = drm_atomic_get_plane_state(drm_state, plane);
-				if (IS_ERR(state)) {
-					DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n",
-						plane->base.id);
-					return PTR_ERR(state);
+				plane = to_intel_plane(drm_plane_from_index(&dev_priv->drm, i));
+				plane_state =
+					intel_atomic_get_plane_state_after_check(state,
+										 crtc_state,
+										 plane);
+				if (IS_ERR(plane_state)) {
+					DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state: %li\n",
+						plane->base.base.id, PTR_ERR(plane_state));
+					return PTR_ERR(plane_state);
 				}
+			} else {
+				plane = to_intel_plane(drm_state->planes[i].ptr);
+				plane_state = intel_atomic_get_new_plane_state(state,
+									       plane);
 			}
 
-			intel_plane = to_intel_plane(plane);
-			idx = plane->base.id;
-
 			/* plane on different crtc cannot be a scaler user of this crtc */
-			if (WARN_ON(intel_plane->pipe != intel_crtc->pipe))
+			if (WARN_ON(plane->pipe != intel_crtc->pipe))
 				continue;
 
-			plane_state = intel_atomic_get_new_plane_state(intel_state,
-								       intel_plane);
+			name = "PLANE";
+			idx = plane->base.base.id;
 			scaler_id = &plane_state->scaler_id;
 		}
 
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index a6cff5a160fb..847f9c4ecbbd 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -363,6 +363,21 @@ void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
 	}
 }
 
+struct intel_plane_state *
+intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
+					 struct intel_crtc_state *new_crtc_state,
+					 struct intel_plane *plane)
+{
+	struct intel_plane_state *plane_state =
+		intel_atomic_get_plane_state(state, plane);
+
+	if (IS_ERR(plane_state))
+		return plane_state;
+
+	new_crtc_state->update_planes |= BIT(plane->id);
+	return plane_state;
+}
+
 const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
 	.prepare_fb = intel_prepare_plane_fb,
 	.cleanup_fb = intel_cleanup_plane_fb,
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 3d867963a6d1..ab1f7cec50c6 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2253,6 +2253,7 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
 	 */
 	for_each_intel_crtc(&dev_priv->drm, crtc) {
 		struct intel_crtc_state *crtc_state;
+		struct intel_plane *plane;
 		int ret;
 
 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
@@ -2270,12 +2271,14 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
 		if (ret)
 			return ret;
 
-		ret = drm_atomic_add_affected_planes(&state->base,
-						     &crtc->base);
-		if (ret)
-			return ret;
-
-		crtc_state->update_planes |= crtc_state->active_planes;
+		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+			struct intel_plane_state *plane_state =
+				intel_atomic_get_plane_state_after_check(state,
+									 crtc_state,
+									 plane);
+			if (IS_ERR(plane_state))
+				return PTR_ERR(plane_state);
+		}
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index fa44eb73d088..95586a588234 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1077,11 +1077,12 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
 		if (!need_plane_update(plane, new_crtc_state))
 			continue;
 
-		plane_state = intel_atomic_get_plane_state(state, plane);
+		plane_state =
+			intel_atomic_get_plane_state_after_check(state,
+								 new_crtc_state,
+								 plane);
 		if (IS_ERR(plane_state))
 			return PTR_ERR(plane_state);
-
-		new_crtc_state->update_planes |= BIT(plane->id);
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 40390d855815..244e881474fb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1543,4 +1543,10 @@ static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
 	return i915_ggtt_offset(state->vma);
 }
 
+/* intel_atomic_plane.c */
+struct intel_plane_state *
+intel_atomic_get_plane_state_after_check(struct intel_atomic_state *state,
+					 struct intel_crtc_state *crtc_state,
+					 struct intel_plane *plane);
+
 #endif /*  __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b306e2338f5a..ef36e7834ed4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5267,11 +5267,12 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
 					&new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
 			continue;
 
-		plane_state = intel_atomic_get_plane_state(state, plane);
+		plane_state =
+			intel_atomic_get_plane_state_after_check(state,
+								 new_crtc_state,
+								 plane);
 		if (IS_ERR(plane_state))
 			return PTR_ERR(plane_state);
-
-		new_crtc_state->update_planes |= BIT(plane_id);
 	}
 
 	return 0;
@@ -5559,11 +5560,12 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
 					&new_crtc_state->wm.skl.optimal.planes[plane_id]))
 			continue;
 
-		plane_state = intel_atomic_get_plane_state(state, plane);
+		plane_state =
+			intel_atomic_get_plane_state_after_check(state,
+								 new_crtc_state,
+								 plane);
 		if (IS_ERR(plane_state))
 			return PTR_ERR(plane_state);
-
-		new_crtc_state->update_planes |= BIT(plane_id);
 	}
 
 	return 0;
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH 03/14] drm/i915: Handle a few more cases for crtc hw/uapi split, v2.
  2019-10-17 13:20 [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Maarten Lankhorst
  2019-10-17 13:20 ` [PATCH 02/14] drm/i915: Introduce intel_atomic_get_plane_state_after_check(), v2 Maarten Lankhorst
@ 2019-10-17 13:20 ` Maarten Lankhorst
  2019-10-18 10:33   ` Ville Syrjälä
  2019-10-17 13:20 ` [PATCH 04/14] drm/i915: Add aliases for uapi and hw to crtc_state Maarten Lankhorst
                   ` (17 subsequent siblings)
  19 siblings, 1 reply; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-17 13:20 UTC (permalink / raw)
  To: intel-gfx

We are still looking at drm_crtc_state in a few places, convert those
to use intel_crtc_state instead.

Changes since v1:
- Move to before uapi/hw split.
- Add hunks for intel_pm.c as well.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 14 +++++++-------
 drivers/gpu/drm/i915/display/intel_dp_mst.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c     |  4 ++--
 drivers/gpu/drm/i915/intel_pm.c              |  6 ++----
 4 files changed, 12 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 945ab2180614..5632e13d458d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -16092,8 +16092,8 @@ static int intel_initial_commit(struct drm_device *dev)
 {
 	struct drm_atomic_state *state = NULL;
 	struct drm_modeset_acquire_ctx ctx;
-	struct drm_crtc *crtc;
-	struct drm_crtc_state *crtc_state;
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *crtc_state;
 	int ret = 0;
 
 	state = drm_atomic_state_alloc(dev);
@@ -16105,15 +16105,15 @@ static int intel_initial_commit(struct drm_device *dev)
 retry:
 	state->acquire_ctx = &ctx;
 
-	drm_for_each_crtc(crtc, dev) {
-		crtc_state = drm_atomic_get_crtc_state(state, crtc);
+	for_each_intel_crtc(dev, crtc) {
+		crtc_state = intel_atomic_get_crtc_state(state, crtc);
 		if (IS_ERR(crtc_state)) {
 			ret = PTR_ERR(crtc_state);
 			goto out;
 		}
 
-		if (crtc_state->active) {
-			ret = drm_atomic_add_affected_planes(state, crtc);
+		if (crtc_state->base.active) {
+			ret = drm_atomic_add_affected_planes(state, &crtc->base);
 			if (ret)
 				goto out;
 
@@ -16123,7 +16123,7 @@ static int intel_initial_commit(struct drm_device *dev)
 			 * having a proper LUT loaded. Remove once we
 			 * have readout for pipe gamma enable.
 			 */
-			crtc_state->color_mgmt_changed = true;
+			crtc_state->base.color_mgmt_changed = true;
 		}
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 2203be28ea01..5484bd4534c1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -187,7 +187,7 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
 
 		if (!crtc_state ||
 		    !drm_atomic_crtc_needs_modeset(crtc_state) ||
-		    crtc_state->enable)
+		    to_intel_crtc_state(crtc_state)->base.enable)
 			return 0;
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 50f22abcd30e..211710f5214c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1139,9 +1139,9 @@ static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
 
 		intel_crtc_state = to_intel_crtc_state(crtc_state);
 
-		if (crtc_state->active && intel_crtc_state->has_psr) {
+		if (intel_crtc_state->base.active && intel_crtc_state->has_psr) {
 			/* Mark mode as changed to trigger a pipe->update() */
-			crtc_state->mode_changed = true;
+			intel_crtc_state->base.mode_changed = true;
 			break;
 		}
 	}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ef36e7834ed4..e680df75a970 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3082,11 +3082,9 @@ static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
 /* Compute new watermarks for the pipe */
 static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 {
-	struct drm_atomic_state *state = crtc_state->base.state;
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct intel_pipe_wm *pipe_wm;
-	struct drm_device *dev = state->dev;
-	const struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_plane *plane;
 	const struct intel_plane_state *plane_state;
 	const struct intel_plane_state *pristate = NULL;
@@ -3781,7 +3779,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
 	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 	crtc_state = to_intel_crtc_state(crtc->base.state);
 
-	if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+	if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
 		return false;
 
 	for_each_intel_plane_on_crtc(dev, crtc, plane) {
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH 04/14] drm/i915: Add aliases for uapi and hw to crtc_state
  2019-10-17 13:20 [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Maarten Lankhorst
  2019-10-17 13:20 ` [PATCH 02/14] drm/i915: Introduce intel_atomic_get_plane_state_after_check(), v2 Maarten Lankhorst
  2019-10-17 13:20 ` [PATCH 03/14] drm/i915: Handle a few more cases for crtc hw/uapi split, v2 Maarten Lankhorst
@ 2019-10-17 13:20 ` Maarten Lankhorst
  2019-10-18 10:36   ` Ville Syrjälä
  2019-10-17 13:20 ` [PATCH 05/14] drm/i915: Perform manual conversions for crtc uapi/hw split Maarten Lankhorst
                   ` (16 subsequent siblings)
  19 siblings, 1 reply; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-17 13:20 UTC (permalink / raw)
  To: intel-gfx

Prepare to split up hw and uapi machinally, by adding a uapi and
hw alias. We will remove the base in a bit. This is a split from the
original uapi/hw patch, which did it all in one go.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic.c   |  8 ++++--
 drivers/gpu/drm/i915/display/intel_display.c  |  2 ++
 drivers/gpu/drm/i915/display/intel_display.h  |  6 ++---
 .../drm/i915/display/intel_display_types.h    | 27 ++++++++++++++++++-
 4 files changed, 37 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index e6cb85d41c8d..2cdc92897abd 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -186,9 +186,10 @@ intel_digital_connector_duplicate_state(struct drm_connector *connector)
 struct drm_crtc_state *
 intel_crtc_duplicate_state(struct drm_crtc *crtc)
 {
+	const struct intel_crtc_state *old_crtc_state = to_intel_crtc_state(crtc->state);
 	struct intel_crtc_state *crtc_state;
 
-	crtc_state = kmemdup(crtc->state, sizeof(*crtc_state), GFP_KERNEL);
+	crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL);
 	if (!crtc_state)
 		return NULL;
 
@@ -219,7 +220,10 @@ void
 intel_crtc_destroy_state(struct drm_crtc *crtc,
 			 struct drm_crtc_state *state)
 {
-	drm_atomic_helper_crtc_destroy_state(crtc, state);
+	struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
+
+	__drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
+	kfree(crtc_state);
 }
 
 static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5632e13d458d..fa0abfdff2ae 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12282,6 +12282,8 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
 
 	/* Keep base drm_crtc_state intact, only clear our extended struct */
 	BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
+	BUILD_BUG_ON(offsetof(struct intel_crtc_state, uapi));
+	BUILD_BUG_ON(offsetof(struct intel_crtc_state, hw));
 	memcpy(&crtc_state->base + 1, &saved_state->base + 1,
 	       sizeof(*crtc_state) - sizeof(crtc_state->base));
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 90807603987c..9b53f65386b5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -444,10 +444,10 @@ enum phy_fia {
 #define intel_atomic_crtc_state_for_each_plane_state( \
 		  plane, plane_state, \
 		  crtc_state) \
-	for_each_intel_plane_mask(((crtc_state)->base.state->dev), (plane), \
-				((crtc_state)->base.plane_mask)) \
+	for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
+				((crtc_state)->uapi.plane_mask)) \
 		for_each_if ((plane_state = \
-			      to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->base.state, &plane->base))))
+			      to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
 
 void intel_link_compute_m_n(u16 bpp, int nlanes,
 			    int pixel_clock, int link_clock,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 244e881474fb..4d85ea5832d7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -749,7 +749,32 @@ enum intel_output_format {
 };
 
 struct intel_crtc_state {
+	union {
 	struct drm_crtc_state base;
+	/*
+	 * uapi (drm) state. This is the software state shown to userspace.
+	 * In particular, the following members are used for bookkeeping:
+	 * - crtc
+	 * - state
+	 * - *_changed
+	 * - event
+	 * - commit
+	 * - mode_blob
+	 */
+	struct drm_crtc_state uapi;
+
+	/*
+	 * actual hardware state, the state we program to the hardware.
+	 * The following members are used to verify the hardware state:
+	 * - enable
+	 * - active
+	 * - mode / adjusted_mode
+	 * - color property blobs.
+	 *
+	 * During initial hw readout, they need to be copied to uapi.
+	 */
+	struct drm_crtc_state hw;
+	};
 
 	/**
 	 * quirks - bitfield with hw state readout quirks
@@ -1094,7 +1119,7 @@ struct cxsr_latency {
 
 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
-#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
+#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH 05/14] drm/i915: Perform manual conversions for crtc uapi/hw split
  2019-10-17 13:20 [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Maarten Lankhorst
                   ` (2 preceding siblings ...)
  2019-10-17 13:20 ` [PATCH 04/14] drm/i915: Add aliases for uapi and hw to crtc_state Maarten Lankhorst
@ 2019-10-17 13:20 ` Maarten Lankhorst
  2019-10-18  8:11   ` Maarten Lankhorst
  2019-10-18  8:13   ` [PATCH] drm/i915: Perform manual conversions for crtc uapi/hw split, v2 Maarten Lankhorst
  2019-10-17 13:20 ` [PATCH 06/14] drm/i915: Perform automated conversions for crtc uapi/hw split, base -> hw Maarten Lankhorst
                   ` (15 subsequent siblings)
  19 siblings, 2 replies; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-17 13:20 UTC (permalink / raw)
  To: intel-gfx

intel_get_load_detect_pipe() needs to set uapi active,
uapi enable is set by the call to drm_atomic_set_mode_for_crtc(),
so we can remove it.

intel_pipe_config_compare() needs to look at hw state, but I didn't
change spatch to look at it. It's easy enough to do manually.

intel_atomic_check() definitely needs to check for uapi enable,
otherwise intel_modeset_pipe_config cannot copy uapi state to hw.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 42 ++++++++++----------
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index fa0abfdff2ae..adb70d76a61c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11214,7 +11214,7 @@ int intel_get_load_detect_pipe(struct drm_connector *connector,
 		goto fail;
 	}
 
-	crtc_state->base.active = crtc_state->base.enable = true;
+	crtc_state->hw.active = true;
 
 	if (!mode)
 		mode = &load_detect_mode;
@@ -12754,19 +12754,19 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
 	PIPE_CONF_CHECK_X(output_types);
 
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
 
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
 
 	PIPE_CONF_CHECK_I(pixel_multiplier);
 	PIPE_CONF_CHECK_I(output_format);
@@ -12783,17 +12783,17 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
 	PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
 
-	PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+	PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
 			      DRM_MODE_FLAG_INTERLACE);
 
 	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
-		PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
 				      DRM_MODE_FLAG_PHSYNC);
-		PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
 				      DRM_MODE_FLAG_NHSYNC);
-		PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
 				      DRM_MODE_FLAG_PVSYNC);
-		PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
 				      DRM_MODE_FLAG_NVSYNC);
 	}
 
@@ -12832,7 +12832,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
 		bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
 		if (bp_gamma)
-			PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, base.gamma_lut, bp_gamma);
+			PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
 
 	}
 
@@ -12877,7 +12877,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
 		PIPE_CONF_CHECK_I(pipe_bpp);
 
-	PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
+	PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
 	PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
 
 	PIPE_CONF_CHECK_I(min_voltage_level);
@@ -13572,7 +13572,7 @@ static int intel_atomic_check(struct drm_device *dev,
 		if (!needs_modeset(new_crtc_state))
 			continue;
 
-		if (!new_crtc_state->base.enable) {
+		if (!new_crtc_state->uapi.enable) {
 			any_ms = true;
 			continue;
 		}
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH 06/14] drm/i915: Perform automated conversions for crtc uapi/hw split, base -> hw.
  2019-10-17 13:20 [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Maarten Lankhorst
                   ` (3 preceding siblings ...)
  2019-10-17 13:20 ` [PATCH 05/14] drm/i915: Perform manual conversions for crtc uapi/hw split Maarten Lankhorst
@ 2019-10-17 13:20 ` Maarten Lankhorst
  2019-10-18 12:59   ` Ville Syrjälä
  2019-10-17 13:20 ` [PATCH 07/14] drm/i915: Perform automated conversions for crtc uapi/hw split, base -> uapi Maarten Lankhorst
                   ` (14 subsequent siblings)
  19 siblings, 1 reply; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-17 13:20 UTC (permalink / raw)
  To: intel-gfx

Split up crtc_state->base to hw where appropriate. This is done using the following patch:

@@
struct intel_crtc_state *T;
identifier x =~ "^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
@@
-T->base.x
+T->hw.x

@@
struct drm_crtc_state *T;
identifier x =~ "^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
@@
-to_intel_crtc_state(T)->base.x
+to_intel_crtc_state(T)->hw.x

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c        |  12 +-
 drivers/gpu/drm/i915/display/intel_audio.c    |   4 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |   8 +-
 drivers/gpu/drm/i915/display/intel_color.c    | 108 ++++----
 drivers/gpu/drm/i915/display/intel_crt.c      |  18 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  18 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 252 +++++++++---------
 drivers/gpu/drm/i915/display/intel_dp.c       |  22 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   6 +-
 drivers/gpu/drm/i915/display/intel_dvo.c      |  12 +-
 drivers/gpu/drm/i915/display/intel_fbc.c      |   2 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     |  20 +-
 drivers/gpu/drm/i915/display/intel_lspcon.c   |   4 +-
 drivers/gpu/drm/i915/display/intel_lvds.c     |   8 +-
 drivers/gpu/drm/i915/display/intel_panel.c    |   8 +-
 drivers/gpu/drm/i915/display/intel_pipe_crc.c |   2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |  12 +-
 drivers/gpu/drm/i915/display/intel_sdvo.c     |  16 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |   8 +-
 drivers/gpu/drm/i915/display/intel_tv.c       |   4 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     |   4 +-
 drivers/gpu/drm/i915/display/vlv_dsi.c        |  10 +-
 drivers/gpu/drm/i915/i915_debugfs.c           |   8 +-
 drivers/gpu/drm/i915/intel_pm.c               |  62 ++---
 24 files changed, 316 insertions(+), 312 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 6e398c33a524..4ec493e4755b 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -276,7 +276,7 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
 
 	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 		const struct drm_display_mode *adjusted_mode =
-					&pipe_config->base.adjusted_mode;
+					&pipe_config->hw.adjusted_mode;
 		u32 dss_ctl2;
 		u16 hactive = adjusted_mode->crtc_hdisplay;
 		u16 dl_buffer_depth;
@@ -768,7 +768,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	const struct drm_display_mode *adjusted_mode =
-					&pipe_config->base.adjusted_mode;
+					&pipe_config->hw.adjusted_mode;
 	enum port port;
 	enum transcoder dsi_trans;
 	/* horizontal timings */
@@ -1216,7 +1216,7 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
 {
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	struct drm_display_mode *adjusted_mode =
-					&pipe_config->base.adjusted_mode;
+					&pipe_config->hw.adjusted_mode;
 
 	if (intel_dsi->dual_link) {
 		adjusted_mode->crtc_hdisplay *= 2;
@@ -1249,9 +1249,9 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
 	pipe_config->port_clock =
 		cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
 
-	pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
+	pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
 	if (intel_dsi->dual_link)
-		pipe_config->base.adjusted_mode.crtc_clock *= 2;
+		pipe_config->hw.adjusted_mode.crtc_clock *= 2;
 
 	gen11_dsi_get_timings(encoder, pipe_config);
 	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
@@ -1269,7 +1269,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 	const struct drm_display_mode *fixed_mode =
 					intel_connector->panel.fixed_mode;
 	struct drm_display_mode *adjusted_mode =
-					&pipe_config->base.adjusted_mode;
+					&pipe_config->hw.adjusted_mode;
 
 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 	intel_fixed_panel_mode(fixed_mode, adjusted_mode);
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index ed18511befa3..6a58e8ad86f8 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -233,7 +233,7 @@ static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
 {
 	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->base.adjusted_mode;
+		&crtc_state->hw.adjusted_mode;
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
@@ -694,7 +694,7 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_connector *connector = conn_state->connector;
 	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->base.adjusted_mode;
+		&crtc_state->hw.adjusted_mode;
 	enum port port = encoder->port;
 	enum pipe pipe = crtc->pipe;
 
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ab1f7cec50c6..fd1ed0fb8748 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1924,7 +1924,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 		to_i915(crtc_state->base.crtc->dev);
 	int min_cdclk;
 
-	if (!crtc_state->base.enable)
+	if (!crtc_state->hw.enable)
 		return 0;
 
 	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
@@ -2047,7 +2047,7 @@ static u8 bxt_compute_min_voltage_level(struct intel_atomic_state *state)
 	       sizeof(state->min_voltage_level));
 
 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
-		if (crtc_state->base.enable)
+		if (crtc_state->hw.enable)
 			state->min_voltage_level[i] =
 				crtc_state->min_voltage_level;
 		else
@@ -2133,7 +2133,7 @@ static int skl_dpll0_vco(struct intel_atomic_state *state)
 		vco = dev_priv->skl_preferred_vco_freq;
 
 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
-		if (!crtc_state->base.enable)
+		if (!crtc_state->hw.enable)
 			continue;
 
 		if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
@@ -2260,7 +2260,7 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
 		if (IS_ERR(crtc_state))
 			return PTR_ERR(crtc_state);
 
-		if (!crtc_state->base.active ||
+		if (!crtc_state->hw.active ||
 		    drm_atomic_crtc_needs_modeset(&crtc_state->base))
 			continue;
 
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 95586a588234..65e1b18bd7e3 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -117,10 +117,10 @@ static bool lut_is_legacy(const struct drm_property_blob *lut)
 
 static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state)
 {
-	return !crtc_state->base.degamma_lut &&
-		!crtc_state->base.ctm &&
-		crtc_state->base.gamma_lut &&
-		lut_is_legacy(crtc_state->base.gamma_lut);
+	return !crtc_state->hw.degamma_lut &&
+		!crtc_state->hw.ctm &&
+		crtc_state->hw.gamma_lut &&
+		lut_is_legacy(crtc_state->hw.gamma_lut);
 }
 
 /*
@@ -219,7 +219,7 @@ static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
 static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
 				u16 coeffs[9])
 {
-	const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
+	const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
 	const u64 *input;
 	u64 temp[9];
 	int i;
@@ -274,7 +274,7 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	bool limited_color_range = ilk_csc_limited_range(crtc_state);
 
-	if (crtc_state->base.ctm) {
+	if (crtc_state->hw.ctm) {
 		u16 coeff[9];
 
 		ilk_csc_convert_ctm(crtc_state, coeff);
@@ -312,7 +312,7 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-	if (crtc_state->base.ctm) {
+	if (crtc_state->hw.ctm) {
 		u16 coeff[9];
 
 		ilk_csc_convert_ctm(crtc_state, coeff);
@@ -342,8 +342,8 @@ static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
-	if (crtc_state->base.ctm) {
-		const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
+	if (crtc_state->hw.ctm) {
+		const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
 		u16 coeffs[9] = {};
 		int i;
 
@@ -435,7 +435,7 @@ static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
 
 static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
 {
-	i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
+	i9xx_load_luts_internal(crtc_state, crtc_state->hw.gamma_lut);
 }
 
 static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
@@ -525,7 +525,7 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc,
 static void i965_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
+	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
 		i9xx_load_luts(crtc_state);
@@ -548,7 +548,7 @@ static void ilk_load_lut_10(struct intel_crtc *crtc,
 static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
+	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
 		i9xx_load_luts(crtc_state);
@@ -655,8 +655,8 @@ static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
 static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
-	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
+	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
 		i9xx_load_luts(crtc_state);
@@ -678,8 +678,8 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
 static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
-	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
+	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
 		i9xx_load_luts(crtc_state);
@@ -704,7 +704,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
-	const struct drm_color_lut *lut = crtc_state->base.degamma_lut->data;
+	const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
 	u32 i;
 
 	/*
@@ -766,7 +766,7 @@ static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_stat
 
 static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 {
-	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
+	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 
 	/*
@@ -777,7 +777,7 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 	 * the degama LUT so that we don't have to reload
 	 * it every time the pipe CSC is being enabled.
 	 */
-	if (crtc_state->base.degamma_lut)
+	if (crtc_state->hw.degamma_lut)
 		glk_load_degamma_lut(crtc_state);
 	else
 		glk_load_degamma_lut_linear(crtc_state);
@@ -823,7 +823,7 @@ static void
 icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-	const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
+	const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
 	const struct drm_color_lut *lut = blob->data;
 	struct intel_dsb *dsb = intel_dsb_get(crtc);
 	enum pipe pipe = crtc->pipe;
@@ -855,7 +855,7 @@ static void
 icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-	const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
+	const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
 	const struct drm_color_lut *lut = blob->data;
 	const struct drm_color_lut *entry;
 	struct intel_dsb *dsb = intel_dsb_get(crtc);
@@ -910,11 +910,11 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
 
 static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 {
-	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
+	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct intel_dsb *dsb = intel_dsb_get(crtc);
 
-	if (crtc_state->base.degamma_lut)
+	if (crtc_state->hw.degamma_lut)
 		glk_load_degamma_lut(crtc_state);
 
 	switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
@@ -991,8 +991,8 @@ static void chv_load_cgm_gamma(struct intel_crtc *crtc,
 static void chv_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
-	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
+	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 
 	cherryview_load_csc_matrix(crtc_state);
 
@@ -1063,7 +1063,7 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
 		intel_atomic_get_old_crtc_state(state, crtc);
 	struct intel_plane *plane;
 
-	if (!new_crtc_state->base.active ||
+	if (!new_crtc_state->hw.active ||
 	    drm_atomic_crtc_needs_modeset(&new_crtc_state->base))
 		return 0;
 
@@ -1108,8 +1108,8 @@ static int check_lut_size(const struct drm_property_blob *lut, int expected)
 static int check_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
-	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
-	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
+	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 	int gamma_length, degamma_length;
 	u32 gamma_tests, degamma_tests;
 
@@ -1157,7 +1157,7 @@ static int i9xx_color_check(struct intel_crtc_state *crtc_state)
 		return ret;
 
 	crtc_state->gamma_enable =
-		crtc_state->base.gamma_lut &&
+		crtc_state->hw.gamma_lut &&
 		!crtc_state->c8_planes;
 
 	crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
@@ -1176,11 +1176,11 @@ static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
 	if (crtc_state_is_legacy_gamma(crtc_state))
 		return 0;
 
-	if (crtc_state->base.degamma_lut)
+	if (crtc_state->hw.degamma_lut)
 		cgm_mode |= CGM_PIPE_MODE_DEGAMMA;
-	if (crtc_state->base.ctm)
+	if (crtc_state->hw.ctm)
 		cgm_mode |= CGM_PIPE_MODE_CSC;
-	if (crtc_state->base.gamma_lut)
+	if (crtc_state->hw.gamma_lut)
 		cgm_mode |= CGM_PIPE_MODE_GAMMA;
 
 	return cgm_mode;
@@ -1254,7 +1254,7 @@ static int ilk_color_check(struct intel_crtc_state *crtc_state)
 		return ret;
 
 	crtc_state->gamma_enable =
-		crtc_state->base.gamma_lut &&
+		crtc_state->hw.gamma_lut &&
 		!crtc_state->c8_planes;
 
 	/*
@@ -1280,8 +1280,8 @@ static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)
 	if (!crtc_state->gamma_enable ||
 	    crtc_state_is_legacy_gamma(crtc_state))
 		return GAMMA_MODE_MODE_8BIT;
-	else if (crtc_state->base.gamma_lut &&
-		 crtc_state->base.degamma_lut)
+	else if (crtc_state->hw.gamma_lut &&
+		 crtc_state->hw.degamma_lut)
 		return GAMMA_MODE_MODE_SPLIT;
 	else
 		return GAMMA_MODE_MODE_10BIT;
@@ -1295,7 +1295,7 @@ static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
 	 * CSC comes after the LUT in degamma, RGB->YCbCr,
 	 * and RGB full->limited range mode.
 	 */
-	if (crtc_state->base.degamma_lut ||
+	if (crtc_state->hw.degamma_lut ||
 	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
 	    limited_color_range)
 		return 0;
@@ -1313,13 +1313,13 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state)
 		return ret;
 
 	crtc_state->gamma_enable =
-		(crtc_state->base.gamma_lut ||
-		 crtc_state->base.degamma_lut) &&
+		(crtc_state->hw.gamma_lut ||
+		 crtc_state->hw.degamma_lut) &&
 		!crtc_state->c8_planes;
 
 	crtc_state->csc_enable =
 		crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
-		crtc_state->base.ctm || limited_color_range;
+		crtc_state->hw.ctm || limited_color_range;
 
 	crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);
 
@@ -1350,14 +1350,14 @@ static int glk_color_check(struct intel_crtc_state *crtc_state)
 		return ret;
 
 	crtc_state->gamma_enable =
-		crtc_state->base.gamma_lut &&
+		crtc_state->hw.gamma_lut &&
 		!crtc_state->c8_planes;
 
 	/* On GLK+ degamma LUT is controlled by csc_enable */
 	crtc_state->csc_enable =
-		crtc_state->base.degamma_lut ||
+		crtc_state->hw.degamma_lut ||
 		crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
-		crtc_state->base.ctm || crtc_state->limited_color_range;
+		crtc_state->hw.ctm || crtc_state->limited_color_range;
 
 	crtc_state->gamma_mode = glk_gamma_mode(crtc_state);
 
@@ -1374,14 +1374,14 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
 {
 	u32 gamma_mode = 0;
 
-	if (crtc_state->base.degamma_lut)
+	if (crtc_state->hw.degamma_lut)
 		gamma_mode |= PRE_CSC_GAMMA_ENABLE;
 
-	if (crtc_state->base.gamma_lut &&
+	if (crtc_state->hw.gamma_lut &&
 	    !crtc_state->c8_planes)
 		gamma_mode |= POST_CSC_GAMMA_ENABLE;
 
-	if (!crtc_state->base.gamma_lut ||
+	if (!crtc_state->hw.gamma_lut ||
 	    crtc_state_is_legacy_gamma(crtc_state))
 		gamma_mode |= GAMMA_MODE_MODE_8BIT;
 	else
@@ -1394,7 +1394,7 @@ static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)
 {
 	u32 csc_mode = 0;
 
-	if (crtc_state->base.ctm)
+	if (crtc_state->hw.ctm)
 		csc_mode |= ICL_CSC_ENABLE;
 
 	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
@@ -1623,7 +1623,7 @@ static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
 	if (!crtc_state->gamma_enable)
 		return;
 
-	crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+	crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
 }
 
 static struct drm_property_blob *
@@ -1673,9 +1673,9 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
 	else
-		crtc_state->base.gamma_lut = i965_read_lut_10p6(crtc_state);
+		crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc_state);
 }
 
 static struct drm_property_blob *
@@ -1715,7 +1715,7 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
 static void chv_read_luts(struct intel_crtc_state *crtc_state)
 {
 	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
-		crtc_state->base.gamma_lut = chv_read_cgm_lut(crtc_state);
+		crtc_state->hw.gamma_lut = chv_read_cgm_lut(crtc_state);
 	else
 		i965_read_luts(crtc_state);
 }
@@ -1762,9 +1762,9 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
 	else
-		crtc_state->base.gamma_lut = ilk_read_lut_10(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc_state);
 }
 
 static struct drm_property_blob *
@@ -1811,9 +1811,9 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
 	else
-		crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
+		crtc_state->hw.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
 }
 
 void intel_color_init(struct intel_crtc *crtc)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index ff6126ea793c..399abc3d521e 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -132,9 +132,9 @@ static void intel_crt_get_config(struct intel_encoder *encoder,
 {
 	pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
 
-	pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
+	pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 
-	pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
+	pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
 }
 
 static void hsw_crt_get_config(struct intel_encoder *encoder,
@@ -144,13 +144,13 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
 
 	intel_ddi_get_config(encoder, pipe_config);
 
-	pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
+	pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
 					      DRM_MODE_FLAG_NHSYNC |
 					      DRM_MODE_FLAG_PVSYNC |
 					      DRM_MODE_FLAG_NVSYNC);
-	pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
+	pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 
-	pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
+	pipe_config->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
 }
 
 /* Note: The caller is required to filter out dpms modes not supported by the
@@ -162,7 +162,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_crt *crt = intel_encoder_to_crt(encoder);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-	const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	u32 adpa;
 
 	if (INTEL_GEN(dev_priv) >= 5)
@@ -358,7 +358,7 @@ static int intel_crt_compute_config(struct intel_encoder *encoder,
 				    struct drm_connector_state *conn_state)
 {
 	struct drm_display_mode *adjusted_mode =
-		&pipe_config->base.adjusted_mode;
+		&pipe_config->hw.adjusted_mode;
 
 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return -EINVAL;
@@ -373,7 +373,7 @@ static int pch_crt_compute_config(struct intel_encoder *encoder,
 				  struct drm_connector_state *conn_state)
 {
 	struct drm_display_mode *adjusted_mode =
-		&pipe_config->base.adjusted_mode;
+		&pipe_config->hw.adjusted_mode;
 
 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return -EINVAL;
@@ -390,7 +390,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct drm_display_mode *adjusted_mode =
-		&pipe_config->base.adjusted_mode;
+		&pipe_config->hw.adjusted_mode;
 
 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 		return -EINVAL;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4c81449ec144..c8639b92a6da 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1528,7 +1528,7 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 	if (pipe_config->pixel_multiplier)
 		dotclock /= pipe_config->pixel_multiplier;
 
-	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
+	pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
 }
 
 static void icl_ddi_clock_get(struct intel_encoder *encoder,
@@ -1860,9 +1860,9 @@ intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
 		BUG();
 	}
 
-	if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
+	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
 		temp |= TRANS_DDI_PVSYNC;
-	if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
+	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
 		temp |= TRANS_DDI_PHSYNC;
 
 	if (cpu_transcoder == TRANSCODER_EDP) {
@@ -3371,7 +3371,7 @@ static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
 {
 	u32 exit_scanlines;
 	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
-	u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay;
+	u32 crtc_vdisplay = cstate->hw.adjusted_mode.crtc_vdisplay;
 
 	cstate->dc3co_exitline = 0;
 
@@ -3383,7 +3383,7 @@ static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
 	    encoder->port != PORT_A)
 		return;
 
-	if (!cstate->has_psr2 || !cstate->base.active)
+	if (!cstate->has_psr2 || !cstate->hw.active)
 		return;
 
 	/*
@@ -3391,7 +3391,7 @@ static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
 	 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
 	 */
 	exit_scanlines =
-		intel_usecs_to_scanlines(&cstate->base.adjusted_mode, 200) + 1;
+		intel_usecs_to_scanlines(&cstate->hw.adjusted_mode, 200) + 1;
 
 	if (WARN_ON(exit_scanlines > crtc_vdisplay))
 		return;
@@ -4076,7 +4076,7 @@ intel_ddi_update_prepare(struct intel_atomic_state *state,
 	WARN_ON(crtc && crtc->active);
 
 	intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes);
-	if (crtc_state && crtc_state->base.active)
+	if (crtc_state && crtc_state->hw.active)
 		intel_update_active_dpll(state, crtc, encoder);
 }
 
@@ -4224,7 +4224,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 	else
 		flags |= DRM_MODE_FLAG_NVSYNC;
 
-	pipe_config->base.adjusted_mode.flags |= flags;
+	pipe_config->hw.adjusted_mode.flags |= flags;
 
 	switch (temp & TRANS_DDI_BPC_MASK) {
 	case TRANS_DDI_BPC_6:
@@ -4507,7 +4507,7 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder,
 
 	WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
 
-	if (!crtc_state->base.active)
+	if (!crtc_state->hw.active)
 		return 0;
 
 	if (!crtc_state->hdmi_high_tmds_clock_ratio &&
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index adb70d76a61c..3106aaf55f17 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1013,7 +1013,7 @@ bool intel_crtc_active(struct intel_crtc *crtc)
 	 * for atomic.
 	 */
 	return crtc->active && crtc->base.primary->state->fb &&
-		crtc->config->base.adjusted_mode.crtc_clock;
+		crtc->config->hw.adjusted_mode.crtc_clock;
 }
 
 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
@@ -4951,7 +4951,7 @@ static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int clock = crtc_state->base.adjusted_mode.crtc_clock;
+	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
 	u32 divsel, phaseinc, auxdiv, phasedir = 0;
 	u32 temp;
 
@@ -5224,7 +5224,7 @@ static void ironlake_pch_enable(const struct intel_atomic_state *state,
 	if (HAS_PCH_CPT(dev_priv) &&
 	    intel_crtc_has_dp_encoder(crtc_state)) {
 		const struct drm_display_mode *adjusted_mode =
-			&crtc_state->base.adjusted_mode;
+			&crtc_state->hw.adjusted_mode;
 		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
 		i915_reg_t reg = TRANS_DP_CTL(pipe);
 		enum port port;
@@ -5374,7 +5374,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 		to_intel_crtc(crtc_state->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
 	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->base.adjusted_mode;
+		&crtc_state->hw.adjusted_mode;
 
 	/*
 	 * Src coordinates are already rotated by 270 degrees for
@@ -5390,7 +5390,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 	 * Once NV12 is enabled, handle it here while allocating scaler
 	 * for NV12.
 	 */
-	if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
+	if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
 	    need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 		DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
 		return -EINVAL;
@@ -5462,13 +5462,13 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
  */
 int skl_update_scaler_crtc(struct intel_crtc_state *state)
 {
-	const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
+	const struct drm_display_mode *adjusted_mode = &state->hw.adjusted_mode;
 	bool need_scaler = false;
 
 	if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 		need_scaler = true;
 
-	return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
+	return skl_update_scaler(state, !state->hw.active, SKL_CRTC_INDEX,
 				 &state->scaler_state.scaler_id,
 				 state->pipe_src_w, state->pipe_src_h,
 				 adjusted_mode->crtc_hdisplay,
@@ -5820,7 +5820,7 @@ static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_s
 	 * forcibly enable IPS on the first fastset.
 	 */
 	if (new_crtc_state->update_pipe &&
-	    old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
+	    old_crtc_state->hw.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
 		return true;
 
 	return !old_crtc_state->ips_enabled;
@@ -5864,7 +5864,7 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 
 	intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
 
-	if (pipe_config->update_wm_post && pipe_config->base.active)
+	if (pipe_config->update_wm_post && pipe_config->hw.active)
 		intel_update_watermarks(crtc);
 
 	if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
@@ -5942,7 +5942,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 	 * event which is after the vblank start event, so we need to have a
 	 * wait-for-vblank between disabling the plane and the pipe.
 	 */
-	if (HAS_GMCH(dev_priv) && old_crtc_state->base.active &&
+	if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
 	    pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
 		intel_wait_for_vblank(dev_priv, crtc->pipe);
 
@@ -5954,7 +5954,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 	 * WaCxSRDisabledForSpriteScaling:ivb
 	 */
 	if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
-	    old_crtc_state->base.active)
+	    old_crtc_state->hw.active)
 		intel_wait_for_vblank(dev_priv, crtc->pipe);
 
 	/*
@@ -6752,7 +6752,7 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
 	u64 mask;
 	enum transcoder transcoder = crtc_state->cpu_transcoder;
 
-	if (!crtc_state->base.active)
+	if (!crtc_state->hw.active)
 		return 0;
 
 	mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
@@ -7109,8 +7109,8 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
 		if (!crtc_state)
 			return;
 
-		I915_STATE_WARN(!crtc_state->base.active,
-		      "connector is active, but attached crtc isn't\n");
+		I915_STATE_WARN(!crtc_state->hw.active,
+				"connector is active, but attached crtc isn't\n");
 
 		if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
 			return;
@@ -7121,8 +7121,8 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
 		I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
 			"attached encoder crtc differs from connector crtc\n");
 	} else {
-		I915_STATE_WARN(crtc_state && crtc_state->base.active,
-			"attached crtc is active, but connector isn't\n");
+		I915_STATE_WARN(crtc_state && crtc_state->hw.active,
+				"attached crtc is active, but connector isn't\n");
 		I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
 			"best encoder set without crtc!\n");
 	}
@@ -7130,7 +7130,7 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
 
 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
 {
-	if (crtc_state->base.enable && crtc_state->has_pch_encoder)
+	if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
 		return crtc_state->fdi_lanes;
 
 	return 0;
@@ -7213,7 +7213,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
 				       struct intel_crtc_state *pipe_config)
 {
 	struct drm_device *dev = intel_crtc->base.dev;
-	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	int lane, link_bw, fdi_dotclock, ret;
 	bool needs_recompute = false;
 
@@ -7330,7 +7330,7 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
 {
 	u32 pixel_rate;
 
-	pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
+	pixel_rate = pipe_config->hw.adjusted_mode.crtc_clock;
 
 	/*
 	 * We only use IF-ID interlacing. If we ever use
@@ -7368,7 +7368,7 @@ static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
 	if (HAS_GMCH(dev_priv))
 		/* FIXME calculate proper pipe pixel rate for GMCH pfit */
 		crtc_state->pixel_rate =
-			crtc_state->base.adjusted_mode.crtc_clock;
+			crtc_state->hw.adjusted_mode.crtc_clock;
 	else
 		crtc_state->pixel_rate =
 			ilk_pipe_pixel_rate(crtc_state);
@@ -7378,7 +7378,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
 				     struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	int clock_limit = dev_priv->max_dotclk_freq;
 
 	if (INTEL_GEN(dev_priv) < 4) {
@@ -7404,7 +7404,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
 
 	if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
 	     pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
-	     pipe_config->base.ctm) {
+	     pipe_config->hw.ctm) {
 		/*
 		 * There is only one pipe CSC unit per pipe, and we need that
 		 * for output conversion from RGB->YCBCR. So if CTM is already
@@ -8102,7 +8102,7 @@ static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-	const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	u32 crtc_vtotal, crtc_vblank_end;
 	int vsyncshift = 0;
 
@@ -8196,39 +8196,39 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
 	u32 tmp;
 
 	tmp = I915_READ(HTOTAL(cpu_transcoder));
-	pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
-	pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
+	pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
+	pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
 
 	if (!transcoder_is_dsi(cpu_transcoder)) {
 		tmp = I915_READ(HBLANK(cpu_transcoder));
-		pipe_config->base.adjusted_mode.crtc_hblank_start =
+		pipe_config->hw.adjusted_mode.crtc_hblank_start =
 							(tmp & 0xffff) + 1;
-		pipe_config->base.adjusted_mode.crtc_hblank_end =
+		pipe_config->hw.adjusted_mode.crtc_hblank_end =
 						((tmp >> 16) & 0xffff) + 1;
 	}
 	tmp = I915_READ(HSYNC(cpu_transcoder));
-	pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
-	pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
+	pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
+	pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
 
 	tmp = I915_READ(VTOTAL(cpu_transcoder));
-	pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
-	pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
+	pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
+	pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
 
 	if (!transcoder_is_dsi(cpu_transcoder)) {
 		tmp = I915_READ(VBLANK(cpu_transcoder));
-		pipe_config->base.adjusted_mode.crtc_vblank_start =
+		pipe_config->hw.adjusted_mode.crtc_vblank_start =
 							(tmp & 0xffff) + 1;
-		pipe_config->base.adjusted_mode.crtc_vblank_end =
+		pipe_config->hw.adjusted_mode.crtc_vblank_end =
 						((tmp >> 16) & 0xffff) + 1;
 	}
 	tmp = I915_READ(VSYNC(cpu_transcoder));
-	pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
-	pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
+	pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
+	pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
 
 	if (intel_pipe_is_interlaced(pipe_config)) {
-		pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
-		pipe_config->base.adjusted_mode.crtc_vtotal += 1;
-		pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
+		pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
+		pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
+		pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
 	}
 }
 
@@ -8243,27 +8243,27 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
 	pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
 	pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
 
-	pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
-	pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
+	pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
+	pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
 }
 
 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 				 struct intel_crtc_state *pipe_config)
 {
-	mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
-	mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
-	mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
-	mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
+	mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
+	mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
+	mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
+	mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
 
-	mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
-	mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
-	mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
-	mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
+	mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
+	mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
+	mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
+	mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
 
-	mode->flags = pipe_config->base.adjusted_mode.flags;
+	mode->flags = pipe_config->hw.adjusted_mode.flags;
 	mode->type = DRM_MODE_TYPE_DRIVER;
 
-	mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
+	mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
 
 	mode->hsync = drm_mode_hsync(mode);
 	mode->vrefresh = drm_mode_vrefresh(mode);
@@ -8309,7 +8309,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
 		}
 	}
 
-	if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
 		if (INTEL_GEN(dev_priv) < 4 ||
 		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
 			pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
@@ -8841,7 +8841,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 	 * but in case the pipe is enabled w/o any ports we need a sane
 	 * default.
 	 */
-	pipe_config->base.adjusted_mode.crtc_clock =
+	pipe_config->hw.adjusted_mode.crtc_clock =
 		pipe_config->port_clock / pipe_config->pixel_multiplier;
 
 	ret = true;
@@ -9384,7 +9384,7 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->dither)
 		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
 
-	if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
 		val |= PIPECONF_INTERLACED_ILK;
 	else
 		val |= PIPECONF_PROGRESSIVE;
@@ -9418,7 +9418,7 @@ static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
 	if (IS_HASWELL(dev_priv) && crtc_state->dither)
 		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
 
-	if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
 		val |= PIPECONF_INTERLACED_ILK;
 	else
 		val |= PIPECONF_PROGRESSIVE;
@@ -11427,7 +11427,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 	 * we may need some idea for the dotclock anyway.
 	 * Calculate one based on the FDI configuration.
 	 */
-	pipe_config->base.adjusted_mode.crtc_clock =
+	pipe_config->hw.adjusted_mode.crtc_clock =
 		intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
 					 &pipe_config->fdi_m_n);
 }
@@ -11532,8 +11532,8 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	bool mode_changed = needs_modeset(crtc_state);
-	bool was_crtc_enabled = old_crtc_state->base.active;
-	bool is_crtc_enabled = crtc_state->base.active;
+	bool was_crtc_enabled = old_crtc_state->hw.active;
+	bool is_crtc_enabled = crtc_state->hw.active;
 	bool turn_off, turn_on, visible, was_visible;
 	int ret;
 
@@ -11791,10 +11791,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 	int ret;
 
 	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
-	    mode_changed && !crtc_state->base.active)
+	    mode_changed && !crtc_state->hw.active)
 		crtc_state->update_wm_post = true;
 
-	if (mode_changed && crtc_state->base.enable &&
+	if (mode_changed && crtc_state->hw.enable &&
 	    dev_priv->display.crtc_compute_clock &&
 	    !WARN_ON(crtc_state->shared_dpll)) {
 		ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
@@ -12090,14 +12090,14 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 
 	DRM_DEBUG_KMS("[CRTC:%d:%s] enable: %s %s\n",
 		      crtc->base.base.id, crtc->base.name,
-		      yesno(pipe_config->base.enable), context);
+		      yesno(pipe_config->hw.enable), context);
 
-	if (!pipe_config->base.enable)
+	if (!pipe_config->hw.enable)
 		goto dump_planes;
 
 	snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
 	DRM_DEBUG_KMS("active: %s, output_types: %s (0x%x), output format: %s\n",
-		      yesno(pipe_config->base.active),
+		      yesno(pipe_config->hw.active),
 		      buf, pipe_config->output_types,
 		      output_formats(pipe_config->output_format));
 
@@ -12137,10 +12137,10 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
 
 	DRM_DEBUG_KMS("requested mode:\n");
-	drm_mode_debug_printmodeline(&pipe_config->base.mode);
+	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
 	DRM_DEBUG_KMS("adjusted mode:\n");
-	drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
-	intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
+	drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
+	intel_dump_crtc_timings(&pipe_config->hw.adjusted_mode);
 	DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
 		      pipe_config->port_clock,
 		      pipe_config->pipe_src_w, pipe_config->pipe_src_h,
@@ -12315,13 +12315,13 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
 	 * positive or negative polarity is requested, treat this as meaning
 	 * negative polarity.
 	 */
-	if (!(pipe_config->base.adjusted_mode.flags &
+	if (!(pipe_config->hw.adjusted_mode.flags &
 	      (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
-		pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
+		pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
 
-	if (!(pipe_config->base.adjusted_mode.flags &
+	if (!(pipe_config->hw.adjusted_mode.flags &
 	      (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
-		pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
+		pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
 
 	ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
 					pipe_config);
@@ -12338,7 +12338,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
 	 * computation to clearly distinguish it from the adjusted mode, which
 	 * can be changed by the connectors in the below retry loop.
 	 */
-	drm_mode_get_hv_timing(&pipe_config->base.mode,
+	drm_mode_get_hv_timing(&pipe_config->hw.mode,
 			       &pipe_config->pipe_src_w,
 			       &pipe_config->pipe_src_h);
 
@@ -12371,7 +12371,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
 	pipe_config->pixel_multiplier = 1;
 
 	/* Fill in default crtc timings, allow encoders to overwrite them. */
-	drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
+	drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
 			      CRTC_STEREO_DOUBLE);
 
 	/* Pass our mode to the connectors and the CRTC to give them a chance to
@@ -12396,7 +12396,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
 	/* Set default port clock if not overwritten by the encoder. Needs to be
 	 * done afterwards in case the encoder adjusts the mode. */
 	if (!pipe_config->port_clock)
-		pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
+		pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
 			* pipe_config->pixel_multiplier;
 
 	ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
@@ -12564,8 +12564,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	bool ret = true;
 	u32 bp_gamma = 0;
 	bool fixup_inherited = fastset &&
-		(current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
-		!(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
+		(current_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
+		!(pipe_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED);
 
 	if (fixup_inherited && !fastboot_enabled(dev_priv)) {
 		DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
@@ -12908,7 +12908,7 @@ static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
 	if (pipe_config->has_pch_encoder) {
 		int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
 							    &pipe_config->fdi_m_n);
-		int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
+		int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
 
 		/*
 		 * FDI already provided one idea for the dotclock.
@@ -12937,7 +12937,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
 	int level, max_level = ilk_wm_max_level(dev_priv);
 	struct intel_plane *plane;
 
-	if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->base.active)
+	if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
 		return;
 
 	hw = kzalloc(sizeof(*hw), GFP_KERNEL);
@@ -13121,23 +13121,26 @@ verify_crtc_state(struct intel_crtc *crtc,
 
 	/* we keep both pipes enabled on 830 */
 	if (IS_I830(dev_priv))
-		active = new_crtc_state->base.active;
+		active = new_crtc_state->hw.active;
 
-	I915_STATE_WARN(new_crtc_state->base.active != active,
-	     "crtc active state doesn't match with hw state "
-	     "(expected %i, found %i)\n", new_crtc_state->base.active, active);
+	I915_STATE_WARN(new_crtc_state->hw.active != active,
+			"crtc active state doesn't match with hw state "
+			"(expected %i, found %i)\n",
+			new_crtc_state->hw.active, active);
 
-	I915_STATE_WARN(crtc->active != new_crtc_state->base.active,
-	     "transitional active state does not match atomic hw state "
-	     "(expected %i, found %i)\n", new_crtc_state->base.active, crtc->active);
+	I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
+			"transitional active state does not match atomic hw state "
+			"(expected %i, found %i)\n",
+			new_crtc_state->hw.active, crtc->active);
 
 	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
 		enum pipe pipe;
 
 		active = encoder->get_hw_state(encoder, &pipe);
-		I915_STATE_WARN(active != new_crtc_state->base.active,
-			"[ENCODER:%i] active %i with crtc active %i\n",
-			encoder->base.base.id, active, new_crtc_state->base.active);
+		I915_STATE_WARN(active != new_crtc_state->hw.active,
+				"[ENCODER:%i] active %i with crtc active %i\n",
+				encoder->base.base.id, active,
+				new_crtc_state->hw.active);
 
 		I915_STATE_WARN(active && crtc->pipe != pipe,
 				"Encoder connected to wrong pipe %c\n",
@@ -13149,7 +13152,7 @@ verify_crtc_state(struct intel_crtc *crtc,
 
 	intel_crtc_compute_pixel_rate(pipe_config);
 
-	if (!new_crtc_state->base.active)
+	if (!new_crtc_state->hw.active)
 		return;
 
 	intel_pipe_config_sanity_check(dev_priv, pipe_config);
@@ -13211,7 +13214,7 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
 
 	crtc_mask = drm_crtc_mask(&crtc->base);
 
-	if (new_crtc_state->base.active)
+	if (new_crtc_state->hw.active)
 		I915_STATE_WARN(!(pll->active_mask & crtc_mask),
 				"pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
 				pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
@@ -13293,7 +13296,7 @@ intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->base.adjusted_mode;
+		&crtc_state->hw.adjusted_mode;
 
 	drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
 
@@ -13375,7 +13378,7 @@ static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
 
 	/* look at all crtc's that are going to be enabled in during modeset */
 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
-		if (!crtc_state->base.active ||
+		if (!crtc_state->hw.active ||
 		    !needs_modeset(crtc_state))
 			continue;
 
@@ -13400,7 +13403,7 @@ static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
 
 		crtc_state->hsw_workaround_pipe = INVALID_PIPE;
 
-		if (!crtc_state->base.active ||
+		if (!crtc_state->hw.active ||
 		    needs_modeset(crtc_state))
 			continue;
 
@@ -13443,12 +13446,12 @@ static int intel_modeset_checks(struct intel_atomic_state *state)
 
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i) {
-		if (new_crtc_state->base.active)
+		if (new_crtc_state->hw.active)
 			state->active_pipes |= BIT(crtc->pipe);
 		else
 			state->active_pipes &= ~BIT(crtc->pipe);
 
-		if (old_crtc_state->base.active != new_crtc_state->base.active)
+		if (old_crtc_state->hw.active != new_crtc_state->hw.active)
 			state->active_pipe_changes |= BIT(crtc->pipe);
 	}
 
@@ -13558,8 +13561,8 @@ static int intel_atomic_check(struct drm_device *dev,
 	/* Catch I915_MODE_FLAG_INHERITED */
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i) {
-		if (new_crtc_state->base.mode.private_flags !=
-		    old_crtc_state->base.mode.private_flags)
+		if (new_crtc_state->hw.mode.private_flags !=
+		    old_crtc_state->hw.mode.private_flags)
 			new_crtc_state->base.mode_changed = true;
 	}
 
@@ -13688,7 +13691,7 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	/* drm_atomic_helper_update_legacy_modeset_state might not be called. */
-	crtc->base.mode = new_crtc_state->base.mode;
+	crtc->base.mode = new_crtc_state->hw.mode;
 
 	/*
 	 * Update pipe size and adjust fitter if needed: the reason for this is
@@ -13797,7 +13800,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
 	 * of enabling them on the CRTC's first fastset.
 	 */
 	if (new_crtc_state->update_pipe && !modeset &&
-	    old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
+	    old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
 		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
 }
 
@@ -13829,7 +13832,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
 	intel_check_pch_fifo_underruns(dev_priv);
 
 	/* FIXME unify this for all platforms */
-	if (!new_crtc_state->base.active &&
+	if (!new_crtc_state->hw.active &&
 	    !HAS_GMCH(dev_priv) &&
 	    dev_priv->display.initial_watermarks)
 		dev_priv->display.initial_watermarks(state,
@@ -13856,7 +13859,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
 
 		intel_pre_plane_update(old_crtc_state, new_crtc_state);
 
-		if (old_crtc_state->base.active)
+		if (old_crtc_state->hw.active)
 			intel_old_crtc_state_disables(state,
 						      old_crtc_state,
 						      new_crtc_state,
@@ -13871,7 +13874,7 @@ static void intel_commit_modeset_enables(struct intel_atomic_state *state)
 	int i;
 
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
-		if (!new_crtc_state->base.active)
+		if (!new_crtc_state->hw.active)
 			continue;
 
 		intel_update_crtc(crtc, state, old_crtc_state,
@@ -13894,7 +13897,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
 
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
 		/* ignore allocations for crtc's that have been turned off. */
-		if (new_crtc_state->base.active)
+		if (new_crtc_state->hw.active)
 			entries[i] = old_crtc_state->wm.skl.ddb;
 
 	/* If 2nd DBuf slice required, enable it here */
@@ -13916,7 +13919,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
 
 			pipe = crtc->pipe;
 
-			if (updated & cmask || !new_crtc_state->base.active)
+			if (updated & cmask || !new_crtc_state->hw.active)
 				continue;
 
 			if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
@@ -14068,7 +14071,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		bool modeset = needs_modeset(new_crtc_state);
 
 		/* Complete events for now disable pipes here. */
-		if (modeset && !new_crtc_state->base.active && new_crtc_state->base.event) {
+		if (modeset && !new_crtc_state->hw.active && new_crtc_state->base.event) {
 			spin_lock_irq(&dev->event_lock);
 			drm_crtc_send_vblank_event(&crtc->base, new_crtc_state->base.event);
 			spin_unlock_irq(&dev->event_lock);
@@ -14104,7 +14107,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	drm_atomic_helper_wait_for_flip_done(dev, &state->base);
 
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
-		if (new_crtc_state->base.active &&
+		if (new_crtc_state->hw.active &&
 		    !needs_modeset(new_crtc_state) &&
 		    (new_crtc_state->base.color_mgmt_changed ||
 		     new_crtc_state->update_pipe))
@@ -14559,10 +14562,10 @@ skl_max_scale(const struct intel_crtc_state *crtc_state,
 	int max_scale;
 	int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
 
-	if (!crtc_state->base.enable)
+	if (!crtc_state->hw.enable)
 		return DRM_PLANE_HELPER_NO_SCALING;
 
-	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
+	crtc_clock = crtc_state->hw.adjusted_mode.crtc_clock;
 	max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
 
 	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
@@ -14698,7 +14701,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 	 * When crtc is inactive or there is a modeset pending,
 	 * wait for it to complete in the slowpath
 	 */
-	if (!crtc_state->base.active || needs_modeset(crtc_state) ||
+	if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
 	    crtc_state->update_pipe)
 		goto slow;
 
@@ -16114,7 +16117,7 @@ static int intel_initial_commit(struct drm_device *dev)
 			goto out;
 		}
 
-		if (crtc_state->base.active) {
+		if (crtc_state->hw.active) {
 			ret = drm_atomic_add_affected_planes(state, &crtc->base);
 			if (ret)
 				goto out;
@@ -16464,7 +16467,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
 			   I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
 	}
 
-	if (crtc_state->base.active) {
+	if (crtc_state->hw.active) {
 		struct intel_plane *plane;
 
 		/* Disable everything but the primary plane */
@@ -16489,10 +16492,10 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
 
 	/* Adjust the state of the output pipe according to whether we
 	 * have active connectors/encoders. */
-	if (crtc_state->base.active && !intel_crtc_has_encoders(crtc))
+	if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
 		intel_crtc_disable_noatomic(&crtc->base, ctx);
 
-	if (crtc_state->base.active || HAS_GMCH(dev_priv)) {
+	if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
 		/*
 		 * We start out with underrun reporting disabled to avoid races.
 		 * For correct bookkeeping mark this on active crtcs.
@@ -16536,7 +16539,7 @@ static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
 	 * road.
 	 */
 	return IS_GEN(dev_priv, 6) &&
-		crtc_state->base.active &&
+		crtc_state->hw.active &&
 		crtc_state->shared_dpll &&
 		crtc_state->port_clock == 0;
 }
@@ -16553,7 +16556,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
 	 * encoder is active and trying to read from a pipe) and the
 	 * pipe itself being active. */
 	bool has_active_crtc = crtc_state &&
-		crtc_state->base.active;
+		crtc_state->hw.active;
 
 	if (crtc_state && has_bogus_dpll_config(crtc_state)) {
 		DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
@@ -16661,18 +16664,18 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 		memset(crtc_state, 0, sizeof(*crtc_state));
 		__drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->base);
 
-		crtc_state->base.active = crtc_state->base.enable =
+		crtc_state->hw.active = crtc_state->hw.enable =
 			dev_priv->display.get_pipe_config(crtc, crtc_state);
 
-		crtc->base.enabled = crtc_state->base.enable;
-		crtc->active = crtc_state->base.active;
+		crtc->base.enabled = crtc_state->hw.enable;
+		crtc->active = crtc_state->hw.active;
 
-		if (crtc_state->base.active)
+		if (crtc_state->hw.active)
 			dev_priv->active_pipes |= BIT(crtc->pipe);
 
 		DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
 			      crtc->base.base.id, crtc->base.name,
-			      enableddisabled(crtc_state->base.active));
+			      enableddisabled(crtc_state->hw.active));
 	}
 
 	readout_plane_state(dev_priv);
@@ -16694,7 +16697,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 			struct intel_crtc_state *crtc_state =
 				to_intel_crtc_state(crtc->base.state);
 
-			if (crtc_state->base.active &&
+			if (crtc_state->hw.active &&
 			    crtc_state->shared_dpll == pll)
 				pll->state.crtc_mask |= 1 << crtc->pipe;
 		}
@@ -16739,7 +16742,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 			crtc = to_intel_crtc(encoder->base.crtc);
 			crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
 
-			if (crtc_state && crtc_state->base.active) {
+			if (crtc_state && crtc_state->hw.active) {
 				/*
 				 * This has to be done during hardware readout
 				 * because anything calling .crtc_disable may
@@ -16769,11 +16772,12 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 		int min_cdclk = 0;
 
 		memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
-		if (crtc_state->base.active) {
+		if (crtc_state->hw.active) {
 			intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
 			crtc->base.mode.hdisplay = crtc_state->pipe_src_w;
 			crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
-			intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
+			intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
+						    crtc_state);
 			WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->base, &crtc->base.mode));
 
 			/*
@@ -16785,7 +16789,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 			 * set a flag to indicate that a full recalculation is
 			 * needed on the next commit.
 			 */
-			crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
+			crtc_state->hw.mode.private_flags = I915_MODE_FLAG_INHERITED;
 
 			intel_crtc_compute_pixel_rate(crtc_state);
 
@@ -16963,7 +16967,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
 
 		drm_crtc_vblank_reset(&crtc->base);
 
-		if (crtc_state->base.active)
+		if (crtc_state->hw.active)
 			intel_crtc_vblank_on(crtc_state);
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c4c081c79dd9..213b0c0cdd67 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1968,7 +1968,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
 				  struct intel_crtc_state *pipe_config,
 				  const struct link_config_limits *limits)
 {
-	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	int bpp, clock, lane_count;
 	int mode_rate, link_clock, link_avail;
 
@@ -2022,7 +2022,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
-	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	u8 dsc_max_bpc;
 	int pipe_bpp;
 	int ret;
@@ -2133,7 +2133,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 			     struct intel_crtc_state *pipe_config,
 			     struct drm_connector_state *conn_state)
 {
-	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	struct link_config_limits limits;
 	int common_len;
@@ -2221,7 +2221,7 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
 {
 	const struct drm_display_info *info = &connector->display_info;
 	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->base.adjusted_mode;
+		&crtc_state->hw.adjusted_mode;
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	int ret;
 
@@ -2250,7 +2250,7 @@ bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
 	const struct intel_digital_connector_state *intel_conn_state =
 		to_intel_digital_connector_state(conn_state);
 	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->base.adjusted_mode;
+		&crtc_state->hw.adjusted_mode;
 
 	/*
 	 * Our YCbCr output is always limited range.
@@ -2283,7 +2283,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 			struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
 	enum port port = encoder->port;
@@ -2403,7 +2403,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	enum port port = encoder->port;
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
-	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 
 	intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
 				 pipe_config->lane_count,
@@ -3235,7 +3235,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
 			flags |= DRM_MODE_FLAG_NVSYNC;
 	}
 
-	pipe_config->base.adjusted_mode.flags |= flags;
+	pipe_config->hw.adjusted_mode.flags |= flags;
 
 	if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
 		pipe_config->limited_color_range = true;
@@ -3252,7 +3252,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
 			pipe_config->port_clock = 270000;
 	}
 
-	pipe_config->base.adjusted_mode.crtc_clock =
+	pipe_config->hw.adjusted_mode.crtc_clock =
 		intel_dotclock_calculate(pipe_config->port_clock,
 					 &pipe_config->dp_m_n);
 
@@ -5045,7 +5045,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
 
 	WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
 
-	if (!crtc_state->base.active)
+	if (!crtc_state->hw.active)
 		return 0;
 
 	if (conn_state->commit &&
@@ -6907,7 +6907,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
 		return;
 	}
 
-	if (!crtc_state->base.active) {
+	if (!crtc_state->hw.active) {
 		DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
 		return;
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 5484bd4534c1..7d63f0a79ca1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -48,7 +48,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
 	struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
 	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->base.adjusted_mode;
+		&crtc_state->hw.adjusted_mode;
 	void *port = connector->port;
 	bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
 					   DP_DPCD_QUIRK_CONSTANT_N);
@@ -99,7 +99,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 	struct intel_digital_connector_state *intel_conn_state =
 		to_intel_digital_connector_state(conn_state);
 	const struct drm_display_mode *adjusted_mode =
-		&pipe_config->base.adjusted_mode;
+		&pipe_config->hw.adjusted_mode;
 	void *port = connector->port;
 	struct link_config_limits limits;
 	int ret;
@@ -187,7 +187,7 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
 
 		if (!crtc_state ||
 		    !drm_atomic_crtc_needs_modeset(crtc_state) ||
-		    to_intel_crtc_state(crtc_state)->base.enable)
+		    to_intel_crtc_state(crtc_state)->hw.enable)
 			return 0;
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index 9827f99491d1..a68e5c5b91b4 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -178,9 +178,9 @@ static void intel_dvo_get_config(struct intel_encoder *encoder,
 	else
 		flags |= DRM_MODE_FLAG_NVSYNC;
 
-	pipe_config->base.adjusted_mode.flags |= flags;
+	pipe_config->hw.adjusted_mode.flags |= flags;
 
-	pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
+	pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
 }
 
 static void intel_disable_dvo(struct intel_encoder *encoder,
@@ -207,8 +207,8 @@ static void intel_enable_dvo(struct intel_encoder *encoder,
 	u32 temp = I915_READ(dvo_reg);
 
 	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
-					 &pipe_config->base.mode,
-					 &pipe_config->base.adjusted_mode);
+					 &pipe_config->hw.mode,
+					 &pipe_config->hw.adjusted_mode);
 
 	I915_WRITE(dvo_reg, temp | DVO_ENABLE);
 	I915_READ(dvo_reg);
@@ -253,7 +253,7 @@ static int intel_dvo_compute_config(struct intel_encoder *encoder,
 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
 	const struct drm_display_mode *fixed_mode =
 		intel_dvo->attached_connector->panel.fixed_mode;
-	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 
 	/*
 	 * If we have timings from the BIOS for the panel, put them in
@@ -278,7 +278,7 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
-	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
 	enum pipe pipe = crtc->pipe;
 	u32 dvo_val;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 3111ecaeabd0..c6cc3775f3b8 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -667,7 +667,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 	cache->vma = NULL;
 	cache->flags = 0;
 
-	cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
+	cache->crtc.mode_flags = crtc_state->hw.adjusted_mode.flags;
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
 
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 92d1cbbbee2b..2f5fc71ac9a0 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -708,7 +708,7 @@ intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
 {
 	struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
 	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->base.adjusted_mode;
+		&crtc_state->hw.adjusted_mode;
 	struct drm_connector *connector = conn_state->connector;
 	int ret;
 
@@ -804,7 +804,7 @@ intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
 
 	ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
 							  conn_state->connector,
-							  &crtc_state->base.adjusted_mode);
+							  &crtc_state->hw.adjusted_mode);
 	if (WARN_ON(ret))
 		return false;
 
@@ -1027,7 +1027,7 @@ static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
 
 	/* Enable default_phase whenever the display mode is suitably aligned */
 	if (gcp_default_phase_possible(crtc_state->pipe_bpp,
-				       &crtc_state->base.adjusted_mode))
+				       &crtc_state->hw.adjusted_mode))
 		crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
 }
 
@@ -1743,7 +1743,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
-	const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	u32 hdmi_val;
 
 	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
@@ -1834,7 +1834,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
 	    tmp & HDMI_COLOR_RANGE_16_235)
 		pipe_config->limited_color_range = true;
 
-	pipe_config->base.adjusted_mode.flags |= flags;
+	pipe_config->hw.adjusted_mode.flags |= flags;
 
 	if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 		dotclock = pipe_config->port_clock * 2 / 3;
@@ -1844,7 +1844,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
 	if (pipe_config->pixel_multiplier)
 		dotclock /= pipe_config->pixel_multiplier;
 
-	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
+	pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
 
 	pipe_config->lane_count = 4;
 
@@ -2220,7 +2220,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
 	struct drm_connector_state *connector_state;
 	struct drm_connector *connector;
 	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->base.adjusted_mode;
+		&crtc_state->hw.adjusted_mode;
 	int i;
 
 	if (HAS_GMCH(dev_priv))
@@ -2341,7 +2341,7 @@ static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
 {
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->base.adjusted_mode;
+		&crtc_state->hw.adjusted_mode;
 	int bpc, clock = adjusted_mode->crtc_clock;
 
 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
@@ -2383,7 +2383,7 @@ static bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_s
 	const struct intel_digital_connector_state *intel_conn_state =
 		to_intel_digital_connector_state(conn_state);
 	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->base.adjusted_mode;
+		&crtc_state->hw.adjusted_mode;
 
 	/*
 	 * Our YCbCr output is always limited range.
@@ -2411,7 +2411,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
 {
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	struct drm_connector *connector = conn_state->connector;
 	struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
 	struct intel_digital_connector_state *intel_conn_state =
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index f8f1308643a9..5145ff8b962b 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -189,7 +189,7 @@ void lspcon_ycbcr420_config(struct drm_connector *connector,
 {
 	const struct drm_display_info *info = &connector->display_info;
 	const struct drm_display_mode *adjusted_mode =
-					&crtc_state->base.adjusted_mode;
+					&crtc_state->hw.adjusted_mode;
 
 	if (drm_mode_is_420_only(info, adjusted_mode) &&
 	    connector->ycbcr_420_allowed) {
@@ -475,7 +475,7 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
 	struct intel_lspcon *lspcon = &dig_port->lspcon;
 	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->base.adjusted_mode;
+		&crtc_state->hw.adjusted_mode;
 
 	if (!lspcon->active) {
 		DRM_ERROR("Writing infoframes while LSPCON disabled ?\n");
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 13841d7c455b..f17d6e02460f 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -135,7 +135,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
 	else
 		flags |= DRM_MODE_FLAG_PVSYNC;
 
-	pipe_config->base.adjusted_mode.flags |= flags;
+	pipe_config->hw.adjusted_mode.flags |= flags;
 
 	if (INTEL_GEN(dev_priv) < 5)
 		pipe_config->gmch_pfit.lvds_border_bits =
@@ -148,7 +148,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
 		pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
 	}
 
-	pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
+	pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
 }
 
 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
@@ -231,7 +231,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder,
 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
-	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	enum pipe pipe = crtc->pipe;
 	u32 temp;
 
@@ -392,7 +392,7 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 		to_lvds_encoder(&intel_encoder->base);
 	struct intel_connector *intel_connector =
 		lvds_encoder->attached_connector;
-	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
 	unsigned int lvds_bpp;
 
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index bc14e9c0285a..5e3fd37d9471 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -178,7 +178,7 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
 			struct intel_crtc_state *pipe_config,
 			int fitting_mode)
 {
-	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	int x = 0, y = 0, width = 0, height = 0;
 
 	/* Native modes don't need fitting */
@@ -300,7 +300,7 @@ static inline u32 panel_fitter_scaling(u32 source, u32 target)
 static void i965_scale_aspect(struct intel_crtc_state *pipe_config,
 			      u32 *pfit_control)
 {
-	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	u32 scaled_width = adjusted_mode->crtc_hdisplay *
 		pipe_config->pipe_src_h;
 	u32 scaled_height = pipe_config->pipe_src_w *
@@ -321,7 +321,7 @@ static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
 			      u32 *pfit_control, u32 *pfit_pgm_ratios,
 			      u32 *border)
 {
-	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	u32 scaled_width = adjusted_mode->crtc_hdisplay *
 		pipe_config->pipe_src_h;
 	u32 scaled_height = pipe_config->pipe_src_w *
@@ -380,7 +380,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
 	u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
-	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 
 	/* Native modes don't need fitting */
 	if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w &&
diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
index 6260a2082719..fc602533a602 100644
--- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
@@ -313,7 +313,7 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
 	pipe_config->crc_enabled = enable;
 
 	if (IS_HASWELL(dev_priv) &&
-	    pipe_config->base.active && crtc->pipe == PIPE_A &&
+	    pipe_config->hw.active && crtc->pipe == PIPE_A &&
 	    pipe_config->cpu_transcoder == TRANSCODER_EDP)
 		pipe_config->base.mode_changed = true;
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 211710f5214c..347004981cff 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -536,11 +536,11 @@ transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)
 
 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
 {
-	if (!cstate || !cstate->base.active)
+	if (!cstate || !cstate->hw.active)
 		return 0;
 
 	return DIV_ROUND_UP(1000 * 1000,
-			    drm_mode_vrefresh(&cstate->base.adjusted_mode));
+			    drm_mode_vrefresh(&cstate->hw.adjusted_mode));
 }
 
 static void psr2_program_idle_frames(struct drm_i915_private *dev_priv,
@@ -605,8 +605,8 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 				    struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay;
-	int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay;
+	int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
+	int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
 	int psr_max_h = 0, psr_max_v = 0;
 
 	if (!dev_priv->psr.sink_psr2_support)
@@ -672,7 +672,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->base.adjusted_mode;
+		&crtc_state->hw.adjusted_mode;
 	int psr_setup_time;
 
 	if (!CAN_PSR(dev_priv))
@@ -1139,7 +1139,7 @@ static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
 
 		intel_crtc_state = to_intel_crtc_state(crtc_state);
 
-		if (intel_crtc_state->base.active && intel_crtc_state->has_psr) {
+		if (intel_crtc_state->hw.active && intel_crtc_state->has_psr) {
 			/* Mark mode as changed to trigger a pipe->update() */
 			intel_crtc_state->base.mode_changed = true;
 			break;
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 47f5d87a938a..97ae8cc1314e 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -1087,7 +1087,7 @@ static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
 {
 	struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
 	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->base.adjusted_mode;
+		&crtc_state->hw.adjusted_mode;
 	int ret;
 
 	if (!crtc_state->has_hdmi_sink)
@@ -1276,8 +1276,8 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder,
 		to_intel_sdvo_connector_state(conn_state);
 	struct intel_sdvo_connector *intel_sdvo_connector =
 		to_intel_sdvo_connector(conn_state->connector);
-	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
-	struct drm_display_mode *mode = &pipe_config->base.mode;
+	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+	struct drm_display_mode *mode = &pipe_config->hw.mode;
 
 	DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
 	pipe_config->pipe_bpp = 8*3;
@@ -1430,12 +1430,12 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-	const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	const struct intel_sdvo_connector_state *sdvo_state =
 		to_intel_sdvo_connector_state(conn_state);
 	const struct intel_sdvo_connector *intel_sdvo_connector =
 		to_intel_sdvo_connector(conn_state->connector);
-	const struct drm_display_mode *mode = &crtc_state->base.mode;
+	const struct drm_display_mode *mode = &crtc_state->hw.mode;
 	struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
 	u32 sdvox;
 	struct intel_sdvo_in_out_map in_out;
@@ -1629,7 +1629,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
 			flags |= DRM_MODE_FLAG_NVSYNC;
 	}
 
-	pipe_config->base.adjusted_mode.flags |= flags;
+	pipe_config->hw.adjusted_mode.flags |= flags;
 
 	/*
 	 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
@@ -1649,7 +1649,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
 	if (pipe_config->pixel_multiplier)
 		dotclock /= pipe_config->pixel_multiplier;
 
-	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
+	pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
 
 	/* Cross check the port pixel multiplier with the sdvo encoder state. */
 	if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
@@ -1701,7 +1701,7 @@ static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo,
 				    const struct drm_connector_state *conn_state)
 {
 	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->base.adjusted_mode;
+		&crtc_state->hw.adjusted_mode;
 	struct drm_connector *connector = conn_state->connector;
 	u8 *eld = connector->eld;
 
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 5ae12ab3c5b7..ef0ca7c6d11f 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -83,7 +83,7 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
+	const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
 	long timeout = msecs_to_jiffies_timeout(1);
 	int scanline, min, max, vblank_start;
 	wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
@@ -1513,7 +1513,7 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
 	const struct drm_rect *dst = &plane_state->base.dst;
 	int src_x, src_w, src_h, crtc_w, crtc_h;
 	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->base.adjusted_mode;
+		&crtc_state->hw.adjusted_mode;
 	unsigned int stride = plane_state->color_plane[0].stride;
 	unsigned int cpp = fb->format->cpp[0];
 	unsigned int width_bytes;
@@ -1727,8 +1727,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	}
 
 	/* Y-tiling is not supported in IF-ID Interlace mode */
-	if (crtc_state->base.enable &&
-	    crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
+	if (crtc_state->hw.enable &&
+	    crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
 	    (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
index 70726b481244..e800d45b813d 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.c
+++ b/drivers/gpu/drm/i915/display/intel_tv.c
@@ -1085,7 +1085,7 @@ intel_tv_get_config(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct drm_display_mode *adjusted_mode =
-		&pipe_config->base.adjusted_mode;
+		&pipe_config->hw.adjusted_mode;
 	struct drm_display_mode mode = {};
 	u32 tv_ctl, hctl1, hctl3, vctl1, vctl2, tmp;
 	struct tv_mode tv_mode = {};
@@ -1188,7 +1188,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
 		to_intel_tv_connector_state(conn_state);
 	const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
 	struct drm_display_mode *adjusted_mode =
-		&pipe_config->base.adjusted_mode;
+		&pipe_config->hw.adjusted_mode;
 	int hdisplay = adjusted_mode->crtc_hdisplay;
 	int vdisplay = adjusted_mode->crtc_vdisplay;
 
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index d4fb7f16f9f6..6a338a83aaed 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -329,8 +329,8 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
 	int column_index = 0;
 	u8 line_buf_depth = 0;
 
-	vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay;
-	vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay;
+	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
+	vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
 	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
 					     pipe_config->dsc_params.slice_count);
 	/*
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 50064cde0724..3bf838279fc2 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -263,7 +263,7 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
 	struct intel_connector *intel_connector = intel_dsi->attached_connector;
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 	const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
-	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	int ret;
 
 	DRM_DEBUG_KMS("\n");
@@ -1032,7 +1032,7 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct drm_display_mode *adjusted_mode =
-					&pipe_config->base.adjusted_mode;
+					&pipe_config->hw.adjusted_mode;
 	struct drm_display_mode *adjusted_mode_sw;
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -1045,7 +1045,7 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
 				crtc_hblank_start_sw, crtc_hblank_end_sw;
 
 	/* FIXME: hw readout should not depend on SW state */
-	adjusted_mode_sw = &crtc->config->base.adjusted_mode;
+	adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
 
 	/*
 	 * Atleast one port is active as encoder->get_config called only if
@@ -1204,7 +1204,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
 	}
 
 	if (pclk) {
-		pipe_config->base.adjusted_mode.crtc_clock = pclk;
+		pipe_config->hw.adjusted_mode.crtc_clock = pclk;
 		pipe_config->port_clock = pclk;
 	}
 }
@@ -1317,7 +1317,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
-	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	enum port port;
 	unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 	u32 val, tmp;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ada57eee914a..51e83da21738 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2751,11 +2751,11 @@ static int i915_display_info(struct seq_file *m, void *unused)
 
 		seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
 			   crtc->base.base.id, pipe_name(crtc->pipe),
-			   yesno(pipe_config->base.active),
+			   yesno(pipe_config->hw.active),
 			   pipe_config->pipe_src_w, pipe_config->pipe_src_h,
 			   yesno(pipe_config->dither), pipe_config->pipe_bpp);
 
-		if (pipe_config->base.active) {
+		if (pipe_config->hw.active) {
 			struct intel_plane *cursor =
 				to_intel_plane(crtc->base.cursor);
 
@@ -4218,7 +4218,7 @@ static int i915_drrs_ctl_set(void *data, u64 val)
 
 		crtc_state = to_intel_crtc_state(crtc->base.state);
 
-		if (!crtc_state->base.active ||
+		if (!crtc_state->hw.active ||
 		    !crtc_state->has_drrs)
 			goto out;
 
@@ -4300,7 +4300,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
 				ret = wait_for_completion_interruptible(&commit->flip_done);
 		}
 
-		if (!ret && crtc_state->base.active) {
+		if (!ret && crtc_state->hw.active) {
 			DRM_DEBUG_KMS("Re-arming FIFO underruns on pipe %c\n",
 				      pipe_name(intel_crtc->pipe));
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e680df75a970..9671ff29c25f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -798,7 +798,7 @@ static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 
 	/* FIXME check the 'enable' instead */
-	if (!crtc_state->base.active)
+	if (!crtc_state->hw.active)
 		return false;
 
 	/*
@@ -851,7 +851,7 @@ static void pineview_update_wm(struct intel_crtc *unused_crtc)
 	crtc = single_enabled_crtc(dev_priv);
 	if (crtc) {
 		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->base.adjusted_mode;
+			&crtc->config->hw.adjusted_mode;
 		const struct drm_framebuffer *fb =
 			crtc->base.primary->state->fb;
 		int cpp = fb->format->cpp[0];
@@ -1087,7 +1087,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->base.adjusted_mode;
+		&crtc_state->hw.adjusted_mode;
 	unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
 	unsigned int clock, htotal, cpp, width, wm;
 
@@ -1399,7 +1399,7 @@ static int g4x_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
 	const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
 	enum plane_id plane_id;
 
-	if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
+	if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
 		*intermediate = *optimal;
 
 		intermediate->cxsr = false;
@@ -1593,7 +1593,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->base.adjusted_mode;
+		&crtc_state->hw.adjusted_mode;
 	unsigned int clock, htotal, cpp, width, wm;
 
 	if (dev_priv->wm.pri_latency[level] == 0)
@@ -2032,7 +2032,7 @@ static int vlv_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
 	const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
 	int level;
 
-	if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
+	if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
 		*intermediate = *optimal;
 
 		intermediate->cxsr = false;
@@ -2188,7 +2188,7 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
 		/* self-refresh has much higher latency */
 		static const int sr_latency_ns = 12000;
 		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->base.adjusted_mode;
+			&crtc->config->hw.adjusted_mode;
 		const struct drm_framebuffer *fb =
 			crtc->base.primary->state->fb;
 		int clock = adjusted_mode->crtc_clock;
@@ -2269,7 +2269,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
 	if (intel_crtc_active(crtc)) {
 		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->base.adjusted_mode;
+			&crtc->config->hw.adjusted_mode;
 		const struct drm_framebuffer *fb =
 			crtc->base.primary->state->fb;
 		int cpp;
@@ -2296,7 +2296,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
 	if (intel_crtc_active(crtc)) {
 		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->base.adjusted_mode;
+			&crtc->config->hw.adjusted_mode;
 		const struct drm_framebuffer *fb =
 			crtc->base.primary->state->fb;
 		int cpp;
@@ -2344,7 +2344,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 		/* self-refresh has much higher latency */
 		static const int sr_latency_ns = 6000;
 		const struct drm_display_mode *adjusted_mode =
-			&enabled->config->base.adjusted_mode;
+			&enabled->config->hw.adjusted_mode;
 		const struct drm_framebuffer *fb =
 			enabled->base.primary->state->fb;
 		int clock = adjusted_mode->crtc_clock;
@@ -2402,7 +2402,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
 	if (crtc == NULL)
 		return;
 
-	adjusted_mode = &crtc->config->base.adjusted_mode;
+	adjusted_mode = &crtc->config->hw.adjusted_mode;
 	planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
 				       &i845_wm_info,
 				       dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
@@ -2492,7 +2492,7 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
 		return method1;
 
 	method2 = ilk_wm_method2(crtc_state->pixel_rate,
-				 crtc_state->base.adjusted_mode.crtc_htotal,
+				 crtc_state->hw.adjusted_mode.crtc_htotal,
 				 drm_rect_width(&plane_state->base.dst),
 				 cpp, mem_value);
 
@@ -2520,7 +2520,7 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
 
 	method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
 	method2 = ilk_wm_method2(crtc_state->pixel_rate,
-				 crtc_state->base.adjusted_mode.crtc_htotal,
+				 crtc_state->hw.adjusted_mode.crtc_htotal,
 				 drm_rect_width(&plane_state->base.dst),
 				 cpp, mem_value);
 	return min(method1, method2);
@@ -2545,7 +2545,7 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
 	cpp = plane_state->base.fb->format->cpp[0];
 
 	return ilk_wm_method2(crtc_state->pixel_rate,
-			      crtc_state->base.adjusted_mode.crtc_htotal,
+			      crtc_state->hw.adjusted_mode.crtc_htotal,
 			      drm_rect_width(&plane_state->base.dst),
 			      cpp, mem_value);
 }
@@ -2769,10 +2769,10 @@ hsw_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
 	const struct intel_atomic_state *intel_state =
 		to_intel_atomic_state(crtc_state->base.state);
 	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->base.adjusted_mode;
+		&crtc_state->hw.adjusted_mode;
 	u32 linetime, ips_linetime;
 
-	if (!crtc_state->base.active)
+	if (!crtc_state->hw.active)
 		return 0;
 	if (WARN_ON(adjusted_mode->crtc_clock == 0))
 		return 0;
@@ -3104,7 +3104,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 			curstate = plane_state;
 	}
 
-	pipe_wm->pipe_enabled = crtc_state->base.active;
+	pipe_wm->pipe_enabled = crtc_state->hw.active;
 	if (sprstate) {
 		pipe_wm->sprites_enabled = sprstate->base.visible;
 		pipe_wm->sprites_scaled = sprstate->base.visible &&
@@ -3177,7 +3177,7 @@ static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
 	 * and after the vblank.
 	 */
 	*a = newstate->wm.ilk.optimal;
-	if (!newstate->base.active || drm_atomic_crtc_needs_modeset(&newstate->base) ||
+	if (!newstate->hw.active || drm_atomic_crtc_needs_modeset(&newstate->base) ||
 	    intel_state->skip_intermediate_wm)
 		return 0;
 
@@ -3779,7 +3779,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
 	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 	crtc_state = to_intel_crtc_state(crtc->base.state);
 
-	if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
 		return false;
 
 	for_each_intel_plane_on_crtc(dev, crtc, plane) {
@@ -3829,7 +3829,7 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
 	if (INTEL_GEN(dev_priv) < 11)
 		return ddb_size - 4; /* 4 blocks for bypass path allocation */
 
-	adjusted_mode = &crtc_state->base.adjusted_mode;
+	adjusted_mode = &crtc_state->hw.adjusted_mode;
 	total_data_bw = total_data_rate * drm_mode_vrefresh(adjusted_mode);
 
 	/*
@@ -3867,7 +3867,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
 	u16 ddb_size;
 	u32 i;
 
-	if (WARN_ON(!state) || !crtc_state->base.active) {
+	if (WARN_ON(!state) || !crtc_state->hw.active) {
 		alloc->start = 0;
 		alloc->end = 0;
 		*num_active = hweight8(dev_priv->active_pipes);
@@ -3906,11 +3906,11 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
 	 */
 	for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
 		const struct drm_display_mode *adjusted_mode =
-			&crtc_state->base.adjusted_mode;
+			&crtc_state->hw.adjusted_mode;
 		enum pipe pipe = crtc->pipe;
 		int hdisplay, vdisplay;
 
-		if (!crtc_state->base.enable)
+		if (!crtc_state->hw.enable)
 			continue;
 
 		drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
@@ -4099,7 +4099,7 @@ skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
 {
 	uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1);
 
-	if (!crtc_state->base.enable)
+	if (!crtc_state->hw.enable)
 		return pipe_downscale;
 
 	if (crtc_state->pch_pfit.enabled) {
@@ -4139,7 +4139,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 	uint_fixed_16_16_t pipe_downscale;
 	uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);
 
-	if (!crtc_state->base.enable)
+	if (!crtc_state->hw.enable)
 		return 0;
 
 	intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
@@ -4165,7 +4165,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 
 	pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
 
-	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
+	crtc_clock = crtc_state->hw.adjusted_mode.crtc_clock;
 	dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
 
 	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
@@ -4334,7 +4334,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 	if (WARN_ON(!state))
 		return 0;
 
-	if (!crtc_state->base.active) {
+	if (!crtc_state->hw.active) {
 		alloc->start = alloc->end = 0;
 		return 0;
 	}
@@ -4576,7 +4576,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
 	u32 crtc_htotal;
 	uint_fixed_16_16_t linetime_us;
 
-	if (!crtc_state->base.active)
+	if (!crtc_state->hw.active)
 		return u32_to_fixed16(0);
 
 	pixel_rate = crtc_state->pixel_rate;
@@ -4584,7 +4584,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
 	if (WARN_ON(pixel_rate == 0))
 		return u32_to_fixed16(0);
 
-	crtc_htotal = crtc_state->base.adjusted_mode.crtc_htotal;
+	crtc_htotal = crtc_state->hw.adjusted_mode.crtc_htotal;
 	linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
 
 	return linetime_us;
@@ -4766,14 +4766,14 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 	method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
 				 wp->cpp, latency, wp->dbuf_block_size);
 	method2 = skl_wm_method2(wp->plane_pixel_rate,
-				 crtc_state->base.adjusted_mode.crtc_htotal,
+				 crtc_state->hw.adjusted_mode.crtc_htotal,
 				 latency,
 				 wp->plane_blocks_per_line);
 
 	if (wp->y_tiled) {
 		selected_result = max_fixed16(method2, wp->y_tile_minimum);
 	} else {
-		if ((wp->cpp * crtc_state->base.adjusted_mode.crtc_htotal /
+		if ((wp->cpp * crtc_state->hw.adjusted_mode.crtc_htotal /
 		     wp->dbuf_block_size < 1) &&
 		     (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
 			selected_result = method2;
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH 07/14] drm/i915: Perform automated conversions for crtc uapi/hw split, base -> uapi.
  2019-10-17 13:20 [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Maarten Lankhorst
                   ` (4 preceding siblings ...)
  2019-10-17 13:20 ` [PATCH 06/14] drm/i915: Perform automated conversions for crtc uapi/hw split, base -> hw Maarten Lankhorst
@ 2019-10-17 13:20 ` Maarten Lankhorst
  2019-10-22 18:24   ` Ville Syrjälä
  2019-10-17 13:20 ` [PATCH 08/14] drm/i915: Complete crtc hw/uapi split, v2 Maarten Lankhorst
                   ` (13 subsequent siblings)
  19 siblings, 1 reply; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-17 13:20 UTC (permalink / raw)
  To: intel-gfx

Split up crtc_state->base to uapi. This is done using the following patch,
ran after the previous commit that splits out any hw references:

@@
struct intel_crtc_state *T;
@@
-T->base
+T->uapi

@@
struct intel_crtc_state *T;
identifier x =~ "^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
@@
-T->base.x
+T->uapi.x

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c        |   6 +-
 drivers/gpu/drm/i915/display/intel_atomic.c   |   8 +-
 .../gpu/drm/i915/display/intel_atomic_plane.c |   6 +-
 drivers/gpu/drm/i915/display/intel_audio.c    |   8 +-
 drivers/gpu/drm/i915/display/intel_bw.c       |   4 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  10 +-
 drivers/gpu/drm/i915/display/intel_color.c    |  70 ++---
 drivers/gpu/drm/i915/display/intel_crt.c      |   6 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  32 +--
 drivers/gpu/drm/i915/display/intel_display.c  | 241 +++++++++---------
 drivers/gpu/drm/i915/display/intel_dp.c       |  20 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |  14 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  20 +-
 drivers/gpu/drm/i915/display/intel_dvo.c      |   2 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     |  44 ++--
 drivers/gpu/drm/i915/display/intel_lvds.c     |   4 +-
 drivers/gpu/drm/i915/display/intel_panel.c    |   6 +-
 drivers/gpu/drm/i915/display/intel_pipe_crc.c |   4 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |   6 +-
 drivers/gpu/drm/i915/display/intel_sdvo.c     |   6 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  17 +-
 drivers/gpu/drm/i915/display/intel_tv.c       |   4 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     |   8 +-
 drivers/gpu/drm/i915/display/vlv_dsi.c        |  10 +-
 drivers/gpu/drm/i915/i915_debugfs.c           |   6 +-
 drivers/gpu/drm/i915/intel_pm.c               | 112 ++++----
 27 files changed, 339 insertions(+), 337 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 4ec493e4755b..0e24b8e257e5 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -625,7 +625,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
-	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	enum pipe pipe = intel_crtc->pipe;
 	u32 tmp;
 	enum port port;
@@ -1242,7 +1242,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
 				 struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 
 	/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
@@ -1265,7 +1265,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 	struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 						   base);
 	struct intel_connector *intel_connector = intel_dsi->attached_connector;
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	const struct drm_display_mode *fixed_mode =
 					intel_connector->panel.fixed_mode;
 	struct drm_display_mode *adjusted_mode =
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 2cdc92897abd..7cf13b9c7d38 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -193,7 +193,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
 	if (!crtc_state)
 		return NULL;
 
-	__drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->base);
+	__drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);
 
 	crtc_state->update_pipe = false;
 	crtc_state->disable_lp_wm = false;
@@ -205,7 +205,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
 	crtc_state->fb_bits = 0;
 	crtc_state->update_planes = 0;
 
-	return &crtc_state->base;
+	return &crtc_state->uapi;
 }
 
 /**
@@ -222,7 +222,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
 {
 	struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
 
-	__drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
+	__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
 	kfree(crtc_state);
 }
 
@@ -319,7 +319,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
 {
 	struct intel_crtc_scaler_state *scaler_state =
 		&crtc_state->scaler_state;
-	struct drm_atomic_state *drm_state = crtc_state->base.state;
+	struct drm_atomic_state *drm_state = crtc_state->uapi.state;
 	struct intel_atomic_state *state = to_intel_atomic_state(drm_state);
 	int num_scalers_need;
 	int i;
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 847f9c4ecbbd..d92c185d4b4a 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -268,7 +268,7 @@ void intel_update_plane(struct intel_plane *plane,
 			const struct intel_crtc_state *crtc_state,
 			const struct intel_plane_state *plane_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	trace_intel_update_plane(&plane->base, crtc);
 	plane->update_plane(plane, crtc_state, plane_state);
@@ -278,7 +278,7 @@ void intel_update_slave(struct intel_plane *plane,
 			const struct intel_crtc_state *crtc_state,
 			const struct intel_plane_state *plane_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	trace_intel_update_plane(&plane->base, crtc);
 	plane->update_slave(plane, crtc_state, plane_state);
@@ -287,7 +287,7 @@ void intel_update_slave(struct intel_plane *plane,
 void intel_disable_plane(struct intel_plane *plane,
 			 const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	trace_intel_disable_plane(&plane->base, crtc);
 	plane->disable_plane(plane, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 6a58e8ad86f8..5680eed9c71f 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -554,7 +554,7 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder,
 				    const struct drm_connector_state *old_conn_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
 	enum port port = encoder->port;
 	u32 tmp, eldv;
@@ -601,7 +601,7 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder,
 				   const struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_connector *connector = conn_state->connector;
 	enum pipe pipe = crtc->pipe;
 	enum port port = encoder->port;
@@ -691,7 +691,7 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct i915_audio_component *acomp = dev_priv->audio_component;
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_connector *connector = conn_state->connector;
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
@@ -752,7 +752,7 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct i915_audio_component *acomp = dev_priv->audio_component;
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	enum port port = encoder->port;
 	enum pipe pipe = crtc->pipe;
 
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 22e83f857de8..3f6e29f61323 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -297,7 +297,7 @@ static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_stat
 
 static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	unsigned int data_rate = 0;
 	enum plane_id plane_id;
 
@@ -318,7 +318,7 @@ static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_
 void intel_bw_crtc_update(struct intel_bw_state *bw_state,
 			  const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	bw_state->data_rate[crtc->pipe] =
 		intel_bw_crtc_data_rate(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index fd1ed0fb8748..931f19dbd4dd 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1902,7 +1902,7 @@ intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv,
 
 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	int pixel_rate = crtc_state->pixel_rate;
 
 	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
@@ -1921,7 +1921,7 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv =
-		to_i915(crtc_state->base.crtc->dev);
+		to_i915(crtc_state->uapi.crtc->dev);
 	int min_cdclk;
 
 	if (!crtc_state->hw.enable)
@@ -2261,10 +2261,10 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
 			return PTR_ERR(crtc_state);
 
 		if (!crtc_state->hw.active ||
-		    drm_atomic_crtc_needs_modeset(&crtc_state->base))
+		    drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
 			continue;
 
-		crtc_state->base.mode_changed = true;
+		crtc_state->uapi.mode_changed = true;
 
 		ret = drm_atomic_add_affected_connectors(&state->base,
 							 &crtc->base);
@@ -2330,7 +2330,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
 		crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 		if (crtc_state &&
-		    drm_atomic_crtc_needs_modeset(&crtc_state->base))
+		    drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
 			pipe = INVALID_PIPE;
 	} else {
 		pipe = INVALID_PIPE;
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 65e1b18bd7e3..52712bb9ed15 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -205,7 +205,7 @@ static void icl_update_output_csc(struct intel_crtc *crtc,
 
 static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
 	/*
 	 * FIXME if there's a gamma LUT after the CSC, we should
@@ -270,7 +270,7 @@ static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
 
 static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	bool limited_color_range = ilk_csc_limited_range(crtc_state);
 
@@ -309,7 +309,7 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 
 static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	if (crtc_state->hw.ctm) {
@@ -338,7 +338,7 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
  */
 static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
@@ -404,7 +404,7 @@ static u32 ilk_lut_10(const struct drm_color_lut *color)
 static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
 				    const struct drm_property_blob *blob)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	int i;
@@ -440,7 +440,7 @@ static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
 
 static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	u32 val;
@@ -453,7 +453,7 @@ static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
 
 static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	u32 val;
@@ -468,7 +468,7 @@ static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
 
 static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
@@ -478,7 +478,7 @@ static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
 
 static void skl_color_commit(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	u32 val = 0;
@@ -524,7 +524,7 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc,
 
 static void i965_load_luts(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
@@ -547,7 +547,7 @@ static void ilk_load_lut_10(struct intel_crtc *crtc,
 
 static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
@@ -654,7 +654,7 @@ static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
 
 static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 
@@ -677,7 +677,7 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
 
 static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 
@@ -700,7 +700,7 @@ static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
 
 static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
@@ -739,7 +739,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 
 static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
@@ -767,7 +767,7 @@ static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_stat
 static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	/*
 	 * On GLK+ both pipe CSC and degamma LUT are controlled
@@ -808,7 +808,7 @@ static void
 icl_load_gcmax(const struct intel_crtc_state *crtc_state,
 	       const struct drm_color_lut *color)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct intel_dsb *dsb = intel_dsb_get(crtc);
 	enum pipe pipe = crtc->pipe;
 
@@ -822,7 +822,7 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
 static void
 icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
 	const struct drm_color_lut *lut = blob->data;
 	struct intel_dsb *dsb = intel_dsb_get(crtc);
@@ -854,7 +854,7 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
 static void
 icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
 	const struct drm_color_lut *lut = blob->data;
 	const struct drm_color_lut *entry;
@@ -911,7 +911,7 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
 static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct intel_dsb *dsb = intel_dsb_get(crtc);
 
 	if (crtc_state->hw.degamma_lut)
@@ -990,7 +990,7 @@ static void chv_load_cgm_gamma(struct intel_crtc *crtc,
 
 static void chv_load_luts(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 
@@ -1010,28 +1010,28 @@ static void chv_load_luts(const struct intel_crtc_state *crtc_state)
 
 void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
 	dev_priv->display.load_luts(crtc_state);
 }
 
 void intel_color_commit(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
 	dev_priv->display.color_commit(crtc_state);
 }
 
 int intel_color_check(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
 	return dev_priv->display.color_check(crtc_state);
 }
 
 void intel_color_get_config(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
 	if (dev_priv->display.read_luts)
 		dev_priv->display.read_luts(crtc_state);
@@ -1055,16 +1055,16 @@ static bool need_plane_update(struct intel_plane *plane,
 static int
 intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_atomic_state *state =
-		to_intel_atomic_state(new_crtc_state->base.state);
+		to_intel_atomic_state(new_crtc_state->uapi.state);
 	const struct intel_crtc_state *old_crtc_state =
 		intel_atomic_get_old_crtc_state(state, crtc);
 	struct intel_plane *plane;
 
 	if (!new_crtc_state->hw.active ||
-	    drm_atomic_crtc_needs_modeset(&new_crtc_state->base))
+	    drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
 		return 0;
 
 	if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
@@ -1107,7 +1107,7 @@ static int check_lut_size(const struct drm_property_blob *lut, int expected)
 
 static int check_luts(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 	int gamma_length, degamma_length;
@@ -1480,7 +1480,7 @@ static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
 
 int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	if (HAS_GMCH(dev_priv)) {
@@ -1586,7 +1586,7 @@ static u32 intel_color_lut_pack(u32 val, u32 bit_precision)
 static struct drm_property_blob *
 i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
@@ -1629,7 +1629,7 @@ static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
 static struct drm_property_blob *
 i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
@@ -1681,7 +1681,7 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
 static struct drm_property_blob *
 chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
@@ -1723,7 +1723,7 @@ static void chv_read_luts(struct intel_crtc_state *crtc_state)
 static struct drm_property_blob *
 ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
@@ -1770,7 +1770,7 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
 static struct drm_property_blob *
 glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int hw_lut_size = ivb_lut_10_size(prec_index);
 	enum pipe pipe = crtc->pipe;
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 399abc3d521e..164af1936d38 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -161,7 +161,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_crt *crt = intel_encoder_to_crt(encoder);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	u32 adpa;
 
@@ -271,7 +271,7 @@ static void hsw_pre_enable_crt(struct intel_encoder *encoder,
 			       const struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
 
 	WARN_ON(!crtc_state->has_pch_encoder);
@@ -288,7 +288,7 @@ static void hsw_enable_crt(struct intel_encoder *encoder,
 			   const struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
 
 	WARN_ON(!crtc_state->has_pch_encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index c8639b92a6da..1b9f68d4c566 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1744,7 +1744,7 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
 			  const struct drm_connector_state *conn_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	u32 temp;
@@ -1806,7 +1806,7 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
 				    bool state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	u32 temp;
@@ -1828,7 +1828,7 @@ void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
 static u32
 intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
@@ -1915,7 +1915,7 @@ intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
 
 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	u32 temp;
@@ -1931,7 +1931,7 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
 static void
 intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	u32 temp;
@@ -1943,7 +1943,7 @@ intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
 
 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
@@ -2241,7 +2241,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 
 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
 	enum port port = encoder->port;
@@ -2259,7 +2259,7 @@ void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
 
 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 	if (cpu_transcoder != TRANSCODER_EDP) {
@@ -3337,7 +3337,7 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
 static void
 tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
 {
-	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
 	u32 val;
 
 	if (!cstate->dc3co_exitline)
@@ -3352,7 +3352,7 @@ static void
 tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
 {
 	u32 val, exit_scanlines;
-	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
 
 	if (!cstate->dc3co_exitline)
 		return;
@@ -3370,7 +3370,7 @@ static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
 					      struct intel_crtc_state *cstate)
 {
 	u32 exit_scanlines;
-	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
 	u32 crtc_vdisplay = cstate->hw.adjusted_mode.crtc_vdisplay;
 
 	cstate->dc3co_exitline = 0;
@@ -3379,7 +3379,7 @@ static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
 		return;
 
 	/* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
-	if (to_intel_crtc(cstate->base.crtc)->pipe != PIPE_A ||
+	if (to_intel_crtc(cstate->uapi.crtc)->pipe != PIPE_A ||
 	    encoder->port != PORT_A)
 		return;
 
@@ -3403,7 +3403,7 @@ static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
 static void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state)
 {
 	u32 val;
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
 	if (INTEL_GEN(dev_priv) < 12)
 		return;
@@ -3649,7 +3649,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *crtc_state,
 				 const struct drm_connector_state *conn_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
@@ -4206,7 +4206,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 			  struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
 	u32 temp, flags = 0;
 
@@ -4373,7 +4373,7 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder,
 				    struct intel_crtc_state *pipe_config,
 				    struct drm_connector_state *conn_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 	int ret;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3106aaf55f17..06c593d56d92 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -516,7 +516,7 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 static bool
 needs_modeset(const struct intel_crtc_state *state)
 {
-	return drm_atomic_crtc_needs_modeset(&state->base);
+	return drm_atomic_crtc_needs_modeset(&state->uapi);
 }
 
 /*
@@ -630,7 +630,7 @@ i9xx_select_p2_div(const struct intel_limit *limit,
 		   const struct intel_crtc_state *crtc_state,
 		   int target)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 		/*
@@ -666,7 +666,7 @@ i9xx_find_best_dpll(const struct intel_limit *limit,
 		    int target, int refclk, struct dpll *match_clock,
 		    struct dpll *best_clock)
 {
-	struct drm_device *dev = crtc_state->base.crtc->dev;
+	struct drm_device *dev = crtc_state->uapi.crtc->dev;
 	struct dpll clock;
 	int err = target;
 
@@ -724,7 +724,7 @@ pnv_find_best_dpll(const struct intel_limit *limit,
 		   int target, int refclk, struct dpll *match_clock,
 		   struct dpll *best_clock)
 {
-	struct drm_device *dev = crtc_state->base.crtc->dev;
+	struct drm_device *dev = crtc_state->uapi.crtc->dev;
 	struct dpll clock;
 	int err = target;
 
@@ -780,7 +780,7 @@ g4x_find_best_dpll(const struct intel_limit *limit,
 		   int target, int refclk, struct dpll *match_clock,
 		   struct dpll *best_clock)
 {
-	struct drm_device *dev = crtc_state->base.crtc->dev;
+	struct drm_device *dev = crtc_state->uapi.crtc->dev;
 	struct dpll clock;
 	int max_n;
 	bool found = false;
@@ -874,7 +874,7 @@ vlv_find_best_dpll(const struct intel_limit *limit,
 		   int target, int refclk, struct dpll *match_clock,
 		   struct dpll *best_clock)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_device *dev = crtc->base.dev;
 	struct dpll clock;
 	unsigned int bestppm = 1000000;
@@ -934,7 +934,7 @@ chv_find_best_dpll(const struct intel_limit *limit,
 		   int target, int refclk, struct dpll *match_clock,
 		   struct dpll *best_clock)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_device *dev = crtc->base.dev;
 	unsigned int best_error_ppm;
 	struct dpll clock;
@@ -1067,7 +1067,7 @@ static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
 static void
 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	if (INTEL_GEN(dev_priv) >= 4) {
@@ -1526,7 +1526,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc,
 
 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
@@ -1617,7 +1617,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 
 static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	i915_reg_t reg;
@@ -1761,7 +1761,7 @@ enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
 
 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
 	/*
 	 * On i965gm the hardware frame counter reads
@@ -1781,7 +1781,7 @@ static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state
 
 static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	drm_crtc_set_max_vblank_count(&crtc->base,
 				      intel_crtc_max_vblank_count(crtc_state));
@@ -1790,7 +1790,7 @@ static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
 
 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 	enum pipe pipe = crtc->pipe;
@@ -1848,7 +1848,7 @@ static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
 
 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 	enum pipe pipe = crtc->pipe;
@@ -3103,14 +3103,14 @@ intel_set_plane_visible(struct intel_crtc_state *crtc_state,
 	plane_state->base.visible = visible;
 
 	if (visible)
-		crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);
+		crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
 	else
-		crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);
+		crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
 }
 
 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	struct drm_plane *plane;
 
 	/*
@@ -3121,7 +3121,7 @@ static void fixup_active_planes(struct intel_crtc_state *crtc_state)
 	crtc_state->active_planes = 0;
 
 	drm_for_each_plane_mask(plane, &dev_priv->drm,
-				crtc_state->base.plane_mask)
+				crtc_state->uapi.plane_mask)
 		crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
 }
 
@@ -3592,7 +3592,7 @@ i9xx_plane_max_stride(struct intel_plane *plane,
 
 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 dspcntr = 0;
 
@@ -3745,7 +3745,7 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
 		return ret;
 
 	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
-						  &crtc_state->base,
+						  &crtc_state->uapi,
 						  DRM_PLANE_HELPER_NO_SCALING,
 						  DRM_PLANE_HELPER_NO_SCALING,
 						  i9xx_plane_has_windowing(plane),
@@ -3921,7 +3921,7 @@ static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
  */
 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct intel_crtc_scaler_state *scaler_state =
 		&crtc_state->scaler_state;
 	int i;
@@ -4116,7 +4116,7 @@ static u32 cnl_plane_ctl_flip(unsigned int reflect)
 
 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	u32 plane_ctl = 0;
 
 	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
@@ -4172,7 +4172,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 
 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	u32 plane_color_ctl = 0;
 
 	if (INTEL_GEN(dev_priv) >= 11)
@@ -4788,7 +4788,7 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
 
 static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
 	enum pipe pipe = intel_crtc->pipe;
 	i915_reg_t reg;
@@ -4949,7 +4949,7 @@ void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
 /* Program iCLKIP clock to the desired frequency */
 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
 	u32 divsel, phaseinc, auxdiv, phasedir = 0;
@@ -5065,7 +5065,7 @@ int lpt_get_iclkip(struct drm_i915_private *dev_priv)
 static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
 						enum pipe pch_transcoder)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
@@ -5108,7 +5108,7 @@ static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool e
 
 static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	switch (crtc->pipe) {
@@ -5138,7 +5138,7 @@ static struct intel_encoder *
 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
 			   const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct drm_connector_state *connector_state;
 	const struct drm_connector *connector;
 	struct intel_encoder *encoder = NULL;
@@ -5170,7 +5170,7 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
 static void ironlake_pch_enable(const struct intel_atomic_state *state,
 				const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	enum pipe pipe = crtc->pipe;
@@ -5254,7 +5254,7 @@ static void ironlake_pch_enable(const struct intel_atomic_state *state,
 static void lpt_pch_enable(const struct intel_atomic_state *state,
 			   const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
@@ -5371,7 +5371,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 	struct intel_crtc_scaler_state *scaler_state =
 		&crtc_state->scaler_state;
 	struct intel_crtc *intel_crtc =
-		to_intel_crtc(crtc_state->base.crtc);
+		to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
@@ -5568,7 +5568,7 @@ static void skylake_scaler_disable(struct intel_crtc *crtc)
 
 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	const struct intel_crtc_scaler_state *scaler_state =
@@ -5605,7 +5605,7 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
 
 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
@@ -5626,7 +5626,7 @@ static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
 
 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
@@ -5662,7 +5662,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
 
 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
@@ -5767,7 +5767,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
 				       const struct intel_crtc_state *new_crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	if (!old_crtc_state->ips_enabled)
@@ -5783,7 +5783,7 @@ static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_s
 	 * Disable IPS before we program the LUT.
 	 */
 	if (IS_HASWELL(dev_priv) &&
-	    (new_crtc_state->base.color_mgmt_changed ||
+	    (new_crtc_state->uapi.color_mgmt_changed ||
 	     new_crtc_state->update_pipe) &&
 	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
 		return true;
@@ -5794,7 +5794,7 @@ static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_s
 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
 				       const struct intel_crtc_state *new_crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	if (!new_crtc_state->ips_enabled)
@@ -5810,7 +5810,7 @@ static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_s
 	 * Re-enable IPS after the LUT has been programmed.
 	 */
 	if (IS_HASWELL(dev_priv) &&
-	    (new_crtc_state->base.color_mgmt_changed ||
+	    (new_crtc_state->uapi.color_mgmt_changed ||
 	     new_crtc_state->update_pipe) &&
 	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
 		return true;
@@ -5851,10 +5851,10 @@ static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv,
 
 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct drm_atomic_state *state = old_crtc_state->base.state;
+	struct drm_atomic_state *state = old_crtc_state->uapi.state;
 	struct intel_crtc_state *pipe_config =
 		intel_atomic_get_new_crtc_state(to_intel_atomic_state(state),
 						crtc);
@@ -5894,10 +5894,10 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 				   struct intel_crtc_state *pipe_config)
 {
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct drm_atomic_state *state = old_crtc_state->base.state;
+	struct drm_atomic_state *state = old_crtc_state->uapi.state;
 	struct drm_plane *primary = crtc->base.primary;
 	struct drm_plane_state *old_primary_state =
 		drm_atomic_get_old_plane_state(state, primary);
@@ -6249,7 +6249,7 @@ static void intel_encoders_update_pipe(struct intel_crtc *crtc,
 
 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
 
 	plane->disable_plane(plane, crtc_state);
@@ -6258,7 +6258,7 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
 				 struct intel_atomic_state *state)
 {
-	struct drm_crtc *crtc = pipe_config->base.crtc;
+	struct drm_crtc *crtc = pipe_config->uapi.crtc;
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -6392,7 +6392,7 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 				struct intel_atomic_state *state)
 {
-	struct drm_crtc *crtc = pipe_config->base.crtc;
+	struct drm_crtc *crtc = pipe_config->uapi.crtc;
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	enum pipe pipe = intel_crtc->pipe, hsw_workaround_pipe;
@@ -6500,7 +6500,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 
 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
@@ -6516,7 +6516,7 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
 				  struct intel_atomic_state *state)
 {
-	struct drm_crtc *crtc = old_crtc_state->base.crtc;
+	struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -6575,7 +6575,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
 				 struct intel_atomic_state *state)
 {
-	struct drm_crtc *crtc = old_crtc_state->base.crtc;
+	struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
@@ -6609,7 +6609,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
 
 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	if (!crtc_state->gmch_pfit.control)
@@ -6745,7 +6745,7 @@ intel_aux_power_domain(struct intel_digital_port *dig_port)
 
 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct drm_encoder *encoder;
 	enum pipe pipe = crtc->pipe;
@@ -6762,7 +6762,7 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
 		mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
 
 	drm_for_each_encoder_mask(encoder, &dev_priv->drm,
-				  crtc_state->base.encoder_mask) {
+				  crtc_state->uapi.encoder_mask) {
 		struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 
 		mask |= BIT_ULL(intel_encoder->power_domain);
@@ -6780,7 +6780,7 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
 static u64
 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum intel_display_power_domain domain;
 	u64 domains, new_domains, old_domains;
@@ -6809,7 +6809,7 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
 				   struct intel_atomic_state *state)
 {
-	struct drm_crtc *crtc = pipe_config->base.crtc;
+	struct drm_crtc *crtc = pipe_config->uapi.crtc;
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -6865,7 +6865,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
 
 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
@@ -6875,7 +6875,7 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
 			     struct intel_atomic_state *state)
 {
-	struct drm_crtc *crtc = pipe_config->base.crtc;
+	struct drm_crtc *crtc = pipe_config->uapi.crtc;
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -6925,7 +6925,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
 
 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	if (!old_crtc_state->gmch_pfit.control)
@@ -6941,7 +6941,7 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
 			      struct intel_atomic_state *state)
 {
-	struct drm_crtc *crtc = old_crtc_state->base.crtc;
+	struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -7140,7 +7140,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
 				     struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct drm_atomic_state *state = pipe_config->base.state;
+	struct drm_atomic_state *state = pipe_config->uapi.state;
 	struct intel_crtc *other_crtc;
 	struct intel_crtc_state *other_crtc_state;
 
@@ -7259,7 +7259,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
 
 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	/* IPS only exists on ULT machines and is tied to pipe A. */
@@ -7289,9 +7289,9 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv =
-		to_i915(crtc_state->base.crtc->dev);
+		to_i915(crtc_state->uapi.crtc->dev);
 	struct intel_atomic_state *intel_state =
-		to_intel_atomic_state(crtc_state->base.state);
+		to_intel_atomic_state(crtc_state->uapi.state);
 
 	if (!hsw_crtc_state_ips_capable(crtc_state))
 		return false;
@@ -7363,7 +7363,7 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
 
 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
 	if (HAS_GMCH(dev_priv))
 		/* FIXME calculate proper pipe pixel rate for GMCH pfit */
@@ -7598,7 +7598,7 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
 					 const struct intel_link_m_n *m_n)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
@@ -7625,7 +7625,7 @@ static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta
 					 const struct intel_link_m_n *m_n,
 					 const struct intel_link_m_n *m2_n2)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	enum transcoder transcoder = crtc_state->cpu_transcoder;
@@ -7938,7 +7938,7 @@ int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
 	if (!pipe_config)
 		return -ENOMEM;
 
-	pipe_config->base.crtc = &crtc->base;
+	pipe_config->uapi.crtc = &crtc->base;
 	pipe_config->pixel_multiplier = 1;
 	pipe_config->dpll = *dpll;
 
@@ -8098,7 +8098,7 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
 
 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
@@ -8160,7 +8160,7 @@ static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
 
 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
@@ -8174,7 +8174,7 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
 
 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 	if (IS_GEN(dev_priv, 2))
@@ -8272,7 +8272,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 
 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 pipeconf;
 
@@ -8718,7 +8718,7 @@ bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
 
 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
@@ -9356,7 +9356,7 @@ void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
 
 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	u32 val;
@@ -9410,7 +9410,7 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
 
 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	u32 val = 0;
@@ -9433,7 +9433,7 @@ static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
 
 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 val = 0;
 
@@ -9619,7 +9619,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_atomic_state *state =
-		to_intel_atomic_state(crtc_state->base.state);
+		to_intel_atomic_state(crtc_state->uapi.state);
 	const struct intel_limit *limit;
 	int refclk = 120000;
 
@@ -10044,7 +10044,7 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_atomic_state *state =
-		to_intel_atomic_state(crtc_state->base.state);
+		to_intel_atomic_state(crtc_state->uapi.state);
 
 	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
 	    INTEL_GEN(dev_priv) >= 11) {
@@ -10615,7 +10615,7 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
 	}
 
 	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
-						  &crtc_state->base,
+						  &crtc_state->uapi,
 						  DRM_PLANE_HELPER_NO_SCALING,
 						  DRM_PLANE_HELPER_NO_SCALING,
 						  true, true);
@@ -10802,7 +10802,7 @@ i9xx_cursor_max_stride(struct intel_plane *plane,
 
 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 cntl = 0;
 
@@ -11219,7 +11219,7 @@ int intel_get_load_detect_pipe(struct drm_connector *connector,
 	if (!mode)
 		mode = &load_detect_mode;
 
-	ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
+	ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, mode);
 	if (ret)
 		goto fail;
 
@@ -11457,7 +11457,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
 		return NULL;
 	}
 
-	crtc_state->base.crtc = &crtc->base;
+	crtc_state->uapi.crtc = &crtc->base;
 
 	if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
 		kfree(crtc_state);
@@ -11528,7 +11528,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
 				    const struct intel_plane_state *old_plane_state,
 				    struct intel_plane_state *plane_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	bool mode_changed = needs_modeset(crtc_state);
@@ -11700,9 +11700,9 @@ static int icl_add_linked_planes(struct intel_atomic_state *state)
 
 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->base.state);
+	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
 	struct intel_plane *plane, *linked;
 	struct intel_plane_state *plane_state;
 	int i;
@@ -11772,9 +11772,9 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
 
 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 	struct intel_atomic_state *state =
-		to_intel_atomic_state(new_crtc_state->base.state);
+		to_intel_atomic_state(new_crtc_state->uapi.state);
 	const struct intel_crtc_state *old_crtc_state =
 		intel_atomic_get_old_crtc_state(state, crtc);
 
@@ -11807,10 +11807,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 	 * when C8 planes are getting enabled/disabled.
 	 */
 	if (c8_planes_changed(crtc_state))
-		crtc_state->base.color_mgmt_changed = true;
+		crtc_state->uapi.color_mgmt_changed = true;
 
 	if (mode_changed || crtc_state->update_pipe ||
-	    crtc_state->base.color_mgmt_changed) {
+	    crtc_state->uapi.color_mgmt_changed) {
 		ret = intel_color_check(crtc_state);
 		if (ret)
 			return ret;
@@ -11928,7 +11928,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
 			  struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	struct drm_atomic_state *state = pipe_config->base.state;
+	struct drm_atomic_state *state = pipe_config->uapi.state;
 	struct drm_connector *connector;
 	struct drm_connector_state *connector_state;
 	int bpp, i;
@@ -12081,7 +12081,7 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 				   struct intel_atomic_state *state,
 				   const char *context)
 {
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct intel_plane_state *plane_state;
 	struct intel_plane *plane;
@@ -12258,7 +12258,7 @@ static int
 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv =
-		to_i915(crtc_state->base.crtc->dev);
+		to_i915(crtc_state->uapi.crtc->dev);
 	struct intel_crtc_state *saved_state;
 
 	saved_state = kzalloc(sizeof(*saved_state), GFP_KERNEL);
@@ -12284,8 +12284,8 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
 	BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
 	BUILD_BUG_ON(offsetof(struct intel_crtc_state, uapi));
 	BUILD_BUG_ON(offsetof(struct intel_crtc_state, hw));
-	memcpy(&crtc_state->base + 1, &saved_state->base + 1,
-	       sizeof(*crtc_state) - sizeof(crtc_state->base));
+	memcpy(&crtc_state->uapi + 1, &saved_state->uapi + 1,
+	       sizeof(*crtc_state) - sizeof(crtc_state->uapi));
 
 	kfree(saved_state);
 	return 0;
@@ -12294,8 +12294,8 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
 static int
 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
 {
-	struct drm_crtc *crtc = pipe_config->base.crtc;
-	struct drm_atomic_state *state = pipe_config->base.state;
+	struct drm_crtc *crtc = pipe_config->uapi.crtc;
+	struct drm_atomic_state *state = pipe_config->uapi.state;
 	struct intel_encoder *encoder;
 	struct drm_connector *connector;
 	struct drm_connector_state *connector_state;
@@ -12560,7 +12560,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 			  const struct intel_crtc_state *pipe_config,
 			  bool fastset)
 {
-	struct drm_i915_private *dev_priv = to_i915(current_config->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
 	bool ret = true;
 	u32 bp_gamma = 0;
 	bool fixup_inherited = fastset &&
@@ -13108,12 +13108,12 @@ verify_crtc_state(struct intel_crtc *crtc,
 	struct drm_atomic_state *state;
 	bool active;
 
-	state = old_crtc_state->base.state;
-	__drm_atomic_helper_crtc_destroy_state(&old_crtc_state->base);
+	state = old_crtc_state->uapi.state;
+	__drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
 	pipe_config = old_crtc_state;
 	memset(pipe_config, 0, sizeof(*pipe_config));
-	pipe_config->base.crtc = &crtc->base;
-	pipe_config->base.state = state;
+	pipe_config->uapi.crtc = &crtc->base;
+	pipe_config->uapi.state = state;
 
 	DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.base.id, crtc->base.name);
 
@@ -13293,7 +13293,7 @@ intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
 static void
 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
@@ -13490,7 +13490,7 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
 	if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
 		return;
 
-	new_crtc_state->base.mode_changed = false;
+	new_crtc_state->uapi.mode_changed = false;
 	new_crtc_state->update_pipe = true;
 
 	/*
@@ -13563,7 +13563,7 @@ static int intel_atomic_check(struct drm_device *dev,
 					    new_crtc_state, i) {
 		if (new_crtc_state->hw.mode.private_flags !=
 		    old_crtc_state->hw.mode.private_flags)
-			new_crtc_state->base.mode_changed = true;
+			new_crtc_state->uapi.mode_changed = true;
 	}
 
 	ret = drm_atomic_helper_check_modeset(dev, &state->base);
@@ -13687,7 +13687,7 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
 			       const struct intel_crtc_state *new_crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	/* drm_atomic_helper_update_legacy_modeset_state might not be called. */
@@ -13732,7 +13732,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
 	 * CRTC was enabled.
 	 */
 	if (!modeset) {
-		if (new_crtc_state->base.color_mgmt_changed ||
+		if (new_crtc_state->uapi.color_mgmt_changed ||
 		    new_crtc_state->update_pipe)
 			intel_color_commit(new_crtc_state);
 
@@ -13938,7 +13938,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
 			 */
 			if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
 						 &old_crtc_state->wm.skl.ddb) &&
-			    !new_crtc_state->base.active_changed &&
+			    !new_crtc_state->uapi.active_changed &&
 			    state->wm_results.dirty_pipes != updated)
 				vbl_wait = true;
 
@@ -14071,12 +14071,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		bool modeset = needs_modeset(new_crtc_state);
 
 		/* Complete events for now disable pipes here. */
-		if (modeset && !new_crtc_state->hw.active && new_crtc_state->base.event) {
+		if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
 			spin_lock_irq(&dev->event_lock);
-			drm_crtc_send_vblank_event(&crtc->base, new_crtc_state->base.event);
+			drm_crtc_send_vblank_event(&crtc->base,
+						   new_crtc_state->uapi.event);
 			spin_unlock_irq(&dev->event_lock);
 
-			new_crtc_state->base.event = NULL;
+			new_crtc_state->uapi.event = NULL;
 		}
 	}
 
@@ -14109,7 +14110,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
 		if (new_crtc_state->hw.active &&
 		    !needs_modeset(new_crtc_state) &&
-		    (new_crtc_state->base.color_mgmt_changed ||
+		    (new_crtc_state->uapi.color_mgmt_changed ||
 		     new_crtc_state->update_pipe))
 			intel_color_load_luts(new_crtc_state);
 	}
@@ -14557,7 +14558,7 @@ int
 skl_max_scale(const struct intel_crtc_state *crtc_state,
 	      const struct drm_format_info *format)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int max_scale;
 	int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
@@ -14566,7 +14567,7 @@ skl_max_scale(const struct intel_crtc_state *crtc_state,
 		return DRM_PLANE_HELPER_NO_SCALING;
 
 	crtc_clock = crtc_state->hw.adjusted_mode.crtc_clock;
-	max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
+	max_dotclk = to_intel_atomic_state(crtc_state->uapi.state)->cdclk.logical.cdclk;
 
 	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
 		max_dotclk *= 2;
@@ -14786,7 +14787,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 
 out_free:
 	if (new_crtc_state)
-		intel_crtc_destroy_state(&crtc->base, &new_crtc_state->base);
+		intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
 	if (ret)
 		intel_plane_destroy_state(&plane->base, &new_plane_state->base);
 	else
@@ -15112,7 +15113,7 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
 		ret = -ENOMEM;
 		goto fail;
 	}
-	__drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->base);
+	__drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->uapi);
 	intel_crtc->config = crtc_state;
 
 	primary = intel_primary_plane_create(dev_priv, pipe);
@@ -16128,7 +16129,7 @@ static int intel_initial_commit(struct drm_device *dev)
 			 * having a proper LUT loaded. Remove once we
 			 * have readout for pipe gamma enable.
 			 */
-			crtc_state->base.color_mgmt_changed = true;
+			crtc_state->uapi.color_mgmt_changed = true;
 		}
 	}
 
@@ -16526,7 +16527,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
 
 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
 	/*
 	 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
@@ -16660,9 +16661,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 		struct intel_crtc_state *crtc_state =
 			to_intel_crtc_state(crtc->base.state);
 
-		__drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
+		__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
 		memset(crtc_state, 0, sizeof(*crtc_state));
-		__drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->base);
+		__drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->uapi);
 
 		crtc_state->hw.active = crtc_state->hw.enable =
 			dev_priv->display.get_pipe_config(crtc, crtc_state);
@@ -16748,9 +16749,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 				 * because anything calling .crtc_disable may
 				 * rely on the connector_mask being accurate.
 				 */
-				crtc_state->base.connector_mask |=
+				crtc_state->uapi.connector_mask |=
 					drm_connector_mask(&connector->base);
-				crtc_state->base.encoder_mask |=
+				crtc_state->uapi.encoder_mask |=
 					drm_encoder_mask(&encoder->base);
 			}
 		} else {
@@ -16778,7 +16779,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 			crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
 			intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
 						    crtc_state);
-			WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->base, &crtc->base.mode));
+			WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc->base.mode));
 
 			/*
 			 * The initial mode needs to be set in order to keep
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 213b0c0cdd67..7d691f6fc369 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2222,7 +2222,7 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
 	const struct drm_display_info *info = &connector->display_info;
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	int ret;
 
 	if (!drm_mode_is_420_only(info, adjusted_mode) ||
@@ -2287,7 +2287,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
 	enum port port = encoder->port;
-	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
 	struct intel_digital_connector_state *intel_conn_state =
 		to_intel_digital_connector_state(conn_state);
@@ -2402,7 +2402,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	enum port port = encoder->port;
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 
 	intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
@@ -3000,7 +3000,7 @@ static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
 				const struct intel_crtc_state *pipe_config)
 {
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	assert_pipe_disabled(dev_priv, crtc->pipe);
@@ -3040,7 +3040,7 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
 				 const struct intel_crtc_state *old_crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	assert_pipe_disabled(dev_priv, crtc->pipe);
@@ -3200,7 +3200,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	u32 tmp, flags = 0;
 	enum port port = encoder->port;
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 
 	if (encoder->type == INTEL_OUTPUT_EDP)
 		pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
@@ -3467,7 +3467,7 @@ static void intel_enable_dp(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	u32 dp_reg = I915_READ(intel_dp->output_reg);
 	enum pipe pipe = crtc->pipe;
 	intel_wakeref_t wakeref;
@@ -3600,7 +3600,7 @@ static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	lockdep_assert_held(&dev_priv->pps_mutex);
 
@@ -4122,7 +4122,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	enum port port = encoder->port;
 	u32 DP = intel_dp->DP;
 
@@ -6874,7 +6874,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
 				    int refresh_rate)
 {
 	struct intel_dp *intel_dp = dev_priv->drrs.dp;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
 
 	if (refresh_rate <= 0) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 7d63f0a79ca1..adf1d3895419 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -42,7 +42,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
 					    struct drm_connector_state *conn_state,
 					    struct link_config_limits *limits)
 {
-	struct drm_atomic_state *state = crtc_state->base.state;
+	struct drm_atomic_state *state = crtc_state->uapi.state;
 	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
 	struct intel_dp *intel_dp = &intel_mst->primary->dp;
 	struct intel_connector *connector =
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 556d1b30f06a..704f38681c4b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -739,7 +739,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
 	u32 val;
 
@@ -783,7 +783,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
 {
 	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum dpio_channel ch = vlv_dport_to_channel(dport);
 	enum pipe pipe = crtc->pipe;
 	unsigned int lane_mask =
@@ -864,7 +864,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum dpio_channel ch = vlv_dport_to_channel(dport);
 	enum pipe pipe = crtc->pipe;
 	int data, i, stagger;
@@ -953,7 +953,7 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *old_crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum pipe pipe = to_intel_crtc(old_crtc_state->base.crtc)->pipe;
+	enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe;
 	u32 val;
 
 	vlv_dpio_get(dev_priv);
@@ -1016,7 +1016,7 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
 {
 	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum dpio_channel port = vlv_dport_to_channel(dport);
 	enum pipe pipe = crtc->pipe;
 
@@ -1046,7 +1046,7 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum dpio_channel port = vlv_dport_to_channel(dport);
 	enum pipe pipe = crtc->pipe;
 	u32 val;
@@ -1075,7 +1075,7 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
 {
 	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	enum dpio_channel port = vlv_dport_to_channel(dport);
 	enum pipe pipe = crtc->pipe;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index ec10fa7d3c69..33db1f59b406 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -136,7 +136,7 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
  */
 void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 
@@ -163,7 +163,7 @@ void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)
  */
 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
@@ -208,7 +208,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
  */
 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
@@ -827,7 +827,7 @@ hsw_ddi_hdmi_get_dpll(struct intel_atomic_state *state,
 static struct intel_shared_dpll *
 hsw_ddi_dp_get_dpll(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	struct intel_shared_dpll *pll;
 	enum intel_dpll_id pll_id;
 	int clock = crtc_state->port_clock;
@@ -1736,7 +1736,7 @@ static bool
 bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
 			  struct bxt_clk_div *clk_div)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct dpll best_clock;
 
 	/* Calculate HDMI div */
@@ -2259,7 +2259,7 @@ static bool
 cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
 			struct skl_wrpll_params *wrpll_params)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	u32 afe_clock = crtc_state->port_clock * 5;
 	u32 ref_clock;
 	u32 dco_min = 7998000;
@@ -2538,7 +2538,7 @@ static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
 static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
 				  struct skl_wrpll_params *pll_params)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	const struct icl_combo_pll_params *params =
 		dev_priv->cdclk.hw.ref == 24000 ?
 		icl_dp_combo_pll_24MHz_values :
@@ -2560,7 +2560,7 @@ static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
 static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
 			     struct skl_wrpll_params *pll_params)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
 	if (INTEL_GEN(dev_priv) >= 12) {
 		switch (dev_priv->cdclk.hw.ref) {
@@ -2597,7 +2597,7 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
 				struct intel_encoder *encoder,
 				struct intel_dpll_hw_state *pll_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	u32 cfgcr0, cfgcr1;
 	struct skl_wrpll_params pll_params = { 0 };
 	bool ret;
@@ -2729,7 +2729,7 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
 static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
 				  struct intel_dpll_hw_state *pll_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	int refclk_khz = dev_priv->cdclk.hw.ref;
 	int clock = crtc_state->port_clock;
 	u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index a68e5c5b91b4..28770c5765ad 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -277,7 +277,7 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder,
 				 const struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
 	enum pipe pipe = crtc->pipe;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 2f5fc71ac9a0..357ad459bfbc 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -285,7 +285,7 @@ static void ibx_write_infoframe(struct intel_encoder *encoder,
 {
 	const u32 *data = frame;
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 	u32 val = I915_READ(reg);
 	int i;
@@ -321,7 +321,7 @@ static void ibx_read_infoframe(struct intel_encoder *encoder,
 			       void *frame, ssize_t len)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	u32 val, *data = frame;
 	int i;
 
@@ -340,7 +340,7 @@ static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
+	enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 	i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 	u32 val = I915_READ(reg);
 
@@ -362,7 +362,7 @@ static void cpt_write_infoframe(struct intel_encoder *encoder,
 {
 	const u32 *data = frame;
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 	u32 val = I915_READ(reg);
 	int i;
@@ -401,7 +401,7 @@ static void cpt_read_infoframe(struct intel_encoder *encoder,
 			       void *frame, ssize_t len)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	u32 val, *data = frame;
 	int i;
 
@@ -420,7 +420,7 @@ static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
+	enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 	u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
 
 	if ((val & VIDEO_DIP_ENABLE) == 0)
@@ -438,7 +438,7 @@ static void vlv_write_infoframe(struct intel_encoder *encoder,
 {
 	const u32 *data = frame;
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 	u32 val = I915_READ(reg);
 	int i;
@@ -474,7 +474,7 @@ static void vlv_read_infoframe(struct intel_encoder *encoder,
 			       void *frame, ssize_t len)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	u32 val, *data = frame;
 	int i;
 
@@ -493,7 +493,7 @@ static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
+	enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 	u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
 
 	if ((val & VIDEO_DIP_ENABLE) == 0)
@@ -965,7 +965,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
 					 const struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	i915_reg_t reg;
 
 	if ((crtc_state->infoframes.enable &
@@ -990,7 +990,7 @@ void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
 				   struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	i915_reg_t reg;
 
 	if ((crtc_state->infoframes.enable &
@@ -1037,7 +1037,7 @@ static void ibx_set_infoframes(struct intel_encoder *encoder,
 			       const struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
@@ -1096,7 +1096,7 @@ static void cpt_set_infoframes(struct intel_encoder *encoder,
 			       const struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 	u32 val = I915_READ(reg);
@@ -1145,7 +1145,7 @@ static void vlv_set_infoframes(struct intel_encoder *encoder,
 			       const struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 	u32 val = I915_READ(reg);
@@ -1741,7 +1741,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder,
 {
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	u32 hdmi_val;
@@ -1865,7 +1865,7 @@ static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
 				    const struct intel_crtc_state *pipe_config,
 				    const struct drm_connector_state *conn_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 
 	WARN_ON(!pipe_config->has_hdmi_sink);
 	DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
@@ -1951,7 +1951,7 @@ static void cpt_enable_hdmi(struct intel_encoder *encoder,
 {
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 	enum pipe pipe = crtc->pipe;
 	u32 temp;
@@ -2015,7 +2015,7 @@ static void intel_disable_hdmi(struct intel_encoder *encoder,
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 	struct intel_digital_port *intel_dig_port =
 		hdmi_to_dig_port(intel_hdmi);
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	u32 temp;
 
 	temp = I915_READ(intel_hdmi->hdmi_reg);
@@ -2215,8 +2215,8 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
 				     int bpc)
 {
 	struct drm_i915_private *dev_priv =
-		to_i915(crtc_state->base.crtc->dev);
-	struct drm_atomic_state *state = crtc_state->base.state;
+		to_i915(crtc_state->uapi.crtc->dev);
+	struct drm_atomic_state *state = crtc_state->uapi.state;
 	struct drm_connector_state *connector_state;
 	struct drm_connector *connector;
 	const struct drm_display_mode *adjusted_mode =
@@ -2245,7 +2245,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
 	for_each_new_connector_in_state(state, connector, connector_state, i) {
 		const struct drm_display_info *info = &connector->display_info;
 
-		if (connector_state->crtc != crtc_state->base.crtc)
+		if (connector_state->crtc != crtc_state->uapi.crtc)
 			continue;
 
 		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
@@ -2286,7 +2286,7 @@ static bool
 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
 			   struct intel_crtc_state *config)
 {
-	struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(config->uapi.crtc);
 
 	if (!connector->ycbcr_420_allowed) {
 		DRM_ERROR("Platform doesn't support YCBCR420 output\n");
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index f17d6e02460f..ca4ebb0f2230 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -230,7 +230,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder,
 {
 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	enum pipe pipe = crtc->pipe;
 	u32 temp;
@@ -393,7 +393,7 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 	struct intel_connector *intel_connector =
 		lvds_encoder->attached_connector;
 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
-	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	unsigned int lvds_bpp;
 
 	/* Should never happen!! */
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 5e3fd37d9471..6f3eaae3761f 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -1047,7 +1047,7 @@ static void vlv_enable_backlight(const struct intel_crtc_state *crtc_state,
 	struct intel_connector *connector = to_intel_connector(conn_state->connector);
 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
-	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
+	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
 	u32 ctl, ctl2;
 
 	ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe));
@@ -1077,7 +1077,7 @@ static void bxt_enable_backlight(const struct intel_crtc_state *crtc_state,
 	struct intel_connector *connector = to_intel_connector(conn_state->connector);
 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
-	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
+	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
 	u32 pwm_ctl, val;
 
 	/* Controller 1 uses the utility pin. */
@@ -1189,7 +1189,7 @@ void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
 	struct intel_connector *connector = to_intel_connector(conn_state->connector);
 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	struct intel_panel *panel = &connector->panel;
-	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
+	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
 
 	if (!panel->backlight.present)
 		return;
diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
index fc602533a602..2746512f4466 100644
--- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
@@ -309,13 +309,13 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
 		goto put_state;
 	}
 
-	pipe_config->base.mode_changed = pipe_config->has_psr;
+	pipe_config->uapi.mode_changed = pipe_config->has_psr;
 	pipe_config->crc_enabled = enable;
 
 	if (IS_HASWELL(dev_priv) &&
 	    pipe_config->hw.active && crtc->pipe == PIPE_A &&
 	    pipe_config->cpu_transcoder == TRANSCODER_EDP)
-		pipe_config->base.mode_changed = true;
+		pipe_config->uapi.mode_changed = true;
 
 	ret = drm_atomic_commit(state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 347004981cff..9c76ad5383b9 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -812,7 +812,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
 
 	dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
 	dev_priv->psr.busy_frontbuffer_bits = 0;
-	dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
+	dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
 	dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
 	dev_priv->psr.dc3co_exit_delay = intel_get_frame_time_us(crtc_state);
 	dev_priv->psr.transcoder = crtc_state->cpu_transcoder;
@@ -1059,7 +1059,7 @@ void intel_psr_update(struct intel_dp *intel_dp,
 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
 			    u32 *out_value)
 {
-	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	if (!dev_priv->psr.enabled || !new_crtc_state->has_psr)
@@ -1141,7 +1141,7 @@ static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
 
 		if (intel_crtc_state->hw.active && intel_crtc_state->has_psr) {
 			/* Mark mode as changed to trigger a pipe->update() */
-			intel_crtc_state->base.mode_changed = true;
+			intel_crtc_state->uapi.mode_changed = true;
 			break;
 		}
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 97ae8cc1314e..1047357c15c4 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -1429,7 +1429,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
 				  const struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	const struct intel_sdvo_connector_state *sdvo_state =
 		to_intel_sdvo_connector_state(conn_state);
@@ -1723,7 +1723,7 @@ static void intel_disable_sdvo(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	u32 temp;
 
 	if (old_crtc_state->has_audio)
@@ -1785,7 +1785,7 @@ static void intel_enable_sdvo(struct intel_encoder *encoder,
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
-	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	u32 temp;
 	bool input1, input2;
 	int i;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index ef0ca7c6d11f..fa687c05b1ed 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -81,7 +81,7 @@ int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  */
 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
 	long timeout = msecs_to_jiffies_timeout(1);
@@ -190,7 +190,7 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
  */
 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
 	int scanline_end = intel_get_crtc_scanline(crtc);
 	u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
@@ -203,14 +203,15 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 	 * Would be slightly nice to just grab the vblank count and arm the
 	 * event outside of the critical section - the spinlock might spin for a
 	 * while ... */
-	if (new_crtc_state->base.event) {
+	if (new_crtc_state->uapi.event) {
 		WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
 
 		spin_lock(&crtc->base.dev->event_lock);
-		drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
+		drm_crtc_arm_vblank_event(&crtc->base,
+				          new_crtc_state->uapi.event);
 		spin_unlock(&crtc->base.dev->event_lock);
 
-		new_crtc_state->base.event = NULL;
+		new_crtc_state->uapi.event = NULL;
 	}
 
 	local_irq_enable();
@@ -1586,7 +1587,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
 	}
 
 	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
-						  &crtc_state->base,
+						  &crtc_state->uapi,
 						  min_scale, max_scale,
 						  true, true);
 	if (ret)
@@ -1643,7 +1644,7 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
 		return ret;
 
 	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
-						  &crtc_state->base,
+						  &crtc_state->uapi,
 						  DRM_PLANE_HELPER_NO_SCALING,
 						  DRM_PLANE_HELPER_NO_SCALING,
 						  true, true);
@@ -1808,7 +1809,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
 	}
 
 	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
-						  &crtc_state->base,
+						  &crtc_state->uapi,
 						  min_scale, max_scale,
 						  true, true);
 	if (ret)
diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
index e800d45b813d..4499d402c316 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.c
+++ b/drivers/gpu/drm/i915/display/intel_tv.c
@@ -924,7 +924,7 @@ intel_enable_tv(struct intel_encoder *encoder,
 
 	/* Prevents vblank waits from timing out in intel_tv_detect_type() */
 	intel_wait_for_vblank(dev_priv,
-			      to_intel_crtc(pipe_config->base.crtc)->pipe);
+			      to_intel_crtc(pipe_config->uapi.crtc)->pipe);
 
 	I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
 }
@@ -1417,7 +1417,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder,
 				const struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct intel_tv *intel_tv = enc_to_tv(encoder);
 	const struct intel_tv_connector_state *tv_conn_state =
 		to_intel_tv_connector_state(conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 6a338a83aaed..38c181499505 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -459,7 +459,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
 enum intel_display_power_domain
 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 	/*
@@ -483,7 +483,7 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
 static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
 						const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
 	enum pipe pipe = crtc->pipe;
@@ -902,7 +902,7 @@ static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
 void intel_dsc_enable(struct intel_encoder *encoder,
 		      const struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum pipe pipe = crtc->pipe;
 	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
@@ -938,7 +938,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
 
 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 3bf838279fc2..16f93d1e71e5 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -261,7 +261,7 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
 	struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 						   base);
 	struct intel_connector *intel_connector = intel_dsi->attached_connector;
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	int ret;
@@ -624,7 +624,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	enum port port;
 
@@ -746,7 +746,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 				 const struct drm_connector_state *conn_state)
 {
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
-	struct drm_crtc *crtc = pipe_config->base.crtc;
+	struct drm_crtc *crtc = pipe_config->uapi.crtc;
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	enum pipe pipe = intel_crtc->pipe;
@@ -1034,7 +1034,7 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
 	struct drm_display_mode *adjusted_mode =
 					&pipe_config->hw.adjusted_mode;
 	struct drm_display_mode *adjusted_mode_sw;
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	unsigned int lane_count = intel_dsi->lane_count;
 	unsigned int bpp, fmt;
@@ -1315,7 +1315,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 	struct drm_encoder *encoder = &intel_encoder->base;
 	struct drm_device *dev = encoder->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	enum port port;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 51e83da21738..bdace2f14cde 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4222,7 +4222,7 @@ static int i915_drrs_ctl_set(void *data, u64 val)
 		    !crtc_state->has_drrs)
 			goto out;
 
-		commit = crtc_state->base.commit;
+		commit = crtc_state->uapi.commit;
 		if (commit) {
 			ret = wait_for_completion_interruptible(&commit->hw_done);
 			if (ret)
@@ -4234,7 +4234,7 @@ static int i915_drrs_ctl_set(void *data, u64 val)
 			struct intel_encoder *encoder;
 			struct intel_dp *intel_dp;
 
-			if (!(crtc_state->base.connector_mask &
+			if (!(crtc_state->uapi.connector_mask &
 			      drm_connector_mask(connector)))
 				continue;
 
@@ -4293,7 +4293,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
 			return ret;
 
 		crtc_state = to_intel_crtc_state(intel_crtc->base.state);
-		commit = crtc_state->base.commit;
+		commit = crtc_state->uapi.commit;
 		if (commit) {
 			ret = wait_for_completion_interruptible(&commit->hw_done);
 			if (!ret)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9671ff29c25f..76f8eea15ddf 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -464,7 +464,7 @@ static const int pessimal_latency_ns = 5000;
 
 static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
 	enum pipe pipe = crtc->pipe;
@@ -1144,7 +1144,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
 static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
 				 int level, enum plane_id plane_id, u16 value)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	bool dirty = false;
 
 	for (; level < intel_wm_num_levels(dev_priv); level++) {
@@ -1160,7 +1160,7 @@ static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
 static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
 			       int level, u16 value)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	bool dirty = false;
 
 	/* NORMAL level doesn't have an FBC watermark */
@@ -1262,7 +1262,7 @@ static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
 static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
 				     int level)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
 	if (level > dev_priv->wm.max_level)
 		return false;
@@ -1300,9 +1300,9 @@ static void g4x_invalidate_wms(struct intel_crtc *crtc,
 
 static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct intel_atomic_state *state =
-		to_intel_atomic_state(crtc_state->base.state);
+		to_intel_atomic_state(crtc_state->uapi.state);
 	struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
 	int num_active_planes = hweight8(crtc_state->active_planes &
 					 ~BIT(PLANE_CURSOR));
@@ -1389,17 +1389,17 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 
 static int g4x_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 	struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;
 	const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;
 	struct intel_atomic_state *intel_state =
-		to_intel_atomic_state(new_crtc_state->base.state);
+		to_intel_atomic_state(new_crtc_state->uapi.state);
 	const struct intel_crtc_state *old_crtc_state =
 		intel_atomic_get_old_crtc_state(intel_state, crtc);
 	const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
 	enum plane_id plane_id;
 
-	if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
+	if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
 		*intermediate = *optimal;
 
 		intermediate->cxsr = false;
@@ -1531,8 +1531,8 @@ static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
 static void g4x_initial_watermarks(struct intel_atomic_state *state,
 				   struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	mutex_lock(&dev_priv->wm.wm_mutex);
 	crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
@@ -1543,8 +1543,8 @@ static void g4x_initial_watermarks(struct intel_atomic_state *state,
 static void g4x_optimize_watermarks(struct intel_atomic_state *state,
 				    struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	if (!crtc_state->wm.need_postvbl_update)
 		return;
@@ -1631,7 +1631,7 @@ static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
 
 static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct g4x_pipe_wm *raw =
 		&crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
 	struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
@@ -1743,7 +1743,7 @@ static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
 static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
 				 int level, enum plane_id plane_id, u16 value)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	int num_levels = intel_wm_num_levels(dev_priv);
 	bool dirty = false;
 
@@ -1818,16 +1818,16 @@ static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
 
 static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_atomic_state *state =
-		to_intel_atomic_state(crtc_state->base.state);
+		to_intel_atomic_state(crtc_state->uapi.state);
 	struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
 	const struct vlv_fifo_state *fifo_state =
 		&crtc_state->wm.vlv.fifo_state;
 	int num_active_planes = hweight8(crtc_state->active_planes &
 					 ~BIT(PLANE_CURSOR));
-	bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base);
+	bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
 	const struct intel_plane_state *old_plane_state;
 	const struct intel_plane_state *new_plane_state;
 	struct intel_plane *plane;
@@ -1926,7 +1926,7 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
 				   struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_uncore *uncore = &dev_priv->uncore;
 	const struct vlv_fifo_state *fifo_state =
@@ -2022,17 +2022,17 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
 
 static int vlv_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 	struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate;
 	const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;
 	struct intel_atomic_state *intel_state =
-		to_intel_atomic_state(new_crtc_state->base.state);
+		to_intel_atomic_state(new_crtc_state->uapi.state);
 	const struct intel_crtc_state *old_crtc_state =
 		intel_atomic_get_old_crtc_state(intel_state, crtc);
 	const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
 	int level;
 
-	if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
+	if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
 		*intermediate = *optimal;
 
 		intermediate->cxsr = false;
@@ -2150,8 +2150,8 @@ static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
 static void vlv_initial_watermarks(struct intel_atomic_state *state,
 				   struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	mutex_lock(&dev_priv->wm.wm_mutex);
 	crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
@@ -2162,8 +2162,8 @@ static void vlv_initial_watermarks(struct intel_atomic_state *state,
 static void vlv_optimize_watermarks(struct intel_atomic_state *state,
 				    struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	if (!crtc_state->wm.need_postvbl_update)
 		return;
@@ -2767,7 +2767,7 @@ static u32
 hsw_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
 {
 	const struct intel_atomic_state *intel_state =
-		to_intel_atomic_state(crtc_state->base.state);
+		to_intel_atomic_state(crtc_state->uapi.state);
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
 	u32 linetime, ips_linetime;
@@ -3082,8 +3082,8 @@ static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
 /* Compute new watermarks for the pipe */
 static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct intel_pipe_wm *pipe_wm;
 	struct intel_plane *plane;
 	const struct intel_plane_state *plane_state;
@@ -3161,11 +3161,11 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
  */
 static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
 {
-	struct intel_crtc *intel_crtc = to_intel_crtc(newstate->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(newstate->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
 	struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
 	struct intel_atomic_state *intel_state =
-		to_intel_atomic_state(newstate->base.state);
+		to_intel_atomic_state(newstate->uapi.state);
 	const struct intel_crtc_state *oldstate =
 		intel_atomic_get_old_crtc_state(intel_state, intel_crtc);
 	const struct intel_pipe_wm *b = &oldstate->wm.ilk.optimal;
@@ -3177,7 +3177,7 @@ static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
 	 * and after the vblank.
 	 */
 	*a = newstate->wm.ilk.optimal;
-	if (!newstate->hw.active || drm_atomic_crtc_needs_modeset(&newstate->base) ||
+	if (!newstate->hw.active || drm_atomic_crtc_needs_modeset(&newstate->uapi) ||
 	    intel_state->skip_intermediate_wm)
 		return 0;
 
@@ -3858,9 +3858,9 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
 				   struct skl_ddb_entry *alloc, /* out */
 				   int *num_active /* out */)
 {
-	struct drm_atomic_state *state = crtc_state->base.state;
+	struct drm_atomic_state *state = crtc_state->uapi.state;
 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-	struct drm_crtc *for_crtc = crtc_state->base.crtc;
+	struct drm_crtc *for_crtc = crtc_state->uapi.crtc;
 	const struct intel_crtc *crtc;
 	u32 pipe_width = 0, total_width = 0, width_before_pipe = 0;
 	enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
@@ -3941,7 +3941,7 @@ static unsigned int
 skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
 		      int num_active)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	int level, max_level = ilk_wm_max_level(dev_priv);
 	struct skl_wm_level wm = {};
 	int ret, min_ddb_alloc = 0;
@@ -4131,7 +4131,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 				  struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
-	struct drm_atomic_state *state = crtc_state->base.state;
+	struct drm_atomic_state *state = crtc_state->uapi.state;
 	const struct intel_plane_state *plane_state;
 	struct intel_plane *plane;
 	int crtc_clock, dotclk;
@@ -4232,7 +4232,7 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
 				 u64 *plane_data_rate,
 				 u64 *uv_plane_data_rate)
 {
-	struct drm_atomic_state *state = crtc_state->base.state;
+	struct drm_atomic_state *state = crtc_state->uapi.state;
 	struct intel_plane *plane;
 	const struct intel_plane_state *plane_state;
 	u64 total_data_rate = 0;
@@ -4267,7 +4267,7 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
 	const struct intel_plane_state *plane_state;
 	u64 total_data_rate = 0;
 
-	if (WARN_ON(!crtc_state->base.state))
+	if (WARN_ON(!crtc_state->uapi.state))
 		return 0;
 
 	/* Calculate and cache data rate for each plane */
@@ -4311,8 +4311,8 @@ static int
 skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 		      struct skl_ddb_allocation *ddb /* out */)
 {
-	struct drm_atomic_state *state = crtc_state->base.state;
-	struct drm_crtc *crtc = crtc_state->base.crtc;
+	struct drm_atomic_state *state = crtc_state->uapi.state;
+	struct drm_crtc *crtc = crtc_state->uapi.crtc;
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
@@ -4619,7 +4619,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
 		      u32 plane_pixel_rate, struct skl_wm_params *wp,
 		      int color_plane)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 interm_pbpl;
 
@@ -4740,7 +4740,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 				 const struct skl_wm_level *result_prev,
 				 struct skl_wm_level *result /* out */)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	u32 latency = dev_priv->wm.skl_latency[level];
 	uint_fixed_16_16_t method1, method2;
 	uint_fixed_16_16_t selected_result;
@@ -4864,7 +4864,7 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
 		      const struct skl_wm_params *wm_params,
 		      struct skl_wm_level *levels)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	int level, max_level = ilk_wm_max_level(dev_priv);
 	struct skl_wm_level *result_prev = &levels[0];
 
@@ -4881,7 +4881,7 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
 static u32
 skl_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_atomic_state *state = crtc_state->base.state;
+	struct drm_atomic_state *state = crtc_state->uapi.state;
 	struct drm_i915_private *dev_priv = to_i915(state->dev);
 	uint_fixed_16_16_t linetime_us;
 	u32 linetime_wm;
@@ -4900,7 +4900,7 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
 				      const struct skl_wm_params *wp,
 				      struct skl_plane_wm *wm)
 {
-	struct drm_device *dev = crtc_state->base.crtc->dev;
+	struct drm_device *dev = crtc_state->uapi.crtc->dev;
 	const struct drm_i915_private *dev_priv = to_i915(dev);
 	u16 trans_min, trans_y_tile_min;
 	const u16 trans_amount = 10; /* This is configurable amount */
@@ -5060,7 +5060,7 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
 
 static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
 	struct intel_plane *plane;
 	const struct intel_plane_state *plane_state;
@@ -5250,8 +5250,8 @@ static int
 skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
 			    struct intel_crtc_state *new_crtc_state)
 {
-	struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->base.state);
-	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+	struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->uapi.state);
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_plane *plane;
 
@@ -5552,7 +5552,7 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
 		 * power well the hardware state will go out of sync
 		 * with the software state.
 		 */
-		if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) &&
+		if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi) &&
 		    skl_plane_wm_equals(dev_priv,
 					&old_crtc_state->wm.skl.optimal.planes[plane_id],
 					&new_crtc_state->wm.skl.optimal.planes[plane_id]))
@@ -5620,7 +5620,7 @@ skl_compute_wm(struct intel_atomic_state *state)
 static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
 				      struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
 	enum pipe pipe = crtc->pipe;
@@ -5634,7 +5634,7 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
 static void skl_initial_wm(struct intel_atomic_state *state,
 			   struct intel_crtc_state *crtc_state)
 {
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct skl_ddb_values *results = &state->wm_results;
@@ -5644,7 +5644,7 @@ static void skl_initial_wm(struct intel_atomic_state *state,
 
 	mutex_lock(&dev_priv->wm.wm_mutex);
 
-	if (crtc_state->base.active_changed)
+	if (crtc_state->uapi.active_changed)
 		skl_atomic_update_crtc_wm(state, crtc_state);
 
 	mutex_unlock(&dev_priv->wm.wm_mutex);
@@ -5703,8 +5703,8 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
 static void ilk_initial_watermarks(struct intel_atomic_state *state,
 				   struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	mutex_lock(&dev_priv->wm.wm_mutex);
 	crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
@@ -5715,8 +5715,8 @@ static void ilk_initial_watermarks(struct intel_atomic_state *state,
 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
 				    struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	if (!crtc_state->wm.need_postvbl_update)
 		return;
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH 08/14] drm/i915: Complete crtc hw/uapi split, v2.
  2019-10-17 13:20 [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Maarten Lankhorst
                   ` (5 preceding siblings ...)
  2019-10-17 13:20 ` [PATCH 07/14] drm/i915: Perform automated conversions for crtc uapi/hw split, base -> uapi Maarten Lankhorst
@ 2019-10-17 13:20 ` Maarten Lankhorst
  2019-10-22 18:32   ` Ville Syrjälä
  2019-10-17 13:21 ` [PATCH 09/14] drm/i915: Add aliases for uapi and hw to plane_state Maarten Lankhorst
                   ` (12 subsequent siblings)
  19 siblings, 1 reply; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-17 13:20 UTC (permalink / raw)
  To: intel-gfx

Now that we separated everything into uapi and hw, it's
time to make the split definitive. Remove the union and
make a copy of the hw state on modeset and fastset.

Color blobs are copied in crtc atomic_check(), right
before color management is checked.

Changes since v1:
- Copy all blobs immediately after drm_atomic_helper_check_modeset().
- Clear crtc_state->hw on disable, instead of using clear_intel_crtc_state().

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic.c   | 44 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_atomic.h   |  2 +
 drivers/gpu/drm/i915/display/intel_display.c  | 45 ++++++++++++++++---
 .../drm/i915/display/intel_display_types.h    |  9 ++--
 4 files changed, 89 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 7cf13b9c7d38..266d0ce9d03d 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -195,6 +195,14 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
 
 	__drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);
 
+	/* copy color blobs */
+	if (crtc_state->hw.degamma_lut)
+		drm_property_blob_get(crtc_state->hw.degamma_lut);
+	if (crtc_state->hw.ctm)
+		drm_property_blob_get(crtc_state->hw.ctm);
+	if (crtc_state->hw.gamma_lut)
+		drm_property_blob_get(crtc_state->hw.gamma_lut);
+
 	crtc_state->update_pipe = false;
 	crtc_state->disable_lp_wm = false;
 	crtc_state->disable_cxsr = false;
@@ -208,6 +216,41 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
 	return &crtc_state->uapi;
 }
 
+static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state)
+{
+	drm_property_blob_put(crtc_state->hw.degamma_lut);
+	drm_property_blob_put(crtc_state->hw.gamma_lut);
+	drm_property_blob_put(crtc_state->hw.ctm);
+}
+
+void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
+{
+	intel_crtc_put_color_blobs(crtc_state);
+}
+
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
+{
+	intel_crtc_put_color_blobs(crtc_state);
+
+	if (crtc_state->uapi.degamma_lut)
+		crtc_state->hw.degamma_lut =
+			drm_property_blob_get(crtc_state->uapi.degamma_lut);
+	else
+		crtc_state->hw.degamma_lut = NULL;
+
+	if (crtc_state->uapi.gamma_lut)
+		crtc_state->hw.gamma_lut =
+			drm_property_blob_get(crtc_state->uapi.gamma_lut);
+	else
+		crtc_state->hw.gamma_lut = NULL;
+
+	if (crtc_state->uapi.ctm)
+		crtc_state->hw.ctm =
+			drm_property_blob_get(crtc_state->uapi.ctm);
+	else
+		crtc_state->hw.ctm = NULL;
+}
+
 /**
  * intel_crtc_destroy_state - destroy crtc state
  * @crtc: drm crtc
@@ -223,6 +266,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
 	struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
 
 	__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
+	intel_crtc_free_hw_state(crtc_state);
 	kfree(crtc_state);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
index 58065d3161a3..42be91e0772a 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -35,6 +35,8 @@ intel_digital_connector_duplicate_state(struct drm_connector *connector);
 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
 void intel_crtc_destroy_state(struct drm_crtc *crtc,
 			       struct drm_crtc_state *state);
+void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
 void intel_atomic_state_clear(struct drm_atomic_state *state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 06c593d56d92..c009489641bd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -114,6 +114,7 @@ static const u64 cursor_format_modifiers[] = {
 	DRM_FORMAT_MOD_INVALID
 };
 
+static void copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state);
 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 				struct intel_crtc_state *pipe_config);
 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
@@ -7041,6 +7042,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
 	crtc->enabled = false;
 	crtc->state->connector_mask = 0;
 	crtc->state->encoder_mask = 0;
+	copy_uapi_to_hw_state(to_intel_crtc_state(crtc->state));
 
 	for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
 		encoder->base.crtc = NULL;
@@ -12254,6 +12256,23 @@ static bool check_digital_port_conflicts(struct intel_atomic_state *state)
 	return ret;
 }
 
+static void copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
+{
+	crtc_state->hw.enable = crtc_state->uapi.enable;
+	crtc_state->hw.active = crtc_state->uapi.active;
+	crtc_state->hw.mode = crtc_state->uapi.mode;
+	crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
+	intel_crtc_copy_color_blobs(crtc_state);
+}
+
+static void copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
+{
+	crtc_state->uapi.enable = crtc_state->hw.enable;
+	crtc_state->uapi.active = crtc_state->hw.active;
+	crtc_state->uapi.mode = crtc_state->hw.mode;
+	crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
+}
+
 static int
 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
 {
@@ -12270,6 +12289,7 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
 	 * fixed, so that the crtc_state can be safely duplicated. For now,
 	 * only fields that are know to not cause problems are preserved. */
 
+	saved_state->uapi = crtc_state->uapi;
 	saved_state->scaler_state = crtc_state->scaler_state;
 	saved_state->shared_dpll = crtc_state->shared_dpll;
 	saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
@@ -12280,12 +12300,9 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
 	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		saved_state->wm = crtc_state->wm;
 
-	/* Keep base drm_crtc_state intact, only clear our extended struct */
-	BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
-	BUILD_BUG_ON(offsetof(struct intel_crtc_state, uapi));
-	BUILD_BUG_ON(offsetof(struct intel_crtc_state, hw));
-	memcpy(&crtc_state->uapi + 1, &saved_state->uapi + 1,
-	       sizeof(*crtc_state) - sizeof(crtc_state->uapi));
+	intel_crtc_free_hw_state(crtc_state);
+	memcpy(crtc_state, saved_state, sizeof(*crtc_state));
+	copy_uapi_to_hw_state(crtc_state);
 
 	kfree(saved_state);
 	return 0;
@@ -12425,6 +12442,9 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
 	DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
 		      base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
 
+	/* uapi wants a copy of the adjusted_mode for vblank bookkeeping */
+	pipe_config->uapi.adjusted_mode = pipe_config->hw.adjusted_mode;
+
 	return 0;
 }
 
@@ -13110,6 +13130,8 @@ verify_crtc_state(struct intel_crtc *crtc,
 
 	state = old_crtc_state->uapi.state;
 	__drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
+	intel_crtc_free_hw_state(old_crtc_state);
+
 	pipe_config = old_crtc_state;
 	memset(pipe_config, 0, sizeof(*pipe_config));
 	pipe_config->uapi.crtc = &crtc->base;
@@ -13572,11 +13594,17 @@ static int intel_atomic_check(struct drm_device *dev,
 
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i) {
-		if (!needs_modeset(new_crtc_state))
+		if (!needs_modeset(new_crtc_state)) {
+			if (new_crtc_state->uapi.color_mgmt_changed)
+				intel_crtc_copy_color_blobs(new_crtc_state);
 			continue;
+		}
 
 		if (!new_crtc_state->uapi.enable) {
 			any_ms = true;
+			intel_crtc_free_hw_state(new_crtc_state);
+			memset(&new_crtc_state->hw, 0,
+			       sizeof(new_crtc_state->hw));
 			continue;
 		}
 
@@ -16662,6 +16690,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 			to_intel_crtc_state(crtc->base.state);
 
 		__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
+		intel_crtc_free_hw_state(crtc_state);
 		memset(crtc_state, 0, sizeof(*crtc_state));
 		__drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->uapi);
 
@@ -16790,6 +16819,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 			 * set a flag to indicate that a full recalculation is
 			 * needed on the next commit.
 			 */
+			crtc_state->hw.mode = crtc->base.mode;
 			crtc_state->hw.mode.private_flags = I915_MODE_FLAG_INHERITED;
 
 			intel_crtc_compute_pixel_rate(crtc_state);
@@ -16820,6 +16850,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 
 		intel_bw_crtc_update(bw_state, crtc_state);
 
+		copy_hw_to_uapi_state(crtc_state);
 		intel_pipe_config_sanity_check(dev_priv, crtc_state);
 	}
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 4d85ea5832d7..41d471ab9a64 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -749,8 +749,6 @@ enum intel_output_format {
 };
 
 struct intel_crtc_state {
-	union {
-	struct drm_crtc_state base;
 	/*
 	 * uapi (drm) state. This is the software state shown to userspace.
 	 * In particular, the following members are used for bookkeeping:
@@ -773,8 +771,11 @@ struct intel_crtc_state {
 	 *
 	 * During initial hw readout, they need to be copied to uapi.
 	 */
-	struct drm_crtc_state hw;
-	};
+	struct {
+		bool active, enable;
+		struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
+		struct drm_display_mode mode, adjusted_mode;
+	} hw;
 
 	/**
 	 * quirks - bitfield with hw state readout quirks
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH 09/14] drm/i915: Add aliases for uapi and hw to plane_state
  2019-10-17 13:20 [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Maarten Lankhorst
                   ` (6 preceding siblings ...)
  2019-10-17 13:20 ` [PATCH 08/14] drm/i915: Complete crtc hw/uapi split, v2 Maarten Lankhorst
@ 2019-10-17 13:21 ` Maarten Lankhorst
  2019-10-17 13:21 ` [PATCH 10/14] drm/i915: Perform manual conversions for plane uapi/hw split Maarten Lankhorst
                   ` (11 subsequent siblings)
  19 siblings, 0 replies; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-17 13:21 UTC (permalink / raw)
  To: intel-gfx

Prepare to split up hw and uapi machinally, by adding a uapi and
hw alias. We will remove the base in a bit. This is a split from the
original uapi/hw patch, which did it all in one go.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 .../gpu/drm/i915/display/intel_atomic_plane.c    | 16 ++++++++--------
 .../gpu/drm/i915/display/intel_display_types.h   |  8 ++++++--
 2 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index d92c185d4b4a..4b12eeb6850d 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -80,22 +80,20 @@ void intel_plane_free(struct intel_plane *plane)
 struct drm_plane_state *
 intel_plane_duplicate_state(struct drm_plane *plane)
 {
-	struct drm_plane_state *state;
 	struct intel_plane_state *intel_state;
 
-	intel_state = kmemdup(plane->state, sizeof(*intel_state), GFP_KERNEL);
+	intel_state = to_intel_plane_state(plane->state);
+	intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL);
 
 	if (!intel_state)
 		return NULL;
 
-	state = &intel_state->base;
-
-	__drm_atomic_helper_plane_duplicate_state(plane, state);
+	__drm_atomic_helper_plane_duplicate_state(plane, &intel_state->base);
 
 	intel_state->vma = NULL;
 	intel_state->flags = 0;
 
-	return state;
+	return &intel_state->base;
 }
 
 /**
@@ -110,9 +108,11 @@ void
 intel_plane_destroy_state(struct drm_plane *plane,
 			  struct drm_plane_state *state)
 {
-	WARN_ON(to_intel_plane_state(state)->vma);
+	struct intel_plane_state *plane_state = to_intel_plane_state(state);
+	WARN_ON(plane_state->vma);
 
-	drm_atomic_helper_plane_destroy_state(plane, state);
+	__drm_atomic_helper_plane_destroy_state(&plane_state->base);
+	kfree(plane_state);
 }
 
 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 41d471ab9a64..9cae42e6520f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -515,7 +515,11 @@ struct intel_atomic_state {
 };
 
 struct intel_plane_state {
-	struct drm_plane_state base;
+	union {
+		struct drm_plane_state base;
+		struct drm_plane_state uapi;
+		struct drm_plane_state hw;
+	};
 	struct i915_ggtt_view view;
 	struct i915_vma *vma;
 	unsigned long flags;
@@ -1125,7 +1129,7 @@ struct cxsr_latency {
 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
-#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
+#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
 
 struct intel_hdmi {
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH 10/14] drm/i915: Perform manual conversions for plane uapi/hw split
  2019-10-17 13:20 [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Maarten Lankhorst
                   ` (7 preceding siblings ...)
  2019-10-17 13:21 ` [PATCH 09/14] drm/i915: Add aliases for uapi and hw to plane_state Maarten Lankhorst
@ 2019-10-17 13:21 ` Maarten Lankhorst
  2019-10-17 13:21 ` [PATCH 11/14] drm/i915: Perform automated conversions for plane uapi/hw split, base -> hw Maarten Lankhorst
                   ` (10 subsequent siblings)
  19 siblings, 0 replies; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-17 13:21 UTC (permalink / raw)
  To: intel-gfx

get_crtc_from_states() is called before plane_state is copied to uapi,
so use the uapi state there.

intel_legacy_cursor_update() could probably get away with looking at
the hw state, but for clarity look at the uapi state always

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 ++++----
 drivers/gpu/drm/i915/display/intel_display.c      | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 4b12eeb6850d..0db20da7781c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -186,11 +186,11 @@ static struct intel_crtc *
 get_crtc_from_states(const struct intel_plane_state *old_plane_state,
 		     const struct intel_plane_state *new_plane_state)
 {
-	if (new_plane_state->base.crtc)
-		return to_intel_crtc(new_plane_state->base.crtc);
+	if (new_plane_state->uapi.crtc)
+		return to_intel_crtc(new_plane_state->uapi.crtc);
 
-	if (old_plane_state->base.crtc)
-		return to_intel_crtc(old_plane_state->base.crtc);
+	if (old_plane_state->uapi.crtc)
+		return to_intel_crtc(old_plane_state->uapi.crtc);
 
 	return NULL;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c009489641bd..76402df8e698 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14748,12 +14748,12 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 	 * take the slowpath. Only changing fb or position should be
 	 * in the fastpath.
 	 */
-	if (old_plane_state->base.crtc != &crtc->base ||
+	if (old_plane_state->uapi.crtc != &crtc->base ||
 	    old_plane_state->base.src_w != src_w ||
 	    old_plane_state->base.src_h != src_h ||
 	    old_plane_state->base.crtc_w != crtc_w ||
 	    old_plane_state->base.crtc_h != crtc_h ||
-	    !old_plane_state->base.fb != !fb)
+	    !old_plane_state->uapi.fb != !fb)
 		goto slow;
 
 	new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH 11/14] drm/i915: Perform automated conversions for plane uapi/hw split, base -> hw.
  2019-10-17 13:20 [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Maarten Lankhorst
                   ` (8 preceding siblings ...)
  2019-10-17 13:21 ` [PATCH 10/14] drm/i915: Perform manual conversions for plane uapi/hw split Maarten Lankhorst
@ 2019-10-17 13:21 ` Maarten Lankhorst
  2019-10-17 13:21 ` [PATCH 12/14] drm/i915: Perform automated conversions for plane uapi/hw split, base -> uapi Maarten Lankhorst
                   ` (9 subsequent siblings)
  19 siblings, 0 replies; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-17 13:21 UTC (permalink / raw)
  To: intel-gfx

Split up plane_state->base to hw. This is done using the following patch:

@@
struct intel_plane_state *T;
identifier x =~ "^(crtc|fb|alpha|pixel_blend_mode|rotation|color_encoding|color_range)$";
@@
-T->base.x
+T->hw.x

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic.c   |   6 +-
 .../gpu/drm/i915/display/intel_atomic_plane.c |   6 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 127 +++++++++---------
 drivers/gpu/drm/i915/display/intel_fbc.c      |   8 +-
 drivers/gpu/drm/i915/display/intel_overlay.c  |   2 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  76 +++++------
 drivers/gpu/drm/i915/intel_pm.c               |  36 ++---
 7 files changed, 131 insertions(+), 130 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 266d0ce9d03d..9ba50fd1116c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -296,9 +296,9 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
 		return;
 
 	/* set scaler mode */
-	if (plane_state && plane_state->base.fb &&
-	    plane_state->base.fb->format->is_yuv &&
-	    plane_state->base.fb->format->num_planes > 1) {
+	if (plane_state && plane_state->hw.fb &&
+	    plane_state->hw.fb->format->is_yuv &&
+	    plane_state->hw.fb->format->num_planes > 1) {
 		struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 		if (IS_GEN(dev_priv, 9) &&
 		    !IS_GEMINILAKE(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 0db20da7781c..fd5a8012859c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -118,7 +118,7 @@ intel_plane_destroy_state(struct drm_plane *plane,
 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
 				   const struct intel_plane_state *plane_state)
 {
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	unsigned int cpp;
 
 	if (!plane_state->base.visible)
@@ -144,7 +144,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 					struct intel_plane_state *new_plane_state)
 {
 	struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
-	const struct drm_framebuffer *fb = new_plane_state->base.fb;
+	const struct drm_framebuffer *fb = new_plane_state->hw.fb;
 	int ret;
 
 	new_crtc_state->active_planes &= ~BIT(plane->id);
@@ -153,7 +153,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 	new_crtc_state->data_rate[plane->id] = 0;
 	new_plane_state->base.visible = false;
 
-	if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
+	if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
 		return 0;
 
 	ret = plane->check_plane(new_crtc_state, new_plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 76402df8e698..91e9fb2b4df8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2189,7 +2189,7 @@ u32 intel_fb_xy_to_linear(int x, int y,
 			  const struct intel_plane_state *state,
 			  int color_plane)
 {
-	const struct drm_framebuffer *fb = state->base.fb;
+	const struct drm_framebuffer *fb = state->hw.fb;
 	unsigned int cpp = fb->format->cpp[color_plane];
 	unsigned int pitch = state->color_plane[color_plane].stride;
 
@@ -2290,8 +2290,8 @@ static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
 					     int color_plane,
 					     u32 old_offset, u32 new_offset)
 {
-	return intel_adjust_aligned_offset(x, y, state->base.fb, color_plane,
-					   state->base.rotation,
+	return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
+					   state->hw.rotation,
 					   state->color_plane[color_plane].stride,
 					   old_offset, new_offset);
 }
@@ -2367,8 +2367,8 @@ static u32 intel_plane_compute_aligned_offset(int *x, int *y,
 {
 	struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
-	const struct drm_framebuffer *fb = state->base.fb;
-	unsigned int rotation = state->base.rotation;
+	const struct drm_framebuffer *fb = state->hw.fb;
+	unsigned int rotation = state->hw.rotation;
 	int pitch = state->color_plane[color_plane].stride;
 	u32 alignment;
 
@@ -2555,7 +2555,7 @@ bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int i;
 
 	/* We don't want to deal with remapping with cursors */
@@ -2594,8 +2594,8 @@ bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
-	unsigned int rotation = plane_state->base.rotation;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+	unsigned int rotation = plane_state->hw.rotation;
 	u32 stride, max_stride;
 
 	/*
@@ -2786,10 +2786,10 @@ intel_plane_remap_gtt(struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv =
 		to_i915(plane_state->base.plane->dev);
-	struct drm_framebuffer *fb = plane_state->base.fb;
+	struct drm_framebuffer *fb = plane_state->hw.fb;
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 	struct intel_rotation_info *info = &plane_state->view.rotated;
-	unsigned int rotation = plane_state->base.rotation;
+	unsigned int rotation = plane_state->hw.rotation;
 	int i, num_planes = fb->format->num_planes;
 	unsigned int tile_size = intel_tile_size(dev_priv);
 	unsigned int src_x, src_y;
@@ -2895,8 +2895,8 @@ static int
 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
 {
 	const struct intel_framebuffer *fb =
-		to_intel_framebuffer(plane_state->base.fb);
-	unsigned int rotation = plane_state->base.rotation;
+		to_intel_framebuffer(plane_state->hw.fb);
+	unsigned int rotation = plane_state->hw.rotation;
 	int i, num_planes;
 
 	if (!fb)
@@ -3196,7 +3196,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
 			continue;
 
 		if (intel_plane_ggtt_offset(state) == plane_config->base) {
-			fb = state->base.fb;
+			fb = state->hw.fb;
 			drm_framebuffer_get(fb);
 			goto valid_fb;
 		}
@@ -3214,11 +3214,11 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
 	return;
 
 valid_fb:
-	intel_state->base.rotation = plane_config->rotation;
+	intel_state->hw.rotation = plane_config->rotation;
 	intel_fill_fb_ggtt_view(&intel_state->view, fb,
-				intel_state->base.rotation);
+				intel_state->hw.rotation);
 	intel_state->color_plane[0].stride =
-		intel_fb_pitch(fb, 0, intel_state->base.rotation);
+		intel_fb_pitch(fb, 0, intel_state->hw.rotation);
 
 	intel_state->vma =
 		intel_pin_and_fence_fb_obj(fb,
@@ -3345,7 +3345,7 @@ static int icl_max_plane_height(void)
 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
 					   int main_x, int main_y, u32 main_offset)
 {
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int hsub = fb->format->hsub;
 	int vsub = fb->format->vsub;
 	int aux_x = plane_state->color_plane[1].x;
@@ -3383,8 +3383,8 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
 static int skl_check_main_surface(struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
-	unsigned int rotation = plane_state->base.rotation;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+	unsigned int rotation = plane_state->hw.rotation;
 	int x = plane_state->base.src.x1 >> 16;
 	int y = plane_state->base.src.y1 >> 16;
 	int w = drm_rect_width(&plane_state->base.src) >> 16;
@@ -3479,8 +3479,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
 
 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 {
-	const struct drm_framebuffer *fb = plane_state->base.fb;
-	unsigned int rotation = plane_state->base.rotation;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+	unsigned int rotation = plane_state->hw.rotation;
 	int max_width = skl_max_plane_width(fb, 1, rotation);
 	int max_height = 4096;
 	int x = plane_state->base.src.x1 >> 17;
@@ -3508,7 +3508,7 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 
 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
 {
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int src_x = plane_state->base.src.x1 >> 16;
 	int src_y = plane_state->base.src.y1 >> 16;
 	int hsub = fb->format->hsub;
@@ -3529,7 +3529,7 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
 
 int skl_check_plane_surface(struct intel_plane_state *plane_state)
 {
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int ret;
 
 	ret = intel_plane_compute_gtt(plane_state);
@@ -3614,8 +3614,8 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
 {
 	struct drm_i915_private *dev_priv =
 		to_i915(plane_state->base.plane->dev);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
-	unsigned int rotation = plane_state->base.rotation;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+	unsigned int rotation = plane_state->hw.rotation;
 	u32 dspcntr;
 
 	dspcntr = DISPLAY_PLANE_ENABLE;
@@ -3699,7 +3699,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
 
 	/* HSW/BDW do this automagically in hardware */
 	if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
-		unsigned int rotation = plane_state->base.rotation;
+		unsigned int rotation = plane_state->hw.rotation;
 		int src_w = drm_rect_width(&plane_state->base.src) >> 16;
 		int src_h = drm_rect_height(&plane_state->base.src) >> 16;
 
@@ -3952,8 +3952,8 @@ static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
 		     int color_plane)
 {
-	const struct drm_framebuffer *fb = plane_state->base.fb;
-	unsigned int rotation = plane_state->base.rotation;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+	unsigned int rotation = plane_state->hw.rotation;
 	u32 stride = plane_state->color_plane[color_plane].stride;
 
 	if (color_plane >= fb->format->num_planes)
@@ -4022,10 +4022,10 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
 
 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
 {
-	if (!plane_state->base.fb->format->has_alpha)
+	if (!plane_state->hw.fb->format->has_alpha)
 		return PLANE_CTL_ALPHA_DISABLE;
 
-	switch (plane_state->base.pixel_blend_mode) {
+	switch (plane_state->hw.pixel_blend_mode) {
 	case DRM_MODE_BLEND_PIXEL_NONE:
 		return PLANE_CTL_ALPHA_DISABLE;
 	case DRM_MODE_BLEND_PREMULTI:
@@ -4033,17 +4033,17 @@ static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
 	case DRM_MODE_BLEND_COVERAGE:
 		return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
 	default:
-		MISSING_CASE(plane_state->base.pixel_blend_mode);
+		MISSING_CASE(plane_state->hw.pixel_blend_mode);
 		return PLANE_CTL_ALPHA_DISABLE;
 	}
 }
 
 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
 {
-	if (!plane_state->base.fb->format->has_alpha)
+	if (!plane_state->hw.fb->format->has_alpha)
 		return PLANE_COLOR_ALPHA_DISABLE;
 
-	switch (plane_state->base.pixel_blend_mode) {
+	switch (plane_state->hw.pixel_blend_mode) {
 	case DRM_MODE_BLEND_PIXEL_NONE:
 		return PLANE_COLOR_ALPHA_DISABLE;
 	case DRM_MODE_BLEND_PREMULTI:
@@ -4051,7 +4051,7 @@ static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state
 	case DRM_MODE_BLEND_COVERAGE:
 		return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
 	default:
-		MISSING_CASE(plane_state->base.pixel_blend_mode);
+		MISSING_CASE(plane_state->hw.pixel_blend_mode);
 		return PLANE_COLOR_ALPHA_DISABLE;
 	}
 }
@@ -4137,8 +4137,8 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 {
 	struct drm_i915_private *dev_priv =
 		to_i915(plane_state->base.plane->dev);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
-	unsigned int rotation = plane_state->base.rotation;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+	unsigned int rotation = plane_state->hw.rotation;
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 	u32 plane_ctl;
 
@@ -4148,10 +4148,10 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 		plane_ctl |= skl_plane_ctl_alpha(plane_state);
 		plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
 
-		if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
+		if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
 			plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
 
-		if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
+		if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 			plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
 	}
 
@@ -4193,7 +4193,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 {
 	struct drm_i915_private *dev_priv =
 		to_i915(plane_state->base.plane->dev);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	u32 plane_color_ctl = 0;
 
@@ -4201,12 +4201,12 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 	plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
 
 	if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
-		if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
+		if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
 			plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
 		else
 			plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
 
-		if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
+		if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 			plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
 	} else if (fb->format->is_yuv) {
 		plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
@@ -5491,7 +5491,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 	struct intel_plane *intel_plane =
 		to_intel_plane(plane_state->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
-	struct drm_framebuffer *fb = plane_state->base.fb;
+	struct drm_framebuffer *fb = plane_state->hw.fb;
 	int ret;
 	bool force_detach = !fb || !plane_state->base.visible;
 	bool need_scaler = false;
@@ -10523,7 +10523,7 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv =
 		to_i915(plane_state->base.plane->dev);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 	u32 base;
 
@@ -10536,7 +10536,7 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
 
 	/* ILK+ do this automagically */
 	if (HAS_GMCH(dev_priv) &&
-	    plane_state->base.rotation & DRM_MODE_ROTATE_180)
+	    plane_state->hw.rotation & DRM_MODE_ROTATE_180)
 		base += (drm_rect_height(&plane_state->base.dst) *
 			 drm_rect_width(&plane_state->base.dst) - 1) * fb->format->cpp[0];
 
@@ -10608,7 +10608,7 @@ static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
 			      struct intel_plane_state *plane_state)
 {
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int ret;
 
 	if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
@@ -10682,7 +10682,7 @@ static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
 			     struct intel_plane_state *plane_state)
 {
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int ret;
 
 	ret = intel_check_cursor(crtc_state, plane_state);
@@ -10848,7 +10848,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
 		return 0;
 	}
 
-	if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
+	if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
 		cntl |= MCURSOR_ROTATE_180;
 
 	return cntl;
@@ -10881,7 +10881,7 @@ static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
 	 * cursors.
 	 */
 	if (HAS_CUR_FBC(dev_priv) &&
-	    plane_state->base.rotation & DRM_MODE_ROTATE_0) {
+	    plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
 		if (height < 8 || height > width)
 			return false;
 	} else {
@@ -10897,7 +10897,7 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	enum pipe pipe = plane->pipe;
 	int ret;
 
@@ -11501,11 +11501,11 @@ static bool intel_wm_need_update(const struct intel_plane_state *cur,
 	if (new->base.visible != cur->base.visible)
 		return true;
 
-	if (!cur->base.fb || !new->base.fb)
+	if (!cur->hw.fb || !new->hw.fb)
 		return false;
 
-	if (cur->base.fb->modifier != new->base.fb->modifier ||
-	    cur->base.rotation != new->base.rotation ||
+	if (cur->hw.fb->modifier != new->hw.fb->modifier ||
+	    cur->hw.rotation != new->hw.rotation ||
 	    drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
 	    drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
 	    drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
@@ -12056,7 +12056,7 @@ static const char *output_formats(enum intel_output_format format)
 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	struct drm_format_name_buf format_name;
 
 	if (!fb) {
@@ -12072,7 +12072,7 @@ static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
 		      drm_get_format_name(fb->format->format, &format_name),
 		      yesno(plane_state->base.visible));
 	DRM_DEBUG_KMS("\trotation: 0x%x, scaler: %d\n",
-		      plane_state->base.rotation, plane_state->scaler_id);
+		      plane_state->hw.rotation, plane_state->scaler_id);
 	if (plane_state->base.visible)
 		DRM_DEBUG_KMS("\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
 			      DRM_RECT_FP_ARG(&plane_state->base.src),
@@ -14238,8 +14238,8 @@ static void intel_atomic_track_fbs(struct intel_atomic_state *state)
 
 	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
 					     new_plane_state, i)
-		intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->base.fb),
-					to_intel_frontbuffer(new_plane_state->base.fb),
+		intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
+					to_intel_frontbuffer(new_plane_state->hw.fb),
 					plane->frontbuffer_bit);
 }
 
@@ -14398,7 +14398,7 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	struct drm_framebuffer *fb = plane_state->base.fb;
+	struct drm_framebuffer *fb = plane_state->hw.fb;
 	struct i915_vma *vma;
 
 	if (plane->id == PLANE_CURSOR &&
@@ -14463,7 +14463,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
 	struct intel_atomic_state *intel_state =
 		to_intel_atomic_state(new_plane_state->base.state);
 	struct drm_i915_private *dev_priv = to_i915(plane->dev);
-	struct drm_framebuffer *fb = new_plane_state->base.fb;
+	struct drm_framebuffer *fb = new_plane_state->hw.fb;
 	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 	struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
 	int ret;
@@ -14531,12 +14531,12 @@ intel_prepare_plane_fb(struct drm_plane *plane,
 
 		fence = dma_resv_get_excl_rcu(obj->base.resv);
 		if (fence) {
-			add_rps_boost_after_vblank(new_plane_state->base.crtc,
+			add_rps_boost_after_vblank(new_plane_state->hw.crtc,
 						   fence);
 			dma_fence_put(fence);
 		}
 	} else {
-		add_rps_boost_after_vblank(new_plane_state->base.crtc,
+		add_rps_boost_after_vblank(new_plane_state->hw.crtc,
 					   new_plane_state->base.fence);
 	}
 
@@ -14786,9 +14786,10 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 	if (ret)
 		goto out_free;
 
-	intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->base.fb), ORIGIN_FLIP);
-	intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->base.fb),
-				to_intel_frontbuffer(new_plane_state->base.fb),
+	intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
+				ORIGIN_FLIP);
+	intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
+				to_intel_frontbuffer(new_plane_state->hw.fb),
 				plane->frontbuffer_bit);
 
 	/* Swap plane state */
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index c6cc3775f3b8..3ea8d010db6c 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -662,7 +662,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_fbc *fbc = &dev_priv->fbc;
 	struct intel_fbc_state_cache *cache = &fbc->state_cache;
-	struct drm_framebuffer *fb = plane_state->base.fb;
+	struct drm_framebuffer *fb = plane_state->hw.fb;
 
 	cache->vma = NULL;
 	cache->flags = 0;
@@ -671,7 +671,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
 
-	cache->plane.rotation = plane_state->base.rotation;
+	cache->plane.rotation = plane_state->hw.rotation;
 	/*
 	 * Src coordinates are already rotated by 270 degrees for
 	 * the 90/270 degree plane rotation cases (to match the
@@ -684,7 +684,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 	cache->plane.adjusted_y = plane_state->color_plane[0].y;
 	cache->plane.y = plane_state->base.src.y1 >> 16;
 
-	cache->plane.pixel_blend_mode = plane_state->base.pixel_blend_mode;
+	cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
 
 	if (!cache->plane.visible)
 		return;
@@ -1047,7 +1047,7 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
 	 * to pipe or plane A. */
 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
 		struct intel_crtc_state *crtc_state;
-		struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
+		struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
 
 		if (!plane->has_fbc)
 			continue;
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index 2360f19f9694..b5f105e346b4 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -668,7 +668,7 @@ static void update_colorkey(struct intel_overlay *overlay,
 		flags |= DST_KEY_ENABLE;
 
 	if (state->base.visible)
-		format = state->base.fb->format->format;
+		format = state->hw.fb->format->format;
 
 	switch (format) {
 	case DRM_FORMAT_C8:
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index fa687c05b1ed..245263031299 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -241,8 +241,8 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 int intel_plane_check_stride(const struct intel_plane_state *plane_state)
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
-	unsigned int rotation = plane_state->base.rotation;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+	unsigned int rotation = plane_state->hw.rotation;
 	u32 stride, max_stride;
 
 	/*
@@ -272,10 +272,10 @@ int intel_plane_check_stride(const struct intel_plane_state *plane_state)
 
 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 {
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	struct drm_rect *src = &plane_state->base.src;
 	u32 src_x, src_y, src_w, src_h, hsub, vsub;
-	bool rotated = drm_rotation_90_or_270(plane_state->base.rotation);
+	bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation);
 
 	/*
 	 * Hardware doesn't handle subpixel coordinates.
@@ -347,7 +347,7 @@ skl_program_scaler(struct intel_plane *plane,
 		   const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	enum pipe pipe = plane->pipe;
 	int scaler_id = plane_state->scaler_id;
 	const struct intel_scaler *scaler =
@@ -493,10 +493,10 @@ icl_program_input_csc(struct intel_plane *plane,
 	};
 	const u16 *csc;
 
-	if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
-		csc = input_csc_matrix[plane_state->base.color_encoding];
+	if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
+		csc = input_csc_matrix[plane_state->hw.color_encoding];
 	else
-		csc = input_csc_matrix_lr[plane_state->base.color_encoding];
+		csc = input_csc_matrix_lr[plane_state->hw.color_encoding];
 
 	I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), ROFF(csc[0]) |
 		      GOFF(csc[1]));
@@ -510,7 +510,7 @@ icl_program_input_csc(struct intel_plane *plane,
 
 	I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
 		      PREOFF_YUV_TO_RGB_HI);
-	if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
+	if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 		I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 0);
 	else
 		I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
@@ -542,8 +542,8 @@ skl_program_plane(struct intel_plane *plane,
 	u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
 	u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
 	struct intel_plane *linked = plane_state->planar_linked_plane;
-	const struct drm_framebuffer *fb = plane_state->base.fb;
-	u8 alpha = plane_state->base.alpha >> 8;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+	u8 alpha = plane_state->hw.alpha >> 8;
 	u32 plane_color_ctl = 0;
 	unsigned long irqflags;
 	u32 keymsk, keymax;
@@ -719,7 +719,7 @@ chv_update_csc(const struct intel_plane_state *plane_state)
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	enum plane_id plane_id = plane->id;
 	/*
 	 * |r|   | c0 c1 c2 |   |cr|
@@ -745,7 +745,7 @@ chv_update_csc(const struct intel_plane_state *plane_state)
 			    0, 4096,  7601,
 		},
 	};
-	const s16 *csc = csc_matrix[plane_state->base.color_encoding];
+	const s16 *csc = csc_matrix[plane_state->hw.color_encoding];
 
 	/* Seems RGB data bypasses the CSC always */
 	if (!fb->format->is_yuv)
@@ -778,13 +778,13 @@ vlv_update_clrc(const struct intel_plane_state *plane_state)
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	enum pipe pipe = plane->pipe;
 	enum plane_id plane_id = plane->id;
 	int contrast, brightness, sh_scale, sh_sin, sh_cos;
 
 	if (fb->format->is_yuv &&
-	    plane_state->base.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
+	    plane_state->hw.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
 		/*
 		 * Expand limited range to full range:
 		 * Contrast is applied first and is used to expand Y range.
@@ -825,8 +825,8 @@ static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
 			  const struct intel_plane_state *plane_state)
 {
-	const struct drm_framebuffer *fb = plane_state->base.fb;
-	unsigned int rotation = plane_state->base.rotation;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+	unsigned int rotation = plane_state->hw.rotation;
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 	u32 sprctl;
 
@@ -871,7 +871,7 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
 		return 0;
 	}
 
-	if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
+	if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
 		sprctl |= SP_YUV_FORMAT_BT709;
 
 	if (fb->modifier == I915_FORMAT_MOD_X_TILED)
@@ -893,7 +893,7 @@ static void vlv_update_gamma(const struct intel_plane_state *plane_state)
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	enum pipe pipe = plane->pipe;
 	enum plane_id plane_id = plane->id;
 	u16 gamma[8];
@@ -1036,8 +1036,8 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
 {
 	struct drm_i915_private *dev_priv =
 		to_i915(plane_state->base.plane->dev);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
-	unsigned int rotation = plane_state->base.rotation;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+	unsigned int rotation = plane_state->hw.rotation;
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 	u32 sprctl;
 
@@ -1072,10 +1072,10 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
 
 	sprctl |= SPRITE_INT_GAMMA_DISABLE;
 
-	if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
+	if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
 		sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
 
-	if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
+	if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 		sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE;
 
 	if (fb->modifier == I915_FORMAT_MOD_X_TILED)
@@ -1270,8 +1270,8 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
 {
 	struct drm_i915_private *dev_priv =
 		to_i915(plane_state->base.plane->dev);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
-	unsigned int rotation = plane_state->base.rotation;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+	unsigned int rotation = plane_state->hw.rotation;
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 	u32 dvscntr;
 
@@ -1304,10 +1304,10 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
 		return 0;
 	}
 
-	if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
+	if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
 		dvscntr |= DVS_YUV_FORMAT_BT709;
 
-	if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
+	if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 		dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE;
 
 	if (fb->modifier == I915_FORMAT_MOD_X_TILED)
@@ -1328,7 +1328,7 @@ static void g4x_update_gamma(const struct intel_plane_state *plane_state)
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	enum pipe pipe = plane->pipe;
 	u16 gamma[8];
 	int i;
@@ -1360,7 +1360,7 @@ static void ilk_update_gamma(const struct intel_plane_state *plane_state)
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	enum pipe pipe = plane->pipe;
 	u16 gamma[17];
 	int i;
@@ -1509,7 +1509,7 @@ static int
 g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
 			 struct intel_plane_state *plane_state)
 {
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	const struct drm_rect *src = &plane_state->base.src;
 	const struct drm_rect *dst = &plane_state->base.dst;
 	int src_x, src_w, src_h, crtc_w, crtc_h;
@@ -1576,7 +1576,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
 	int max_scale = DRM_PLANE_HELPER_NO_SCALING;
 	int ret;
 
-	if (intel_fb_scalable(plane_state->base.fb)) {
+	if (intel_fb_scalable(plane_state->hw.fb)) {
 		if (INTEL_GEN(dev_priv) < 7) {
 			min_scale = 1;
 			max_scale = 16 << 16;
@@ -1620,7 +1620,7 @@ int chv_plane_check_rotation(const struct intel_plane_state *plane_state)
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	unsigned int rotation = plane_state->base.rotation;
+	unsigned int rotation = plane_state->hw.rotation;
 
 	/* CHV ignores the mirror bit when the rotate bit is set :( */
 	if (IS_CHERRYVIEW(dev_priv) &&
@@ -1672,8 +1672,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
-	unsigned int rotation = plane_state->base.rotation;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+	unsigned int rotation = plane_state->hw.rotation;
 	struct drm_format_name_buf format_name;
 
 	if (!fb)
@@ -1773,8 +1773,8 @@ static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_s
 
 static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state)
 {
-	const struct drm_framebuffer *fb = plane_state->base.fb;
-	unsigned int rotation = plane_state->base.rotation;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+	unsigned int rotation = plane_state->hw.rotation;
 	int src_w = drm_rect_width(&plane_state->base.src) >> 16;
 
 	/* Display WA #1106 */
@@ -1793,7 +1793,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int min_scale = DRM_PLANE_HELPER_NO_SCALING;
 	int max_scale = DRM_PLANE_HELPER_NO_SCALING;
 	int ret;
@@ -1835,7 +1835,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
 		return ret;
 
 	/* HW only has 8 bits pixel precision, disable plane if invisible */
-	if (!(plane_state->base.alpha >> 8))
+	if (!(plane_state->hw.alpha >> 8))
 		plane_state->base.visible = false;
 
 	plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 76f8eea15ddf..5020f6ef4d08 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -810,7 +810,7 @@ static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
 	 * around this problem with the watermark code.
 	 */
 	if (plane->id == PLANE_CURSOR)
-		return plane_state->base.fb != NULL;
+		return plane_state->hw.fb != NULL;
 	else
 		return plane_state->base.visible;
 }
@@ -1097,7 +1097,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
 	if (!intel_wm_plane_visible(crtc_state, plane_state))
 		return 0;
 
-	cpp = plane_state->base.fb->format->cpp[0];
+	cpp = plane_state->hw.fb->format->cpp[0];
 
 	/*
 	 * Not 100% sure which way ELK should go here as the
@@ -1317,8 +1317,8 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 	for_each_oldnew_intel_plane_in_state(state, plane,
 					     old_plane_state,
 					     new_plane_state, i) {
-		if (new_plane_state->base.crtc != &crtc->base &&
-		    old_plane_state->base.crtc != &crtc->base)
+		if (new_plane_state->hw.crtc != &crtc->base &&
+		    old_plane_state->hw.crtc != &crtc->base)
 			continue;
 
 		if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state))
@@ -1602,7 +1602,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
 	if (!intel_wm_plane_visible(crtc_state, plane_state))
 		return 0;
 
-	cpp = plane_state->base.fb->format->cpp[0];
+	cpp = plane_state->hw.fb->format->cpp[0];
 	clock = adjusted_mode->crtc_clock;
 	htotal = adjusted_mode->crtc_htotal;
 	width = crtc_state->pipe_src_w;
@@ -1838,8 +1838,8 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 	for_each_oldnew_intel_plane_in_state(state, plane,
 					     old_plane_state,
 					     new_plane_state, i) {
-		if (new_plane_state->base.crtc != &crtc->base &&
-		    old_plane_state->base.crtc != &crtc->base)
+		if (new_plane_state->hw.crtc != &crtc->base &&
+		    old_plane_state->hw.crtc != &crtc->base)
 			continue;
 
 		if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state))
@@ -2484,7 +2484,7 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
 	if (!intel_wm_plane_visible(crtc_state, plane_state))
 		return 0;
 
-	cpp = plane_state->base.fb->format->cpp[0];
+	cpp = plane_state->hw.fb->format->cpp[0];
 
 	method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
 
@@ -2516,7 +2516,7 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
 	if (!intel_wm_plane_visible(crtc_state, plane_state))
 		return 0;
 
-	cpp = plane_state->base.fb->format->cpp[0];
+	cpp = plane_state->hw.fb->format->cpp[0];
 
 	method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
 	method2 = ilk_wm_method2(crtc_state->pixel_rate,
@@ -2542,7 +2542,7 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
 	if (!intel_wm_plane_visible(crtc_state, plane_state))
 		return 0;
 
-	cpp = plane_state->base.fb->format->cpp[0];
+	cpp = plane_state->hw.fb->format->cpp[0];
 
 	return ilk_wm_method2(crtc_state->pixel_rate,
 			      crtc_state->hw.adjusted_mode.crtc_htotal,
@@ -2560,7 +2560,7 @@ static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
 	if (!intel_wm_plane_visible(crtc_state, plane_state))
 		return 0;
 
-	cpp = plane_state->base.fb->format->cpp[0];
+	cpp = plane_state->hw.fb->format->cpp[0];
 
 	return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->base.dst), cpp);
 }
@@ -4150,11 +4150,11 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 		if (!intel_wm_plane_visible(crtc_state, plane_state))
 			continue;
 
-		if (WARN_ON(!plane_state->base.fb))
+		if (WARN_ON(!plane_state->hw.fb))
 			return -EINVAL;
 
 		plane_downscale = skl_plane_downscale_amount(crtc_state, plane_state);
-		bpp = plane_state->base.fb->format->cpp[0] * 8;
+		bpp = plane_state->hw.fb->format->cpp[0] * 8;
 		if (bpp == 64)
 			plane_downscale = mul_fixed16(plane_downscale,
 						      fp_9_div_8);
@@ -4187,7 +4187,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 			     int color_plane)
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	u32 data_rate;
 	u32 width = 0, height = 0;
 	uint_fixed_16_16_t down_scale_amount;
@@ -4708,7 +4708,7 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
 			    const struct intel_plane_state *plane_state,
 			    struct skl_wm_params *wp, int color_plane)
 {
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int width;
 
 	/*
@@ -4720,7 +4720,7 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
 
 	return skl_compute_wm_params(crtc_state, width,
 				     fb->format, fb->modifier,
-				     plane_state->base.rotation,
+				     plane_state->hw.rotation,
 				     skl_adjusted_plane_pixel_rate(crtc_state, plane_state),
 				     wp, color_plane);
 }
@@ -4999,7 +4999,7 @@ static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,
 			      const struct intel_plane_state *plane_state)
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
-	const struct drm_framebuffer *fb = plane_state->base.fb;
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	enum plane_id plane_id = plane->id;
 	int ret;
 
@@ -5032,7 +5032,7 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
 		return 0;
 
 	if (plane_state->planar_linked_plane) {
-		const struct drm_framebuffer *fb = plane_state->base.fb;
+		const struct drm_framebuffer *fb = plane_state->hw.fb;
 		enum plane_id y_plane_id = plane_state->planar_linked_plane->id;
 
 		WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state));
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH 12/14] drm/i915: Perform automated conversions for plane uapi/hw split, base -> uapi.
  2019-10-17 13:20 [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Maarten Lankhorst
                   ` (9 preceding siblings ...)
  2019-10-17 13:21 ` [PATCH 11/14] drm/i915: Perform automated conversions for plane uapi/hw split, base -> hw Maarten Lankhorst
@ 2019-10-17 13:21 ` Maarten Lankhorst
  2019-10-17 13:21 ` [PATCH 13/14] drm/i915: Complete plane hw and uapi split, v2 Maarten Lankhorst
                   ` (8 subsequent siblings)
  19 siblings, 0 replies; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-17 13:21 UTC (permalink / raw)
  To: intel-gfx

Split up plane_state->base to uapi. This is done using the following patch,
ran after the previous commit that splits out any hw references:

@@
struct intel_plane_state *T;
identifier x;
@@
-T->base.x
+T->uapi.x

@@
struct intel_plane_state *T;
@@
-T->base
+T->uapi

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic.c   |   2 +-
 .../gpu/drm/i915/display/intel_atomic_plane.c |  28 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 290 +++++++++---------
 drivers/gpu/drm/i915/display/intel_fbc.c      |  12 +-
 drivers/gpu/drm/i915/display/intel_overlay.c  |   2 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   | 114 +++----
 drivers/gpu/drm/i915/intel_pm.c               |  57 ++--
 7 files changed, 254 insertions(+), 251 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 9ba50fd1116c..4783d7ff4fcf 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -299,7 +299,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
 	if (plane_state && plane_state->hw.fb &&
 	    plane_state->hw.fb->format->is_yuv &&
 	    plane_state->hw.fb->format->num_planes > 1) {
-		struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+		struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 		if (IS_GEN(dev_priv, 9) &&
 		    !IS_GEMINILAKE(dev_priv)) {
 			mode = SKL_PS_SCALER_MODE_NV12;
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index fd5a8012859c..e4044abc2d21 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -56,7 +56,7 @@ struct intel_plane *intel_plane_alloc(void)
 		return ERR_PTR(-ENOMEM);
 	}
 
-	__drm_atomic_helper_plane_reset(&plane->base, &plane_state->base);
+	__drm_atomic_helper_plane_reset(&plane->base, &plane_state->uapi);
 	plane_state->scaler_id = -1;
 
 	return plane;
@@ -88,12 +88,12 @@ intel_plane_duplicate_state(struct drm_plane *plane)
 	if (!intel_state)
 		return NULL;
 
-	__drm_atomic_helper_plane_duplicate_state(plane, &intel_state->base);
+	__drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);
 
 	intel_state->vma = NULL;
 	intel_state->flags = 0;
 
-	return &intel_state->base;
+	return &intel_state->uapi;
 }
 
 /**
@@ -111,7 +111,7 @@ intel_plane_destroy_state(struct drm_plane *plane,
 	struct intel_plane_state *plane_state = to_intel_plane_state(state);
 	WARN_ON(plane_state->vma);
 
-	__drm_atomic_helper_plane_destroy_state(&plane_state->base);
+	__drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
 	kfree(plane_state);
 }
 
@@ -121,7 +121,7 @@ unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	unsigned int cpp;
 
-	if (!plane_state->base.visible)
+	if (!plane_state->uapi.visible)
 		return 0;
 
 	cpp = fb->format->cpp[0];
@@ -143,7 +143,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 					const struct intel_plane_state *old_plane_state,
 					struct intel_plane_state *new_plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
 	const struct drm_framebuffer *fb = new_plane_state->hw.fb;
 	int ret;
 
@@ -151,7 +151,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 	new_crtc_state->nv12_planes &= ~BIT(plane->id);
 	new_crtc_state->c8_planes &= ~BIT(plane->id);
 	new_crtc_state->data_rate[plane->id] = 0;
-	new_plane_state->base.visible = false;
+	new_plane_state->uapi.visible = false;
 
 	if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
 		return 0;
@@ -161,18 +161,18 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 		return ret;
 
 	/* FIXME pre-g4x don't work like this */
-	if (new_plane_state->base.visible)
+	if (new_plane_state->uapi.visible)
 		new_crtc_state->active_planes |= BIT(plane->id);
 
-	if (new_plane_state->base.visible &&
+	if (new_plane_state->uapi.visible &&
 	    drm_format_info_is_yuv_semiplanar(fb->format))
 		new_crtc_state->nv12_planes |= BIT(plane->id);
 
-	if (new_plane_state->base.visible &&
+	if (new_plane_state->uapi.visible &&
 	    fb->format->format == DRM_FORMAT_C8)
 		new_crtc_state->c8_planes |= BIT(plane->id);
 
-	if (new_plane_state->base.visible || old_plane_state->base.visible)
+	if (new_plane_state->uapi.visible || old_plane_state->uapi.visible)
 		new_crtc_state->update_planes |= BIT(plane->id);
 
 	new_crtc_state->data_rate[plane->id] =
@@ -207,7 +207,7 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
 	const struct intel_crtc_state *old_crtc_state;
 	struct intel_crtc_state *new_crtc_state;
 
-	new_plane_state->base.visible = false;
+	new_plane_state->uapi.visible = false;
 	if (!crtc)
 		return 0;
 
@@ -316,7 +316,7 @@ void skl_update_planes_on_crtc(struct intel_atomic_state *state,
 		struct intel_plane_state *new_plane_state =
 			intel_atomic_get_new_plane_state(state, plane);
 
-		if (new_plane_state->base.visible) {
+		if (new_plane_state->uapi.visible) {
 			intel_update_plane(plane, new_crtc_state, new_plane_state);
 		} else if (new_plane_state->planar_slave) {
 			struct intel_plane *master =
@@ -356,7 +356,7 @@ void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
 		    !(update_mask & BIT(plane->id)))
 			continue;
 
-		if (new_plane_state->base.visible)
+		if (new_plane_state->uapi.visible)
 			intel_update_plane(plane, new_crtc_state, new_plane_state);
 		else
 			intel_disable_plane(plane, new_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 91e9fb2b4df8..a09034a1241f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2056,7 +2056,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 
 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 
 	return INTEL_GEN(dev_priv) < 4 ||
@@ -2365,7 +2365,7 @@ static u32 intel_plane_compute_aligned_offset(int *x, int *y,
 					      const struct intel_plane_state *state,
 					      int color_plane)
 {
-	struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
+	struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
 	const struct drm_framebuffer *fb = state->hw.fb;
 	unsigned int rotation = state->hw.rotation;
@@ -2553,7 +2553,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
 
 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int i;
@@ -2593,7 +2593,7 @@ bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
 
 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	unsigned int rotation = plane_state->hw.rotation;
 	u32 stride, max_stride;
@@ -2602,7 +2602,7 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
 	 * No remapping for invisible planes since we don't have
 	 * an actual source viewport to remap.
 	 */
-	if (!plane_state->base.visible)
+	if (!plane_state->uapi.visible)
 		return false;
 
 	if (!intel_plane_can_remap(plane_state))
@@ -2785,7 +2785,7 @@ static void
 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv =
-		to_i915(plane_state->base.plane->dev);
+		to_i915(plane_state->uapi.plane->dev);
 	struct drm_framebuffer *fb = plane_state->hw.fb;
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 	struct intel_rotation_info *info = &plane_state->view.rotated;
@@ -2800,20 +2800,20 @@ intel_plane_remap_gtt(struct intel_plane_state *plane_state)
 	plane_state->view.type = drm_rotation_90_or_270(rotation) ?
 		I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
 
-	src_x = plane_state->base.src.x1 >> 16;
-	src_y = plane_state->base.src.y1 >> 16;
-	src_w = drm_rect_width(&plane_state->base.src) >> 16;
-	src_h = drm_rect_height(&plane_state->base.src) >> 16;
+	src_x = plane_state->uapi.src.x1 >> 16;
+	src_y = plane_state->uapi.src.y1 >> 16;
+	src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
+	src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 
 	WARN_ON(is_ccs_modifier(fb->modifier));
 
 	/* Make src coordinates relative to the viewport */
-	drm_rect_translate(&plane_state->base.src,
+	drm_rect_translate(&plane_state->uapi.src,
 			   -(src_x << 16), -(src_y << 16));
 
 	/* Rotate src coordinates to match rotated GTT view */
 	if (drm_rotation_90_or_270(rotation))
-		drm_rect_rotate(&plane_state->base.src,
+		drm_rect_rotate(&plane_state->uapi.src,
 				src_w << 16, src_h << 16,
 				DRM_MODE_ROTATE_270);
 
@@ -2933,7 +2933,7 @@ intel_plane_compute_gtt(struct intel_plane_state *plane_state)
 
 	/* Rotate src coordinates to match rotated GTT view */
 	if (drm_rotation_90_or_270(rotation))
-		drm_rect_rotate(&plane_state->base.src,
+		drm_rect_rotate(&plane_state->uapi.src,
 				fb->base.width << 16, fb->base.height << 16,
 				DRM_MODE_ROTATE_270);
 
@@ -3099,9 +3099,9 @@ intel_set_plane_visible(struct intel_crtc_state *crtc_state,
 			struct intel_plane_state *plane_state,
 			bool visible)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 
-	plane_state->base.visible = visible;
+	plane_state->uapi.visible = visible;
 
 	if (visible)
 		crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
@@ -3246,8 +3246,8 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
 	plane_state->crtc_w = fb->width;
 	plane_state->crtc_h = fb->height;
 
-	intel_state->base.src = drm_plane_state_src(plane_state);
-	intel_state->base.dst = drm_plane_state_dest(plane_state);
+	intel_state->uapi.src = drm_plane_state_src(plane_state);
+	intel_state->uapi.dst = drm_plane_state_dest(plane_state);
 
 	if (plane_config->tiling)
 		dev_priv->preserve_bios_swizzle = true;
@@ -3382,13 +3382,13 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
 
 static int skl_check_main_surface(struct intel_plane_state *plane_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
+	struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	unsigned int rotation = plane_state->hw.rotation;
-	int x = plane_state->base.src.x1 >> 16;
-	int y = plane_state->base.src.y1 >> 16;
-	int w = drm_rect_width(&plane_state->base.src) >> 16;
-	int h = drm_rect_height(&plane_state->base.src) >> 16;
+	int x = plane_state->uapi.src.x1 >> 16;
+	int y = plane_state->uapi.src.y1 >> 16;
+	int w = drm_rect_width(&plane_state->uapi.src) >> 16;
+	int h = drm_rect_height(&plane_state->uapi.src) >> 16;
 	int max_width;
 	int max_height;
 	u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
@@ -3471,7 +3471,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
 	 * Put the final coordinates back so that the src
 	 * coordinate checks will see the right values.
 	 */
-	drm_rect_translate_to(&plane_state->base.src,
+	drm_rect_translate_to(&plane_state->uapi.src,
 			      x << 16, y << 16);
 
 	return 0;
@@ -3483,10 +3483,10 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 	unsigned int rotation = plane_state->hw.rotation;
 	int max_width = skl_max_plane_width(fb, 1, rotation);
 	int max_height = 4096;
-	int x = plane_state->base.src.x1 >> 17;
-	int y = plane_state->base.src.y1 >> 17;
-	int w = drm_rect_width(&plane_state->base.src) >> 17;
-	int h = drm_rect_height(&plane_state->base.src) >> 17;
+	int x = plane_state->uapi.src.x1 >> 17;
+	int y = plane_state->uapi.src.y1 >> 17;
+	int w = drm_rect_width(&plane_state->uapi.src) >> 17;
+	int h = drm_rect_height(&plane_state->uapi.src) >> 17;
 	u32 offset;
 
 	intel_add_fb_offsets(&x, &y, plane_state, 1);
@@ -3509,8 +3509,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
 {
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
-	int src_x = plane_state->base.src.x1 >> 16;
-	int src_y = plane_state->base.src.y1 >> 16;
+	int src_x = plane_state->uapi.src.x1 >> 16;
+	int src_y = plane_state->uapi.src.y1 >> 16;
 	int hsub = fb->format->hsub;
 	int vsub = fb->format->vsub;
 	int x = src_x / hsub;
@@ -3536,7 +3536,7 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
 	if (ret)
 		return ret;
 
-	if (!plane_state->base.visible)
+	if (!plane_state->uapi.visible)
 		return 0;
 
 	/*
@@ -3613,7 +3613,7 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
 			  const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv =
-		to_i915(plane_state->base.plane->dev);
+		to_i915(plane_state->uapi.plane->dev);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	unsigned int rotation = plane_state->hw.rotation;
 	u32 dspcntr;
@@ -3667,7 +3667,7 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv =
-		to_i915(plane_state->base.plane->dev);
+		to_i915(plane_state->uapi.plane->dev);
 	int src_x, src_y;
 	u32 offset;
 	int ret;
@@ -3676,11 +3676,11 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
 	if (ret)
 		return ret;
 
-	if (!plane_state->base.visible)
+	if (!plane_state->uapi.visible)
 		return 0;
 
-	src_x = plane_state->base.src.x1 >> 16;
-	src_y = plane_state->base.src.y1 >> 16;
+	src_x = plane_state->uapi.src.x1 >> 16;
+	src_y = plane_state->uapi.src.y1 >> 16;
 
 	intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
 
@@ -3694,14 +3694,14 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
 	 * Put the final coordinates back so that the src
 	 * coordinate checks will see the right values.
 	 */
-	drm_rect_translate_to(&plane_state->base.src,
+	drm_rect_translate_to(&plane_state->uapi.src,
 			      src_x << 16, src_y << 16);
 
 	/* HSW/BDW do this automagically in hardware */
 	if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
 		unsigned int rotation = plane_state->hw.rotation;
-		int src_w = drm_rect_width(&plane_state->base.src) >> 16;
-		int src_h = drm_rect_height(&plane_state->base.src) >> 16;
+		int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
+		int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 
 		if (rotation & DRM_MODE_ROTATE_180) {
 			src_x += src_w - 1;
@@ -3738,14 +3738,14 @@ static int
 i9xx_plane_check(struct intel_crtc_state *crtc_state,
 		 struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	int ret;
 
 	ret = chv_plane_check_rotation(plane_state);
 	if (ret)
 		return ret;
 
-	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
+	ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
 						  &crtc_state->uapi,
 						  DRM_PLANE_HELPER_NO_SCALING,
 						  DRM_PLANE_HELPER_NO_SCALING,
@@ -3758,7 +3758,7 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
 	if (ret)
 		return ret;
 
-	if (!plane_state->base.visible)
+	if (!plane_state->uapi.visible)
 		return 0;
 
 	ret = intel_plane_check_src_coordinates(plane_state);
@@ -3779,10 +3779,10 @@ static void i9xx_update_plane(struct intel_plane *plane,
 	u32 linear_offset;
 	int x = plane_state->color_plane[0].x;
 	int y = plane_state->color_plane[0].y;
-	int crtc_x = plane_state->base.dst.x1;
-	int crtc_y = plane_state->base.dst.y1;
-	int crtc_w = drm_rect_width(&plane_state->base.dst);
-	int crtc_h = drm_rect_height(&plane_state->base.dst);
+	int crtc_x = plane_state->uapi.dst.x1;
+	int crtc_y = plane_state->uapi.dst.y1;
+	int crtc_w = drm_rect_width(&plane_state->uapi.dst);
+	int crtc_h = drm_rect_height(&plane_state->uapi.dst);
 	unsigned long irqflags;
 	u32 dspaddr_offset;
 	u32 dspcntr;
@@ -4136,7 +4136,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 		  const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv =
-		to_i915(plane_state->base.plane->dev);
+		to_i915(plane_state->uapi.plane->dev);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	unsigned int rotation = plane_state->hw.rotation;
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
@@ -4192,9 +4192,9 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 			const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv =
-		to_i915(plane_state->base.plane->dev);
+		to_i915(plane_state->uapi.plane->dev);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	u32 plane_color_ctl = 0;
 
 	plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
@@ -5489,11 +5489,11 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 				   struct intel_plane_state *plane_state)
 {
 	struct intel_plane *intel_plane =
-		to_intel_plane(plane_state->base.plane);
+		to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
 	struct drm_framebuffer *fb = plane_state->hw.fb;
 	int ret;
-	bool force_detach = !fb || !plane_state->base.visible;
+	bool force_detach = !fb || !plane_state->uapi.visible;
 	bool need_scaler = false;
 
 	/* Pre-gen11 and SDR planes always need a scaler for planar formats. */
@@ -5504,10 +5504,10 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 	ret = skl_update_scaler(crtc_state, force_detach,
 				drm_plane_index(&intel_plane->base),
 				&plane_state->scaler_id,
-				drm_rect_width(&plane_state->base.src) >> 16,
-				drm_rect_height(&plane_state->base.src) >> 16,
-				drm_rect_width(&plane_state->base.dst),
-				drm_rect_height(&plane_state->base.dst),
+				drm_rect_width(&plane_state->uapi.src) >> 16,
+				drm_rect_height(&plane_state->uapi.src) >> 16,
+				drm_rect_width(&plane_state->uapi.dst),
+				drm_rect_height(&plane_state->uapi.dst),
 				fb ? fb->format : NULL, need_scaler);
 
 	if (ret || plane_state->scaler_id < 0)
@@ -5920,7 +5920,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 		 * So disable underrun reporting before all the planes get disabled.
 		 */
 		if (IS_GEN(dev_priv, 2) && old_primary_state->visible &&
-		    (modeset || !new_primary_state->base.visible))
+		    (modeset || !new_primary_state->uapi.visible))
 			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
 	}
 
@@ -6007,7 +6007,7 @@ static void intel_crtc_disable_planes(struct intel_atomic_state *state,
 
 		intel_disable_plane(plane, new_crtc_state);
 
-		if (old_plane_state->base.visible)
+		if (old_plane_state->uapi.visible)
 			fb_bits |= plane->frontbuffer_bit;
 	}
 
@@ -7010,7 +7010,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
 		const struct intel_plane_state *plane_state =
 			to_intel_plane_state(plane->base.state);
 
-		if (plane_state->base.visible)
+		if (plane_state->uapi.visible)
 			intel_plane_disable_noatomic(intel_crtc, plane);
 	}
 
@@ -10522,7 +10522,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv =
-		to_i915(plane_state->base.plane->dev);
+		to_i915(plane_state->uapi.plane->dev);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 	u32 base;
@@ -10537,16 +10537,16 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
 	/* ILK+ do this automagically */
 	if (HAS_GMCH(dev_priv) &&
 	    plane_state->hw.rotation & DRM_MODE_ROTATE_180)
-		base += (drm_rect_height(&plane_state->base.dst) *
-			 drm_rect_width(&plane_state->base.dst) - 1) * fb->format->cpp[0];
+		base += (drm_rect_height(&plane_state->uapi.dst) *
+			 drm_rect_width(&plane_state->uapi.dst) - 1) * fb->format->cpp[0];
 
 	return base;
 }
 
 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
 {
-	int x = plane_state->base.dst.x1;
-	int y = plane_state->base.dst.y1;
+	int x = plane_state->uapi.dst.x1;
+	int y = plane_state->uapi.dst.y1;
 	u32 pos = 0;
 
 	if (x < 0) {
@@ -10567,9 +10567,9 @@ static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
 {
 	const struct drm_mode_config *config =
-		&plane_state->base.plane->dev->mode_config;
-	int width = drm_rect_width(&plane_state->base.dst);
-	int height = drm_rect_height(&plane_state->base.dst);
+		&plane_state->uapi.plane->dev->mode_config;
+	int width = drm_rect_width(&plane_state->uapi.dst);
+	int height = drm_rect_height(&plane_state->uapi.dst);
 
 	return width > 0 && width <= config->cursor_width &&
 		height > 0 && height <= config->cursor_height;
@@ -10585,11 +10585,11 @@ static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
 	if (ret)
 		return ret;
 
-	if (!plane_state->base.visible)
+	if (!plane_state->uapi.visible)
 		return 0;
 
-	src_x = plane_state->base.src.x1 >> 16;
-	src_y = plane_state->base.src.y1 >> 16;
+	src_x = plane_state->uapi.src.x1 >> 16;
+	src_y = plane_state->uapi.src.y1 >> 16;
 
 	intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
 	offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
@@ -10616,7 +10616,7 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
 		return -EINVAL;
 	}
 
-	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
+	ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
 						  &crtc_state->uapi,
 						  DRM_PLANE_HELPER_NO_SCALING,
 						  DRM_PLANE_HELPER_NO_SCALING,
@@ -10625,14 +10625,14 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
 		return ret;
 
 	/* Use the unclipped src/dst rectangles, which we program to hw */
-	plane_state->base.src = drm_plane_state_src(&plane_state->base);
-	plane_state->base.dst = drm_plane_state_dest(&plane_state->base);
+	plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
+	plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
 
 	ret = intel_cursor_check_surface(plane_state);
 	if (ret)
 		return ret;
 
-	if (!plane_state->base.visible)
+	if (!plane_state->uapi.visible)
 		return 0;
 
 	ret = intel_plane_check_src_coordinates(plane_state);
@@ -10670,7 +10670,7 @@ static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
 
 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
 {
-	int width = drm_rect_width(&plane_state->base.dst);
+	int width = drm_rect_width(&plane_state->uapi.dst);
 
 	/*
 	 * 845g/865g are only limited by the width of their cursors,
@@ -10696,12 +10696,12 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state,
 	/* Check for which cursor types we support */
 	if (!i845_cursor_size_ok(plane_state)) {
 		DRM_DEBUG("Cursor dimension %dx%d not supported\n",
-			  drm_rect_width(&plane_state->base.dst),
-			  drm_rect_height(&plane_state->base.dst));
+			  drm_rect_width(&plane_state->uapi.dst),
+			  drm_rect_height(&plane_state->uapi.dst));
 		return -EINVAL;
 	}
 
-	WARN_ON(plane_state->base.visible &&
+	WARN_ON(plane_state->uapi.visible &&
 		plane_state->color_plane[0].stride != fb->pitches[0]);
 
 	switch (fb->pitches[0]) {
@@ -10729,9 +10729,9 @@ static void i845_update_cursor(struct intel_plane *plane,
 	u32 cntl = 0, base = 0, pos = 0, size = 0;
 	unsigned long irqflags;
 
-	if (plane_state && plane_state->base.visible) {
-		unsigned int width = drm_rect_width(&plane_state->base.src);
-		unsigned int height = drm_rect_height(&plane_state->base.dst);
+	if (plane_state && plane_state->uapi.visible) {
+		unsigned int width = drm_rect_width(&plane_state->uapi.src);
+		unsigned int height = drm_rect_height(&plane_state->uapi.dst);
 
 		cntl = plane_state->ctl |
 			i845_cursor_ctl_crtc(crtc_state);
@@ -10827,13 +10827,13 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
 			   const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv =
-		to_i915(plane_state->base.plane->dev);
+		to_i915(plane_state->uapi.plane->dev);
 	u32 cntl = 0;
 
 	if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
 		cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
 
-	switch (drm_rect_width(&plane_state->base.dst)) {
+	switch (drm_rect_width(&plane_state->uapi.dst)) {
 	case 64:
 		cntl |= MCURSOR_MODE_64_ARGB_AX;
 		break;
@@ -10844,7 +10844,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
 		cntl |= MCURSOR_MODE_256_ARGB_AX;
 		break;
 	default:
-		MISSING_CASE(drm_rect_width(&plane_state->base.dst));
+		MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
 		return 0;
 	}
 
@@ -10857,9 +10857,9 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv =
-		to_i915(plane_state->base.plane->dev);
-	int width = drm_rect_width(&plane_state->base.dst);
-	int height = drm_rect_height(&plane_state->base.dst);
+		to_i915(plane_state->uapi.plane->dev);
+	int width = drm_rect_width(&plane_state->uapi.dst);
+	int height = drm_rect_height(&plane_state->uapi.dst);
 
 	if (!intel_cursor_size_ok(plane_state))
 		return false;
@@ -10895,7 +10895,7 @@ static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
 			     struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	enum pipe pipe = plane->pipe;
@@ -10912,19 +10912,19 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
 	/* Check for which cursor types we support */
 	if (!i9xx_cursor_size_ok(plane_state)) {
 		DRM_DEBUG("Cursor dimension %dx%d not supported\n",
-			  drm_rect_width(&plane_state->base.dst),
-			  drm_rect_height(&plane_state->base.dst));
+			  drm_rect_width(&plane_state->uapi.dst),
+			  drm_rect_height(&plane_state->uapi.dst));
 		return -EINVAL;
 	}
 
-	WARN_ON(plane_state->base.visible &&
+	WARN_ON(plane_state->uapi.visible &&
 		plane_state->color_plane[0].stride != fb->pitches[0]);
 
 	if (fb->pitches[0] !=
-	    drm_rect_width(&plane_state->base.dst) * fb->format->cpp[0]) {
+	    drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
 		DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
 			      fb->pitches[0],
-			      drm_rect_width(&plane_state->base.dst));
+			      drm_rect_width(&plane_state->uapi.dst));
 		return -EINVAL;
 	}
 
@@ -10939,7 +10939,7 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
 	 * Refuse the put the cursor into that compromised position.
 	 */
 	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
-	    plane_state->base.visible && plane_state->base.dst.x1 < 0) {
+	    plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
 		DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
 		return -EINVAL;
 	}
@@ -10958,9 +10958,9 @@ static void i9xx_update_cursor(struct intel_plane *plane,
 	u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
 	unsigned long irqflags;
 
-	if (plane_state && plane_state->base.visible) {
-		unsigned width = drm_rect_width(&plane_state->base.dst);
-		unsigned height = drm_rect_height(&plane_state->base.dst);
+	if (plane_state && plane_state->uapi.visible) {
+		unsigned width = drm_rect_width(&plane_state->uapi.dst);
+		unsigned height = drm_rect_height(&plane_state->uapi.dst);
 
 		cntl = plane_state->ctl |
 			i9xx_cursor_ctl_crtc(crtc_state);
@@ -11498,7 +11498,7 @@ static bool intel_wm_need_update(const struct intel_plane_state *cur,
 				 struct intel_plane_state *new)
 {
 	/* Update watermarks on tiling or size changes. */
-	if (new->base.visible != cur->base.visible)
+	if (new->uapi.visible != cur->uapi.visible)
 		return true;
 
 	if (!cur->hw.fb || !new->hw.fb)
@@ -11506,10 +11506,10 @@ static bool intel_wm_need_update(const struct intel_plane_state *cur,
 
 	if (cur->hw.fb->modifier != new->hw.fb->modifier ||
 	    cur->hw.rotation != new->hw.rotation ||
-	    drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
-	    drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
-	    drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
-	    drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
+	    drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
+	    drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
+	    drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
+	    drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
 		return true;
 
 	return false;
@@ -11517,10 +11517,10 @@ static bool intel_wm_need_update(const struct intel_plane_state *cur,
 
 static bool needs_scaling(const struct intel_plane_state *state)
 {
-	int src_w = drm_rect_width(&state->base.src) >> 16;
-	int src_h = drm_rect_height(&state->base.src) >> 16;
-	int dst_w = drm_rect_width(&state->base.dst);
-	int dst_h = drm_rect_height(&state->base.dst);
+	int src_w = drm_rect_width(&state->uapi.src) >> 16;
+	int src_h = drm_rect_height(&state->uapi.src) >> 16;
+	int dst_w = drm_rect_width(&state->uapi.dst);
+	int dst_h = drm_rect_height(&state->uapi.dst);
 
 	return (src_w != dst_w || src_h != dst_h);
 }
@@ -11531,7 +11531,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
 				    struct intel_plane_state *plane_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	bool mode_changed = needs_modeset(crtc_state);
 	bool was_crtc_enabled = old_crtc_state->hw.active;
@@ -11545,8 +11545,8 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
 			return ret;
 	}
 
-	was_visible = old_plane_state->base.visible;
-	visible = plane_state->base.visible;
+	was_visible = old_plane_state->uapi.visible;
+	visible = plane_state->uapi.visible;
 
 	if (!was_crtc_enabled && WARN_ON(was_visible))
 		was_visible = false;
@@ -11562,7 +11562,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
 	 * only combine the results from all planes in the current place?
 	 */
 	if (!is_crtc_enabled) {
-		plane_state->base.visible = visible = false;
+		plane_state->uapi.visible = visible = false;
 		crtc_state->active_planes &= ~BIT(plane->id);
 		crtc_state->data_rate[plane->id] = 0;
 	}
@@ -11721,7 +11721,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
 			continue;
 
 		plane_state->planar_linked_plane = NULL;
-		if (plane_state->planar_slave && !plane_state->base.visible) {
+		if (plane_state->planar_slave && !plane_state->uapi.visible) {
 			crtc_state->active_planes &= ~BIT(plane->id);
 			crtc_state->update_planes |= BIT(plane->id);
 		}
@@ -12055,14 +12055,14 @@ static const char *output_formats(enum intel_output_format format)
 
 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	struct drm_format_name_buf format_name;
 
 	if (!fb) {
 		DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
 			      plane->base.base.id, plane->base.name,
-			      yesno(plane_state->base.visible));
+			      yesno(plane_state->uapi.visible));
 		return;
 	}
 
@@ -12070,13 +12070,13 @@ static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
 		      plane->base.base.id, plane->base.name,
 		      fb->base.id, fb->width, fb->height,
 		      drm_get_format_name(fb->format->format, &format_name),
-		      yesno(plane_state->base.visible));
+		      yesno(plane_state->uapi.visible));
 	DRM_DEBUG_KMS("\trotation: 0x%x, scaler: %d\n",
 		      plane_state->hw.rotation, plane_state->scaler_id);
-	if (plane_state->base.visible)
+	if (plane_state->uapi.visible)
 		DRM_DEBUG_KMS("\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
-			      DRM_RECT_FP_ARG(&plane_state->base.src),
-			      DRM_RECT_ARG(&plane_state->base.dst));
+			      DRM_RECT_FP_ARG(&plane_state->uapi.src),
+			      DRM_RECT_ARG(&plane_state->uapi.dst));
 }
 
 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
@@ -13197,7 +13197,7 @@ intel_verify_planes(struct intel_atomic_state *state)
 	for_each_new_intel_plane_in_state(state, plane,
 					  plane_state, i)
 		assert_plane(plane, plane_state->planar_slave ||
-			     plane_state->base.visible);
+			     plane_state->uapi.visible);
 }
 
 static void
@@ -14396,7 +14396,7 @@ static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
 
 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	struct drm_framebuffer *fb = plane_state->hw.fb;
 	struct i915_vma *vma;
@@ -14461,7 +14461,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
 	struct intel_plane_state *new_plane_state =
 		to_intel_plane_state(_new_plane_state);
 	struct intel_atomic_state *intel_state =
-		to_intel_atomic_state(new_plane_state->base.state);
+		to_intel_atomic_state(new_plane_state->uapi.state);
 	struct drm_i915_private *dev_priv = to_i915(plane->dev);
 	struct drm_framebuffer *fb = new_plane_state->hw.fb;
 	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
@@ -14494,9 +14494,9 @@ intel_prepare_plane_fb(struct drm_plane *plane,
 		}
 	}
 
-	if (new_plane_state->base.fence) { /* explicit fencing */
+	if (new_plane_state->uapi.fence) { /* explicit fencing */
 		ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
-						    new_plane_state->base.fence,
+						    new_plane_state->uapi.fence,
 						    I915_FENCE_TIMEOUT,
 						    GFP_KERNEL);
 		if (ret < 0)
@@ -14519,7 +14519,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
 	fb_obj_bump_render_priority(obj);
 	intel_frontbuffer_flush(obj->frontbuffer, ORIGIN_DIRTYFB);
 
-	if (!new_plane_state->base.fence) { /* implicit fencing */
+	if (!new_plane_state->uapi.fence) { /* implicit fencing */
 		struct dma_fence *fence;
 
 		ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
@@ -14537,7 +14537,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
 		}
 	} else {
 		add_rps_boost_after_vblank(new_plane_state->hw.crtc,
-					   new_plane_state->base.fence);
+					   new_plane_state->uapi.fence);
 	}
 
 	/*
@@ -14570,7 +14570,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
 	struct intel_plane_state *old_plane_state =
 		to_intel_plane_state(_old_plane_state);
 	struct intel_atomic_state *intel_state =
-		to_intel_atomic_state(old_plane_state->base.state);
+		to_intel_atomic_state(old_plane_state->uapi.state);
 	struct drm_i915_private *dev_priv = to_i915(plane->dev);
 
 	if (intel_state->rps_interactive) {
@@ -14739,8 +14739,8 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 	 * the plane.  This prevents our async update's changes from getting
 	 * overridden by a previous synchronous update's state.
 	 */
-	if (old_plane_state->base.commit &&
-	    !try_wait_for_completion(&old_plane_state->base.commit->hw_done))
+	if (old_plane_state->uapi.commit &&
+	    !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
 		goto slow;
 
 	/*
@@ -14749,10 +14749,10 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 	 * in the fastpath.
 	 */
 	if (old_plane_state->uapi.crtc != &crtc->base ||
-	    old_plane_state->base.src_w != src_w ||
-	    old_plane_state->base.src_h != src_h ||
-	    old_plane_state->base.crtc_w != crtc_w ||
-	    old_plane_state->base.crtc_h != crtc_h ||
+	    old_plane_state->uapi.src_w != src_w ||
+	    old_plane_state->uapi.src_h != src_h ||
+	    old_plane_state->uapi.crtc_w != crtc_w ||
+	    old_plane_state->uapi.crtc_h != crtc_h ||
 	    !old_plane_state->uapi.fb != !fb)
 		goto slow;
 
@@ -14766,16 +14766,16 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 		goto out_free;
 	}
 
-	drm_atomic_set_fb_for_plane(&new_plane_state->base, fb);
+	drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
 
-	new_plane_state->base.src_x = src_x;
-	new_plane_state->base.src_y = src_y;
-	new_plane_state->base.src_w = src_w;
-	new_plane_state->base.src_h = src_h;
-	new_plane_state->base.crtc_x = crtc_x;
-	new_plane_state->base.crtc_y = crtc_y;
-	new_plane_state->base.crtc_w = crtc_w;
-	new_plane_state->base.crtc_h = crtc_h;
+	new_plane_state->uapi.src_x = src_x;
+	new_plane_state->uapi.src_y = src_y;
+	new_plane_state->uapi.src_w = src_w;
+	new_plane_state->uapi.src_h = src_h;
+	new_plane_state->uapi.crtc_x = crtc_x;
+	new_plane_state->uapi.crtc_y = crtc_y;
+	new_plane_state->uapi.crtc_w = crtc_w;
+	new_plane_state->uapi.crtc_h = crtc_h;
 
 	ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
 						  old_plane_state, new_plane_state);
@@ -14793,7 +14793,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 				plane->frontbuffer_bit);
 
 	/* Swap plane state */
-	plane->base.state = &new_plane_state->base;
+	plane->base.state = &new_plane_state->uapi;
 
 	/*
 	 * We cannot swap crtc_state as it may be in use by an atomic commit or
@@ -14807,7 +14807,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 	 */
 	crtc_state->active_planes = new_crtc_state->active_planes;
 
-	if (new_plane_state->base.visible)
+	if (new_plane_state->uapi.visible)
 		intel_update_plane(plane, crtc_state, new_plane_state);
 	else
 		intel_disable_plane(plane, crtc_state);
@@ -14818,9 +14818,11 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 	if (new_crtc_state)
 		intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
 	if (ret)
-		intel_plane_destroy_state(&plane->base, &new_plane_state->base);
+		intel_plane_destroy_state(&plane->base,
+					  &new_plane_state->uapi);
 	else
-		intel_plane_destroy_state(&plane->base, &old_plane_state->base);
+		intel_plane_destroy_state(&plane->base,
+					  &old_plane_state->uapi);
 	return ret;
 
 slow:
@@ -16505,7 +16507,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
 			const struct intel_plane_state *plane_state =
 				to_intel_plane_state(plane->base.state);
 
-			if (plane_state->base.visible &&
+			if (plane_state->uapi.visible &&
 			    plane->base.type != DRM_PLANE_TYPE_PRIMARY)
 				intel_plane_disable_noatomic(crtc, plane);
 		}
@@ -16844,7 +16846,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 			 * FIXME don't have the fb yet, so can't
 			 * use intel_plane_data_rate() :(
 			 */
-			if (plane_state->base.visible)
+			if (plane_state->uapi.visible)
 				crtc_state->data_rate[plane->id] =
 					4 * crtc_state->pixel_rate;
 		}
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 3ea8d010db6c..92c7eb243559 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -430,7 +430,7 @@ static bool multiple_pipes_ok(struct intel_crtc *crtc,
 	if (!no_fbc_on_multiple_pipes(dev_priv))
 		return true;
 
-	if (plane_state->base.visible)
+	if (plane_state->uapi.visible)
 		fbc->visible_pipes_mask |= (1 << pipe);
 	else
 		fbc->visible_pipes_mask &= ~(1 << pipe);
@@ -677,12 +677,12 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 	 * the 90/270 degree plane rotation cases (to match the
 	 * GTT mapping), hence no need to account for rotation here.
 	 */
-	cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
-	cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
-	cache->plane.visible = plane_state->base.visible;
+	cache->plane.src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
+	cache->plane.src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
+	cache->plane.visible = plane_state->uapi.visible;
 	cache->plane.adjusted_x = plane_state->color_plane[0].x;
 	cache->plane.adjusted_y = plane_state->color_plane[0].y;
-	cache->plane.y = plane_state->base.src.y1 >> 16;
+	cache->plane.y = plane_state->uapi.src.y1 >> 16;
 
 	cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
 
@@ -1052,7 +1052,7 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
 		if (!plane->has_fbc)
 			continue;
 
-		if (!plane_state->base.visible)
+		if (!plane_state->uapi.visible)
 			continue;
 
 		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index b5f105e346b4..502b37ee6d25 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -667,7 +667,7 @@ static void update_colorkey(struct intel_overlay *overlay,
 	if (overlay->color_key_enabled)
 		flags |= DST_KEY_ENABLE;
 
-	if (state->base.visible)
+	if (state->uapi.visible)
 		format = state->hw.fb->format->format;
 
 	switch (format) {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 245263031299..00f83d37abcf 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -240,7 +240,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 
 int intel_plane_check_stride(const struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	unsigned int rotation = plane_state->hw.rotation;
 	u32 stride, max_stride;
@@ -252,7 +252,7 @@ int intel_plane_check_stride(const struct intel_plane_state *plane_state)
 	 * kick in due the plane being invisible.
 	 */
 	if (intel_plane_can_remap(plane_state) &&
-	    !plane_state->base.visible)
+	    !plane_state->uapi.visible)
 		return 0;
 
 	/* FIXME other color planes? */
@@ -273,7 +273,7 @@ int intel_plane_check_stride(const struct intel_plane_state *plane_state)
 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 {
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
-	struct drm_rect *src = &plane_state->base.src;
+	struct drm_rect *src = &plane_state->uapi.src;
 	u32 src_x, src_y, src_w, src_h, hsub, vsub;
 	bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation);
 
@@ -352,19 +352,19 @@ skl_program_scaler(struct intel_plane *plane,
 	int scaler_id = plane_state->scaler_id;
 	const struct intel_scaler *scaler =
 		&crtc_state->scaler_state.scalers[scaler_id];
-	int crtc_x = plane_state->base.dst.x1;
-	int crtc_y = plane_state->base.dst.y1;
-	u32 crtc_w = drm_rect_width(&plane_state->base.dst);
-	u32 crtc_h = drm_rect_height(&plane_state->base.dst);
+	int crtc_x = plane_state->uapi.dst.x1;
+	int crtc_y = plane_state->uapi.dst.y1;
+	u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
+	u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
 	u16 y_hphase, uv_rgb_hphase;
 	u16 y_vphase, uv_rgb_vphase;
 	int hscale, vscale;
 
-	hscale = drm_rect_calc_hscale(&plane_state->base.src,
-				      &plane_state->base.dst,
+	hscale = drm_rect_calc_hscale(&plane_state->uapi.src,
+				      &plane_state->uapi.dst,
 				      0, INT_MAX);
-	vscale = drm_rect_calc_vscale(&plane_state->base.src,
-				      &plane_state->base.dst,
+	vscale = drm_rect_calc_vscale(&plane_state->uapi.src,
+				      &plane_state->uapi.dst,
 				      0, INT_MAX);
 
 	/* TODO: handle sub-pixel coordinates */
@@ -535,12 +535,12 @@ skl_program_plane(struct intel_plane *plane,
 	u32 surf_addr = plane_state->color_plane[color_plane].offset;
 	u32 stride = skl_plane_stride(plane_state, color_plane);
 	u32 aux_stride = skl_plane_stride(plane_state, 1);
-	int crtc_x = plane_state->base.dst.x1;
-	int crtc_y = plane_state->base.dst.y1;
+	int crtc_x = plane_state->uapi.dst.x1;
+	int crtc_y = plane_state->uapi.dst.y1;
 	u32 x = plane_state->color_plane[color_plane].x;
 	u32 y = plane_state->color_plane[color_plane].y;
-	u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
-	u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
+	u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
+	u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 	struct intel_plane *linked = plane_state->planar_linked_plane;
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	u8 alpha = plane_state->hw.alpha >> 8;
@@ -717,7 +717,7 @@ static void i9xx_plane_linear_gamma(u16 gamma[8])
 static void
 chv_update_csc(const struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	enum plane_id plane_id = plane->id;
@@ -776,7 +776,7 @@ chv_update_csc(const struct intel_plane_state *plane_state)
 static void
 vlv_update_clrc(const struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	enum pipe pipe = plane->pipe;
@@ -891,7 +891,7 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
 
 static void vlv_update_gamma(const struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	enum pipe pipe = plane->pipe;
@@ -925,10 +925,10 @@ vlv_update_plane(struct intel_plane *plane,
 	u32 sprsurf_offset = plane_state->color_plane[0].offset;
 	u32 linear_offset;
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
-	int crtc_x = plane_state->base.dst.x1;
-	int crtc_y = plane_state->base.dst.y1;
-	u32 crtc_w = drm_rect_width(&plane_state->base.dst);
-	u32 crtc_h = drm_rect_height(&plane_state->base.dst);
+	int crtc_x = plane_state->uapi.dst.x1;
+	int crtc_y = plane_state->uapi.dst.y1;
+	u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
+	u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
 	u32 x = plane_state->color_plane[0].x;
 	u32 y = plane_state->color_plane[0].y;
 	unsigned long irqflags;
@@ -1035,7 +1035,7 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
 			  const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv =
-		to_i915(plane_state->base.plane->dev);
+		to_i915(plane_state->uapi.plane->dev);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	unsigned int rotation = plane_state->hw.rotation;
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
@@ -1105,7 +1105,7 @@ static void ivb_sprite_linear_gamma(u16 gamma[18])
 
 static void ivb_update_gamma(const struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum pipe pipe = plane->pipe;
 	u16 gamma[18];
@@ -1141,14 +1141,14 @@ ivb_update_plane(struct intel_plane *plane,
 	u32 sprsurf_offset = plane_state->color_plane[0].offset;
 	u32 linear_offset;
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
-	int crtc_x = plane_state->base.dst.x1;
-	int crtc_y = plane_state->base.dst.y1;
-	u32 crtc_w = drm_rect_width(&plane_state->base.dst);
-	u32 crtc_h = drm_rect_height(&plane_state->base.dst);
+	int crtc_x = plane_state->uapi.dst.x1;
+	int crtc_y = plane_state->uapi.dst.y1;
+	u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
+	u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
 	u32 x = plane_state->color_plane[0].x;
 	u32 y = plane_state->color_plane[0].y;
-	u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
-	u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
+	u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
+	u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 	u32 sprctl, sprscale = 0;
 	unsigned long irqflags;
 
@@ -1269,7 +1269,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
 			  const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv =
-		to_i915(plane_state->base.plane->dev);
+		to_i915(plane_state->uapi.plane->dev);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	unsigned int rotation = plane_state->hw.rotation;
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
@@ -1326,7 +1326,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
 
 static void g4x_update_gamma(const struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	enum pipe pipe = plane->pipe;
@@ -1358,7 +1358,7 @@ static void ilk_sprite_linear_gamma(u16 gamma[17])
 
 static void ilk_update_gamma(const struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	enum pipe pipe = plane->pipe;
@@ -1394,14 +1394,14 @@ g4x_update_plane(struct intel_plane *plane,
 	u32 dvssurf_offset = plane_state->color_plane[0].offset;
 	u32 linear_offset;
 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
-	int crtc_x = plane_state->base.dst.x1;
-	int crtc_y = plane_state->base.dst.y1;
-	u32 crtc_w = drm_rect_width(&plane_state->base.dst);
-	u32 crtc_h = drm_rect_height(&plane_state->base.dst);
+	int crtc_x = plane_state->uapi.dst.x1;
+	int crtc_y = plane_state->uapi.dst.y1;
+	u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
+	u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
 	u32 x = plane_state->color_plane[0].x;
 	u32 y = plane_state->color_plane[0].y;
-	u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
-	u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
+	u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
+	u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 	u32 dvscntr, dvsscale = 0;
 	unsigned long irqflags;
 
@@ -1510,8 +1510,8 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
 			 struct intel_plane_state *plane_state)
 {
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
-	const struct drm_rect *src = &plane_state->base.src;
-	const struct drm_rect *dst = &plane_state->base.dst;
+	const struct drm_rect *src = &plane_state->uapi.src;
+	const struct drm_rect *dst = &plane_state->uapi.dst;
 	int src_x, src_w, src_h, crtc_w, crtc_h;
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
@@ -1570,7 +1570,7 @@ static int
 g4x_sprite_check(struct intel_crtc_state *crtc_state,
 		 struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	int min_scale = DRM_PLANE_HELPER_NO_SCALING;
 	int max_scale = DRM_PLANE_HELPER_NO_SCALING;
@@ -1586,7 +1586,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
 		}
 	}
 
-	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
+	ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
 						  &crtc_state->uapi,
 						  min_scale, max_scale,
 						  true, true);
@@ -1597,7 +1597,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
 	if (ret)
 		return ret;
 
-	if (!plane_state->base.visible)
+	if (!plane_state->uapi.visible)
 		return 0;
 
 	ret = intel_plane_check_src_coordinates(plane_state);
@@ -1618,7 +1618,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
 
 int chv_plane_check_rotation(const struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	unsigned int rotation = plane_state->hw.rotation;
 
@@ -1643,7 +1643,7 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
 	if (ret)
 		return ret;
 
-	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
+	ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
 						  &crtc_state->uapi,
 						  DRM_PLANE_HELPER_NO_SCALING,
 						  DRM_PLANE_HELPER_NO_SCALING,
@@ -1655,7 +1655,7 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
 	if (ret)
 		return ret;
 
-	if (!plane_state->base.visible)
+	if (!plane_state->uapi.visible)
 		return 0;
 
 	ret = intel_plane_check_src_coordinates(plane_state);
@@ -1670,7 +1670,7 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 			      const struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	unsigned int rotation = plane_state->hw.rotation;
@@ -1745,9 +1745,9 @@ static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_s
 					   const struct intel_plane_state *plane_state)
 {
 	struct drm_i915_private *dev_priv =
-		to_i915(plane_state->base.plane->dev);
-	int crtc_x = plane_state->base.dst.x1;
-	int crtc_w = drm_rect_width(&plane_state->base.dst);
+		to_i915(plane_state->uapi.plane->dev);
+	int crtc_x = plane_state->uapi.dst.x1;
+	int crtc_w = drm_rect_width(&plane_state->uapi.dst);
 	int pipe_src_w = crtc_state->pipe_src_w;
 
 	/*
@@ -1775,7 +1775,7 @@ static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_s
 {
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	unsigned int rotation = plane_state->hw.rotation;
-	int src_w = drm_rect_width(&plane_state->base.src) >> 16;
+	int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 
 	/* Display WA #1106 */
 	if (drm_format_info_is_yuv_semiplanar(fb->format) && src_w & 3 &&
@@ -1791,7 +1791,7 @@ static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_s
 static int skl_plane_check(struct intel_crtc_state *crtc_state,
 			   struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int min_scale = DRM_PLANE_HELPER_NO_SCALING;
@@ -1808,7 +1808,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
 		max_scale = skl_max_scale(crtc_state, fb->format);
 	}
 
-	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
+	ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
 						  &crtc_state->uapi,
 						  min_scale, max_scale,
 						  true, true);
@@ -1819,7 +1819,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
 	if (ret)
 		return ret;
 
-	if (!plane_state->base.visible)
+	if (!plane_state->uapi.visible)
 		return 0;
 
 	ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);
@@ -1836,7 +1836,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
 
 	/* HW only has 8 bits pixel precision, disable plane if invisible */
 	if (!(plane_state->hw.alpha >> 8))
-		plane_state->base.visible = false;
+		plane_state->uapi.visible = false;
 
 	plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
 
@@ -1855,7 +1855,7 @@ static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv)
 static void intel_plane_set_ckey(struct intel_plane_state *plane_state,
 				 const struct drm_intel_sprite_colorkey *set)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5020f6ef4d08..7cc2517b80f2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -795,7 +795,7 @@ static int intel_wm_num_levels(struct drm_i915_private *dev_priv)
 static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
 				   const struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 
 	/* FIXME check the 'enable' instead */
 	if (!crtc_state->hw.active)
@@ -812,7 +812,7 @@ static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
 	if (plane->id == PLANE_CURSOR)
 		return plane_state->hw.fb != NULL;
 	else
-		return plane_state->base.visible;
+		return plane_state->uapi.visible;
 }
 
 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
@@ -1084,7 +1084,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
 			  const struct intel_plane_state *plane_state,
 			  int level)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
@@ -1117,7 +1117,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
 	clock = adjusted_mode->crtc_clock;
 	htotal = adjusted_mode->crtc_htotal;
 
-	width = drm_rect_width(&plane_state->base.dst);
+	width = drm_rect_width(&plane_state->uapi.dst);
 
 	if (plane->id == PLANE_CURSOR) {
 		wm = intel_wm_method2(clock, htotal, width, cpp, latency);
@@ -1183,7 +1183,7 @@ static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
 static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
 				     const struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
 	enum plane_id plane_id = plane->id;
 	bool dirty = false;
@@ -1590,7 +1590,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
 				const struct intel_plane_state *plane_state,
 				int level)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
@@ -1760,7 +1760,7 @@ static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
 static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
 				     const struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	enum plane_id plane_id = plane->id;
 	int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
 	int level;
@@ -2493,7 +2493,7 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
 
 	method2 = ilk_wm_method2(crtc_state->pixel_rate,
 				 crtc_state->hw.adjusted_mode.crtc_htotal,
-				 drm_rect_width(&plane_state->base.dst),
+				 drm_rect_width(&plane_state->uapi.dst),
 				 cpp, mem_value);
 
 	return min(method1, method2);
@@ -2521,7 +2521,7 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
 	method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
 	method2 = ilk_wm_method2(crtc_state->pixel_rate,
 				 crtc_state->hw.adjusted_mode.crtc_htotal,
-				 drm_rect_width(&plane_state->base.dst),
+				 drm_rect_width(&plane_state->uapi.dst),
 				 cpp, mem_value);
 	return min(method1, method2);
 }
@@ -2546,7 +2546,7 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
 
 	return ilk_wm_method2(crtc_state->pixel_rate,
 			      crtc_state->hw.adjusted_mode.crtc_htotal,
-			      drm_rect_width(&plane_state->base.dst),
+			      drm_rect_width(&plane_state->uapi.dst),
 			      cpp, mem_value);
 }
 
@@ -2562,7 +2562,8 @@ static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
 
 	cpp = plane_state->hw.fb->format->cpp[0];
 
-	return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->base.dst), cpp);
+	return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->uapi.dst),
+			  cpp);
 }
 
 static unsigned int
@@ -3106,10 +3107,10 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 
 	pipe_wm->pipe_enabled = crtc_state->hw.active;
 	if (sprstate) {
-		pipe_wm->sprites_enabled = sprstate->base.visible;
-		pipe_wm->sprites_scaled = sprstate->base.visible &&
-			(drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
-			 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
+		pipe_wm->sprites_enabled = sprstate->uapi.visible;
+		pipe_wm->sprites_scaled = sprstate->uapi.visible &&
+			(drm_rect_width(&sprstate->uapi.dst) != drm_rect_width(&sprstate->uapi.src) >> 16 ||
+			 drm_rect_height(&sprstate->uapi.dst) != drm_rect_height(&sprstate->uapi.src) >> 16);
 	}
 
 	usable_level = max_level;
@@ -4081,10 +4082,10 @@ skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
 	 *
 	 * n.b., src is 16.16 fixed point, dst is whole integer.
 	 */
-	src_w = drm_rect_width(&plane_state->base.src) >> 16;
-	src_h = drm_rect_height(&plane_state->base.src) >> 16;
-	dst_w = drm_rect_width(&plane_state->base.dst);
-	dst_h = drm_rect_height(&plane_state->base.dst);
+	src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
+	src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
+	dst_w = drm_rect_width(&plane_state->uapi.dst);
+	dst_h = drm_rect_height(&plane_state->uapi.dst);
 
 	fp_w_ratio = div_fixed16(src_w, dst_w);
 	fp_h_ratio = div_fixed16(src_h, dst_h);
@@ -4186,14 +4187,14 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 			     const struct intel_plane_state *plane_state,
 			     int color_plane)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	u32 data_rate;
 	u32 width = 0, height = 0;
 	uint_fixed_16_16_t down_scale_amount;
 	u64 rate;
 
-	if (!plane_state->base.visible)
+	if (!plane_state->uapi.visible)
 		return 0;
 
 	if (plane->id == PLANE_CURSOR)
@@ -4208,8 +4209,8 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 	 * the 90/270 degree plane rotation cases (to match the
 	 * GTT mapping), hence no need to account for rotation here.
 	 */
-	width = drm_rect_width(&plane_state->base.src) >> 16;
-	height = drm_rect_height(&plane_state->base.src) >> 16;
+	width = drm_rect_width(&plane_state->uapi.src) >> 16;
+	height = drm_rect_height(&plane_state->uapi.src) >> 16;
 
 	/* UV plane does 1/2 pixel sub-sampling */
 	if (color_plane == 1) {
@@ -4716,7 +4717,7 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
 	 * the 90/270 degree plane rotation cases (to match the
 	 * GTT mapping), hence no need to account for rotation here.
 	 */
-	width = drm_rect_width(&plane_state->base.src) >> 16;
+	width = drm_rect_width(&plane_state->uapi.src) >> 16;
 
 	return skl_compute_wm_params(crtc_state, width,
 				     fb->format, fb->modifier,
@@ -4998,7 +4999,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
 static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,
 			      const struct intel_plane_state *plane_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	enum plane_id plane_id = plane->id;
 	int ret;
@@ -5024,7 +5025,7 @@ static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,
 static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
 			      const struct intel_plane_state *plane_state)
 {
-	enum plane_id plane_id = to_intel_plane(plane_state->base.plane)->id;
+	enum plane_id plane_id = to_intel_plane(plane_state->uapi.plane)->id;
 	int ret;
 
 	/* Watermarks calculated in master */
@@ -6057,7 +6058,7 @@ void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
 		enum plane_id plane_id = plane->id;
 		int level;
 
-		if (plane_state->base.visible)
+		if (plane_state->uapi.visible)
 			continue;
 
 		for (level = 0; level < 3; level++) {
@@ -6212,7 +6213,7 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
 		enum plane_id plane_id = plane->id;
 		int level;
 
-		if (plane_state->base.visible)
+		if (plane_state->uapi.visible)
 			continue;
 
 		for (level = 0; level < wm_state->num_levels; level++) {
-- 
2.23.0

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^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH 13/14] drm/i915: Complete plane hw and uapi split, v2.
  2019-10-17 13:20 [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Maarten Lankhorst
                   ` (10 preceding siblings ...)
  2019-10-17 13:21 ` [PATCH 12/14] drm/i915: Perform automated conversions for plane uapi/hw split, base -> uapi Maarten Lankhorst
@ 2019-10-17 13:21 ` Maarten Lankhorst
  2019-10-17 13:21 ` [PATCH 14/14] drm/i915: Remove special case slave handling during hw programming, v2 Maarten Lankhorst
                   ` (7 subsequent siblings)
  19 siblings, 0 replies; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-17 13:21 UTC (permalink / raw)
  To: intel-gfx

Splitting plane state is easier than splitting crtc_state,
before plane check we copy the drm properties to hw so we can
do the same in bigjoiner later on.

We copy the state after we did all the modeset handling, but fortunately
i915 seems to be split correctly and nothing during modeset looks
at plane_state.

Changes since v1:
- Do not clear hw state on duplication.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 .../gpu/drm/i915/display/intel_atomic_plane.c | 37 ++++++++++++++++++-
 .../gpu/drm/i915/display/intel_atomic_plane.h |  2 +
 drivers/gpu/drm/i915/display/intel_display.c  |  1 +
 .../drm/i915/display/intel_display_types.h    | 23 +++++++++---
 4 files changed, 57 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index e4044abc2d21..d9b65e9c45fc 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -93,6 +93,10 @@ intel_plane_duplicate_state(struct drm_plane *plane)
 	intel_state->vma = NULL;
 	intel_state->flags = 0;
 
+	/* add reference to fb */
+	if (intel_state->hw.fb)
+		drm_framebuffer_get(intel_state->hw.fb);
+
 	return &intel_state->uapi;
 }
 
@@ -112,6 +116,8 @@ intel_plane_destroy_state(struct drm_plane *plane,
 	WARN_ON(plane_state->vma);
 
 	__drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
+	if (plane_state->hw.fb)
+		drm_framebuffer_put(plane_state->hw.fb);
 	kfree(plane_state);
 }
 
@@ -138,15 +144,44 @@ unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
 	return cpp * crtc_state->pixel_rate;
 }
 
+static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
+{
+	if (plane_state->hw.fb)
+		drm_framebuffer_put(plane_state->hw.fb);
+
+	memset(&plane_state->hw, 0, sizeof(plane_state->hw));
+}
+
+void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
+				       const struct intel_plane_state *from_plane_state)
+{
+	intel_plane_clear_hw_state(plane_state);
+
+	plane_state->hw.crtc = from_plane_state->uapi.crtc;
+	plane_state->hw.fb = from_plane_state->uapi.fb;
+	if (plane_state->hw.fb)
+		drm_framebuffer_get(plane_state->hw.fb);
+
+	plane_state->hw.alpha = from_plane_state->uapi.alpha;
+	plane_state->hw.pixel_blend_mode =
+		from_plane_state->uapi.pixel_blend_mode;
+	plane_state->hw.rotation = from_plane_state->uapi.rotation;
+	plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
+	plane_state->hw.color_range = from_plane_state->uapi.color_range;
+}
+
 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
 					struct intel_crtc_state *new_crtc_state,
 					const struct intel_plane_state *old_plane_state,
 					struct intel_plane_state *new_plane_state)
 {
 	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
-	const struct drm_framebuffer *fb = new_plane_state->hw.fb;
+	const struct drm_framebuffer *fb;
 	int ret;
 
+	intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
+	fb = new_plane_state->hw.fb;
+
 	new_crtc_state->active_planes &= ~BIT(plane->id);
 	new_crtc_state->nv12_planes &= ~BIT(plane->id);
 	new_crtc_state->c8_planes &= ~BIT(plane->id);
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index dc85af02e9b7..123404a9cf23 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -20,6 +20,8 @@ extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
 
 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
 				   const struct intel_plane_state *plane_state);
+void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
+				       const struct intel_plane_state *from_plane_state);
 void intel_update_plane(struct intel_plane *plane,
 			const struct intel_crtc_state *crtc_state,
 			const struct intel_plane_state *plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a09034a1241f..de520d5f1374 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3254,6 +3254,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
 
 	plane_state->fb = fb;
 	plane_state->crtc = &intel_crtc->base;
+	intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
 
 	atomic_or(to_intel_plane(primary)->frontbuffer_bit,
 		  &to_intel_frontbuffer(fb)->bits);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9cae42e6520f..5379b93c2fab 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -515,11 +515,24 @@ struct intel_atomic_state {
 };
 
 struct intel_plane_state {
-	union {
-		struct drm_plane_state base;
-		struct drm_plane_state uapi;
-		struct drm_plane_state hw;
-	};
+	struct drm_plane_state uapi;
+
+	/*
+	 * actual hardware state, the state we program to the hardware.
+	 * The following members are used to verify the hardware state:
+	 * During initial hw readout, they need to be copied from uapi.
+	 */
+	struct {
+		struct drm_crtc *crtc;
+		struct drm_framebuffer *fb;
+
+		u16 alpha;
+		uint16_t pixel_blend_mode;
+		unsigned int rotation;
+		enum drm_color_encoding color_encoding;
+		enum drm_color_range color_range;
+	} hw;
+
 	struct i915_ggtt_view view;
 	struct i915_vma *vma;
 	unsigned long flags;
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH 14/14] drm/i915: Remove special case slave handling during hw programming, v2.
  2019-10-17 13:20 [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Maarten Lankhorst
                   ` (11 preceding siblings ...)
  2019-10-17 13:21 ` [PATCH 13/14] drm/i915: Complete plane hw and uapi split, v2 Maarten Lankhorst
@ 2019-10-17 13:21 ` Maarten Lankhorst
  2019-10-18 14:52   ` Maarten Lankhorst
  2019-10-22 10:31   ` [PATCH] drm/i915: Remove special case slave handling during hw programming, v3 Maarten Lankhorst
  2019-10-17 13:37 ` [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Ville Syrjälä
                   ` (6 subsequent siblings)
  19 siblings, 2 replies; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-17 13:21 UTC (permalink / raw)
  To: intel-gfx

Now that we split plane_state which I didn't want to do yet, we can
program the slave plane without requiring the master plane.

This is useful for programming bigjoiner slave planes as well. We
will no longer need the master's plane_state.

Changes since v1:
- set src/dst rectangles after copy_uapi_to_hw_state.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 .../gpu/drm/i915/display/intel_atomic_plane.c | 30 +---------
 .../gpu/drm/i915/display/intel_atomic_plane.h |  3 -
 drivers/gpu/drm/i915/display/intel_display.c  | 18 ++++++
 .../drm/i915/display/intel_display_types.h    |  6 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   | 55 ++++++-------------
 5 files changed, 39 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index d9b65e9c45fc..54d112408716 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -309,16 +309,6 @@ void intel_update_plane(struct intel_plane *plane,
 	plane->update_plane(plane, crtc_state, plane_state);
 }
 
-void intel_update_slave(struct intel_plane *plane,
-			const struct intel_crtc_state *crtc_state,
-			const struct intel_plane_state *plane_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-
-	trace_intel_update_plane(&plane->base, crtc);
-	plane->update_slave(plane, crtc_state, plane_state);
-}
-
 void intel_disable_plane(struct intel_plane *plane,
 			 const struct intel_crtc_state *crtc_state)
 {
@@ -351,25 +341,9 @@ void skl_update_planes_on_crtc(struct intel_atomic_state *state,
 		struct intel_plane_state *new_plane_state =
 			intel_atomic_get_new_plane_state(state, plane);
 
-		if (new_plane_state->uapi.visible) {
+		if (new_plane_state->uapi.visible ||
+		    new_plane_state->planar_slave) {
 			intel_update_plane(plane, new_crtc_state, new_plane_state);
-		} else if (new_plane_state->planar_slave) {
-			struct intel_plane *master =
-				new_plane_state->planar_linked_plane;
-
-			/*
-			 * We update the slave plane from this function because
-			 * programming it from the master plane's update_plane
-			 * callback runs into issues when the Y plane is
-			 * reassigned, disabled or used by a different plane.
-			 *
-			 * The slave plane is updated with the master plane's
-			 * plane_state.
-			 */
-			new_plane_state =
-				intel_atomic_get_new_plane_state(state, master);
-
-			intel_update_slave(plane, new_crtc_state, new_plane_state);
 		} else {
 			intel_disable_plane(plane, new_crtc_state);
 		}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 123404a9cf23..726ececd6abd 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -25,9 +25,6 @@ void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
 void intel_update_plane(struct intel_plane *plane,
 			const struct intel_crtc_state *crtc_state,
 			const struct intel_plane_state *plane_state);
-void intel_update_slave(struct intel_plane *plane,
-			const struct intel_crtc_state *crtc_state,
-			const struct intel_plane_state *plane_state);
 void intel_disable_plane(struct intel_plane *plane,
 			 const struct intel_crtc_state *crtc_state);
 struct intel_plane *intel_plane_alloc(void);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index de520d5f1374..88f149cac198 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11768,6 +11768,24 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
 		crtc_state->active_planes |= BIT(linked->id);
 		crtc_state->update_planes |= BIT(linked->id);
 		DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
+
+		/* Copy parameters to slave plane */
+		linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
+		linked_state->color_ctl = plane_state->color_ctl;
+		linked_state->color_plane[0] = plane_state->color_plane[0];
+
+		intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
+		linked_state->uapi.src = plane_state->uapi.src;
+		linked_state->uapi.dst = plane_state->uapi.dst;
+
+		if (icl_is_hdr_plane(dev_priv, plane->id)) {
+			if (linked->id == PLANE_SPRITE5)
+				plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
+			else if (linked->id == PLANE_SPRITE4)
+				plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
+			else
+				MISSING_CASE(linked->id);
+		}
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5379b93c2fab..dbca1b3c5c67 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -555,6 +555,9 @@ struct intel_plane_state {
 	/* plane color control register */
 	u32 color_ctl;
 
+	/* chroma upsampler control register */
+	u32 cus_ctl;
+
 	/*
 	 * scaler_id
 	 *    = -1 : not using a scaler
@@ -1106,9 +1109,6 @@ struct intel_plane {
 	void (*update_plane)(struct intel_plane *plane,
 			     const struct intel_crtc_state *crtc_state,
 			     const struct intel_plane_state *plane_state);
-	void (*update_slave)(struct intel_plane *plane,
-			     const struct intel_crtc_state *crtc_state,
-			     const struct intel_plane_state *plane_state);
 	void (*disable_plane)(struct intel_plane *plane,
 			      const struct intel_crtc_state *crtc_state);
 	bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 00f83d37abcf..20123fccd081 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -526,7 +526,7 @@ static void
 skl_program_plane(struct intel_plane *plane,
 		  const struct intel_crtc_state *crtc_state,
 		  const struct intel_plane_state *plane_state,
-		  int color_plane, bool slave, u32 plane_ctl)
+		  int color_plane)
 {
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum plane_id plane_id = plane->id;
@@ -541,12 +541,12 @@ skl_program_plane(struct intel_plane *plane,
 	u32 y = plane_state->color_plane[color_plane].y;
 	u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 	u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
-	struct intel_plane *linked = plane_state->planar_linked_plane;
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	u8 alpha = plane_state->hw.alpha >> 8;
 	u32 plane_color_ctl = 0;
 	unsigned long irqflags;
 	u32 keymsk, keymax;
+	u32 plane_ctl = plane_state->ctl;
 
 	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
 
@@ -578,26 +578,8 @@ skl_program_plane(struct intel_plane *plane,
 	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
 		      (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
 
-	if (icl_is_hdr_plane(dev_priv, plane_id)) {
-		u32 cus_ctl = 0;
-
-		if (linked) {
-			/* Enable and use MPEG-2 chroma siting */
-			cus_ctl = PLANE_CUS_ENABLE |
-				PLANE_CUS_HPHASE_0 |
-				PLANE_CUS_VPHASE_SIGN_NEGATIVE |
-				PLANE_CUS_VPHASE_0_25;
-
-			if (linked->id == PLANE_SPRITE5)
-				cus_ctl |= PLANE_CUS_PLANE_7;
-			else if (linked->id == PLANE_SPRITE4)
-				cus_ctl |= PLANE_CUS_PLANE_6;
-			else
-				MISSING_CASE(linked->id);
-		}
-
-		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), cus_ctl);
-	}
+	if (icl_is_hdr_plane(dev_priv, plane_id))
+		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), plane_state->cus_ctl);
 
 	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
@@ -627,7 +609,7 @@ skl_program_plane(struct intel_plane *plane,
 	I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
 		      intel_plane_ggtt_offset(plane_state) + surf_addr);
 
-	if (!slave && plane_state->scaler_id >= 0)
+	if (plane_state->scaler_id >= 0)
 		skl_program_scaler(plane, crtc_state, plane_state);
 
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
@@ -640,24 +622,13 @@ skl_update_plane(struct intel_plane *plane,
 {
 	int color_plane = 0;
 
-	if (plane_state->planar_linked_plane) {
+	if (drm_format_info_is_yuv_semiplanar(plane_state->hw.fb->format) &&
+	    !plane_state->planar_slave)
 		/* Program the UV plane */
 		color_plane = 1;
-	}
 
-	skl_program_plane(plane, crtc_state, plane_state,
-			  color_plane, false, plane_state->ctl);
+	skl_program_plane(plane, crtc_state, plane_state, color_plane);
 }
-
-static void
-icl_update_slave(struct intel_plane *plane,
-		 const struct intel_crtc_state *crtc_state,
-		 const struct intel_plane_state *plane_state)
-{
-	skl_program_plane(plane, crtc_state, plane_state, 0, true,
-			  plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE);
-}
-
 static void
 skl_disable_plane(struct intel_plane *plane,
 		  const struct intel_crtc_state *crtc_state)
@@ -1844,6 +1815,14 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
 		plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
 							     plane_state);
 
+	if (icl_is_hdr_plane(dev_priv, plane->id) && fb->format->is_yuv)
+		/* Enable and use MPEG-2 chroma siting */
+		plane_state->cus_ctl = PLANE_CUS_ENABLE |
+			PLANE_CUS_HPHASE_0 |
+			PLANE_CUS_VPHASE_SIGN_NEGATIVE | PLANE_CUS_VPHASE_0_25;
+	else
+		plane_state->cus_ctl = 0;
+
 	return 0;
 }
 
@@ -2512,8 +2491,6 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 	plane->disable_plane = skl_disable_plane;
 	plane->get_hw_state = skl_plane_get_hw_state;
 	plane->check_plane = skl_plane_check;
-	if (icl_is_nv12_y_plane(plane_id))
-		plane->update_slave = icl_update_slave;
 
 	if (INTEL_GEN(dev_priv) >= 11)
 		formats = icl_get_plane_formats(dev_priv, pipe,
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* Re: [PATCH 01/14] drm/i915: Rework watermark readout to use plane api
  2019-10-17 13:20 [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Maarten Lankhorst
                   ` (12 preceding siblings ...)
  2019-10-17 13:21 ` [PATCH 14/14] drm/i915: Remove special case slave handling during hw programming, v2 Maarten Lankhorst
@ 2019-10-17 13:37 ` Ville Syrjälä
  2019-10-17 14:11   ` Maarten Lankhorst
  2019-10-17 18:25 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/14] " Patchwork
                   ` (5 subsequent siblings)
  19 siblings, 1 reply; 49+ messages in thread
From: Ville Syrjälä @ 2019-10-17 13:37 UTC (permalink / raw)
  To: Maarten Lankhorst; +Cc: intel-gfx

On Thu, Oct 17, 2019 at 03:20:52PM +0200, Maarten Lankhorst wrote:
> Instead of unconditionally verifying the cursor plane, handle it in the
> same way as any other plane, and use our existing api to verify.
> 
> While at it, ensure that on gen9+ we verify active_planes mask as well.
> This should give the correct results for planar YUV planes too, as we
> update active_planes for them.

Why is that hidden in the watermark verification code? We already have
intel_verify_planes() which seems like a better fit.

> 
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 83 ++++++--------------
>  1 file changed, 23 insertions(+), 60 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 164ded862148..945ab2180614 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12932,7 +12932,8 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  	struct skl_pipe_wm *sw_wm;
>  	struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
>  	const enum pipe pipe = crtc->pipe;
> -	int plane, level, max_level = ilk_wm_max_level(dev_priv);
> +	int level, max_level = ilk_wm_max_level(dev_priv);
> +	struct intel_plane *plane;
>  
>  	if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->base.active)
>  		return;
> @@ -12956,63 +12957,25 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  			  hw->ddb.enabled_slices);
>  
>  	/* planes */
> -	for_each_universal_plane(dev_priv, pipe, plane) {
> +	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
>  		struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
> +		enum pipe plane_pipe = pipe;
>  
> -		hw_plane_wm = &hw->wm.planes[plane];
> -		sw_plane_wm = &sw_wm->planes[plane];
> -
> -		/* Watermarks */
> -		for (level = 0; level <= max_level; level++) {
> -			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> -						&sw_plane_wm->wm[level]))
> -				continue;
> -
> -			DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> -				  pipe_name(pipe), plane + 1, level,
> -				  sw_plane_wm->wm[level].plane_en,
> -				  sw_plane_wm->wm[level].plane_res_b,
> -				  sw_plane_wm->wm[level].plane_res_l,
> -				  hw_plane_wm->wm[level].plane_en,
> -				  hw_plane_wm->wm[level].plane_res_b,
> -				  hw_plane_wm->wm[level].plane_res_l);
> -		}
> +		hw_plane_wm = &hw->wm.planes[plane->id];
> +		sw_plane_wm = &sw_wm->planes[plane->id];
>  
> -		if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
> -					 &sw_plane_wm->trans_wm)) {
> -			DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> -				  pipe_name(pipe), plane + 1,
> -				  sw_plane_wm->trans_wm.plane_en,
> -				  sw_plane_wm->trans_wm.plane_res_b,
> -				  sw_plane_wm->trans_wm.plane_res_l,
> -				  hw_plane_wm->trans_wm.plane_en,
> -				  hw_plane_wm->trans_wm.plane_res_b,
> -				  hw_plane_wm->trans_wm.plane_res_l);
> -		}
> -
> -		/* DDB */
> -		hw_ddb_entry = &hw->ddb_y[plane];
> -		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
> -
> -		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
> -			DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
> -				  pipe_name(pipe), plane + 1,
> -				  sw_ddb_entry->start, sw_ddb_entry->end,
> -				  hw_ddb_entry->start, hw_ddb_entry->end);
> +		if (!plane->get_hw_state(plane, &plane_pipe)) {
> +			WARN(new_crtc_state->active_planes & BIT(plane->id),
> +			     "pipe %c %s should be visible, but isn't\n",
> +			     pipe_name(pipe), plane->base.name);
> +			continue;
>  		}
> -	}
>  
> -	/*
> -	 * cursor
> -	 * If the cursor plane isn't active, we may not have updated it's ddb
> -	 * allocation. In that case since the ddb allocation will be updated
> -	 * once the plane becomes visible, we can skip this check
> -	 */
> -	if (1) {
> -		struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
> +		WARN_ON(plane_pipe != pipe);
>  
> -		hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
> -		sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
> +		WARN(!(new_crtc_state->active_planes & BIT(plane->id)),
> +		     "pipe %c %s should be invisible, but visible.\n",
> +		     pipe_name(pipe), plane->base.name);
>  
>  		/* Watermarks */
>  		for (level = 0; level <= max_level; level++) {
> @@ -13020,8 +12983,8 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  						&sw_plane_wm->wm[level]))
>  				continue;
>  
> -			DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> -				  pipe_name(pipe), level,
> +			DRM_ERROR("mismatch in WM pipe %c %s level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> +				  pipe_name(pipe), plane->base.name, level,
>  				  sw_plane_wm->wm[level].plane_en,
>  				  sw_plane_wm->wm[level].plane_res_b,
>  				  sw_plane_wm->wm[level].plane_res_l,
> @@ -13032,8 +12995,8 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  
>  		if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
>  					 &sw_plane_wm->trans_wm)) {
> -			DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> -				  pipe_name(pipe),
> +			DRM_ERROR("mismatch in trans WM pipe %c %s (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> +				  pipe_name(pipe), plane->base.name,
>  				  sw_plane_wm->trans_wm.plane_en,
>  				  sw_plane_wm->trans_wm.plane_res_b,
>  				  sw_plane_wm->trans_wm.plane_res_l,
> @@ -13043,12 +13006,12 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  		}
>  
>  		/* DDB */
> -		hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
> -		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
> +		hw_ddb_entry = &hw->ddb_y[plane->id];
> +		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id];
>  
>  		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
> -			DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
> -				  pipe_name(pipe),
> +			DRM_ERROR("mismatch in DDB state pipe %c %s (expected (%u,%u), found (%u,%u))\n",
> +				  pipe_name(pipe), plane->base.name,
>  				  sw_ddb_entry->start, sw_ddb_entry->end,
>  				  hw_ddb_entry->start, hw_ddb_entry->end);
>  		}
> -- 
> 2.23.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH 01/14] drm/i915: Rework watermark readout to use plane api
  2019-10-17 13:37 ` [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Ville Syrjälä
@ 2019-10-17 14:11   ` Maarten Lankhorst
  0 siblings, 0 replies; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-17 14:11 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

Op 17-10-2019 om 15:37 schreef Ville Syrjälä:
> On Thu, Oct 17, 2019 at 03:20:52PM +0200, Maarten Lankhorst wrote:
>> Instead of unconditionally verifying the cursor plane, handle it in the
>> same way as any other plane, and use our existing api to verify.
>>
>> While at it, ensure that on gen9+ we verify active_planes mask as well.
>> This should give the correct results for planar YUV planes too, as we
>> update active_planes for them.
> Why is that hidden in the watermark verification code? We already have
> intel_verify_planes() which seems like a better fit.
Wasn't aware of it, mostly.
_______________________________________________
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^ permalink raw reply	[flat|nested] 49+ messages in thread

* ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/14] drm/i915: Rework watermark readout to use plane api
  2019-10-17 13:20 [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Maarten Lankhorst
                   ` (13 preceding siblings ...)
  2019-10-17 13:37 ` [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Ville Syrjälä
@ 2019-10-17 18:25 ` Patchwork
  2019-10-17 18:50 ` ✗ Fi.CI.BAT: failure " Patchwork
                   ` (4 subsequent siblings)
  19 siblings, 0 replies; 49+ messages in thread
From: Patchwork @ 2019-10-17 18:25 UTC (permalink / raw)
  To: Maarten Lankhorst; +Cc: intel-gfx

== Series Details ==

Series: series starting with [01/14] drm/i915: Rework watermark readout to use plane api
URL   : https://patchwork.freedesktop.org/series/68154/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
aaabe4f7c23f drm/i915: Rework watermark readout to use plane api
4a9053bede2d drm/i915: Introduce intel_atomic_get_plane_state_after_check(), v2.
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#10: 
In case of intel_modeset_all_pipes() this is not yet done after atomic_check,

-:87: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#87: FILE: drivers/gpu/drm/i915/display/intel_atomic.c:387:
+					DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state: %li\n",
+						plane->base.base.id, PTR_ERR(plane_state));

total: 0 errors, 1 warnings, 1 checks, 185 lines checked
5970fb0393f3 drm/i915: Handle a few more cases for crtc hw/uapi split, v2.
574fdacfb67f drm/i915: Add aliases for uapi and hw to crtc_state
-:67: WARNING:LONG_LINE: line over 100 characters
#67: FILE: drivers/gpu/drm/i915/display/intel_display.h:450:
+			      to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))

total: 0 errors, 1 warnings, 0 checks, 83 lines checked
957c3b363e99 drm/i915: Perform manual conversions for crtc uapi/hw split
57f6e64288f6 drm/i915: Perform automated conversions for crtc uapi/hw split, base -> hw.
-:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#7: 
Split up crtc_state->base to hw where appropriate. This is done using the following patch:

-:1382: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#1382: FILE: drivers/gpu/drm/i915/display/intel_display.c:16667:
+		crtc_state->hw.active = crtc_state->hw.enable =

total: 0 errors, 1 warnings, 1 checks, 2055 lines checked
cefea1fe68bc drm/i915: Perform automated conversions for crtc uapi/hw split, base -> uapi.
-:18: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#18: 
identifier x =~ "^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";

-:2352: ERROR:CODE_INDENT: code indent should use tabs where possible
#2352: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:211:
+^I^I^I^I          new_crtc_state->uapi.event);$

-:2352: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2352: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:211:
+		drm_crtc_arm_vblank_event(&crtc->base,
+				          new_crtc_state->uapi.event);

total: 1 errors, 1 warnings, 1 checks, 2514 lines checked
a17e5b0b742a drm/i915: Complete crtc hw/uapi split, v2.
-:15: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#15: 
- Clear crtc_state->hw on disable, instead of using clear_intel_crtc_state().

total: 0 errors, 1 warnings, 0 checks, 206 lines checked
38d025aa4709 drm/i915: Add aliases for uapi and hw to plane_state
-:49: WARNING:LINE_SPACING: Missing a blank line after declarations
#49: FILE: drivers/gpu/drm/i915/display/intel_atomic_plane.c:112:
+	struct intel_plane_state *plane_state = to_intel_plane_state(state);
+	WARN_ON(plane_state->vma);

total: 0 errors, 1 warnings, 0 checks, 59 lines checked
2b1622595030 drm/i915: Perform manual conversions for plane uapi/hw split
0fae6c91760b drm/i915: Perform automated conversions for plane uapi/hw split, base -> hw.
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#11: 
identifier x =~ "^(crtc|fb|alpha|pixel_blend_mode|rotation|color_encoding|color_range)$";

-:832: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "plane_state->hw.fb"
#832: FILE: drivers/gpu/drm/i915/intel_pm.c:813:
+		return plane_state->hw.fb != NULL;

total: 0 errors, 1 warnings, 1 checks, 836 lines checked
60d57b430c96 drm/i915: Perform automated conversions for plane uapi/hw split, base -> uapi.
-:713: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#713: FILE: drivers/gpu/drm/i915/display/intel_display.c:10962:
+		unsigned width = drm_rect_width(&plane_state->uapi.dst);

-:714: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#714: FILE: drivers/gpu/drm/i915/display/intel_display.c:10963:
+		unsigned height = drm_rect_height(&plane_state->uapi.dst);

-:782: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#782: FILE: drivers/gpu/drm/i915/display/intel_display.c:11565:
+		plane_state->uapi.visible = visible = false;

-:1510: WARNING:LONG_LINE: line over 100 characters
#1510: FILE: drivers/gpu/drm/i915/intel_pm.c:3112:
+			(drm_rect_width(&sprstate->uapi.dst) != drm_rect_width(&sprstate->uapi.src) >> 16 ||

-:1511: WARNING:LONG_LINE: line over 100 characters
#1511: FILE: drivers/gpu/drm/i915/intel_pm.c:3113:
+			 drm_rect_height(&sprstate->uapi.dst) != drm_rect_height(&sprstate->uapi.src) >> 16);

total: 0 errors, 4 warnings, 1 checks, 1415 lines checked
14abe8630757 drm/i915: Complete plane hw and uapi split, v2.
-:139: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u16' over 'uint16_t'
#139: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:530:
+		uint16_t pixel_blend_mode;

total: 0 errors, 0 warnings, 1 checks, 107 lines checked
67171f043d90 drm/i915: Remove special case slave handling during hw programming, v2.

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 49+ messages in thread

* ✗ Fi.CI.BAT: failure for series starting with [01/14] drm/i915: Rework watermark readout to use plane api
  2019-10-17 13:20 [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Maarten Lankhorst
                   ` (14 preceding siblings ...)
  2019-10-17 18:25 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/14] " Patchwork
@ 2019-10-17 18:50 ` Patchwork
  2019-10-18  8:27 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/14] drm/i915: Rework watermark readout to use plane api (rev2) Patchwork
                   ` (3 subsequent siblings)
  19 siblings, 0 replies; 49+ messages in thread
From: Patchwork @ 2019-10-17 18:50 UTC (permalink / raw)
  To: Maarten Lankhorst; +Cc: intel-gfx

== Series Details ==

Series: series starting with [01/14] drm/i915: Rework watermark readout to use plane api
URL   : https://patchwork.freedesktop.org/series/68154/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7122 -> Patchwork_14858
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_14858 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_14858, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14858:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_force_connector_basic@force-connector-state:
    - fi-gdg-551:         [PASS][1] -> [DMESG-FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-gdg-551/igt@kms_force_connector_basic@force-connector-state.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-gdg-551/igt@kms_force_connector_basic@force-connector-state.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-hsw-4770:        [PASS][3] -> [DMESG-WARN][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-hsw-4770/igt@kms_force_connector_basic@force-load-detect.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-hsw-4770/igt@kms_force_connector_basic@force-load-detect.html
    - fi-ivb-3770:        [PASS][5] -> [DMESG-WARN][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-ivb-3770/igt@kms_force_connector_basic@force-load-detect.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-ivb-3770/igt@kms_force_connector_basic@force-load-detect.html
    - fi-byt-j1900:       [PASS][7] -> [DMESG-WARN][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-byt-j1900/igt@kms_force_connector_basic@force-load-detect.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-byt-j1900/igt@kms_force_connector_basic@force-load-detect.html
    - fi-blb-e6850:       [PASS][9] -> [DMESG-WARN][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-blb-e6850/igt@kms_force_connector_basic@force-load-detect.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-blb-e6850/igt@kms_force_connector_basic@force-load-detect.html
    - fi-bwr-2160:        [PASS][11] -> [DMESG-WARN][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-bwr-2160/igt@kms_force_connector_basic@force-load-detect.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-bwr-2160/igt@kms_force_connector_basic@force-load-detect.html
    - fi-snb-2600:        [PASS][13] -> [DMESG-WARN][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-snb-2600/igt@kms_force_connector_basic@force-load-detect.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-snb-2600/igt@kms_force_connector_basic@force-load-detect.html
    - fi-elk-e7500:       [PASS][15] -> [DMESG-WARN][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-elk-e7500/igt@kms_force_connector_basic@force-load-detect.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-elk-e7500/igt@kms_force_connector_basic@force-load-detect.html
    - fi-ilk-650:         [PASS][17] -> [DMESG-WARN][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-ilk-650/igt@kms_force_connector_basic@force-load-detect.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-ilk-650/igt@kms_force_connector_basic@force-load-detect.html
    - fi-pnv-d510:        [PASS][19] -> [DMESG-WARN][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-pnv-d510/igt@kms_force_connector_basic@force-load-detect.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-pnv-d510/igt@kms_force_connector_basic@force-load-detect.html
    - fi-snb-2520m:       [PASS][21] -> [DMESG-WARN][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-snb-2520m/igt@kms_force_connector_basic@force-load-detect.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-snb-2520m/igt@kms_force_connector_basic@force-load-detect.html

  * igt@runner@aborted:
    - fi-ilk-650:         NOTRUN -> [FAIL][23]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-ilk-650/igt@runner@aborted.html
    - fi-pnv-d510:        NOTRUN -> [FAIL][24]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-pnv-d510/igt@runner@aborted.html
    - fi-gdg-551:         NOTRUN -> [FAIL][25]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-gdg-551/igt@runner@aborted.html
    - fi-snb-2520m:       NOTRUN -> [FAIL][26]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-snb-2520m/igt@runner@aborted.html
    - fi-hsw-4770:        NOTRUN -> [FAIL][27]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-hsw-4770/igt@runner@aborted.html
    - fi-ivb-3770:        NOTRUN -> [FAIL][28]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-ivb-3770/igt@runner@aborted.html
    - fi-byt-j1900:       NOTRUN -> [FAIL][29]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-byt-j1900/igt@runner@aborted.html
    - fi-blb-e6850:       NOTRUN -> [FAIL][30]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-blb-e6850/igt@runner@aborted.html
    - fi-snb-2600:        NOTRUN -> [FAIL][31]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-snb-2600/igt@runner@aborted.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live_execlists:
    - {fi-icl-guc}:       NOTRUN -> [DMESG-FAIL][32]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-icl-guc/igt@i915_selftest@live_execlists.html
    - {fi-icl-dsi}:       [PASS][33] -> [DMESG-FAIL][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-dsi/igt@i915_selftest@live_execlists.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-icl-dsi/igt@i915_selftest@live_execlists.html

  
Known issues
------------

  Here are the changes found in Patchwork_14858 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_mmap_gtt@basic-read-write-distinct:
    - fi-icl-u3:          [PASS][35] -> [DMESG-WARN][36] ([fdo#107724]) +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-u3/igt@gem_mmap_gtt@basic-read-write-distinct.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-icl-u3/igt@gem_mmap_gtt@basic-read-write-distinct.html

  * igt@kms_busy@basic-flip-a:
    - fi-icl-u2:          [PASS][37] -> [TIMEOUT][38] ([fdo#111800])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-u2/igt@kms_busy@basic-flip-a.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-icl-u2/igt@kms_busy@basic-flip-a.html

  
#### Possible fixes ####

  * igt@gem_ctx_switch@rcs0:
    - {fi-icl-guc}:       [INCOMPLETE][39] ([fdo#107713]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-guc/igt@gem_ctx_switch@rcs0.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-icl-guc/igt@gem_ctx_switch@rcs0.html

  * igt@gem_workarounds@basic-read:
    - fi-icl-u3:          [DMESG-WARN][41] ([fdo#107724]) -> [PASS][42] +1 similar issue
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-u3/igt@gem_workarounds@basic-read.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-icl-u3/igt@gem_workarounds@basic-read.html

  * igt@i915_selftest@live_execlists:
    - fi-icl-u3:          [DMESG-FAIL][43] -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-icl-u3/igt@i915_selftest@live_execlists.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-icl-u3/igt@i915_selftest@live_execlists.html

  
#### Warnings ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][45] ([fdo#111407]) -> [FAIL][46] ([fdo#111045] / [fdo#111096])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7122/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
  [fdo#111800]: https://bugs.freedesktop.org/show_bug.cgi?id=111800
  [fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880


Participating hosts (53 -> 46)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7122 -> Patchwork_14858

  CI-20190529: 20190529
  CI_DRM_7122: c2f6bdc09f8f046cd38e3c39c92e14e6033dbd44 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5232: bb5735423eaf6fdbf6b2f94ef0b8520e74eab993 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14858: 67171f043d90c0e5d27a72054cf799322193c4f2 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

67171f043d90 drm/i915: Remove special case slave handling during hw programming, v2.
14abe8630757 drm/i915: Complete plane hw and uapi split, v2.
60d57b430c96 drm/i915: Perform automated conversions for plane uapi/hw split, base -> uapi.
0fae6c91760b drm/i915: Perform automated conversions for plane uapi/hw split, base -> hw.
2b1622595030 drm/i915: Perform manual conversions for plane uapi/hw split
38d025aa4709 drm/i915: Add aliases for uapi and hw to plane_state
a17e5b0b742a drm/i915: Complete crtc hw/uapi split, v2.
cefea1fe68bc drm/i915: Perform automated conversions for crtc uapi/hw split, base -> uapi.
57f6e64288f6 drm/i915: Perform automated conversions for crtc uapi/hw split, base -> hw.
957c3b363e99 drm/i915: Perform manual conversions for crtc uapi/hw split
574fdacfb67f drm/i915: Add aliases for uapi and hw to crtc_state
5970fb0393f3 drm/i915: Handle a few more cases for crtc hw/uapi split, v2.
4a9053bede2d drm/i915: Introduce intel_atomic_get_plane_state_after_check(), v2.
aaabe4f7c23f drm/i915: Rework watermark readout to use plane api

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14858/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH 05/14] drm/i915: Perform manual conversions for crtc uapi/hw split
  2019-10-17 13:20 ` [PATCH 05/14] drm/i915: Perform manual conversions for crtc uapi/hw split Maarten Lankhorst
@ 2019-10-18  8:11   ` Maarten Lankhorst
  2019-10-18  8:13   ` [PATCH] drm/i915: Perform manual conversions for crtc uapi/hw split, v2 Maarten Lankhorst
  1 sibling, 0 replies; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-18  8:11 UTC (permalink / raw)
  To: Intel Graphics Development

Op 17-10-2019 om 15:20 schreef Maarten Lankhorst:
> intel_get_load_detect_pipe() needs to set uapi active,
> uapi enable is set by the call to drm_atomic_set_mode_for_crtc(),
> so we can remove it.
>
> intel_pipe_config_compare() needs to look at hw state, but I didn't
> change spatch to look at it. It's easy enough to do manually.
>
> intel_atomic_check() definitely needs to check for uapi enable,
> otherwise intel_modeset_pipe_config cannot copy uapi state to hw.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 42 ++++++++++----------
>  1 file changed, 21 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index fa0abfdff2ae..adb70d76a61c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11214,7 +11214,7 @@ int intel_get_load_detect_pipe(struct drm_connector *connector,
>  		goto fail;
>  	}
>  
> -	crtc_state->base.active = crtc_state->base.enable = true;
> +	crtc_state->hw.active = true;

Ugh, should of course be uapi.active, because I split it out. :(

Will fix.


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^ permalink raw reply	[flat|nested] 49+ messages in thread

* [PATCH] drm/i915: Perform manual conversions for crtc uapi/hw split, v2.
  2019-10-17 13:20 ` [PATCH 05/14] drm/i915: Perform manual conversions for crtc uapi/hw split Maarten Lankhorst
  2019-10-18  8:11   ` Maarten Lankhorst
@ 2019-10-18  8:13   ` Maarten Lankhorst
  2019-10-22 18:16     ` Ville Syrjälä
  1 sibling, 1 reply; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-18  8:13 UTC (permalink / raw)
  To: intel-gfx

intel_get_load_detect_pipe() needs to set uapi active,
uapi enable is set by the call to drm_atomic_set_mode_for_crtc(),
so we can remove it.

intel_pipe_config_compare() needs to look at hw state, but I didn't
change spatch to look at it. It's easy enough to do manually.

intel_atomic_check() definitely needs to check for uapi enable,
otherwise intel_modeset_pipe_config cannot copy uapi state to hw.

Changes since v1:
- Actually set uapi.active in get_load_detect_pipe().

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 42 ++++++++++----------
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index fa0abfdff2ae..bbac6b764d92 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11214,7 +11214,7 @@ int intel_get_load_detect_pipe(struct drm_connector *connector,
 		goto fail;
 	}
 
-	crtc_state->base.active = crtc_state->base.enable = true;
+	crtc_state->uapi.active = true;
 
 	if (!mode)
 		mode = &load_detect_mode;
@@ -12754,19 +12754,19 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
 	PIPE_CONF_CHECK_X(output_types);
 
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
 
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
-	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
 
 	PIPE_CONF_CHECK_I(pixel_multiplier);
 	PIPE_CONF_CHECK_I(output_format);
@@ -12783,17 +12783,17 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
 	PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
 
-	PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+	PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
 			      DRM_MODE_FLAG_INTERLACE);
 
 	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
-		PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
 				      DRM_MODE_FLAG_PHSYNC);
-		PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
 				      DRM_MODE_FLAG_NHSYNC);
-		PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
 				      DRM_MODE_FLAG_PVSYNC);
-		PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
 				      DRM_MODE_FLAG_NVSYNC);
 	}
 
@@ -12832,7 +12832,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
 		bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
 		if (bp_gamma)
-			PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, base.gamma_lut, bp_gamma);
+			PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
 
 	}
 
@@ -12877,7 +12877,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
 		PIPE_CONF_CHECK_I(pipe_bpp);
 
-	PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
+	PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
 	PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
 
 	PIPE_CONF_CHECK_I(min_voltage_level);
@@ -13572,7 +13572,7 @@ static int intel_atomic_check(struct drm_device *dev,
 		if (!needs_modeset(new_crtc_state))
 			continue;
 
-		if (!new_crtc_state->base.enable) {
+		if (!new_crtc_state->uapi.enable) {
 			any_ms = true;
 			continue;
 		}
-- 
2.23.0

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/14] drm/i915: Rework watermark readout to use plane api (rev2)
  2019-10-17 13:20 [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Maarten Lankhorst
                   ` (15 preceding siblings ...)
  2019-10-17 18:50 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2019-10-18  8:27 ` Patchwork
  2019-10-18  8:46 ` ✓ Fi.CI.BAT: success " Patchwork
                   ` (2 subsequent siblings)
  19 siblings, 0 replies; 49+ messages in thread
From: Patchwork @ 2019-10-18  8:27 UTC (permalink / raw)
  To: Maarten Lankhorst; +Cc: intel-gfx

== Series Details ==

Series: series starting with [01/14] drm/i915: Rework watermark readout to use plane api (rev2)
URL   : https://patchwork.freedesktop.org/series/68154/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b7926f94b005 drm/i915: Rework watermark readout to use plane api
ec5541f29359 drm/i915: Introduce intel_atomic_get_plane_state_after_check(), v2.
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#10: 
In case of intel_modeset_all_pipes() this is not yet done after atomic_check,

-:87: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#87: FILE: drivers/gpu/drm/i915/display/intel_atomic.c:387:
+					DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state: %li\n",
+						plane->base.base.id, PTR_ERR(plane_state));

total: 0 errors, 1 warnings, 1 checks, 185 lines checked
c11aa5f9aecb drm/i915: Handle a few more cases for crtc hw/uapi split, v2.
892e45082594 drm/i915: Add aliases for uapi and hw to crtc_state
-:67: WARNING:LONG_LINE: line over 100 characters
#67: FILE: drivers/gpu/drm/i915/display/intel_display.h:450:
+			      to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))

total: 0 errors, 1 warnings, 0 checks, 83 lines checked
d34b44583315 drm/i915: Perform manual conversions for crtc uapi/hw split, v2.
9dcd30df9a3d drm/i915: Perform automated conversions for crtc uapi/hw split, base -> hw.
-:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#7: 
Split up crtc_state->base to hw where appropriate. This is done using the following patch:

-:1382: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#1382: FILE: drivers/gpu/drm/i915/display/intel_display.c:16667:
+		crtc_state->hw.active = crtc_state->hw.enable =

total: 0 errors, 1 warnings, 1 checks, 2055 lines checked
9dcebb8f873c drm/i915: Perform automated conversions for crtc uapi/hw split, base -> uapi.
-:18: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#18: 
identifier x =~ "^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";

-:2352: ERROR:CODE_INDENT: code indent should use tabs where possible
#2352: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:211:
+^I^I^I^I          new_crtc_state->uapi.event);$

-:2352: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2352: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:211:
+		drm_crtc_arm_vblank_event(&crtc->base,
+				          new_crtc_state->uapi.event);

total: 1 errors, 1 warnings, 1 checks, 2514 lines checked
87af32bda7a2 drm/i915: Complete crtc hw/uapi split, v2.
-:15: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#15: 
- Clear crtc_state->hw on disable, instead of using clear_intel_crtc_state().

total: 0 errors, 1 warnings, 0 checks, 206 lines checked
de2e37307e2d drm/i915: Add aliases for uapi and hw to plane_state
-:49: WARNING:LINE_SPACING: Missing a blank line after declarations
#49: FILE: drivers/gpu/drm/i915/display/intel_atomic_plane.c:112:
+	struct intel_plane_state *plane_state = to_intel_plane_state(state);
+	WARN_ON(plane_state->vma);

total: 0 errors, 1 warnings, 0 checks, 59 lines checked
205a73338518 drm/i915: Perform manual conversions for plane uapi/hw split
6aa0728a2af6 drm/i915: Perform automated conversions for plane uapi/hw split, base -> hw.
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#11: 
identifier x =~ "^(crtc|fb|alpha|pixel_blend_mode|rotation|color_encoding|color_range)$";

-:832: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "plane_state->hw.fb"
#832: FILE: drivers/gpu/drm/i915/intel_pm.c:813:
+		return plane_state->hw.fb != NULL;

total: 0 errors, 1 warnings, 1 checks, 836 lines checked
3d5dd6146657 drm/i915: Perform automated conversions for plane uapi/hw split, base -> uapi.
-:713: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#713: FILE: drivers/gpu/drm/i915/display/intel_display.c:10962:
+		unsigned width = drm_rect_width(&plane_state->uapi.dst);

-:714: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#714: FILE: drivers/gpu/drm/i915/display/intel_display.c:10963:
+		unsigned height = drm_rect_height(&plane_state->uapi.dst);

-:782: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#782: FILE: drivers/gpu/drm/i915/display/intel_display.c:11565:
+		plane_state->uapi.visible = visible = false;

-:1510: WARNING:LONG_LINE: line over 100 characters
#1510: FILE: drivers/gpu/drm/i915/intel_pm.c:3112:
+			(drm_rect_width(&sprstate->uapi.dst) != drm_rect_width(&sprstate->uapi.src) >> 16 ||

-:1511: WARNING:LONG_LINE: line over 100 characters
#1511: FILE: drivers/gpu/drm/i915/intel_pm.c:3113:
+			 drm_rect_height(&sprstate->uapi.dst) != drm_rect_height(&sprstate->uapi.src) >> 16);

total: 0 errors, 4 warnings, 1 checks, 1415 lines checked
80a567494d9b drm/i915: Complete plane hw and uapi split, v2.
-:139: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u16' over 'uint16_t'
#139: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:530:
+		uint16_t pixel_blend_mode;

total: 0 errors, 0 warnings, 1 checks, 107 lines checked
073f680610d1 drm/i915: Remove special case slave handling during hw programming, v2.

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 49+ messages in thread

* ✓ Fi.CI.BAT: success for series starting with [01/14] drm/i915: Rework watermark readout to use plane api (rev2)
  2019-10-17 13:20 [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Maarten Lankhorst
                   ` (16 preceding siblings ...)
  2019-10-18  8:27 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/14] drm/i915: Rework watermark readout to use plane api (rev2) Patchwork
@ 2019-10-18  8:46 ` Patchwork
  2019-10-18 10:57 ` ✗ Fi.CI.IGT: failure " Patchwork
  2019-10-22 18:53 ` ✗ Fi.CI.BUILD: failure for series starting with [01/14] drm/i915: Rework watermark readout to use plane api (rev3) Patchwork
  19 siblings, 0 replies; 49+ messages in thread
From: Patchwork @ 2019-10-18  8:46 UTC (permalink / raw)
  To: Maarten Lankhorst; +Cc: intel-gfx

== Series Details ==

Series: series starting with [01/14] drm/i915: Rework watermark readout to use plane api (rev2)
URL   : https://patchwork.freedesktop.org/series/68154/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7125 -> Patchwork_14874
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/index.html

Known issues
------------

  Here are the changes found in Patchwork_14874 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_busy@busy-all:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@gem_busy@busy-all.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/fi-icl-u3/igt@gem_busy@busy-all.html

  * igt@i915_selftest@live_execlists:
    - fi-whl-u:           [PASS][3] -> [DMESG-FAIL][4] ([fdo#112046])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-whl-u/igt@i915_selftest@live_execlists.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/fi-whl-u/igt@i915_selftest@live_execlists.html
    - fi-cml-u2:          [PASS][5] -> [DMESG-FAIL][6] ([fdo#112046])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-cml-u2/igt@i915_selftest@live_execlists.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/fi-cml-u2/igt@i915_selftest@live_execlists.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-icl-u3:          [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@i915_selftest@live_execlists:
    - fi-icl-u2:          [INCOMPLETE][9] ([fdo#107713]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u2/igt@i915_selftest@live_execlists.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/fi-icl-u2/igt@i915_selftest@live_execlists.html
    - fi-apl-guc:         [DMESG-FAIL][11] ([fdo#112046]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-apl-guc/igt@i915_selftest@live_execlists.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/fi-apl-guc/igt@i915_selftest@live_execlists.html
    - {fi-icl-dsi}:       [DMESG-FAIL][13] ([fdo#112046]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-dsi/igt@i915_selftest@live_execlists.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/fi-icl-dsi/igt@i915_selftest@live_execlists.html

  * igt@i915_selftest@live_hangcheck:
    - {fi-tgl-u2}:        [INCOMPLETE][15] ([fdo#111747]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-tgl-u2/igt@i915_selftest@live_hangcheck.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/fi-tgl-u2/igt@i915_selftest@live_hangcheck.html
    - fi-icl-u3:          [INCOMPLETE][17] ([fdo#107713] / [fdo#108569]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
    - {fi-icl-u4}:        [INCOMPLETE][19] ([fdo#107713] / [fdo#108569]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/fi-icl-u4/igt@i915_selftest@live_hangcheck.html

  * igt@kms_busy@basic-flip-c:
    - {fi-icl-u4}:        [DMESG-WARN][21] ([fdo#105602]) -> [PASS][22] +5 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u4/igt@kms_busy@basic-flip-c.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/fi-icl-u4/igt@kms_busy@basic-flip-c.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][23] ([fdo#111407]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
  [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
  [fdo#112046]: https://bugs.freedesktop.org/show_bug.cgi?id=112046


Participating hosts (53 -> 45)
------------------------------

  Missing    (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7125 -> Patchwork_14874

  CI-20190529: 20190529
  CI_DRM_7125: f1ac92f5feb18678a3191a45be0ee4a4d255fc61 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5232: bb5735423eaf6fdbf6b2f94ef0b8520e74eab993 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14874: 073f680610d19513aeee0aefe610784d610b3531 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

073f680610d1 drm/i915: Remove special case slave handling during hw programming, v2.
80a567494d9b drm/i915: Complete plane hw and uapi split, v2.
3d5dd6146657 drm/i915: Perform automated conversions for plane uapi/hw split, base -> uapi.
6aa0728a2af6 drm/i915: Perform automated conversions for plane uapi/hw split, base -> hw.
205a73338518 drm/i915: Perform manual conversions for plane uapi/hw split
de2e37307e2d drm/i915: Add aliases for uapi and hw to plane_state
87af32bda7a2 drm/i915: Complete crtc hw/uapi split, v2.
9dcebb8f873c drm/i915: Perform automated conversions for crtc uapi/hw split, base -> uapi.
9dcd30df9a3d drm/i915: Perform automated conversions for crtc uapi/hw split, base -> hw.
d34b44583315 drm/i915: Perform manual conversions for crtc uapi/hw split, v2.
892e45082594 drm/i915: Add aliases for uapi and hw to crtc_state
c11aa5f9aecb drm/i915: Handle a few more cases for crtc hw/uapi split, v2.
ec5541f29359 drm/i915: Introduce intel_atomic_get_plane_state_after_check(), v2.
b7926f94b005 drm/i915: Rework watermark readout to use plane api

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH 03/14] drm/i915: Handle a few more cases for crtc hw/uapi split, v2.
  2019-10-17 13:20 ` [PATCH 03/14] drm/i915: Handle a few more cases for crtc hw/uapi split, v2 Maarten Lankhorst
@ 2019-10-18 10:33   ` Ville Syrjälä
  0 siblings, 0 replies; 49+ messages in thread
From: Ville Syrjälä @ 2019-10-18 10:33 UTC (permalink / raw)
  To: Maarten Lankhorst; +Cc: intel-gfx

On Thu, Oct 17, 2019 at 03:20:54PM +0200, Maarten Lankhorst wrote:
> We are still looking at drm_crtc_state in a few places, convert those
> to use intel_crtc_state instead.
> 
> Changes since v1:
> - Move to before uapi/hw split.
> - Add hunks for intel_pm.c as well.
> 
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 14 +++++++-------
>  drivers/gpu/drm/i915/display/intel_dp_mst.c  |  2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c     |  4 ++--
>  drivers/gpu/drm/i915/intel_pm.c              |  6 ++----
>  4 files changed, 12 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 945ab2180614..5632e13d458d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -16092,8 +16092,8 @@ static int intel_initial_commit(struct drm_device *dev)
>  {
>  	struct drm_atomic_state *state = NULL;
>  	struct drm_modeset_acquire_ctx ctx;
> -	struct drm_crtc *crtc;
> -	struct drm_crtc_state *crtc_state;
> +	struct intel_crtc *crtc;
> +	struct intel_crtc_state *crtc_state;

crtc_state declaration can be moved into the loop.

>  	int ret = 0;
>  
>  	state = drm_atomic_state_alloc(dev);
> @@ -16105,15 +16105,15 @@ static int intel_initial_commit(struct drm_device *dev)
>  retry:
>  	state->acquire_ctx = &ctx;
>  
> -	drm_for_each_crtc(crtc, dev) {
> -		crtc_state = drm_atomic_get_crtc_state(state, crtc);
> +	for_each_intel_crtc(dev, crtc) {
> +		crtc_state = intel_atomic_get_crtc_state(state, crtc);
>  		if (IS_ERR(crtc_state)) {
>  			ret = PTR_ERR(crtc_state);
>  			goto out;
>  		}
>  
> -		if (crtc_state->active) {
> -			ret = drm_atomic_add_affected_planes(state, crtc);
> +		if (crtc_state->base.active) {
> +			ret = drm_atomic_add_affected_planes(state, &crtc->base);
>  			if (ret)
>  				goto out;
>  
> @@ -16123,7 +16123,7 @@ static int intel_initial_commit(struct drm_device *dev)
>  			 * having a proper LUT loaded. Remove once we
>  			 * have readout for pipe gamma enable.
>  			 */
> -			crtc_state->color_mgmt_changed = true;
> +			crtc_state->base.color_mgmt_changed = true;

I guess this part would be fine with using the drm stuff since it's a
high level thing, so kinda sits at the uapi level. But probably best
to convert to explicit .uapi anyway.

>  		}
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 2203be28ea01..5484bd4534c1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -187,7 +187,7 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
>  
>  		if (!crtc_state ||
>  		    !drm_atomic_crtc_needs_modeset(crtc_state) ||
> -		    crtc_state->enable)
> +		    to_intel_crtc_state(crtc_state)->base.enable)

I'd prefer to get rid the the struct drm_crtc_state type variable
totally because if it remains I'm sure someone will use it.

>  			return 0;
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 50f22abcd30e..211710f5214c 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1139,9 +1139,9 @@ static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
>  
>  		intel_crtc_state = to_intel_crtc_state(crtc_state);
>  
> -		if (crtc_state->active && intel_crtc_state->has_psr) {
> +		if (intel_crtc_state->base.active && intel_crtc_state->has_psr) {
>  			/* Mark mode as changed to trigger a pipe->update() */
> -			crtc_state->mode_changed = true;
> +			intel_crtc_state->base.mode_changed = true;

Ugh, more aliasing variables. Can we just kill the drm_ one?

Otherwise looks good to me, so
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  			break;
>  		}
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ef36e7834ed4..e680df75a970 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3082,11 +3082,9 @@ static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
>  /* Compute new watermarks for the pipe */
>  static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_atomic_state *state = crtc_state->base.state;
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
>  	struct intel_pipe_wm *pipe_wm;
> -	struct drm_device *dev = state->dev;
> -	const struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_plane *plane;
>  	const struct intel_plane_state *plane_state;
>  	const struct intel_plane_state *pristate = NULL;
> @@ -3781,7 +3779,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
>  	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
>  	crtc_state = to_intel_crtc_state(crtc->base.state);
>  
> -	if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> +	if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
>  		return false;
>  
>  	for_each_intel_plane_on_crtc(dev, crtc, plane) {
> -- 
> 2.23.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH 04/14] drm/i915: Add aliases for uapi and hw to crtc_state
  2019-10-17 13:20 ` [PATCH 04/14] drm/i915: Add aliases for uapi and hw to crtc_state Maarten Lankhorst
@ 2019-10-18 10:36   ` Ville Syrjälä
  2019-10-18 12:09     ` Maarten Lankhorst
  0 siblings, 1 reply; 49+ messages in thread
From: Ville Syrjälä @ 2019-10-18 10:36 UTC (permalink / raw)
  To: Maarten Lankhorst; +Cc: intel-gfx

On Thu, Oct 17, 2019 at 03:20:55PM +0200, Maarten Lankhorst wrote:
> Prepare to split up hw and uapi machinally, by adding a uapi and
> hw alias. We will remove the base in a bit. This is a split from the
> original uapi/hw patch, which did it all in one go.
> 
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_atomic.c   |  8 ++++--
>  drivers/gpu/drm/i915/display/intel_display.c  |  2 ++
>  drivers/gpu/drm/i915/display/intel_display.h  |  6 ++---
>  .../drm/i915/display/intel_display_types.h    | 27 ++++++++++++++++++-
>  4 files changed, 37 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index e6cb85d41c8d..2cdc92897abd 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -186,9 +186,10 @@ intel_digital_connector_duplicate_state(struct drm_connector *connector)
>  struct drm_crtc_state *
>  intel_crtc_duplicate_state(struct drm_crtc *crtc)
>  {
> +	const struct intel_crtc_state *old_crtc_state = to_intel_crtc_state(crtc->state);
>  	struct intel_crtc_state *crtc_state;
>  
> -	crtc_state = kmemdup(crtc->state, sizeof(*crtc_state), GFP_KERNEL);
> +	crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL);
>  	if (!crtc_state)
>  		return NULL;
>  
> @@ -219,7 +220,10 @@ void
>  intel_crtc_destroy_state(struct drm_crtc *crtc,
>  			 struct drm_crtc_state *state)
>  {
> -	drm_atomic_helper_crtc_destroy_state(crtc, state);
> +	struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
> +
> +	__drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
> +	kfree(crtc_state);
>  }
>  
>  static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 5632e13d458d..fa0abfdff2ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12282,6 +12282,8 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
>  
>  	/* Keep base drm_crtc_state intact, only clear our extended struct */
>  	BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
> +	BUILD_BUG_ON(offsetof(struct intel_crtc_state, uapi));
> +	BUILD_BUG_ON(offsetof(struct intel_crtc_state, hw));
>  	memcpy(&crtc_state->base + 1, &saved_state->base + 1,
>  	       sizeof(*crtc_state) - sizeof(crtc_state->base));
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 90807603987c..9b53f65386b5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -444,10 +444,10 @@ enum phy_fia {
>  #define intel_atomic_crtc_state_for_each_plane_state( \
>  		  plane, plane_state, \
>  		  crtc_state) \
> -	for_each_intel_plane_mask(((crtc_state)->base.state->dev), (plane), \
> -				((crtc_state)->base.plane_mask)) \
> +	for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
> +				((crtc_state)->uapi.plane_mask)) \
>  		for_each_if ((plane_state = \
> -			      to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->base.state, &plane->base))))
> +			      to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
>  
>  void intel_link_compute_m_n(u16 bpp, int nlanes,
>  			    int pixel_clock, int link_clock,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 244e881474fb..4d85ea5832d7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -749,7 +749,32 @@ enum intel_output_format {
>  };
>  
>  struct intel_crtc_state {
> +	union {
>  	struct drm_crtc_state base;
> +	/*
> +	 * uapi (drm) state. This is the software state shown to userspace.
> +	 * In particular, the following members are used for bookkeeping:
> +	 * - crtc
> +	 * - state
> +	 * - *_changed
> +	 * - event
> +	 * - commit
> +	 * - mode_blob
> +	 */
> +	struct drm_crtc_state uapi;
> +
> +	/*
> +	 * actual hardware state, the state we program to the hardware.
> +	 * The following members are used to verify the hardware state:
> +	 * - enable
> +	 * - active
> +	 * - mode / adjusted_mode
> +	 * - color property blobs.
> +	 *
> +	 * During initial hw readout, they need to be copied to uapi.
> +	 */
> +	struct drm_crtc_state hw;
> +	};

This part confuses me. Can't we just do

- struct drm_crtc_state base;
+ struct drm_crtc_state uapi;
+ struct {
+	...
+ } base;

?

Or if we somehow need 'base' to remain a drm_crtc_state for a bit then
just start with

+ struct drm_crtc_state uapi;
  struct drm_crtc_state base;

?


>  
>  	/**
>  	 * quirks - bitfield with hw state readout quirks
> @@ -1094,7 +1119,7 @@ struct cxsr_latency {
>  
>  #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
>  #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
> -#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
> +#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
>  #define to_intel_connector(x) container_of(x, struct intel_connector, base)
>  #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
>  #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
> -- 
> 2.23.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 49+ messages in thread

* ✗ Fi.CI.IGT: failure for series starting with [01/14] drm/i915: Rework watermark readout to use plane api (rev2)
  2019-10-17 13:20 [PATCH 01/14] drm/i915: Rework watermark readout to use plane api Maarten Lankhorst
                   ` (17 preceding siblings ...)
  2019-10-18  8:46 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-10-18 10:57 ` Patchwork
  2019-10-18 14:03   ` Maarten Lankhorst
  2019-10-22 18:53 ` ✗ Fi.CI.BUILD: failure for series starting with [01/14] drm/i915: Rework watermark readout to use plane api (rev3) Patchwork
  19 siblings, 1 reply; 49+ messages in thread
From: Patchwork @ 2019-10-18 10:57 UTC (permalink / raw)
  To: Maarten Lankhorst; +Cc: intel-gfx

== Series Details ==

Series: series starting with [01/14] drm/i915: Rework watermark readout to use plane api (rev2)
URL   : https://patchwork.freedesktop.org/series/68154/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7125_full -> Patchwork_14874_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_14874_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_14874_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14874_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_ctx_switch@queue-light:
    - shard-glk:          [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-glk6/igt@gem_ctx_switch@queue-light.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-glk7/igt@gem_ctx_switch@queue-light.html

  * igt@kms_plane@pixel-format-pipe-b-planes:
    - shard-kbl:          [PASS][3] -> [FAIL][4] +3 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-kbl3/igt@kms_plane@pixel-format-pipe-b-planes.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-kbl3/igt@kms_plane@pixel-format-pipe-b-planes.html

  * igt@kms_plane@pixel-format-pipe-c-planes:
    - shard-glk:          [PASS][5] -> [FAIL][6] +5 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-glk4/igt@kms_plane@pixel-format-pipe-c-planes.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-glk8/igt@kms_plane@pixel-format-pipe-c-planes.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@mock_requests:
    - {shard-tglb}:       NOTRUN -> [INCOMPLETE][7] +2 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-tglb2/igt@i915_selftest@mock_requests.html

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-d:
    - {shard-tglb}:       [PASS][8] -> [INCOMPLETE][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-tglb1/igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-d.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-tglb3/igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-d.html

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - {shard-tglb}:       NOTRUN -> [FAIL][10] +1 similar issue
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-tglb6/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html

  
Known issues
------------

  Here are the changes found in Patchwork_14874_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@in-flight-contexts-immediate:
    - shard-snb:          [PASS][11] -> [FAIL][12] ([fdo#111925])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-snb2/igt@gem_eio@in-flight-contexts-immediate.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-snb5/igt@gem_eio@in-flight-contexts-immediate.html

  * igt@gem_exec_schedule@in-order-bsd:
    - shard-iclb:         [PASS][13] -> [SKIP][14] ([fdo#111325]) +5 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-iclb5/igt@gem_exec_schedule@in-order-bsd.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-iclb1/igt@gem_exec_schedule@in-order-bsd.html

  * igt@gem_exec_schedule@promotion-bsd1:
    - shard-iclb:         [PASS][15] -> [SKIP][16] ([fdo#109276]) +8 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-iclb2/igt@gem_exec_schedule@promotion-bsd1.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-iclb6/igt@gem_exec_schedule@promotion-bsd1.html

  * igt@gem_pipe_control_store_loop@reused-buffer:
    - shard-iclb:         [PASS][17] -> [INCOMPLETE][18] ([fdo#107713])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-iclb5/igt@gem_pipe_control_store_loop@reused-buffer.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-iclb1/igt@gem_pipe_control_store_loop@reused-buffer.html

  * igt@i915_suspend@sysfs-reader:
    - shard-apl:          [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-apl6/igt@i915_suspend@sysfs-reader.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-apl7/igt@i915_suspend@sysfs-reader.html

  * igt@kms_flip@plain-flip-ts-check-interruptible:
    - shard-skl:          [PASS][21] -> [FAIL][22] ([fdo#100368])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-skl9/igt@kms_flip@plain-flip-ts-check-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
    - shard-iclb:         [PASS][23] -> [FAIL][24] ([fdo#103167]) +3 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_plane@pixel-format-pipe-b-planes:
    - shard-iclb:         [PASS][25] -> [DMESG-FAIL][26] ([fdo#107724]) +4 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-iclb7/igt@kms_plane@pixel-format-pipe-b-planes.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-iclb8/igt@kms_plane@pixel-format-pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][27] -> [FAIL][28] ([fdo#108145] / [fdo#110403])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_plane_lowres@pipe-a-tiling-y:
    - shard-iclb:         [PASS][29] -> [FAIL][30] ([fdo#103166])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-y.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html

  * igt@kms_plane_scaling@pipe-b-scaler-with-rotation:
    - shard-iclb:         [PASS][31] -> [DMESG-WARN][32] ([fdo#107724]) +6 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-iclb3/igt@kms_plane_scaling@pipe-b-scaler-with-rotation.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-iclb5/igt@kms_plane_scaling@pipe-b-scaler-with-rotation.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [PASS][33] -> [SKIP][34] ([fdo#109642] / [fdo#111068])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-iclb6/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [PASS][35] -> [SKIP][36] ([fdo#109441]) +2 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-iclb8/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-iclb:         [PASS][37] -> [DMESG-WARN][38] ([fdo#107724] / [fdo#108336])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-iclb5/igt@kms_rotation_crc@bad-pixel-format.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-iclb1/igt@kms_rotation_crc@bad-pixel-format.html

  * igt@kms_rotation_crc@multiplane-rotation:
    - shard-iclb:         [PASS][39] -> [FAIL][40] ([fdo#109016]) +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-iclb3/igt@kms_rotation_crc@multiplane-rotation.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-iclb5/igt@kms_rotation_crc@multiplane-rotation.html

  * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
    - shard-glk:          [PASS][41] -> [FAIL][42] ([fdo#109016]) +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-glk7/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-glk6/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-kbl:          [PASS][43] -> [FAIL][44] ([fdo#109016]) +2 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-kbl4/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-kbl4/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][45] -> [FAIL][46] ([fdo#99912])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-apl4/igt@kms_setmode@basic.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-apl6/igt@kms_setmode@basic.html
    - shard-hsw:          [PASS][47] -> [FAIL][48] ([fdo#99912])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-hsw6/igt@kms_setmode@basic.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-hsw6/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-c-query-forked-hang:
    - shard-apl:          [PASS][49] -> [INCOMPLETE][50] ([fdo#103927])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-apl8/igt@kms_vblank@pipe-c-query-forked-hang.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-apl4/igt@kms_vblank@pipe-c-query-forked-hang.html

  
#### Possible fixes ####

  * igt@gem_eio@in-flight-contexts-1us:
    - shard-snb:          [FAIL][51] -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-snb4/igt@gem_eio@in-flight-contexts-1us.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-snb4/igt@gem_eio@in-flight-contexts-1us.html

  * igt@gem_eio@reset-stress:
    - shard-snb:          [FAIL][53] ([fdo#109661]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-snb1/igt@gem_eio@reset-stress.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-snb1/igt@gem_eio@reset-stress.html

  * igt@gem_exec_schedule@preempt-hang-bsd:
    - shard-iclb:         [SKIP][55] ([fdo#111325]) -> [PASS][56] +1 similar issue
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-iclb2/igt@gem_exec_schedule@preempt-hang-bsd.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-iclb6/igt@gem_exec_schedule@preempt-hang-bsd.html

  * igt@gem_linear_blits@normal:
    - shard-apl:          [INCOMPLETE][57] ([fdo#103927]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-apl2/igt@gem_linear_blits@normal.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-apl4/igt@gem_linear_blits@normal.html

  * igt@gem_softpin@noreloc-s3:
    - shard-skl:          [INCOMPLETE][59] ([fdo#104108]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-skl2/igt@gem_softpin@noreloc-s3.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-skl4/igt@gem_softpin@noreloc-s3.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
    - shard-hsw:          [DMESG-WARN][61] ([fdo#111870]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-hsw6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-hsw8/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
    - shard-snb:          [SKIP][63] ([fdo#109271]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-snb6/igt@i915_pm_rc6_residency@rc6-accuracy.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-snb5/igt@i915_pm_rc6_residency@rc6-accuracy.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-apl:          [DMESG-WARN][65] ([fdo#108566]) -> [PASS][66] +2 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-apl1/igt@i915_suspend@fence-restore-tiled2untiled.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-apl1/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
    - shard-hsw:          [FAIL][67] ([fdo#105767]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
    - {shard-tglb}:       [INCOMPLETE][69] ([fdo#112035 ]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-tglb2/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-tglb3/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank:
    - shard-skl:          [FAIL][71] -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-skl9/igt@kms_flip@flip-vs-blocking-wf-vblank.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-skl3/igt@kms_flip@flip-vs-blocking-wf-vblank.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-glk:          [FAIL][73] ([fdo#105363]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-glk1/igt@kms_flip@flip-vs-expired-vblank.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-glk3/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [FAIL][75] ([fdo#105363]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-hsw:          [INCOMPLETE][77] ([fdo#103540]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-hsw1/igt@kms_flip@flip-vs-suspend-interruptible.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-hsw8/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@plain-flip-fb-recreate:
    - shard-skl:          [FAIL][79] ([fdo#100368]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-skl3/igt@kms_flip@plain-flip-fb-recreate.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-skl8/igt@kms_flip@plain-flip-fb-recreate.html

  * igt@kms_flip_tiling@flip-x-tiled:
    - shard-skl:          [FAIL][81] ([fdo#108145] / [fdo#108303]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-skl3/igt@kms_flip_tiling@flip-x-tiled.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-skl8/igt@kms_flip_tiling@flip-x-tiled.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt:
    - shard-iclb:         [FAIL][83] ([fdo#103167]) -> [PASS][84] +5 similar issues
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html

  * igt@kms_psr@psr2_dpms:
    - shard-iclb:         [SKIP][85] ([fdo#109441]) -> [PASS][86] +2 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-iclb1/igt@kms_psr@psr2_dpms.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-iclb2/igt@kms_psr@psr2_dpms.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [SKIP][87] ([fdo#109276]) -> [PASS][88] +11 similar issues
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-iclb6/igt@prime_busy@hang-bsd2.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-iclb1/igt@prime_busy@hang-bsd2.html

  
#### Warnings ####

  * igt@gem_mocs_settings@mocs-settings-bsd2:
    - shard-iclb:         [SKIP][89] ([fdo#109276]) -> [FAIL][90] ([fdo#111330])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-iclb5/igt@gem_mocs_settings@mocs-settings-bsd2.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-iclb1/igt@gem_mocs_settings@mocs-settings-bsd2.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108303]: https://bugs.freedesktop.org/show_bug.cgi?id=108303
  [fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110548]: https://bugs.freedesktop.org/show_bug.cgi?id=110548
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
  [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
  [fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
  [fdo#111703]: https://bugs.freedesktop.org/show_bug.cgi?id=111703
  [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
  [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
  [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#111925]: https://bugs.freedesktop.org/show_bug.cgi?id=111925
  [fdo#112035 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112035 
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participa

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH 04/14] drm/i915: Add aliases for uapi and hw to crtc_state
  2019-10-18 10:36   ` Ville Syrjälä
@ 2019-10-18 12:09     ` Maarten Lankhorst
  2019-10-18 13:09       ` Ville Syrjälä
  0 siblings, 1 reply; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-18 12:09 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

Op 18-10-2019 om 12:36 schreef Ville Syrjälä:
> On Thu, Oct 17, 2019 at 03:20:55PM +0200, Maarten Lankhorst wrote:
>> Prepare to split up hw and uapi machinally, by adding a uapi and
>> hw alias. We will remove the base in a bit. This is a split from the
>> original uapi/hw patch, which did it all in one go.
>>
>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_atomic.c   |  8 ++++--
>>  drivers/gpu/drm/i915/display/intel_display.c  |  2 ++
>>  drivers/gpu/drm/i915/display/intel_display.h  |  6 ++---
>>  .../drm/i915/display/intel_display_types.h    | 27 ++++++++++++++++++-
>>  4 files changed, 37 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
>> index e6cb85d41c8d..2cdc92897abd 100644
>> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
>> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
>> @@ -186,9 +186,10 @@ intel_digital_connector_duplicate_state(struct drm_connector *connector)
>>  struct drm_crtc_state *
>>  intel_crtc_duplicate_state(struct drm_crtc *crtc)
>>  {
>> +	const struct intel_crtc_state *old_crtc_state = to_intel_crtc_state(crtc->state);
>>  	struct intel_crtc_state *crtc_state;
>>  
>> -	crtc_state = kmemdup(crtc->state, sizeof(*crtc_state), GFP_KERNEL);
>> +	crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL);
>>  	if (!crtc_state)
>>  		return NULL;
>>  
>> @@ -219,7 +220,10 @@ void
>>  intel_crtc_destroy_state(struct drm_crtc *crtc,
>>  			 struct drm_crtc_state *state)
>>  {
>> -	drm_atomic_helper_crtc_destroy_state(crtc, state);
>> +	struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
>> +
>> +	__drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
>> +	kfree(crtc_state);
>>  }
>>  
>>  static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 5632e13d458d..fa0abfdff2ae 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -12282,6 +12282,8 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
>>  
>>  	/* Keep base drm_crtc_state intact, only clear our extended struct */
>>  	BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
>> +	BUILD_BUG_ON(offsetof(struct intel_crtc_state, uapi));
>> +	BUILD_BUG_ON(offsetof(struct intel_crtc_state, hw));
>>  	memcpy(&crtc_state->base + 1, &saved_state->base + 1,
>>  	       sizeof(*crtc_state) - sizeof(crtc_state->base));
>>  
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
>> index 90807603987c..9b53f65386b5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display.h
>> @@ -444,10 +444,10 @@ enum phy_fia {
>>  #define intel_atomic_crtc_state_for_each_plane_state( \
>>  		  plane, plane_state, \
>>  		  crtc_state) \
>> -	for_each_intel_plane_mask(((crtc_state)->base.state->dev), (plane), \
>> -				((crtc_state)->base.plane_mask)) \
>> +	for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
>> +				((crtc_state)->uapi.plane_mask)) \
>>  		for_each_if ((plane_state = \
>> -			      to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->base.state, &plane->base))))
>> +			      to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
>>  
>>  void intel_link_compute_m_n(u16 bpp, int nlanes,
>>  			    int pixel_clock, int link_clock,
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 244e881474fb..4d85ea5832d7 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -749,7 +749,32 @@ enum intel_output_format {
>>  };
>>  
>>  struct intel_crtc_state {
>> +	union {
>>  	struct drm_crtc_state base;
>> +	/*
>> +	 * uapi (drm) state. This is the software state shown to userspace.
>> +	 * In particular, the following members are used for bookkeeping:
>> +	 * - crtc
>> +	 * - state
>> +	 * - *_changed
>> +	 * - event
>> +	 * - commit
>> +	 * - mode_blob
>> +	 */
>> +	struct drm_crtc_state uapi;
>> +
>> +	/*
>> +	 * actual hardware state, the state we program to the hardware.
>> +	 * The following members are used to verify the hardware state:
>> +	 * - enable
>> +	 * - active
>> +	 * - mode / adjusted_mode
>> +	 * - color property blobs.
>> +	 *
>> +	 * During initial hw readout, they need to be copied to uapi.
>> +	 */
>> +	struct drm_crtc_state hw;
>> +	};
> This part confuses me. Can't we just do
>
> - struct drm_crtc_state base;
> + struct drm_crtc_state uapi;
> + struct {
> +	...
> + } base;
>
> ?

This is basically union { struct drm_crtc_state uapi,base,hw; }; Making all 3 aliases until patch 8/14, which kills off base and splits off hw state.

We keep it as an union because base and uapi temporarily have to be kept in sync, while we split to uapi and hw. So it's easy to keep hw in sync as well.

In the end it doesn't matter whether we split off hw before or after. The diff between before and after is the same.

So does it look ok now? I can't keep reworking patches. I can merge 8/14 to this patch, and remove the union between base and uapi as patch 8/14.

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^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH 06/14] drm/i915: Perform automated conversions for crtc uapi/hw split, base -> hw.
  2019-10-17 13:20 ` [PATCH 06/14] drm/i915: Perform automated conversions for crtc uapi/hw split, base -> hw Maarten Lankhorst
@ 2019-10-18 12:59   ` Ville Syrjälä
  0 siblings, 0 replies; 49+ messages in thread
From: Ville Syrjälä @ 2019-10-18 12:59 UTC (permalink / raw)
  To: Maarten Lankhorst; +Cc: intel-gfx

On Thu, Oct 17, 2019 at 03:20:57PM +0200, Maarten Lankhorst wrote:
> Split up crtc_state->base to hw where appropriate. This is done using the following patch:
> 
> @@
> struct intel_crtc_state *T;
> identifier x =~ "^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
> @@
> -T->base.x
> +T->hw.x
> 
> @@
> struct drm_crtc_state *T;
> identifier x =~ "^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
> @@
> -to_intel_crtc_state(T)->base.x
> +to_intel_crtc_state(T)->hw.x

Ok, this is just now doing the s/base/hw/

Thanks. I *should* be able to read through this I think :)

> 
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c        |  12 +-
>  drivers/gpu/drm/i915/display/intel_audio.c    |   4 +-
>  drivers/gpu/drm/i915/display/intel_cdclk.c    |   8 +-
>  drivers/gpu/drm/i915/display/intel_color.c    | 108 ++++----
>  drivers/gpu/drm/i915/display/intel_crt.c      |  18 +-
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  18 +-
>  drivers/gpu/drm/i915/display/intel_display.c  | 252 +++++++++---------
>  drivers/gpu/drm/i915/display/intel_dp.c       |  22 +-
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   |   6 +-
>  drivers/gpu/drm/i915/display/intel_dvo.c      |  12 +-
>  drivers/gpu/drm/i915/display/intel_fbc.c      |   2 +-
>  drivers/gpu/drm/i915/display/intel_hdmi.c     |  20 +-
>  drivers/gpu/drm/i915/display/intel_lspcon.c   |   4 +-
>  drivers/gpu/drm/i915/display/intel_lvds.c     |   8 +-
>  drivers/gpu/drm/i915/display/intel_panel.c    |   8 +-
>  drivers/gpu/drm/i915/display/intel_pipe_crc.c |   2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c      |  12 +-
>  drivers/gpu/drm/i915/display/intel_sdvo.c     |  16 +-
>  drivers/gpu/drm/i915/display/intel_sprite.c   |   8 +-
>  drivers/gpu/drm/i915/display/intel_tv.c       |   4 +-
>  drivers/gpu/drm/i915/display/intel_vdsc.c     |   4 +-
>  drivers/gpu/drm/i915/display/vlv_dsi.c        |  10 +-
>  drivers/gpu/drm/i915/i915_debugfs.c           |   8 +-
>  drivers/gpu/drm/i915/intel_pm.c               |  62 ++---
>  24 files changed, 316 insertions(+), 312 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 6e398c33a524..4ec493e4755b 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -276,7 +276,7 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
>  
>  	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>  		const struct drm_display_mode *adjusted_mode =
> -					&pipe_config->base.adjusted_mode;
> +					&pipe_config->hw.adjusted_mode;
>  		u32 dss_ctl2;
>  		u16 hactive = adjusted_mode->crtc_hdisplay;
>  		u16 dl_buffer_depth;
> @@ -768,7 +768,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	const struct drm_display_mode *adjusted_mode =
> -					&pipe_config->base.adjusted_mode;
> +					&pipe_config->hw.adjusted_mode;
>  	enum port port;
>  	enum transcoder dsi_trans;
>  	/* horizontal timings */
> @@ -1216,7 +1216,7 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
>  {
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	struct drm_display_mode *adjusted_mode =
> -					&pipe_config->base.adjusted_mode;
> +					&pipe_config->hw.adjusted_mode;
>  
>  	if (intel_dsi->dual_link) {
>  		adjusted_mode->crtc_hdisplay *= 2;
> @@ -1249,9 +1249,9 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
>  	pipe_config->port_clock =
>  		cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
>  
> -	pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
> +	pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
>  	if (intel_dsi->dual_link)
> -		pipe_config->base.adjusted_mode.crtc_clock *= 2;
> +		pipe_config->hw.adjusted_mode.crtc_clock *= 2;
>  
>  	gen11_dsi_get_timings(encoder, pipe_config);
>  	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
> @@ -1269,7 +1269,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
>  	const struct drm_display_mode *fixed_mode =
>  					intel_connector->panel.fixed_mode;
>  	struct drm_display_mode *adjusted_mode =
> -					&pipe_config->base.adjusted_mode;
> +					&pipe_config->hw.adjusted_mode;
>  
>  	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>  	intel_fixed_panel_mode(fixed_mode, adjusted_mode);
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index ed18511befa3..6a58e8ad86f8 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -233,7 +233,7 @@ static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
>  static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
>  {
>  	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->base.adjusted_mode;
> +		&crtc_state->hw.adjusted_mode;
>  	int i;
>  
>  	for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
> @@ -694,7 +694,7 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	struct drm_connector *connector = conn_state->connector;
>  	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->base.adjusted_mode;
> +		&crtc_state->hw.adjusted_mode;
>  	enum port port = encoder->port;
>  	enum pipe pipe = crtc->pipe;
>  

IIRC I had some concerns about the audio stuff, but this looks correct
to me. I guess my concerns were the usual "argh, still using crtc->config!".

OK, I think it all looks good. The one problem with this patch is that
you're not nuking .base at the same time so the fact that this (hopefully)
compiles doesn't prove that you converted absolutely everything.

So with some reservations (due to .base lingering around) this is:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index ab1f7cec50c6..fd1ed0fb8748 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1924,7 +1924,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>  		to_i915(crtc_state->base.crtc->dev);
>  	int min_cdclk;
>  
> -	if (!crtc_state->base.enable)
> +	if (!crtc_state->hw.enable)
>  		return 0;
>  
>  	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
> @@ -2047,7 +2047,7 @@ static u8 bxt_compute_min_voltage_level(struct intel_atomic_state *state)
>  	       sizeof(state->min_voltage_level));
>  
>  	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> -		if (crtc_state->base.enable)
> +		if (crtc_state->hw.enable)
>  			state->min_voltage_level[i] =
>  				crtc_state->min_voltage_level;
>  		else
> @@ -2133,7 +2133,7 @@ static int skl_dpll0_vco(struct intel_atomic_state *state)
>  		vco = dev_priv->skl_preferred_vco_freq;
>  
>  	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> -		if (!crtc_state->base.enable)
> +		if (!crtc_state->hw.enable)
>  			continue;
>  
>  		if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> @@ -2260,7 +2260,7 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
>  		if (IS_ERR(crtc_state))
>  			return PTR_ERR(crtc_state);
>  
> -		if (!crtc_state->base.active ||
> +		if (!crtc_state->hw.active ||
>  		    drm_atomic_crtc_needs_modeset(&crtc_state->base))
>  			continue;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 95586a588234..65e1b18bd7e3 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -117,10 +117,10 @@ static bool lut_is_legacy(const struct drm_property_blob *lut)
>  
>  static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state)
>  {
> -	return !crtc_state->base.degamma_lut &&
> -		!crtc_state->base.ctm &&
> -		crtc_state->base.gamma_lut &&
> -		lut_is_legacy(crtc_state->base.gamma_lut);
> +	return !crtc_state->hw.degamma_lut &&
> +		!crtc_state->hw.ctm &&
> +		crtc_state->hw.gamma_lut &&
> +		lut_is_legacy(crtc_state->hw.gamma_lut);
>  }
>  
>  /*
> @@ -219,7 +219,7 @@ static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
>  static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
>  				u16 coeffs[9])
>  {
> -	const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
> +	const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
>  	const u64 *input;
>  	u64 temp[9];
>  	int i;
> @@ -274,7 +274,7 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	bool limited_color_range = ilk_csc_limited_range(crtc_state);
>  
> -	if (crtc_state->base.ctm) {
> +	if (crtc_state->hw.ctm) {
>  		u16 coeff[9];
>  
>  		ilk_csc_convert_ctm(crtc_state, coeff);
> @@ -312,7 +312,7 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
> -	if (crtc_state->base.ctm) {
> +	if (crtc_state->hw.ctm) {
>  		u16 coeff[9];
>  
>  		ilk_csc_convert_ctm(crtc_state, coeff);
> @@ -342,8 +342,8 @@ static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  
> -	if (crtc_state->base.ctm) {
> -		const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
> +	if (crtc_state->hw.ctm) {
> +		const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
>  		u16 coeffs[9] = {};
>  		int i;
>  
> @@ -435,7 +435,7 @@ static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
>  
>  static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
>  {
> -	i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
> +	i9xx_load_luts_internal(crtc_state, crtc_state->hw.gamma_lut);
>  }
>  
>  static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
> @@ -525,7 +525,7 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc,
>  static void i965_load_luts(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> -	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> +	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
>  
>  	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
>  		i9xx_load_luts(crtc_state);
> @@ -548,7 +548,7 @@ static void ilk_load_lut_10(struct intel_crtc *crtc,
>  static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> -	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> +	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
>  
>  	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
>  		i9xx_load_luts(crtc_state);
> @@ -655,8 +655,8 @@ static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
>  static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> -	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> -	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
> +	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> +	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
>  
>  	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
>  		i9xx_load_luts(crtc_state);
> @@ -678,8 +678,8 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
>  static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> -	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> -	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
> +	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> +	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
>  
>  	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
>  		i9xx_load_luts(crtc_state);
> @@ -704,7 +704,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  	const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> -	const struct drm_color_lut *lut = crtc_state->base.degamma_lut->data;
> +	const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
>  	u32 i;
>  
>  	/*
> @@ -766,7 +766,7 @@ static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_stat
>  
>  static void glk_load_luts(const struct intel_crtc_state *crtc_state)
>  {
> -	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> +	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  
>  	/*
> @@ -777,7 +777,7 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
>  	 * the degama LUT so that we don't have to reload
>  	 * it every time the pipe CSC is being enabled.
>  	 */
> -	if (crtc_state->base.degamma_lut)
> +	if (crtc_state->hw.degamma_lut)
>  		glk_load_degamma_lut(crtc_state);
>  	else
>  		glk_load_degamma_lut_linear(crtc_state);
> @@ -823,7 +823,7 @@ static void
>  icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> -	const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
> +	const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
>  	const struct drm_color_lut *lut = blob->data;
>  	struct intel_dsb *dsb = intel_dsb_get(crtc);
>  	enum pipe pipe = crtc->pipe;
> @@ -855,7 +855,7 @@ static void
>  icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> -	const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
> +	const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
>  	const struct drm_color_lut *lut = blob->data;
>  	const struct drm_color_lut *entry;
>  	struct intel_dsb *dsb = intel_dsb_get(crtc);
> @@ -910,11 +910,11 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
>  
>  static void icl_load_luts(const struct intel_crtc_state *crtc_state)
>  {
> -	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> +	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	struct intel_dsb *dsb = intel_dsb_get(crtc);
>  
> -	if (crtc_state->base.degamma_lut)
> +	if (crtc_state->hw.degamma_lut)
>  		glk_load_degamma_lut(crtc_state);
>  
>  	switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
> @@ -991,8 +991,8 @@ static void chv_load_cgm_gamma(struct intel_crtc *crtc,
>  static void chv_load_luts(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> -	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> -	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
> +	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> +	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
>  
>  	cherryview_load_csc_matrix(crtc_state);
>  
> @@ -1063,7 +1063,7 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
>  		intel_atomic_get_old_crtc_state(state, crtc);
>  	struct intel_plane *plane;
>  
> -	if (!new_crtc_state->base.active ||
> +	if (!new_crtc_state->hw.active ||
>  	    drm_atomic_crtc_needs_modeset(&new_crtc_state->base))
>  		return 0;
>  
> @@ -1108,8 +1108,8 @@ static int check_lut_size(const struct drm_property_blob *lut, int expected)
>  static int check_luts(const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> -	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> -	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
> +	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> +	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
>  	int gamma_length, degamma_length;
>  	u32 gamma_tests, degamma_tests;
>  
> @@ -1157,7 +1157,7 @@ static int i9xx_color_check(struct intel_crtc_state *crtc_state)
>  		return ret;
>  
>  	crtc_state->gamma_enable =
> -		crtc_state->base.gamma_lut &&
> +		crtc_state->hw.gamma_lut &&
>  		!crtc_state->c8_planes;
>  
>  	crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
> @@ -1176,11 +1176,11 @@ static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
>  	if (crtc_state_is_legacy_gamma(crtc_state))
>  		return 0;
>  
> -	if (crtc_state->base.degamma_lut)
> +	if (crtc_state->hw.degamma_lut)
>  		cgm_mode |= CGM_PIPE_MODE_DEGAMMA;
> -	if (crtc_state->base.ctm)
> +	if (crtc_state->hw.ctm)
>  		cgm_mode |= CGM_PIPE_MODE_CSC;
> -	if (crtc_state->base.gamma_lut)
> +	if (crtc_state->hw.gamma_lut)
>  		cgm_mode |= CGM_PIPE_MODE_GAMMA;
>  
>  	return cgm_mode;
> @@ -1254,7 +1254,7 @@ static int ilk_color_check(struct intel_crtc_state *crtc_state)
>  		return ret;
>  
>  	crtc_state->gamma_enable =
> -		crtc_state->base.gamma_lut &&
> +		crtc_state->hw.gamma_lut &&
>  		!crtc_state->c8_planes;
>  
>  	/*
> @@ -1280,8 +1280,8 @@ static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)
>  	if (!crtc_state->gamma_enable ||
>  	    crtc_state_is_legacy_gamma(crtc_state))
>  		return GAMMA_MODE_MODE_8BIT;
> -	else if (crtc_state->base.gamma_lut &&
> -		 crtc_state->base.degamma_lut)
> +	else if (crtc_state->hw.gamma_lut &&
> +		 crtc_state->hw.degamma_lut)
>  		return GAMMA_MODE_MODE_SPLIT;
>  	else
>  		return GAMMA_MODE_MODE_10BIT;
> @@ -1295,7 +1295,7 @@ static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
>  	 * CSC comes after the LUT in degamma, RGB->YCbCr,
>  	 * and RGB full->limited range mode.
>  	 */
> -	if (crtc_state->base.degamma_lut ||
> +	if (crtc_state->hw.degamma_lut ||
>  	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
>  	    limited_color_range)
>  		return 0;
> @@ -1313,13 +1313,13 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state)
>  		return ret;
>  
>  	crtc_state->gamma_enable =
> -		(crtc_state->base.gamma_lut ||
> -		 crtc_state->base.degamma_lut) &&
> +		(crtc_state->hw.gamma_lut ||
> +		 crtc_state->hw.degamma_lut) &&
>  		!crtc_state->c8_planes;
>  
>  	crtc_state->csc_enable =
>  		crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
> -		crtc_state->base.ctm || limited_color_range;
> +		crtc_state->hw.ctm || limited_color_range;
>  
>  	crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);
>  
> @@ -1350,14 +1350,14 @@ static int glk_color_check(struct intel_crtc_state *crtc_state)
>  		return ret;
>  
>  	crtc_state->gamma_enable =
> -		crtc_state->base.gamma_lut &&
> +		crtc_state->hw.gamma_lut &&
>  		!crtc_state->c8_planes;
>  
>  	/* On GLK+ degamma LUT is controlled by csc_enable */
>  	crtc_state->csc_enable =
> -		crtc_state->base.degamma_lut ||
> +		crtc_state->hw.degamma_lut ||
>  		crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
> -		crtc_state->base.ctm || crtc_state->limited_color_range;
> +		crtc_state->hw.ctm || crtc_state->limited_color_range;
>  
>  	crtc_state->gamma_mode = glk_gamma_mode(crtc_state);
>  
> @@ -1374,14 +1374,14 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
>  {
>  	u32 gamma_mode = 0;
>  
> -	if (crtc_state->base.degamma_lut)
> +	if (crtc_state->hw.degamma_lut)
>  		gamma_mode |= PRE_CSC_GAMMA_ENABLE;
>  
> -	if (crtc_state->base.gamma_lut &&
> +	if (crtc_state->hw.gamma_lut &&
>  	    !crtc_state->c8_planes)
>  		gamma_mode |= POST_CSC_GAMMA_ENABLE;
>  
> -	if (!crtc_state->base.gamma_lut ||
> +	if (!crtc_state->hw.gamma_lut ||
>  	    crtc_state_is_legacy_gamma(crtc_state))
>  		gamma_mode |= GAMMA_MODE_MODE_8BIT;
>  	else
> @@ -1394,7 +1394,7 @@ static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)
>  {
>  	u32 csc_mode = 0;
>  
> -	if (crtc_state->base.ctm)
> +	if (crtc_state->hw.ctm)
>  		csc_mode |= ICL_CSC_ENABLE;
>  
>  	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
> @@ -1623,7 +1623,7 @@ static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
>  	if (!crtc_state->gamma_enable)
>  		return;
>  
> -	crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> +	crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
>  }
>  
>  static struct drm_property_blob *
> @@ -1673,9 +1673,9 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
>  		return;
>  
>  	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> -		crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> +		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
>  	else
> -		crtc_state->base.gamma_lut = i965_read_lut_10p6(crtc_state);
> +		crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc_state);
>  }
>  
>  static struct drm_property_blob *
> @@ -1715,7 +1715,7 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
>  static void chv_read_luts(struct intel_crtc_state *crtc_state)
>  {
>  	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
> -		crtc_state->base.gamma_lut = chv_read_cgm_lut(crtc_state);
> +		crtc_state->hw.gamma_lut = chv_read_cgm_lut(crtc_state);
>  	else
>  		i965_read_luts(crtc_state);
>  }
> @@ -1762,9 +1762,9 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
>  		return;
>  
>  	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> -		crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> +		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
>  	else
> -		crtc_state->base.gamma_lut = ilk_read_lut_10(crtc_state);
> +		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc_state);
>  }
>  
>  static struct drm_property_blob *
> @@ -1811,9 +1811,9 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
>  		return;
>  
>  	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> -		crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> +		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
>  	else
> -		crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
> +		crtc_state->hw.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
>  }
>  
>  void intel_color_init(struct intel_crtc *crtc)
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index ff6126ea793c..399abc3d521e 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -132,9 +132,9 @@ static void intel_crt_get_config(struct intel_encoder *encoder,
>  {
>  	pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
>  
> -	pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
> +	pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
>  
> -	pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
> +	pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
>  }
>  
>  static void hsw_crt_get_config(struct intel_encoder *encoder,
> @@ -144,13 +144,13 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
>  
>  	intel_ddi_get_config(encoder, pipe_config);
>  
> -	pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
> +	pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
>  					      DRM_MODE_FLAG_NHSYNC |
>  					      DRM_MODE_FLAG_PVSYNC |
>  					      DRM_MODE_FLAG_NVSYNC);
> -	pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
> +	pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
>  
> -	pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
> +	pipe_config->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
>  }
>  
>  /* Note: The caller is required to filter out dpms modes not supported by the
> @@ -162,7 +162,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_crt *crt = intel_encoder_to_crt(encoder);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> -	const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>  	u32 adpa;
>  
>  	if (INTEL_GEN(dev_priv) >= 5)
> @@ -358,7 +358,7 @@ static int intel_crt_compute_config(struct intel_encoder *encoder,
>  				    struct drm_connector_state *conn_state)
>  {
>  	struct drm_display_mode *adjusted_mode =
> -		&pipe_config->base.adjusted_mode;
> +		&pipe_config->hw.adjusted_mode;
>  
>  	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
>  		return -EINVAL;
> @@ -373,7 +373,7 @@ static int pch_crt_compute_config(struct intel_encoder *encoder,
>  				  struct drm_connector_state *conn_state)
>  {
>  	struct drm_display_mode *adjusted_mode =
> -		&pipe_config->base.adjusted_mode;
> +		&pipe_config->hw.adjusted_mode;
>  
>  	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
>  		return -EINVAL;
> @@ -390,7 +390,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct drm_display_mode *adjusted_mode =
> -		&pipe_config->base.adjusted_mode;
> +		&pipe_config->hw.adjusted_mode;
>  
>  	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
>  		return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4c81449ec144..c8639b92a6da 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1528,7 +1528,7 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
>  	if (pipe_config->pixel_multiplier)
>  		dotclock /= pipe_config->pixel_multiplier;
>  
> -	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> +	pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
>  }
>  
>  static void icl_ddi_clock_get(struct intel_encoder *encoder,
> @@ -1860,9 +1860,9 @@ intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
>  		BUG();
>  	}
>  
> -	if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
> +	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
>  		temp |= TRANS_DDI_PVSYNC;
> -	if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
> +	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
>  		temp |= TRANS_DDI_PHSYNC;
>  
>  	if (cpu_transcoder == TRANSCODER_EDP) {
> @@ -3371,7 +3371,7 @@ static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
>  {
>  	u32 exit_scanlines;
>  	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
> -	u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay;
> +	u32 crtc_vdisplay = cstate->hw.adjusted_mode.crtc_vdisplay;
>  
>  	cstate->dc3co_exitline = 0;
>  
> @@ -3383,7 +3383,7 @@ static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
>  	    encoder->port != PORT_A)
>  		return;
>  
> -	if (!cstate->has_psr2 || !cstate->base.active)
> +	if (!cstate->has_psr2 || !cstate->hw.active)
>  		return;
>  
>  	/*
> @@ -3391,7 +3391,7 @@ static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
>  	 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
>  	 */
>  	exit_scanlines =
> -		intel_usecs_to_scanlines(&cstate->base.adjusted_mode, 200) + 1;
> +		intel_usecs_to_scanlines(&cstate->hw.adjusted_mode, 200) + 1;
>  
>  	if (WARN_ON(exit_scanlines > crtc_vdisplay))
>  		return;
> @@ -4076,7 +4076,7 @@ intel_ddi_update_prepare(struct intel_atomic_state *state,
>  	WARN_ON(crtc && crtc->active);
>  
>  	intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes);
> -	if (crtc_state && crtc_state->base.active)
> +	if (crtc_state && crtc_state->hw.active)
>  		intel_update_active_dpll(state, crtc, encoder);
>  }
>  
> @@ -4224,7 +4224,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>  	else
>  		flags |= DRM_MODE_FLAG_NVSYNC;
>  
> -	pipe_config->base.adjusted_mode.flags |= flags;
> +	pipe_config->hw.adjusted_mode.flags |= flags;
>  
>  	switch (temp & TRANS_DDI_BPC_MASK) {
>  	case TRANS_DDI_BPC_6:
> @@ -4507,7 +4507,7 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder,
>  
>  	WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
>  
> -	if (!crtc_state->base.active)
> +	if (!crtc_state->hw.active)
>  		return 0;
>  
>  	if (!crtc_state->hdmi_high_tmds_clock_ratio &&
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index adb70d76a61c..3106aaf55f17 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1013,7 +1013,7 @@ bool intel_crtc_active(struct intel_crtc *crtc)
>  	 * for atomic.
>  	 */
>  	return crtc->active && crtc->base.primary->state->fb &&
> -		crtc->config->base.adjusted_mode.crtc_clock;
> +		crtc->config->hw.adjusted_mode.crtc_clock;
>  }
>  
>  enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
> @@ -4951,7 +4951,7 @@ static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	int clock = crtc_state->base.adjusted_mode.crtc_clock;
> +	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
>  	u32 divsel, phaseinc, auxdiv, phasedir = 0;
>  	u32 temp;
>  
> @@ -5224,7 +5224,7 @@ static void ironlake_pch_enable(const struct intel_atomic_state *state,
>  	if (HAS_PCH_CPT(dev_priv) &&
>  	    intel_crtc_has_dp_encoder(crtc_state)) {
>  		const struct drm_display_mode *adjusted_mode =
> -			&crtc_state->base.adjusted_mode;
> +			&crtc_state->hw.adjusted_mode;
>  		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
>  		i915_reg_t reg = TRANS_DP_CTL(pipe);
>  		enum port port;
> @@ -5374,7 +5374,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>  		to_intel_crtc(crtc_state->base.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
>  	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->base.adjusted_mode;
> +		&crtc_state->hw.adjusted_mode;
>  
>  	/*
>  	 * Src coordinates are already rotated by 270 degrees for
> @@ -5390,7 +5390,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>  	 * Once NV12 is enabled, handle it here while allocating scaler
>  	 * for NV12.
>  	 */
> -	if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
> +	if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
>  	    need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
>  		DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
>  		return -EINVAL;
> @@ -5462,13 +5462,13 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>   */
>  int skl_update_scaler_crtc(struct intel_crtc_state *state)
>  {
> -	const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
> +	const struct drm_display_mode *adjusted_mode = &state->hw.adjusted_mode;
>  	bool need_scaler = false;
>  
>  	if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
>  		need_scaler = true;
>  
> -	return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
> +	return skl_update_scaler(state, !state->hw.active, SKL_CRTC_INDEX,
>  				 &state->scaler_state.scaler_id,
>  				 state->pipe_src_w, state->pipe_src_h,
>  				 adjusted_mode->crtc_hdisplay,
> @@ -5820,7 +5820,7 @@ static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_s
>  	 * forcibly enable IPS on the first fastset.
>  	 */
>  	if (new_crtc_state->update_pipe &&
> -	    old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
> +	    old_crtc_state->hw.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
>  		return true;
>  
>  	return !old_crtc_state->ips_enabled;
> @@ -5864,7 +5864,7 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
>  
>  	intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
>  
> -	if (pipe_config->update_wm_post && pipe_config->base.active)
> +	if (pipe_config->update_wm_post && pipe_config->hw.active)
>  		intel_update_watermarks(crtc);
>  
>  	if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
> @@ -5942,7 +5942,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
>  	 * event which is after the vblank start event, so we need to have a
>  	 * wait-for-vblank between disabling the plane and the pipe.
>  	 */
> -	if (HAS_GMCH(dev_priv) && old_crtc_state->base.active &&
> +	if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
>  	    pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
>  		intel_wait_for_vblank(dev_priv, crtc->pipe);
>  
> @@ -5954,7 +5954,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
>  	 * WaCxSRDisabledForSpriteScaling:ivb
>  	 */
>  	if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
> -	    old_crtc_state->base.active)
> +	    old_crtc_state->hw.active)
>  		intel_wait_for_vblank(dev_priv, crtc->pipe);
>  
>  	/*
> @@ -6752,7 +6752,7 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
>  	u64 mask;
>  	enum transcoder transcoder = crtc_state->cpu_transcoder;
>  
> -	if (!crtc_state->base.active)
> +	if (!crtc_state->hw.active)
>  		return 0;
>  
>  	mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
> @@ -7109,8 +7109,8 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
>  		if (!crtc_state)
>  			return;
>  
> -		I915_STATE_WARN(!crtc_state->base.active,
> -		      "connector is active, but attached crtc isn't\n");
> +		I915_STATE_WARN(!crtc_state->hw.active,
> +				"connector is active, but attached crtc isn't\n");
>  
>  		if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
>  			return;
> @@ -7121,8 +7121,8 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
>  		I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
>  			"attached encoder crtc differs from connector crtc\n");
>  	} else {
> -		I915_STATE_WARN(crtc_state && crtc_state->base.active,
> -			"attached crtc is active, but connector isn't\n");
> +		I915_STATE_WARN(crtc_state && crtc_state->hw.active,
> +				"attached crtc is active, but connector isn't\n");
>  		I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
>  			"best encoder set without crtc!\n");
>  	}
> @@ -7130,7 +7130,7 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
>  
>  static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
>  {
> -	if (crtc_state->base.enable && crtc_state->has_pch_encoder)
> +	if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
>  		return crtc_state->fdi_lanes;
>  
>  	return 0;
> @@ -7213,7 +7213,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
>  				       struct intel_crtc_state *pipe_config)
>  {
>  	struct drm_device *dev = intel_crtc->base.dev;
> -	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> +	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	int lane, link_bw, fdi_dotclock, ret;
>  	bool needs_recompute = false;
>  
> @@ -7330,7 +7330,7 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
>  {
>  	u32 pixel_rate;
>  
> -	pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
> +	pixel_rate = pipe_config->hw.adjusted_mode.crtc_clock;
>  
>  	/*
>  	 * We only use IF-ID interlacing. If we ever use
> @@ -7368,7 +7368,7 @@ static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
>  	if (HAS_GMCH(dev_priv))
>  		/* FIXME calculate proper pipe pixel rate for GMCH pfit */
>  		crtc_state->pixel_rate =
> -			crtc_state->base.adjusted_mode.crtc_clock;
> +			crtc_state->hw.adjusted_mode.crtc_clock;
>  	else
>  		crtc_state->pixel_rate =
>  			ilk_pipe_pixel_rate(crtc_state);
> @@ -7378,7 +7378,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
>  				     struct intel_crtc_state *pipe_config)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> +	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	int clock_limit = dev_priv->max_dotclk_freq;
>  
>  	if (INTEL_GEN(dev_priv) < 4) {
> @@ -7404,7 +7404,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
>  
>  	if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
>  	     pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
> -	     pipe_config->base.ctm) {
> +	     pipe_config->hw.ctm) {
>  		/*
>  		 * There is only one pipe CSC unit per pipe, and we need that
>  		 * for output conversion from RGB->YCBCR. So if CTM is already
> @@ -8102,7 +8102,7 @@ static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> -	const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>  	u32 crtc_vtotal, crtc_vblank_end;
>  	int vsyncshift = 0;
>  
> @@ -8196,39 +8196,39 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
>  	u32 tmp;
>  
>  	tmp = I915_READ(HTOTAL(cpu_transcoder));
> -	pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
> -	pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
> +	pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
> +	pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
>  
>  	if (!transcoder_is_dsi(cpu_transcoder)) {
>  		tmp = I915_READ(HBLANK(cpu_transcoder));
> -		pipe_config->base.adjusted_mode.crtc_hblank_start =
> +		pipe_config->hw.adjusted_mode.crtc_hblank_start =
>  							(tmp & 0xffff) + 1;
> -		pipe_config->base.adjusted_mode.crtc_hblank_end =
> +		pipe_config->hw.adjusted_mode.crtc_hblank_end =
>  						((tmp >> 16) & 0xffff) + 1;
>  	}
>  	tmp = I915_READ(HSYNC(cpu_transcoder));
> -	pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
> -	pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
> +	pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
> +	pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
>  
>  	tmp = I915_READ(VTOTAL(cpu_transcoder));
> -	pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
> -	pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
> +	pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
> +	pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
>  
>  	if (!transcoder_is_dsi(cpu_transcoder)) {
>  		tmp = I915_READ(VBLANK(cpu_transcoder));
> -		pipe_config->base.adjusted_mode.crtc_vblank_start =
> +		pipe_config->hw.adjusted_mode.crtc_vblank_start =
>  							(tmp & 0xffff) + 1;
> -		pipe_config->base.adjusted_mode.crtc_vblank_end =
> +		pipe_config->hw.adjusted_mode.crtc_vblank_end =
>  						((tmp >> 16) & 0xffff) + 1;
>  	}
>  	tmp = I915_READ(VSYNC(cpu_transcoder));
> -	pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
> -	pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
> +	pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
> +	pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
>  
>  	if (intel_pipe_is_interlaced(pipe_config)) {
> -		pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
> -		pipe_config->base.adjusted_mode.crtc_vtotal += 1;
> -		pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
> +		pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
> +		pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
> +		pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
>  	}
>  }
>  
> @@ -8243,27 +8243,27 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
>  	pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
>  	pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
>  
> -	pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
> -	pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
> +	pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
> +	pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
>  }
>  
>  void intel_mode_from_pipe_config(struct drm_display_mode *mode,
>  				 struct intel_crtc_state *pipe_config)
>  {
> -	mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
> -	mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
> -	mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
> -	mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
> +	mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> +	mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
> +	mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
> +	mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
>  
> -	mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
> -	mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
> -	mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
> -	mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
> +	mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
> +	mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
> +	mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
> +	mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
>  
> -	mode->flags = pipe_config->base.adjusted_mode.flags;
> +	mode->flags = pipe_config->hw.adjusted_mode.flags;
>  	mode->type = DRM_MODE_TYPE_DRIVER;
>  
> -	mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
> +	mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
>  
>  	mode->hsync = drm_mode_hsync(mode);
>  	mode->vrefresh = drm_mode_vrefresh(mode);
> @@ -8309,7 +8309,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
>  		}
>  	}
>  
> -	if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> +	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
>  		if (INTEL_GEN(dev_priv) < 4 ||
>  		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
>  			pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
> @@ -8841,7 +8841,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  	 * but in case the pipe is enabled w/o any ports we need a sane
>  	 * default.
>  	 */
> -	pipe_config->base.adjusted_mode.crtc_clock =
> +	pipe_config->hw.adjusted_mode.crtc_clock =
>  		pipe_config->port_clock / pipe_config->pixel_multiplier;
>  
>  	ret = true;
> @@ -9384,7 +9384,7 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
>  	if (crtc_state->dither)
>  		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
>  
> -	if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> +	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
>  		val |= PIPECONF_INTERLACED_ILK;
>  	else
>  		val |= PIPECONF_PROGRESSIVE;
> @@ -9418,7 +9418,7 @@ static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
>  	if (IS_HASWELL(dev_priv) && crtc_state->dither)
>  		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
>  
> -	if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> +	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
>  		val |= PIPECONF_INTERLACED_ILK;
>  	else
>  		val |= PIPECONF_PROGRESSIVE;
> @@ -11427,7 +11427,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
>  	 * we may need some idea for the dotclock anyway.
>  	 * Calculate one based on the FDI configuration.
>  	 */
> -	pipe_config->base.adjusted_mode.crtc_clock =
> +	pipe_config->hw.adjusted_mode.crtc_clock =
>  		intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
>  					 &pipe_config->fdi_m_n);
>  }
> @@ -11532,8 +11532,8 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
>  	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	bool mode_changed = needs_modeset(crtc_state);
> -	bool was_crtc_enabled = old_crtc_state->base.active;
> -	bool is_crtc_enabled = crtc_state->base.active;
> +	bool was_crtc_enabled = old_crtc_state->hw.active;
> +	bool is_crtc_enabled = crtc_state->hw.active;
>  	bool turn_off, turn_on, visible, was_visible;
>  	int ret;
>  
> @@ -11791,10 +11791,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>  	int ret;
>  
>  	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
> -	    mode_changed && !crtc_state->base.active)
> +	    mode_changed && !crtc_state->hw.active)
>  		crtc_state->update_wm_post = true;
>  
> -	if (mode_changed && crtc_state->base.enable &&
> +	if (mode_changed && crtc_state->hw.enable &&
>  	    dev_priv->display.crtc_compute_clock &&
>  	    !WARN_ON(crtc_state->shared_dpll)) {
>  		ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
> @@ -12090,14 +12090,14 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
>  
>  	DRM_DEBUG_KMS("[CRTC:%d:%s] enable: %s %s\n",
>  		      crtc->base.base.id, crtc->base.name,
> -		      yesno(pipe_config->base.enable), context);
> +		      yesno(pipe_config->hw.enable), context);
>  
> -	if (!pipe_config->base.enable)
> +	if (!pipe_config->hw.enable)
>  		goto dump_planes;
>  
>  	snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
>  	DRM_DEBUG_KMS("active: %s, output_types: %s (0x%x), output format: %s\n",
> -		      yesno(pipe_config->base.active),
> +		      yesno(pipe_config->hw.active),
>  		      buf, pipe_config->output_types,
>  		      output_formats(pipe_config->output_format));
>  
> @@ -12137,10 +12137,10 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
>  		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
>  
>  	DRM_DEBUG_KMS("requested mode:\n");
> -	drm_mode_debug_printmodeline(&pipe_config->base.mode);
> +	drm_mode_debug_printmodeline(&pipe_config->hw.mode);
>  	DRM_DEBUG_KMS("adjusted mode:\n");
> -	drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
> -	intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
> +	drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
> +	intel_dump_crtc_timings(&pipe_config->hw.adjusted_mode);
>  	DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
>  		      pipe_config->port_clock,
>  		      pipe_config->pipe_src_w, pipe_config->pipe_src_h,
> @@ -12315,13 +12315,13 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
>  	 * positive or negative polarity is requested, treat this as meaning
>  	 * negative polarity.
>  	 */
> -	if (!(pipe_config->base.adjusted_mode.flags &
> +	if (!(pipe_config->hw.adjusted_mode.flags &
>  	      (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
> -		pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
> +		pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
>  
> -	if (!(pipe_config->base.adjusted_mode.flags &
> +	if (!(pipe_config->hw.adjusted_mode.flags &
>  	      (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
> -		pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
> +		pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
>  
>  	ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
>  					pipe_config);
> @@ -12338,7 +12338,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
>  	 * computation to clearly distinguish it from the adjusted mode, which
>  	 * can be changed by the connectors in the below retry loop.
>  	 */
> -	drm_mode_get_hv_timing(&pipe_config->base.mode,
> +	drm_mode_get_hv_timing(&pipe_config->hw.mode,
>  			       &pipe_config->pipe_src_w,
>  			       &pipe_config->pipe_src_h);
>  
> @@ -12371,7 +12371,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
>  	pipe_config->pixel_multiplier = 1;
>  
>  	/* Fill in default crtc timings, allow encoders to overwrite them. */
> -	drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
> +	drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
>  			      CRTC_STEREO_DOUBLE);
>  
>  	/* Pass our mode to the connectors and the CRTC to give them a chance to
> @@ -12396,7 +12396,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
>  	/* Set default port clock if not overwritten by the encoder. Needs to be
>  	 * done afterwards in case the encoder adjusts the mode. */
>  	if (!pipe_config->port_clock)
> -		pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
> +		pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
>  			* pipe_config->pixel_multiplier;
>  
>  	ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
> @@ -12564,8 +12564,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	bool ret = true;
>  	u32 bp_gamma = 0;
>  	bool fixup_inherited = fastset &&
> -		(current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
> -		!(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
> +		(current_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
> +		!(pipe_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED);
>  
>  	if (fixup_inherited && !fastboot_enabled(dev_priv)) {
>  		DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
> @@ -12908,7 +12908,7 @@ static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
>  	if (pipe_config->has_pch_encoder) {
>  		int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
>  							    &pipe_config->fdi_m_n);
> -		int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
> +		int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
>  
>  		/*
>  		 * FDI already provided one idea for the dotclock.
> @@ -12937,7 +12937,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  	int level, max_level = ilk_wm_max_level(dev_priv);
>  	struct intel_plane *plane;
>  
> -	if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->base.active)
> +	if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
>  		return;
>  
>  	hw = kzalloc(sizeof(*hw), GFP_KERNEL);
> @@ -13121,23 +13121,26 @@ verify_crtc_state(struct intel_crtc *crtc,
>  
>  	/* we keep both pipes enabled on 830 */
>  	if (IS_I830(dev_priv))
> -		active = new_crtc_state->base.active;
> +		active = new_crtc_state->hw.active;
>  
> -	I915_STATE_WARN(new_crtc_state->base.active != active,
> -	     "crtc active state doesn't match with hw state "
> -	     "(expected %i, found %i)\n", new_crtc_state->base.active, active);
> +	I915_STATE_WARN(new_crtc_state->hw.active != active,
> +			"crtc active state doesn't match with hw state "
> +			"(expected %i, found %i)\n",
> +			new_crtc_state->hw.active, active);
>  
> -	I915_STATE_WARN(crtc->active != new_crtc_state->base.active,
> -	     "transitional active state does not match atomic hw state "
> -	     "(expected %i, found %i)\n", new_crtc_state->base.active, crtc->active);
> +	I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
> +			"transitional active state does not match atomic hw state "
> +			"(expected %i, found %i)\n",
> +			new_crtc_state->hw.active, crtc->active);
>  
>  	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
>  		enum pipe pipe;
>  
>  		active = encoder->get_hw_state(encoder, &pipe);
> -		I915_STATE_WARN(active != new_crtc_state->base.active,
> -			"[ENCODER:%i] active %i with crtc active %i\n",
> -			encoder->base.base.id, active, new_crtc_state->base.active);
> +		I915_STATE_WARN(active != new_crtc_state->hw.active,
> +				"[ENCODER:%i] active %i with crtc active %i\n",
> +				encoder->base.base.id, active,
> +				new_crtc_state->hw.active);
>  
>  		I915_STATE_WARN(active && crtc->pipe != pipe,
>  				"Encoder connected to wrong pipe %c\n",
> @@ -13149,7 +13152,7 @@ verify_crtc_state(struct intel_crtc *crtc,
>  
>  	intel_crtc_compute_pixel_rate(pipe_config);
>  
> -	if (!new_crtc_state->base.active)
> +	if (!new_crtc_state->hw.active)
>  		return;
>  
>  	intel_pipe_config_sanity_check(dev_priv, pipe_config);
> @@ -13211,7 +13214,7 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
>  
>  	crtc_mask = drm_crtc_mask(&crtc->base);
>  
> -	if (new_crtc_state->base.active)
> +	if (new_crtc_state->hw.active)
>  		I915_STATE_WARN(!(pll->active_mask & crtc_mask),
>  				"pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
>  				pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
> @@ -13293,7 +13296,7 @@ intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->base.adjusted_mode;
> +		&crtc_state->hw.adjusted_mode;
>  
>  	drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
>  
> @@ -13375,7 +13378,7 @@ static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
>  
>  	/* look at all crtc's that are going to be enabled in during modeset */
>  	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> -		if (!crtc_state->base.active ||
> +		if (!crtc_state->hw.active ||
>  		    !needs_modeset(crtc_state))
>  			continue;
>  
> @@ -13400,7 +13403,7 @@ static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
>  
>  		crtc_state->hsw_workaround_pipe = INVALID_PIPE;
>  
> -		if (!crtc_state->base.active ||
> +		if (!crtc_state->hw.active ||
>  		    needs_modeset(crtc_state))
>  			continue;
>  
> @@ -13443,12 +13446,12 @@ static int intel_modeset_checks(struct intel_atomic_state *state)
>  
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>  					    new_crtc_state, i) {
> -		if (new_crtc_state->base.active)
> +		if (new_crtc_state->hw.active)
>  			state->active_pipes |= BIT(crtc->pipe);
>  		else
>  			state->active_pipes &= ~BIT(crtc->pipe);
>  
> -		if (old_crtc_state->base.active != new_crtc_state->base.active)
> +		if (old_crtc_state->hw.active != new_crtc_state->hw.active)
>  			state->active_pipe_changes |= BIT(crtc->pipe);
>  	}
>  
> @@ -13558,8 +13561,8 @@ static int intel_atomic_check(struct drm_device *dev,
>  	/* Catch I915_MODE_FLAG_INHERITED */
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>  					    new_crtc_state, i) {
> -		if (new_crtc_state->base.mode.private_flags !=
> -		    old_crtc_state->base.mode.private_flags)
> +		if (new_crtc_state->hw.mode.private_flags !=
> +		    old_crtc_state->hw.mode.private_flags)
>  			new_crtc_state->base.mode_changed = true;
>  	}
>  
> @@ -13688,7 +13691,7 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>  	/* drm_atomic_helper_update_legacy_modeset_state might not be called. */
> -	crtc->base.mode = new_crtc_state->base.mode;
> +	crtc->base.mode = new_crtc_state->hw.mode;
>  
>  	/*
>  	 * Update pipe size and adjust fitter if needed: the reason for this is
> @@ -13797,7 +13800,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
>  	 * of enabling them on the CRTC's first fastset.
>  	 */
>  	if (new_crtc_state->update_pipe && !modeset &&
> -	    old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
> +	    old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
>  		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
>  }
>  
> @@ -13829,7 +13832,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
>  	intel_check_pch_fifo_underruns(dev_priv);
>  
>  	/* FIXME unify this for all platforms */
> -	if (!new_crtc_state->base.active &&
> +	if (!new_crtc_state->hw.active &&
>  	    !HAS_GMCH(dev_priv) &&
>  	    dev_priv->display.initial_watermarks)
>  		dev_priv->display.initial_watermarks(state,
> @@ -13856,7 +13859,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
>  
>  		intel_pre_plane_update(old_crtc_state, new_crtc_state);
>  
> -		if (old_crtc_state->base.active)
> +		if (old_crtc_state->hw.active)
>  			intel_old_crtc_state_disables(state,
>  						      old_crtc_state,
>  						      new_crtc_state,
> @@ -13871,7 +13874,7 @@ static void intel_commit_modeset_enables(struct intel_atomic_state *state)
>  	int i;
>  
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> -		if (!new_crtc_state->base.active)
> +		if (!new_crtc_state->hw.active)
>  			continue;
>  
>  		intel_update_crtc(crtc, state, old_crtc_state,
> @@ -13894,7 +13897,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
>  
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
>  		/* ignore allocations for crtc's that have been turned off. */
> -		if (new_crtc_state->base.active)
> +		if (new_crtc_state->hw.active)
>  			entries[i] = old_crtc_state->wm.skl.ddb;
>  
>  	/* If 2nd DBuf slice required, enable it here */
> @@ -13916,7 +13919,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
>  
>  			pipe = crtc->pipe;
>  
> -			if (updated & cmask || !new_crtc_state->base.active)
> +			if (updated & cmask || !new_crtc_state->hw.active)
>  				continue;
>  
>  			if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
> @@ -14068,7 +14071,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  		bool modeset = needs_modeset(new_crtc_state);
>  
>  		/* Complete events for now disable pipes here. */
> -		if (modeset && !new_crtc_state->base.active && new_crtc_state->base.event) {
> +		if (modeset && !new_crtc_state->hw.active && new_crtc_state->base.event) {
>  			spin_lock_irq(&dev->event_lock);
>  			drm_crtc_send_vblank_event(&crtc->base, new_crtc_state->base.event);
>  			spin_unlock_irq(&dev->event_lock);
> @@ -14104,7 +14107,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	drm_atomic_helper_wait_for_flip_done(dev, &state->base);
>  
>  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> -		if (new_crtc_state->base.active &&
> +		if (new_crtc_state->hw.active &&
>  		    !needs_modeset(new_crtc_state) &&
>  		    (new_crtc_state->base.color_mgmt_changed ||
>  		     new_crtc_state->update_pipe))
> @@ -14559,10 +14562,10 @@ skl_max_scale(const struct intel_crtc_state *crtc_state,
>  	int max_scale;
>  	int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
>  
> -	if (!crtc_state->base.enable)
> +	if (!crtc_state->hw.enable)
>  		return DRM_PLANE_HELPER_NO_SCALING;
>  
> -	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
> +	crtc_clock = crtc_state->hw.adjusted_mode.crtc_clock;
>  	max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
>  
>  	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> @@ -14698,7 +14701,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
>  	 * When crtc is inactive or there is a modeset pending,
>  	 * wait for it to complete in the slowpath
>  	 */
> -	if (!crtc_state->base.active || needs_modeset(crtc_state) ||
> +	if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
>  	    crtc_state->update_pipe)
>  		goto slow;
>  
> @@ -16114,7 +16117,7 @@ static int intel_initial_commit(struct drm_device *dev)
>  			goto out;
>  		}
>  
> -		if (crtc_state->base.active) {
> +		if (crtc_state->hw.active) {
>  			ret = drm_atomic_add_affected_planes(state, &crtc->base);
>  			if (ret)
>  				goto out;
> @@ -16464,7 +16467,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
>  			   I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
>  	}
>  
> -	if (crtc_state->base.active) {
> +	if (crtc_state->hw.active) {
>  		struct intel_plane *plane;
>  
>  		/* Disable everything but the primary plane */
> @@ -16489,10 +16492,10 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
>  
>  	/* Adjust the state of the output pipe according to whether we
>  	 * have active connectors/encoders. */
> -	if (crtc_state->base.active && !intel_crtc_has_encoders(crtc))
> +	if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
>  		intel_crtc_disable_noatomic(&crtc->base, ctx);
>  
> -	if (crtc_state->base.active || HAS_GMCH(dev_priv)) {
> +	if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
>  		/*
>  		 * We start out with underrun reporting disabled to avoid races.
>  		 * For correct bookkeeping mark this on active crtcs.
> @@ -16536,7 +16539,7 @@ static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
>  	 * road.
>  	 */
>  	return IS_GEN(dev_priv, 6) &&
> -		crtc_state->base.active &&
> +		crtc_state->hw.active &&
>  		crtc_state->shared_dpll &&
>  		crtc_state->port_clock == 0;
>  }
> @@ -16553,7 +16556,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
>  	 * encoder is active and trying to read from a pipe) and the
>  	 * pipe itself being active. */
>  	bool has_active_crtc = crtc_state &&
> -		crtc_state->base.active;
> +		crtc_state->hw.active;
>  
>  	if (crtc_state && has_bogus_dpll_config(crtc_state)) {
>  		DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
> @@ -16661,18 +16664,18 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>  		memset(crtc_state, 0, sizeof(*crtc_state));
>  		__drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->base);
>  
> -		crtc_state->base.active = crtc_state->base.enable =
> +		crtc_state->hw.active = crtc_state->hw.enable =
>  			dev_priv->display.get_pipe_config(crtc, crtc_state);
>  
> -		crtc->base.enabled = crtc_state->base.enable;
> -		crtc->active = crtc_state->base.active;
> +		crtc->base.enabled = crtc_state->hw.enable;
> +		crtc->active = crtc_state->hw.active;
>  
> -		if (crtc_state->base.active)
> +		if (crtc_state->hw.active)
>  			dev_priv->active_pipes |= BIT(crtc->pipe);
>  
>  		DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
>  			      crtc->base.base.id, crtc->base.name,
> -			      enableddisabled(crtc_state->base.active));
> +			      enableddisabled(crtc_state->hw.active));
>  	}
>  
>  	readout_plane_state(dev_priv);
> @@ -16694,7 +16697,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>  			struct intel_crtc_state *crtc_state =
>  				to_intel_crtc_state(crtc->base.state);
>  
> -			if (crtc_state->base.active &&
> +			if (crtc_state->hw.active &&
>  			    crtc_state->shared_dpll == pll)
>  				pll->state.crtc_mask |= 1 << crtc->pipe;
>  		}
> @@ -16739,7 +16742,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>  			crtc = to_intel_crtc(encoder->base.crtc);
>  			crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
>  
> -			if (crtc_state && crtc_state->base.active) {
> +			if (crtc_state && crtc_state->hw.active) {
>  				/*
>  				 * This has to be done during hardware readout
>  				 * because anything calling .crtc_disable may
> @@ -16769,11 +16772,12 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>  		int min_cdclk = 0;
>  
>  		memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
> -		if (crtc_state->base.active) {
> +		if (crtc_state->hw.active) {
>  			intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
>  			crtc->base.mode.hdisplay = crtc_state->pipe_src_w;
>  			crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
> -			intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
> +			intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
> +						    crtc_state);
>  			WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->base, &crtc->base.mode));
>  
>  			/*
> @@ -16785,7 +16789,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>  			 * set a flag to indicate that a full recalculation is
>  			 * needed on the next commit.
>  			 */
> -			crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
> +			crtc_state->hw.mode.private_flags = I915_MODE_FLAG_INHERITED;
>  
>  			intel_crtc_compute_pixel_rate(crtc_state);
>  
> @@ -16963,7 +16967,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
>  
>  		drm_crtc_vblank_reset(&crtc->base);
>  
> -		if (crtc_state->base.active)
> +		if (crtc_state->hw.active)
>  			intel_crtc_vblank_on(crtc_state);
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index c4c081c79dd9..213b0c0cdd67 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1968,7 +1968,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
>  				  struct intel_crtc_state *pipe_config,
>  				  const struct link_config_limits *limits)
>  {
> -	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> +	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	int bpp, clock, lane_count;
>  	int mode_rate, link_clock, link_avail;
>  
> @@ -2022,7 +2022,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> -	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> +	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	u8 dsc_max_bpc;
>  	int pipe_bpp;
>  	int ret;
> @@ -2133,7 +2133,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>  			     struct intel_crtc_state *pipe_config,
>  			     struct drm_connector_state *conn_state)
>  {
> -	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> +	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>  	struct link_config_limits limits;
>  	int common_len;
> @@ -2221,7 +2221,7 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
>  {
>  	const struct drm_display_info *info = &connector->display_info;
>  	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->base.adjusted_mode;
> +		&crtc_state->hw.adjusted_mode;
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	int ret;
>  
> @@ -2250,7 +2250,7 @@ bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
>  	const struct intel_digital_connector_state *intel_conn_state =
>  		to_intel_digital_connector_state(conn_state);
>  	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->base.adjusted_mode;
> +		&crtc_state->hw.adjusted_mode;
>  
>  	/*
>  	 * Our YCbCr output is always limited range.
> @@ -2283,7 +2283,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  			struct drm_connector_state *conn_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> +	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>  	struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
>  	enum port port = encoder->port;
> @@ -2403,7 +2403,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>  	enum port port = encoder->port;
>  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> -	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> +	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  
>  	intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
>  				 pipe_config->lane_count,
> @@ -3235,7 +3235,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
>  			flags |= DRM_MODE_FLAG_NVSYNC;
>  	}
>  
> -	pipe_config->base.adjusted_mode.flags |= flags;
> +	pipe_config->hw.adjusted_mode.flags |= flags;
>  
>  	if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
>  		pipe_config->limited_color_range = true;
> @@ -3252,7 +3252,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
>  			pipe_config->port_clock = 270000;
>  	}
>  
> -	pipe_config->base.adjusted_mode.crtc_clock =
> +	pipe_config->hw.adjusted_mode.crtc_clock =
>  		intel_dotclock_calculate(pipe_config->port_clock,
>  					 &pipe_config->dp_m_n);
>  
> @@ -5045,7 +5045,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
>  
>  	WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
>  
> -	if (!crtc_state->base.active)
> +	if (!crtc_state->hw.active)
>  		return 0;
>  
>  	if (conn_state->commit &&
> @@ -6907,7 +6907,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
>  		return;
>  	}
>  
> -	if (!crtc_state->base.active) {
> +	if (!crtc_state->hw.active) {
>  		DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
>  		return;
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 5484bd4534c1..7d63f0a79ca1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -48,7 +48,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
>  	struct intel_connector *connector =
>  		to_intel_connector(conn_state->connector);
>  	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->base.adjusted_mode;
> +		&crtc_state->hw.adjusted_mode;
>  	void *port = connector->port;
>  	bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
>  					   DP_DPCD_QUIRK_CONSTANT_N);
> @@ -99,7 +99,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
>  	struct intel_digital_connector_state *intel_conn_state =
>  		to_intel_digital_connector_state(conn_state);
>  	const struct drm_display_mode *adjusted_mode =
> -		&pipe_config->base.adjusted_mode;
> +		&pipe_config->hw.adjusted_mode;
>  	void *port = connector->port;
>  	struct link_config_limits limits;
>  	int ret;
> @@ -187,7 +187,7 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
>  
>  		if (!crtc_state ||
>  		    !drm_atomic_crtc_needs_modeset(crtc_state) ||
> -		    to_intel_crtc_state(crtc_state)->base.enable)
> +		    to_intel_crtc_state(crtc_state)->hw.enable)
>  			return 0;
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
> index 9827f99491d1..a68e5c5b91b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -178,9 +178,9 @@ static void intel_dvo_get_config(struct intel_encoder *encoder,
>  	else
>  		flags |= DRM_MODE_FLAG_NVSYNC;
>  
> -	pipe_config->base.adjusted_mode.flags |= flags;
> +	pipe_config->hw.adjusted_mode.flags |= flags;
>  
> -	pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
> +	pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
>  }
>  
>  static void intel_disable_dvo(struct intel_encoder *encoder,
> @@ -207,8 +207,8 @@ static void intel_enable_dvo(struct intel_encoder *encoder,
>  	u32 temp = I915_READ(dvo_reg);
>  
>  	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
> -					 &pipe_config->base.mode,
> -					 &pipe_config->base.adjusted_mode);
> +					 &pipe_config->hw.mode,
> +					 &pipe_config->hw.adjusted_mode);
>  
>  	I915_WRITE(dvo_reg, temp | DVO_ENABLE);
>  	I915_READ(dvo_reg);
> @@ -253,7 +253,7 @@ static int intel_dvo_compute_config(struct intel_encoder *encoder,
>  	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
>  	const struct drm_display_mode *fixed_mode =
>  		intel_dvo->attached_connector->panel.fixed_mode;
> -	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> +	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  
>  	/*
>  	 * If we have timings from the BIOS for the panel, put them in
> @@ -278,7 +278,7 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> -	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> +	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
>  	enum pipe pipe = crtc->pipe;
>  	u32 dvo_val;
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 3111ecaeabd0..c6cc3775f3b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -667,7 +667,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
>  	cache->vma = NULL;
>  	cache->flags = 0;
>  
> -	cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
> +	cache->crtc.mode_flags = crtc_state->hw.adjusted_mode.flags;
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>  		cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 92d1cbbbee2b..2f5fc71ac9a0 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -708,7 +708,7 @@ intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
>  {
>  	struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
>  	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->base.adjusted_mode;
> +		&crtc_state->hw.adjusted_mode;
>  	struct drm_connector *connector = conn_state->connector;
>  	int ret;
>  
> @@ -804,7 +804,7 @@ intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
>  
>  	ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
>  							  conn_state->connector,
> -							  &crtc_state->base.adjusted_mode);
> +							  &crtc_state->hw.adjusted_mode);
>  	if (WARN_ON(ret))
>  		return false;
>  
> @@ -1027,7 +1027,7 @@ static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
>  
>  	/* Enable default_phase whenever the display mode is suitably aligned */
>  	if (gcp_default_phase_possible(crtc_state->pipe_bpp,
> -				       &crtc_state->base.adjusted_mode))
> +				       &crtc_state->hw.adjusted_mode))
>  		crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
>  }
>  
> @@ -1743,7 +1743,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder,
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
> -	const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>  	u32 hdmi_val;
>  
>  	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
> @@ -1834,7 +1834,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
>  	    tmp & HDMI_COLOR_RANGE_16_235)
>  		pipe_config->limited_color_range = true;
>  
> -	pipe_config->base.adjusted_mode.flags |= flags;
> +	pipe_config->hw.adjusted_mode.flags |= flags;
>  
>  	if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
>  		dotclock = pipe_config->port_clock * 2 / 3;
> @@ -1844,7 +1844,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
>  	if (pipe_config->pixel_multiplier)
>  		dotclock /= pipe_config->pixel_multiplier;
>  
> -	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> +	pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
>  
>  	pipe_config->lane_count = 4;
>  
> @@ -2220,7 +2220,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
>  	struct drm_connector_state *connector_state;
>  	struct drm_connector *connector;
>  	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->base.adjusted_mode;
> +		&crtc_state->hw.adjusted_mode;
>  	int i;
>  
>  	if (HAS_GMCH(dev_priv))
> @@ -2341,7 +2341,7 @@ static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
>  {
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
>  	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->base.adjusted_mode;
> +		&crtc_state->hw.adjusted_mode;
>  	int bpc, clock = adjusted_mode->crtc_clock;
>  
>  	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
> @@ -2383,7 +2383,7 @@ static bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_s
>  	const struct intel_digital_connector_state *intel_conn_state =
>  		to_intel_digital_connector_state(conn_state);
>  	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->base.adjusted_mode;
> +		&crtc_state->hw.adjusted_mode;
>  
>  	/*
>  	 * Our YCbCr output is always limited range.
> @@ -2411,7 +2411,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
>  {
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> +	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	struct drm_connector *connector = conn_state->connector;
>  	struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
>  	struct intel_digital_connector_state *intel_conn_state =
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
> index f8f1308643a9..5145ff8b962b 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> @@ -189,7 +189,7 @@ void lspcon_ycbcr420_config(struct drm_connector *connector,
>  {
>  	const struct drm_display_info *info = &connector->display_info;
>  	const struct drm_display_mode *adjusted_mode =
> -					&crtc_state->base.adjusted_mode;
> +					&crtc_state->hw.adjusted_mode;
>  
>  	if (drm_mode_is_420_only(info, adjusted_mode) &&
>  	    connector->ycbcr_420_allowed) {
> @@ -475,7 +475,7 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
>  	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
>  	struct intel_lspcon *lspcon = &dig_port->lspcon;
>  	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->base.adjusted_mode;
> +		&crtc_state->hw.adjusted_mode;
>  
>  	if (!lspcon->active) {
>  		DRM_ERROR("Writing infoframes while LSPCON disabled ?\n");
> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
> index 13841d7c455b..f17d6e02460f 100644
> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> @@ -135,7 +135,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
>  	else
>  		flags |= DRM_MODE_FLAG_PVSYNC;
>  
> -	pipe_config->base.adjusted_mode.flags |= flags;
> +	pipe_config->hw.adjusted_mode.flags |= flags;
>  
>  	if (INTEL_GEN(dev_priv) < 5)
>  		pipe_config->gmch_pfit.lvds_border_bits =
> @@ -148,7 +148,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
>  		pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
>  	}
>  
> -	pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
> +	pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
>  }
>  
>  static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
> @@ -231,7 +231,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder,
>  	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> -	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> +	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	enum pipe pipe = crtc->pipe;
>  	u32 temp;
>  
> @@ -392,7 +392,7 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
>  		to_lvds_encoder(&intel_encoder->base);
>  	struct intel_connector *intel_connector =
>  		lvds_encoder->attached_connector;
> -	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> +	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
>  	unsigned int lvds_bpp;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
> index bc14e9c0285a..5e3fd37d9471 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.c
> +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> @@ -178,7 +178,7 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
>  			struct intel_crtc_state *pipe_config,
>  			int fitting_mode)
>  {
> -	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> +	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	int x = 0, y = 0, width = 0, height = 0;
>  
>  	/* Native modes don't need fitting */
> @@ -300,7 +300,7 @@ static inline u32 panel_fitter_scaling(u32 source, u32 target)
>  static void i965_scale_aspect(struct intel_crtc_state *pipe_config,
>  			      u32 *pfit_control)
>  {
> -	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> +	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	u32 scaled_width = adjusted_mode->crtc_hdisplay *
>  		pipe_config->pipe_src_h;
>  	u32 scaled_height = pipe_config->pipe_src_w *
> @@ -321,7 +321,7 @@ static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
>  			      u32 *pfit_control, u32 *pfit_pgm_ratios,
>  			      u32 *border)
>  {
> -	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> +	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	u32 scaled_width = adjusted_mode->crtc_hdisplay *
>  		pipe_config->pipe_src_h;
>  	u32 scaled_height = pipe_config->pipe_src_w *
> @@ -380,7 +380,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
>  	u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
> -	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> +	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  
>  	/* Native modes don't need fitting */
>  	if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w &&
> diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> index 6260a2082719..fc602533a602 100644
> --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> @@ -313,7 +313,7 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
>  	pipe_config->crc_enabled = enable;
>  
>  	if (IS_HASWELL(dev_priv) &&
> -	    pipe_config->base.active && crtc->pipe == PIPE_A &&
> +	    pipe_config->hw.active && crtc->pipe == PIPE_A &&
>  	    pipe_config->cpu_transcoder == TRANSCODER_EDP)
>  		pipe_config->base.mode_changed = true;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 211710f5214c..347004981cff 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -536,11 +536,11 @@ transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)
>  
>  static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
>  {
> -	if (!cstate || !cstate->base.active)
> +	if (!cstate || !cstate->hw.active)
>  		return 0;
>  
>  	return DIV_ROUND_UP(1000 * 1000,
> -			    drm_mode_vrefresh(&cstate->base.adjusted_mode));
> +			    drm_mode_vrefresh(&cstate->hw.adjusted_mode));
>  }
>  
>  static void psr2_program_idle_frames(struct drm_i915_private *dev_priv,
> @@ -605,8 +605,8 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  				    struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -	int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay;
> -	int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay;
> +	int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> +	int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
>  	int psr_max_h = 0, psr_max_v = 0;
>  
>  	if (!dev_priv->psr.sink_psr2_support)
> @@ -672,7 +672,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->base.adjusted_mode;
> +		&crtc_state->hw.adjusted_mode;
>  	int psr_setup_time;
>  
>  	if (!CAN_PSR(dev_priv))
> @@ -1139,7 +1139,7 @@ static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
>  
>  		intel_crtc_state = to_intel_crtc_state(crtc_state);
>  
> -		if (intel_crtc_state->base.active && intel_crtc_state->has_psr) {
> +		if (intel_crtc_state->hw.active && intel_crtc_state->has_psr) {
>  			/* Mark mode as changed to trigger a pipe->update() */
>  			intel_crtc_state->base.mode_changed = true;
>  			break;
> diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
> index 47f5d87a938a..97ae8cc1314e 100644
> --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> @@ -1087,7 +1087,7 @@ static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
>  {
>  	struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
>  	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->base.adjusted_mode;
> +		&crtc_state->hw.adjusted_mode;
>  	int ret;
>  
>  	if (!crtc_state->has_hdmi_sink)
> @@ -1276,8 +1276,8 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder,
>  		to_intel_sdvo_connector_state(conn_state);
>  	struct intel_sdvo_connector *intel_sdvo_connector =
>  		to_intel_sdvo_connector(conn_state->connector);
> -	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> -	struct drm_display_mode *mode = &pipe_config->base.mode;
> +	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> +	struct drm_display_mode *mode = &pipe_config->hw.mode;
>  
>  	DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
>  	pipe_config->pipe_bpp = 8*3;
> @@ -1430,12 +1430,12 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> -	const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>  	const struct intel_sdvo_connector_state *sdvo_state =
>  		to_intel_sdvo_connector_state(conn_state);
>  	const struct intel_sdvo_connector *intel_sdvo_connector =
>  		to_intel_sdvo_connector(conn_state->connector);
> -	const struct drm_display_mode *mode = &crtc_state->base.mode;
> +	const struct drm_display_mode *mode = &crtc_state->hw.mode;
>  	struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
>  	u32 sdvox;
>  	struct intel_sdvo_in_out_map in_out;
> @@ -1629,7 +1629,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
>  			flags |= DRM_MODE_FLAG_NVSYNC;
>  	}
>  
> -	pipe_config->base.adjusted_mode.flags |= flags;
> +	pipe_config->hw.adjusted_mode.flags |= flags;
>  
>  	/*
>  	 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
> @@ -1649,7 +1649,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
>  	if (pipe_config->pixel_multiplier)
>  		dotclock /= pipe_config->pixel_multiplier;
>  
> -	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> +	pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
>  
>  	/* Cross check the port pixel multiplier with the sdvo encoder state. */
>  	if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
> @@ -1701,7 +1701,7 @@ static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo,
>  				    const struct drm_connector_state *conn_state)
>  {
>  	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->base.adjusted_mode;
> +		&crtc_state->hw.adjusted_mode;
>  	struct drm_connector *connector = conn_state->connector;
>  	u8 *eld = connector->eld;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 5ae12ab3c5b7..ef0ca7c6d11f 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -83,7 +83,7 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
> +	const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
>  	long timeout = msecs_to_jiffies_timeout(1);
>  	int scanline, min, max, vblank_start;
>  	wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
> @@ -1513,7 +1513,7 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
>  	const struct drm_rect *dst = &plane_state->base.dst;
>  	int src_x, src_w, src_h, crtc_w, crtc_h;
>  	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->base.adjusted_mode;
> +		&crtc_state->hw.adjusted_mode;
>  	unsigned int stride = plane_state->color_plane[0].stride;
>  	unsigned int cpp = fb->format->cpp[0];
>  	unsigned int width_bytes;
> @@ -1727,8 +1727,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>  	}
>  
>  	/* Y-tiling is not supported in IF-ID Interlace mode */
> -	if (crtc_state->base.enable &&
> -	    crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
> +	if (crtc_state->hw.enable &&
> +	    crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
>  	    (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
>  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
>  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
> index 70726b481244..e800d45b813d 100644
> --- a/drivers/gpu/drm/i915/display/intel_tv.c
> +++ b/drivers/gpu/drm/i915/display/intel_tv.c
> @@ -1085,7 +1085,7 @@ intel_tv_get_config(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct drm_display_mode *adjusted_mode =
> -		&pipe_config->base.adjusted_mode;
> +		&pipe_config->hw.adjusted_mode;
>  	struct drm_display_mode mode = {};
>  	u32 tv_ctl, hctl1, hctl3, vctl1, vctl2, tmp;
>  	struct tv_mode tv_mode = {};
> @@ -1188,7 +1188,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
>  		to_intel_tv_connector_state(conn_state);
>  	const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
>  	struct drm_display_mode *adjusted_mode =
> -		&pipe_config->base.adjusted_mode;
> +		&pipe_config->hw.adjusted_mode;
>  	int hdisplay = adjusted_mode->crtc_hdisplay;
>  	int vdisplay = adjusted_mode->crtc_vdisplay;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index d4fb7f16f9f6..6a338a83aaed 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -329,8 +329,8 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
>  	int column_index = 0;
>  	u8 line_buf_depth = 0;
>  
> -	vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay;
> -	vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay;
> +	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> +	vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
>  	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
>  					     pipe_config->dsc_params.slice_count);
>  	/*
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index 50064cde0724..3bf838279fc2 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -263,7 +263,7 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
>  	struct intel_connector *intel_connector = intel_dsi->attached_connector;
>  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
>  	const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
> -	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> +	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	int ret;
>  
>  	DRM_DEBUG_KMS("\n");
> @@ -1032,7 +1032,7 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
>  	struct drm_device *dev = encoder->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct drm_display_mode *adjusted_mode =
> -					&pipe_config->base.adjusted_mode;
> +					&pipe_config->hw.adjusted_mode;
>  	struct drm_display_mode *adjusted_mode_sw;
>  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> @@ -1045,7 +1045,7 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
>  				crtc_hblank_start_sw, crtc_hblank_end_sw;
>  
>  	/* FIXME: hw readout should not depend on SW state */
> -	adjusted_mode_sw = &crtc->config->base.adjusted_mode;
> +	adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
>  
>  	/*
>  	 * Atleast one port is active as encoder->get_config called only if
> @@ -1204,7 +1204,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
>  	}
>  
>  	if (pclk) {
> -		pipe_config->base.adjusted_mode.crtc_clock = pclk;
> +		pipe_config->hw.adjusted_mode.crtc_clock = pclk;
>  		pipe_config->port_clock = pclk;
>  	}
>  }
> @@ -1317,7 +1317,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> -	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> +	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	enum port port;
>  	unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
>  	u32 val, tmp;
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index ada57eee914a..51e83da21738 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2751,11 +2751,11 @@ static int i915_display_info(struct seq_file *m, void *unused)
>  
>  		seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
>  			   crtc->base.base.id, pipe_name(crtc->pipe),
> -			   yesno(pipe_config->base.active),
> +			   yesno(pipe_config->hw.active),
>  			   pipe_config->pipe_src_w, pipe_config->pipe_src_h,
>  			   yesno(pipe_config->dither), pipe_config->pipe_bpp);
>  
> -		if (pipe_config->base.active) {
> +		if (pipe_config->hw.active) {
>  			struct intel_plane *cursor =
>  				to_intel_plane(crtc->base.cursor);
>  
> @@ -4218,7 +4218,7 @@ static int i915_drrs_ctl_set(void *data, u64 val)
>  
>  		crtc_state = to_intel_crtc_state(crtc->base.state);
>  
> -		if (!crtc_state->base.active ||
> +		if (!crtc_state->hw.active ||
>  		    !crtc_state->has_drrs)
>  			goto out;
>  
> @@ -4300,7 +4300,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
>  				ret = wait_for_completion_interruptible(&commit->flip_done);
>  		}
>  
> -		if (!ret && crtc_state->base.active) {
> +		if (!ret && crtc_state->hw.active) {
>  			DRM_DEBUG_KMS("Re-arming FIFO underruns on pipe %c\n",
>  				      pipe_name(intel_crtc->pipe));
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e680df75a970..9671ff29c25f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -798,7 +798,7 @@ static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
>  	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>  
>  	/* FIXME check the 'enable' instead */
> -	if (!crtc_state->base.active)
> +	if (!crtc_state->hw.active)
>  		return false;
>  
>  	/*
> @@ -851,7 +851,7 @@ static void pineview_update_wm(struct intel_crtc *unused_crtc)
>  	crtc = single_enabled_crtc(dev_priv);
>  	if (crtc) {
>  		const struct drm_display_mode *adjusted_mode =
> -			&crtc->config->base.adjusted_mode;
> +			&crtc->config->hw.adjusted_mode;
>  		const struct drm_framebuffer *fb =
>  			crtc->base.primary->state->fb;
>  		int cpp = fb->format->cpp[0];
> @@ -1087,7 +1087,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
>  	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->base.adjusted_mode;
> +		&crtc_state->hw.adjusted_mode;
>  	unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
>  	unsigned int clock, htotal, cpp, width, wm;
>  
> @@ -1399,7 +1399,7 @@ static int g4x_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
>  	const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
>  	enum plane_id plane_id;
>  
> -	if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
> +	if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
>  		*intermediate = *optimal;
>  
>  		intermediate->cxsr = false;
> @@ -1593,7 +1593,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
>  	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->base.adjusted_mode;
> +		&crtc_state->hw.adjusted_mode;
>  	unsigned int clock, htotal, cpp, width, wm;
>  
>  	if (dev_priv->wm.pri_latency[level] == 0)
> @@ -2032,7 +2032,7 @@ static int vlv_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
>  	const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
>  	int level;
>  
> -	if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
> +	if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
>  		*intermediate = *optimal;
>  
>  		intermediate->cxsr = false;
> @@ -2188,7 +2188,7 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
>  		/* self-refresh has much higher latency */
>  		static const int sr_latency_ns = 12000;
>  		const struct drm_display_mode *adjusted_mode =
> -			&crtc->config->base.adjusted_mode;
> +			&crtc->config->hw.adjusted_mode;
>  		const struct drm_framebuffer *fb =
>  			crtc->base.primary->state->fb;
>  		int clock = adjusted_mode->crtc_clock;
> @@ -2269,7 +2269,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>  	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
>  	if (intel_crtc_active(crtc)) {
>  		const struct drm_display_mode *adjusted_mode =
> -			&crtc->config->base.adjusted_mode;
> +			&crtc->config->hw.adjusted_mode;
>  		const struct drm_framebuffer *fb =
>  			crtc->base.primary->state->fb;
>  		int cpp;
> @@ -2296,7 +2296,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>  	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
>  	if (intel_crtc_active(crtc)) {
>  		const struct drm_display_mode *adjusted_mode =
> -			&crtc->config->base.adjusted_mode;
> +			&crtc->config->hw.adjusted_mode;
>  		const struct drm_framebuffer *fb =
>  			crtc->base.primary->state->fb;
>  		int cpp;
> @@ -2344,7 +2344,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>  		/* self-refresh has much higher latency */
>  		static const int sr_latency_ns = 6000;
>  		const struct drm_display_mode *adjusted_mode =
> -			&enabled->config->base.adjusted_mode;
> +			&enabled->config->hw.adjusted_mode;
>  		const struct drm_framebuffer *fb =
>  			enabled->base.primary->state->fb;
>  		int clock = adjusted_mode->crtc_clock;
> @@ -2402,7 +2402,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
>  	if (crtc == NULL)
>  		return;
>  
> -	adjusted_mode = &crtc->config->base.adjusted_mode;
> +	adjusted_mode = &crtc->config->hw.adjusted_mode;
>  	planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
>  				       &i845_wm_info,
>  				       dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
> @@ -2492,7 +2492,7 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
>  		return method1;
>  
>  	method2 = ilk_wm_method2(crtc_state->pixel_rate,
> -				 crtc_state->base.adjusted_mode.crtc_htotal,
> +				 crtc_state->hw.adjusted_mode.crtc_htotal,
>  				 drm_rect_width(&plane_state->base.dst),
>  				 cpp, mem_value);
>  
> @@ -2520,7 +2520,7 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
>  
>  	method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
>  	method2 = ilk_wm_method2(crtc_state->pixel_rate,
> -				 crtc_state->base.adjusted_mode.crtc_htotal,
> +				 crtc_state->hw.adjusted_mode.crtc_htotal,
>  				 drm_rect_width(&plane_state->base.dst),
>  				 cpp, mem_value);
>  	return min(method1, method2);
> @@ -2545,7 +2545,7 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
>  	cpp = plane_state->base.fb->format->cpp[0];
>  
>  	return ilk_wm_method2(crtc_state->pixel_rate,
> -			      crtc_state->base.adjusted_mode.crtc_htotal,
> +			      crtc_state->hw.adjusted_mode.crtc_htotal,
>  			      drm_rect_width(&plane_state->base.dst),
>  			      cpp, mem_value);
>  }
> @@ -2769,10 +2769,10 @@ hsw_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
>  	const struct intel_atomic_state *intel_state =
>  		to_intel_atomic_state(crtc_state->base.state);
>  	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->base.adjusted_mode;
> +		&crtc_state->hw.adjusted_mode;
>  	u32 linetime, ips_linetime;
>  
> -	if (!crtc_state->base.active)
> +	if (!crtc_state->hw.active)
>  		return 0;
>  	if (WARN_ON(adjusted_mode->crtc_clock == 0))
>  		return 0;
> @@ -3104,7 +3104,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
>  			curstate = plane_state;
>  	}
>  
> -	pipe_wm->pipe_enabled = crtc_state->base.active;
> +	pipe_wm->pipe_enabled = crtc_state->hw.active;
>  	if (sprstate) {
>  		pipe_wm->sprites_enabled = sprstate->base.visible;
>  		pipe_wm->sprites_scaled = sprstate->base.visible &&
> @@ -3177,7 +3177,7 @@ static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
>  	 * and after the vblank.
>  	 */
>  	*a = newstate->wm.ilk.optimal;
> -	if (!newstate->base.active || drm_atomic_crtc_needs_modeset(&newstate->base) ||
> +	if (!newstate->hw.active || drm_atomic_crtc_needs_modeset(&newstate->base) ||
>  	    intel_state->skip_intermediate_wm)
>  		return 0;
>  
> @@ -3779,7 +3779,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
>  	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
>  	crtc_state = to_intel_crtc_state(crtc->base.state);
>  
> -	if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> +	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
>  		return false;
>  
>  	for_each_intel_plane_on_crtc(dev, crtc, plane) {
> @@ -3829,7 +3829,7 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
>  	if (INTEL_GEN(dev_priv) < 11)
>  		return ddb_size - 4; /* 4 blocks for bypass path allocation */
>  
> -	adjusted_mode = &crtc_state->base.adjusted_mode;
> +	adjusted_mode = &crtc_state->hw.adjusted_mode;
>  	total_data_bw = total_data_rate * drm_mode_vrefresh(adjusted_mode);
>  
>  	/*
> @@ -3867,7 +3867,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
>  	u16 ddb_size;
>  	u32 i;
>  
> -	if (WARN_ON(!state) || !crtc_state->base.active) {
> +	if (WARN_ON(!state) || !crtc_state->hw.active) {
>  		alloc->start = 0;
>  		alloc->end = 0;
>  		*num_active = hweight8(dev_priv->active_pipes);
> @@ -3906,11 +3906,11 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
>  	 */
>  	for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
>  		const struct drm_display_mode *adjusted_mode =
> -			&crtc_state->base.adjusted_mode;
> +			&crtc_state->hw.adjusted_mode;
>  		enum pipe pipe = crtc->pipe;
>  		int hdisplay, vdisplay;
>  
> -		if (!crtc_state->base.enable)
> +		if (!crtc_state->hw.enable)
>  			continue;
>  
>  		drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
> @@ -4099,7 +4099,7 @@ skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
>  {
>  	uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1);
>  
> -	if (!crtc_state->base.enable)
> +	if (!crtc_state->hw.enable)
>  		return pipe_downscale;
>  
>  	if (crtc_state->pch_pfit.enabled) {
> @@ -4139,7 +4139,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
>  	uint_fixed_16_16_t pipe_downscale;
>  	uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);
>  
> -	if (!crtc_state->base.enable)
> +	if (!crtc_state->hw.enable)
>  		return 0;
>  
>  	intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> @@ -4165,7 +4165,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
>  
>  	pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
>  
> -	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
> +	crtc_clock = crtc_state->hw.adjusted_mode.crtc_clock;
>  	dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
>  
>  	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> @@ -4334,7 +4334,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  	if (WARN_ON(!state))
>  		return 0;
>  
> -	if (!crtc_state->base.active) {
> +	if (!crtc_state->hw.active) {
>  		alloc->start = alloc->end = 0;
>  		return 0;
>  	}
> @@ -4576,7 +4576,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
>  	u32 crtc_htotal;
>  	uint_fixed_16_16_t linetime_us;
>  
> -	if (!crtc_state->base.active)
> +	if (!crtc_state->hw.active)
>  		return u32_to_fixed16(0);
>  
>  	pixel_rate = crtc_state->pixel_rate;
> @@ -4584,7 +4584,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
>  	if (WARN_ON(pixel_rate == 0))
>  		return u32_to_fixed16(0);
>  
> -	crtc_htotal = crtc_state->base.adjusted_mode.crtc_htotal;
> +	crtc_htotal = crtc_state->hw.adjusted_mode.crtc_htotal;
>  	linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
>  
>  	return linetime_us;
> @@ -4766,14 +4766,14 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
>  	method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
>  				 wp->cpp, latency, wp->dbuf_block_size);
>  	method2 = skl_wm_method2(wp->plane_pixel_rate,
> -				 crtc_state->base.adjusted_mode.crtc_htotal,
> +				 crtc_state->hw.adjusted_mode.crtc_htotal,
>  				 latency,
>  				 wp->plane_blocks_per_line);
>  
>  	if (wp->y_tiled) {
>  		selected_result = max_fixed16(method2, wp->y_tile_minimum);
>  	} else {
> -		if ((wp->cpp * crtc_state->base.adjusted_mode.crtc_htotal /
> +		if ((wp->cpp * crtc_state->hw.adjusted_mode.crtc_htotal /
>  		     wp->dbuf_block_size < 1) &&
>  		     (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
>  			selected_result = method2;
> -- 
> 2.23.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH 04/14] drm/i915: Add aliases for uapi and hw to crtc_state
  2019-10-18 12:09     ` Maarten Lankhorst
@ 2019-10-18 13:09       ` Ville Syrjälä
  0 siblings, 0 replies; 49+ messages in thread
From: Ville Syrjälä @ 2019-10-18 13:09 UTC (permalink / raw)
  To: Maarten Lankhorst; +Cc: intel-gfx

On Fri, Oct 18, 2019 at 02:09:17PM +0200, Maarten Lankhorst wrote:
> Op 18-10-2019 om 12:36 schreef Ville Syrjälä:
> > On Thu, Oct 17, 2019 at 03:20:55PM +0200, Maarten Lankhorst wrote:
> >> Prepare to split up hw and uapi machinally, by adding a uapi and
> >> hw alias. We will remove the base in a bit. This is a split from the
> >> original uapi/hw patch, which did it all in one go.
> >>
> >> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_atomic.c   |  8 ++++--
> >>  drivers/gpu/drm/i915/display/intel_display.c  |  2 ++
> >>  drivers/gpu/drm/i915/display/intel_display.h  |  6 ++---
> >>  .../drm/i915/display/intel_display_types.h    | 27 ++++++++++++++++++-
> >>  4 files changed, 37 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> >> index e6cb85d41c8d..2cdc92897abd 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> >> @@ -186,9 +186,10 @@ intel_digital_connector_duplicate_state(struct drm_connector *connector)
> >>  struct drm_crtc_state *
> >>  intel_crtc_duplicate_state(struct drm_crtc *crtc)
> >>  {
> >> +	const struct intel_crtc_state *old_crtc_state = to_intel_crtc_state(crtc->state);
> >>  	struct intel_crtc_state *crtc_state;
> >>  
> >> -	crtc_state = kmemdup(crtc->state, sizeof(*crtc_state), GFP_KERNEL);
> >> +	crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL);
> >>  	if (!crtc_state)
> >>  		return NULL;
> >>  
> >> @@ -219,7 +220,10 @@ void
> >>  intel_crtc_destroy_state(struct drm_crtc *crtc,
> >>  			 struct drm_crtc_state *state)
> >>  {
> >> -	drm_atomic_helper_crtc_destroy_state(crtc, state);
> >> +	struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
> >> +
> >> +	__drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
> >> +	kfree(crtc_state);
> >>  }
> >>  
> >>  static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> >> index 5632e13d458d..fa0abfdff2ae 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> @@ -12282,6 +12282,8 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
> >>  
> >>  	/* Keep base drm_crtc_state intact, only clear our extended struct */
> >>  	BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
> >> +	BUILD_BUG_ON(offsetof(struct intel_crtc_state, uapi));
> >> +	BUILD_BUG_ON(offsetof(struct intel_crtc_state, hw));
> >>  	memcpy(&crtc_state->base + 1, &saved_state->base + 1,
> >>  	       sizeof(*crtc_state) - sizeof(crtc_state->base));
> >>  
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> >> index 90807603987c..9b53f65386b5 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> >> @@ -444,10 +444,10 @@ enum phy_fia {
> >>  #define intel_atomic_crtc_state_for_each_plane_state( \
> >>  		  plane, plane_state, \
> >>  		  crtc_state) \
> >> -	for_each_intel_plane_mask(((crtc_state)->base.state->dev), (plane), \
> >> -				((crtc_state)->base.plane_mask)) \
> >> +	for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
> >> +				((crtc_state)->uapi.plane_mask)) \
> >>  		for_each_if ((plane_state = \
> >> -			      to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->base.state, &plane->base))))
> >> +			      to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
> >>  
> >>  void intel_link_compute_m_n(u16 bpp, int nlanes,
> >>  			    int pixel_clock, int link_clock,
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> >> index 244e881474fb..4d85ea5832d7 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> >> @@ -749,7 +749,32 @@ enum intel_output_format {
> >>  };
> >>  
> >>  struct intel_crtc_state {
> >> +	union {
> >>  	struct drm_crtc_state base;
> >> +	/*
> >> +	 * uapi (drm) state. This is the software state shown to userspace.
> >> +	 * In particular, the following members are used for bookkeeping:
> >> +	 * - crtc
> >> +	 * - state
> >> +	 * - *_changed
> >> +	 * - event
> >> +	 * - commit
> >> +	 * - mode_blob
> >> +	 */
> >> +	struct drm_crtc_state uapi;
> >> +
> >> +	/*
> >> +	 * actual hardware state, the state we program to the hardware.
> >> +	 * The following members are used to verify the hardware state:
> >> +	 * - enable
> >> +	 * - active
> >> +	 * - mode / adjusted_mode
> >> +	 * - color property blobs.
> >> +	 *
> >> +	 * During initial hw readout, they need to be copied to uapi.
> >> +	 */
> >> +	struct drm_crtc_state hw;
> >> +	};
> > This part confuses me. Can't we just do
> >
> > - struct drm_crtc_state base;
> > + struct drm_crtc_state uapi;
> > + struct {
> > +	...
> > + } base;
> >
> > ?
> 
> This is basically union { struct drm_crtc_state uapi,base,hw; }; Making all 3 aliases until patch 8/14, which kills off base and splits off hw state.
> 
> We keep it as an union because base and uapi temporarily have to be kept in sync, while we split to uapi and hw. So it's easy to keep hw in sync as well.
> 
> In the end it doesn't matter whether we split off hw before or after. The diff between before and after is the same.

Sure but the individual patches are very hard to review. Eg. I can see
a bunch of stuff getting converted from base to hw, but since .base
still exists I have no way of knowing whether the patch really changed
all of them or just some of them.

-- 
Ville Syrjälä
Intel
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: ✗ Fi.CI.IGT: failure for series starting with [01/14] drm/i915: Rework watermark readout to use plane api (rev2)
  2019-10-18 10:57 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-10-18 14:03   ` Maarten Lankhorst
  0 siblings, 0 replies; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-18 14:03 UTC (permalink / raw)
  To: intel-gfx

Op 18-10-2019 om 12:57 schreef Patchwork:
> == Series Details ==
>
> Series: series starting with [01/14] drm/i915: Rework watermark readout to use plane api (rev2)
> URL   : https://patchwork.freedesktop.org/series/68154/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7125_full -> Patchwork_14874_full
> ====================================================
>
> Summary
> -------
>
>   **FAILURE**
>
>   Serious unknown changes coming with Patchwork_14874_full absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_14874_full, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
>
>   
>
> Possible new issues
> -------------------
>
>   Here are the unknown changes that may have been introduced in Patchwork_14874_full:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
>   * igt@gem_ctx_switch@queue-light:
>     - shard-glk:          [PASS][1] -> [DMESG-WARN][2]
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-glk6/igt@gem_ctx_switch@queue-light.html
>    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-glk7/igt@gem_ctx_switch@queue-light.html
>
>   * igt@kms_plane@pixel-format-pipe-b-planes:
>     - shard-kbl:          [PASS][3] -> [FAIL][4] +3 similar issues
>    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-kbl3/igt@kms_plane@pixel-format-pipe-b-planes.html
>    [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-kbl3/igt@kms_plane@pixel-format-pipe-b-planes.html
>
>   * igt@kms_plane@pixel-format-pipe-c-planes:
>     - shard-glk:          [PASS][5] -> [FAIL][6] +5 similar issues
>    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-glk4/igt@kms_plane@pixel-format-pipe-c-planes.html
>    [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14874/shard-glk8/igt@kms_plane@pixel-format-pipe-c-planes.html
>
Guessing this comes from the last patch. Will look at it.
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH 14/14] drm/i915: Remove special case slave handling during hw programming, v2.
  2019-10-17 13:21 ` [PATCH 14/14] drm/i915: Remove special case slave handling during hw programming, v2 Maarten Lankhorst
@ 2019-10-18 14:52   ` Maarten Lankhorst
  2019-10-22 10:31   ` [PATCH] drm/i915: Remove special case slave handling during hw programming, v3 Maarten Lankhorst
  1 sibling, 0 replies; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-18 14:52 UTC (permalink / raw)
  To: Intel Graphics Development

Op 17-10-2019 om 15:21 schreef Maarten Lankhorst:
> Now that we split plane_state which I didn't want to do yet, we can
> program the slave plane without requiring the master plane.
>
> This is useful for programming bigjoiner slave planes as well. We
> will no longer need the master's plane_state.
>
> Changes since v1:
> - set src/dst rectangles after copy_uapi_to_hw_state.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
>  .../gpu/drm/i915/display/intel_atomic_plane.c | 30 +---------
>  .../gpu/drm/i915/display/intel_atomic_plane.h |  3 -
>  drivers/gpu/drm/i915/display/intel_display.c  | 18 ++++++
>  .../drm/i915/display/intel_display_types.h    |  6 +-
>  drivers/gpu/drm/i915/display/intel_sprite.c   | 55 ++++++-------------
>  5 files changed, 39 insertions(+), 73 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index d9b65e9c45fc..54d112408716 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -309,16 +309,6 @@ void intel_update_plane(struct intel_plane *plane,
>  	plane->update_plane(plane, crtc_state, plane_state);
>  }
>  
> -void intel_update_slave(struct intel_plane *plane,
> -			const struct intel_crtc_state *crtc_state,
> -			const struct intel_plane_state *plane_state)
> -{
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -
> -	trace_intel_update_plane(&plane->base, crtc);
> -	plane->update_slave(plane, crtc_state, plane_state);
> -}
> -
>  void intel_disable_plane(struct intel_plane *plane,
>  			 const struct intel_crtc_state *crtc_state)
>  {
> @@ -351,25 +341,9 @@ void skl_update_planes_on_crtc(struct intel_atomic_state *state,
>  		struct intel_plane_state *new_plane_state =
>  			intel_atomic_get_new_plane_state(state, plane);
>  
> -		if (new_plane_state->uapi.visible) {
> +		if (new_plane_state->uapi.visible ||
> +		    new_plane_state->planar_slave) {
>  			intel_update_plane(plane, new_crtc_state, new_plane_state);
> -		} else if (new_plane_state->planar_slave) {
> -			struct intel_plane *master =
> -				new_plane_state->planar_linked_plane;
> -
> -			/*
> -			 * We update the slave plane from this function because
> -			 * programming it from the master plane's update_plane
> -			 * callback runs into issues when the Y plane is
> -			 * reassigned, disabled or used by a different plane.
> -			 *
> -			 * The slave plane is updated with the master plane's
> -			 * plane_state.
> -			 */
> -			new_plane_state =
> -				intel_atomic_get_new_plane_state(state, master);
> -
> -			intel_update_slave(plane, new_crtc_state, new_plane_state);
>  		} else {
>  			intel_disable_plane(plane, new_crtc_state);
>  		}
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> index 123404a9cf23..726ececd6abd 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> @@ -25,9 +25,6 @@ void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
>  void intel_update_plane(struct intel_plane *plane,
>  			const struct intel_crtc_state *crtc_state,
>  			const struct intel_plane_state *plane_state);
> -void intel_update_slave(struct intel_plane *plane,
> -			const struct intel_crtc_state *crtc_state,
> -			const struct intel_plane_state *plane_state);
>  void intel_disable_plane(struct intel_plane *plane,
>  			 const struct intel_crtc_state *crtc_state);
>  struct intel_plane *intel_plane_alloc(void);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index de520d5f1374..88f149cac198 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11768,6 +11768,24 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
>  		crtc_state->active_planes |= BIT(linked->id);
>  		crtc_state->update_planes |= BIT(linked->id);
>  		DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
> +
> +		/* Copy parameters to slave plane */
> +		linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
> +		linked_state->color_ctl = plane_state->color_ctl;
> +		linked_state->color_plane[0] = plane_state->color_plane[0];
> +
> +		intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
> +		linked_state->uapi.src = plane_state->uapi.src;
> +		linked_state->uapi.dst = plane_state->uapi.dst;
> +
> +		if (icl_is_hdr_plane(dev_priv, plane->id)) {
> +			if (linked->id == PLANE_SPRITE5)
> +				plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
> +			else if (linked->id == PLANE_SPRITE4)
> +				plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
> +			else
> +				MISSING_CASE(linked->id);
> +		}
>  	}
>  
>  	return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 5379b93c2fab..dbca1b3c5c67 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -555,6 +555,9 @@ struct intel_plane_state {
>  	/* plane color control register */
>  	u32 color_ctl;
>  
> +	/* chroma upsampler control register */
> +	u32 cus_ctl;
> +
>  	/*
>  	 * scaler_id
>  	 *    = -1 : not using a scaler
> @@ -1106,9 +1109,6 @@ struct intel_plane {
>  	void (*update_plane)(struct intel_plane *plane,
>  			     const struct intel_crtc_state *crtc_state,
>  			     const struct intel_plane_state *plane_state);
> -	void (*update_slave)(struct intel_plane *plane,
> -			     const struct intel_crtc_state *crtc_state,
> -			     const struct intel_plane_state *plane_state);
>  	void (*disable_plane)(struct intel_plane *plane,
>  			      const struct intel_crtc_state *crtc_state);
>  	bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 00f83d37abcf..20123fccd081 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -526,7 +526,7 @@ static void
>  skl_program_plane(struct intel_plane *plane,
>  		  const struct intel_crtc_state *crtc_state,
>  		  const struct intel_plane_state *plane_state,
> -		  int color_plane, bool slave, u32 plane_ctl)
> +		  int color_plane)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	enum plane_id plane_id = plane->id;
> @@ -541,12 +541,12 @@ skl_program_plane(struct intel_plane *plane,
>  	u32 y = plane_state->color_plane[color_plane].y;
>  	u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
>  	u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> -	struct intel_plane *linked = plane_state->planar_linked_plane;
>  	const struct drm_framebuffer *fb = plane_state->hw.fb;
>  	u8 alpha = plane_state->hw.alpha >> 8;
>  	u32 plane_color_ctl = 0;
>  	unsigned long irqflags;
>  	u32 keymsk, keymax;
> +	u32 plane_ctl = plane_state->ctl;
>  
>  	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
>  
> @@ -578,26 +578,8 @@ skl_program_plane(struct intel_plane *plane,
>  	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
>  		      (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
>  
> -	if (icl_is_hdr_plane(dev_priv, plane_id)) {
> -		u32 cus_ctl = 0;
> -
> -		if (linked) {
> -			/* Enable and use MPEG-2 chroma siting */
> -			cus_ctl = PLANE_CUS_ENABLE |
> -				PLANE_CUS_HPHASE_0 |
> -				PLANE_CUS_VPHASE_SIGN_NEGATIVE |
> -				PLANE_CUS_VPHASE_0_25;
> -
> -			if (linked->id == PLANE_SPRITE5)
> -				cus_ctl |= PLANE_CUS_PLANE_7;
> -			else if (linked->id == PLANE_SPRITE4)
> -				cus_ctl |= PLANE_CUS_PLANE_6;
> -			else
> -				MISSING_CASE(linked->id);
> -		}
> -
> -		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), cus_ctl);
> -	}
> +	if (icl_is_hdr_plane(dev_priv, plane_id))
> +		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), plane_state->cus_ctl);
>  
>  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>  		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
> @@ -627,7 +609,7 @@ skl_program_plane(struct intel_plane *plane,
>  	I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
>  		      intel_plane_ggtt_offset(plane_state) + surf_addr);
>  
> -	if (!slave && plane_state->scaler_id >= 0)
> +	if (plane_state->scaler_id >= 0)
>  		skl_program_scaler(plane, crtc_state, plane_state);
>  
>  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> @@ -640,24 +622,13 @@ skl_update_plane(struct intel_plane *plane,
>  {
>  	int color_plane = 0;
>  
> -	if (plane_state->planar_linked_plane) {
> +	if (drm_format_info_is_yuv_semiplanar(plane_state->hw.fb->format) &&
> +	    !plane_state->planar_slave)
>  		/* Program the UV plane */
>  		color_plane = 1;
> -	}
And for pre-icl, this explains the test failures, needs a gen11+ check.
>  
> -	skl_program_plane(plane, crtc_state, plane_state,
> -			  color_plane, false, plane_state->ctl);
> +	skl_program_plane(plane, crtc_state, plane_state, color_plane);
>  }
> -
> -static void
> -icl_update_slave(struct intel_plane *plane,
> -		 const struct intel_crtc_state *crtc_state,
> -		 const struct intel_plane_state *plane_state)
> -{
> -	skl_program_plane(plane, crtc_state, plane_state, 0, true,
> -			  plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE);
> -}
> -
>  static void
>  skl_disable_plane(struct intel_plane *plane,
>  		  const struct intel_crtc_state *crtc_state)
> @@ -1844,6 +1815,14 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
>  		plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
>  							     plane_state);
>  
> +	if (icl_is_hdr_plane(dev_priv, plane->id) && fb->format->is_yuv)
> +		/* Enable and use MPEG-2 chroma siting */
> +		plane_state->cus_ctl = PLANE_CUS_ENABLE |
> +			PLANE_CUS_HPHASE_0 |
> +			PLANE_CUS_VPHASE_SIGN_NEGATIVE | PLANE_CUS_VPHASE_0_25;
> +	else
> +		plane_state->cus_ctl = 0;

needs drm_format_info_is_yuv_semiplanar(fb->format) instead of is_yuv check. This explains the test failures on icl+.

>  	return 0;
>  }
>  
> @@ -2512,8 +2491,6 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>  	plane->disable_plane = skl_disable_plane;
>  	plane->get_hw_state = skl_plane_get_hw_state;
>  	plane->check_plane = skl_plane_check;
> -	if (icl_is_nv12_y_plane(plane_id))
> -		plane->update_slave = icl_update_slave;
>  
>  	if (INTEL_GEN(dev_priv) >= 11)
>  		formats = icl_get_plane_formats(dev_priv, pipe,


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^ permalink raw reply	[flat|nested] 49+ messages in thread

* [PATCH] drm/i915: Remove special case slave handling during hw programming, v3.
  2019-10-17 13:21 ` [PATCH 14/14] drm/i915: Remove special case slave handling during hw programming, v2 Maarten Lankhorst
  2019-10-18 14:52   ` Maarten Lankhorst
@ 2019-10-22 10:31   ` Maarten Lankhorst
  2019-10-22 18:14     ` Ville Syrjälä
  1 sibling, 1 reply; 49+ messages in thread
From: Maarten Lankhorst @ 2019-10-22 10:31 UTC (permalink / raw)
  To: intel-gfx

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

Now that we split plane_state which I didn't want to do yet, we can
program the slave plane without requiring the master plane.

This is useful for programming bigjoiner slave planes as well. We
will no longer need the master's plane_state.

Changes since v1:
- set src/dst rectangles after copy_uapi_to_hw_state.
Changes since v2:
- Use the correct color_plane for pre-gen11 by using planar_linked_plane != NULL.
- Use drm_format_info_is_yuv_semiplanar in skl_plane_check() to fix gen11+.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 .../gpu/drm/i915/display/intel_atomic_plane.c | 30 +---------
 .../gpu/drm/i915/display/intel_atomic_plane.h |  3 -
 drivers/gpu/drm/i915/display/intel_display.c  | 18 ++++++
 .../drm/i915/display/intel_display_types.h    |  6 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   | 57 ++++++-------------
 5 files changed, 40 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index d9b65e9c45fc..54d112408716 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -309,16 +309,6 @@ void intel_update_plane(struct intel_plane *plane,
 	plane->update_plane(plane, crtc_state, plane_state);
 }
 
-void intel_update_slave(struct intel_plane *plane,
-			const struct intel_crtc_state *crtc_state,
-			const struct intel_plane_state *plane_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-
-	trace_intel_update_plane(&plane->base, crtc);
-	plane->update_slave(plane, crtc_state, plane_state);
-}
-
 void intel_disable_plane(struct intel_plane *plane,
 			 const struct intel_crtc_state *crtc_state)
 {
@@ -351,25 +341,9 @@ void skl_update_planes_on_crtc(struct intel_atomic_state *state,
 		struct intel_plane_state *new_plane_state =
 			intel_atomic_get_new_plane_state(state, plane);
 
-		if (new_plane_state->uapi.visible) {
+		if (new_plane_state->uapi.visible ||
+		    new_plane_state->planar_slave) {
 			intel_update_plane(plane, new_crtc_state, new_plane_state);
-		} else if (new_plane_state->planar_slave) {
-			struct intel_plane *master =
-				new_plane_state->planar_linked_plane;
-
-			/*
-			 * We update the slave plane from this function because
-			 * programming it from the master plane's update_plane
-			 * callback runs into issues when the Y plane is
-			 * reassigned, disabled or used by a different plane.
-			 *
-			 * The slave plane is updated with the master plane's
-			 * plane_state.
-			 */
-			new_plane_state =
-				intel_atomic_get_new_plane_state(state, master);
-
-			intel_update_slave(plane, new_crtc_state, new_plane_state);
 		} else {
 			intel_disable_plane(plane, new_crtc_state);
 		}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 123404a9cf23..726ececd6abd 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -25,9 +25,6 @@ void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
 void intel_update_plane(struct intel_plane *plane,
 			const struct intel_crtc_state *crtc_state,
 			const struct intel_plane_state *plane_state);
-void intel_update_slave(struct intel_plane *plane,
-			const struct intel_crtc_state *crtc_state,
-			const struct intel_plane_state *plane_state);
 void intel_disable_plane(struct intel_plane *plane,
 			 const struct intel_crtc_state *crtc_state);
 struct intel_plane *intel_plane_alloc(void);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 490f09264c7f..e51cbf6b4159 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11911,6 +11911,24 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
 		crtc_state->active_planes |= BIT(linked->id);
 		crtc_state->update_planes |= BIT(linked->id);
 		DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
+
+		/* Copy parameters to slave plane */
+		linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
+		linked_state->color_ctl = plane_state->color_ctl;
+		linked_state->color_plane[0] = plane_state->color_plane[0];
+
+		intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
+		linked_state->uapi.src = plane_state->uapi.src;
+		linked_state->uapi.dst = plane_state->uapi.dst;
+
+		if (icl_is_hdr_plane(dev_priv, plane->id)) {
+			if (linked->id == PLANE_SPRITE5)
+				plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
+			else if (linked->id == PLANE_SPRITE4)
+				plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
+			else
+				MISSING_CASE(linked->id);
+		}
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index a38d0f20ef2b..ff481af2b24b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -555,6 +555,9 @@ struct intel_plane_state {
 	/* plane color control register */
 	u32 color_ctl;
 
+	/* chroma upsampler control register */
+	u32 cus_ctl;
+
 	/*
 	 * scaler_id
 	 *    = -1 : not using a scaler
@@ -1112,9 +1115,6 @@ struct intel_plane {
 	void (*update_plane)(struct intel_plane *plane,
 			     const struct intel_crtc_state *crtc_state,
 			     const struct intel_plane_state *plane_state);
-	void (*update_slave)(struct intel_plane *plane,
-			     const struct intel_crtc_state *crtc_state,
-			     const struct intel_plane_state *plane_state);
 	void (*disable_plane)(struct intel_plane *plane,
 			      const struct intel_crtc_state *crtc_state);
 	bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 00f83d37abcf..0036ca6c1aba 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -526,7 +526,7 @@ static void
 skl_program_plane(struct intel_plane *plane,
 		  const struct intel_crtc_state *crtc_state,
 		  const struct intel_plane_state *plane_state,
-		  int color_plane, bool slave, u32 plane_ctl)
+		  int color_plane)
 {
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	enum plane_id plane_id = plane->id;
@@ -541,12 +541,12 @@ skl_program_plane(struct intel_plane *plane,
 	u32 y = plane_state->color_plane[color_plane].y;
 	u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 	u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
-	struct intel_plane *linked = plane_state->planar_linked_plane;
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	u8 alpha = plane_state->hw.alpha >> 8;
 	u32 plane_color_ctl = 0;
 	unsigned long irqflags;
 	u32 keymsk, keymax;
+	u32 plane_ctl = plane_state->ctl;
 
 	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
 
@@ -578,26 +578,8 @@ skl_program_plane(struct intel_plane *plane,
 	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
 		      (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
 
-	if (icl_is_hdr_plane(dev_priv, plane_id)) {
-		u32 cus_ctl = 0;
-
-		if (linked) {
-			/* Enable and use MPEG-2 chroma siting */
-			cus_ctl = PLANE_CUS_ENABLE |
-				PLANE_CUS_HPHASE_0 |
-				PLANE_CUS_VPHASE_SIGN_NEGATIVE |
-				PLANE_CUS_VPHASE_0_25;
-
-			if (linked->id == PLANE_SPRITE5)
-				cus_ctl |= PLANE_CUS_PLANE_7;
-			else if (linked->id == PLANE_SPRITE4)
-				cus_ctl |= PLANE_CUS_PLANE_6;
-			else
-				MISSING_CASE(linked->id);
-		}
-
-		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), cus_ctl);
-	}
+	if (icl_is_hdr_plane(dev_priv, plane_id))
+		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), plane_state->cus_ctl);
 
 	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
@@ -627,7 +609,7 @@ skl_program_plane(struct intel_plane *plane,
 	I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
 		      intel_plane_ggtt_offset(plane_state) + surf_addr);
 
-	if (!slave && plane_state->scaler_id >= 0)
+	if (plane_state->scaler_id >= 0)
 		skl_program_scaler(plane, crtc_state, plane_state);
 
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
@@ -640,24 +622,12 @@ skl_update_plane(struct intel_plane *plane,
 {
 	int color_plane = 0;
 
-	if (plane_state->planar_linked_plane) {
-		/* Program the UV plane */
+	if (plane_state->planar_linked_plane && !plane_state->planar_slave)
+		/* Program the UV plane on planar master */
 		color_plane = 1;
-	}
-
-	skl_program_plane(plane, crtc_state, plane_state,
-			  color_plane, false, plane_state->ctl);
-}
 
-static void
-icl_update_slave(struct intel_plane *plane,
-		 const struct intel_crtc_state *crtc_state,
-		 const struct intel_plane_state *plane_state)
-{
-	skl_program_plane(plane, crtc_state, plane_state, 0, true,
-			  plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE);
+	skl_program_plane(plane, crtc_state, plane_state, color_plane);
 }
-
 static void
 skl_disable_plane(struct intel_plane *plane,
 		  const struct intel_crtc_state *crtc_state)
@@ -1844,6 +1814,15 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
 		plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
 							     plane_state);
 
+	if (drm_format_info_is_yuv_semiplanar(fb->format) &&
+	    icl_is_hdr_plane(dev_priv, plane->id))
+		/* Enable and use MPEG-2 chroma siting */
+		plane_state->cus_ctl = PLANE_CUS_ENABLE |
+			PLANE_CUS_HPHASE_0 |
+			PLANE_CUS_VPHASE_SIGN_NEGATIVE | PLANE_CUS_VPHASE_0_25;
+	else
+		plane_state->cus_ctl = 0;
+
 	return 0;
 }
 
@@ -2512,8 +2491,6 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 	plane->disable_plane = skl_disable_plane;
 	plane->get_hw_state = skl_plane_get_hw_state;
 	plane->check_plane = skl_plane_check;
-	if (icl_is_nv12_y_plane(plane_id))
-		plane->update_slave = icl_update_slave;
 
 	if (INTEL_GEN(dev_priv) >= 11)
 		formats = icl_get_plane_formats(dev_priv, pipe,
-- 
2.23.0

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* Re: [PATCH] drm/i915: Remove special case slave handling during hw programming, v3.
  2019-10-22 10:31   ` [PATCH] drm/i915: Remove special case slave handling during hw programming, v3 Maarten Lankhorst
@ 2019-10-22 18:14     ` Ville Syrjälä
  2019-10-23 10:31         ` [Intel-gfx] " Maarten Lankhorst
  0 siblings, 1 reply; 49+ messages in thread
From: Ville Syrjälä @ 2019-10-22 18:14 UTC (permalink / raw)
  To: Maarten Lankhorst; +Cc: intel-gfx

On Tue, Oct 22, 2019 at 12:31:49PM +0200, Maarten Lankhorst wrote:
> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> 
> Now that we split plane_state which I didn't want to do yet, we can
> program the slave plane without requiring the master plane.
> 
> This is useful for programming bigjoiner slave planes as well. We
> will no longer need the master's plane_state.
> 
> Changes since v1:
> - set src/dst rectangles after copy_uapi_to_hw_state.
> Changes since v2:
> - Use the correct color_plane for pre-gen11 by using planar_linked_plane != NULL.
> - Use drm_format_info_is_yuv_semiplanar in skl_plane_check() to fix gen11+.
> 
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
>  .../gpu/drm/i915/display/intel_atomic_plane.c | 30 +---------
>  .../gpu/drm/i915/display/intel_atomic_plane.h |  3 -
>  drivers/gpu/drm/i915/display/intel_display.c  | 18 ++++++
>  .../drm/i915/display/intel_display_types.h    |  6 +-
>  drivers/gpu/drm/i915/display/intel_sprite.c   | 57 ++++++-------------
>  5 files changed, 40 insertions(+), 74 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index d9b65e9c45fc..54d112408716 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -309,16 +309,6 @@ void intel_update_plane(struct intel_plane *plane,
>  	plane->update_plane(plane, crtc_state, plane_state);
>  }
>  
> -void intel_update_slave(struct intel_plane *plane,
> -			const struct intel_crtc_state *crtc_state,
> -			const struct intel_plane_state *plane_state)
> -{
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -
> -	trace_intel_update_plane(&plane->base, crtc);
> -	plane->update_slave(plane, crtc_state, plane_state);
> -}
> -
>  void intel_disable_plane(struct intel_plane *plane,
>  			 const struct intel_crtc_state *crtc_state)
>  {
> @@ -351,25 +341,9 @@ void skl_update_planes_on_crtc(struct intel_atomic_state *state,
>  		struct intel_plane_state *new_plane_state =
>  			intel_atomic_get_new_plane_state(state, plane);
>  
> -		if (new_plane_state->uapi.visible) {
> +		if (new_plane_state->uapi.visible ||
> +		    new_plane_state->planar_slave) {
>  			intel_update_plane(plane, new_crtc_state, new_plane_state);
> -		} else if (new_plane_state->planar_slave) {
> -			struct intel_plane *master =
> -				new_plane_state->planar_linked_plane;
> -
> -			/*
> -			 * We update the slave plane from this function because
> -			 * programming it from the master plane's update_plane
> -			 * callback runs into issues when the Y plane is
> -			 * reassigned, disabled or used by a different plane.
> -			 *
> -			 * The slave plane is updated with the master plane's
> -			 * plane_state.
> -			 */
> -			new_plane_state =
> -				intel_atomic_get_new_plane_state(state, master);
> -
> -			intel_update_slave(plane, new_crtc_state, new_plane_state);
>  		} else {
>  			intel_disable_plane(plane, new_crtc_state);
>  		}
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> index 123404a9cf23..726ececd6abd 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> @@ -25,9 +25,6 @@ void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
>  void intel_update_plane(struct intel_plane *plane,
>  			const struct intel_crtc_state *crtc_state,
>  			const struct intel_plane_state *plane_state);
> -void intel_update_slave(struct intel_plane *plane,
> -			const struct intel_crtc_state *crtc_state,
> -			const struct intel_plane_state *plane_state);
>  void intel_disable_plane(struct intel_plane *plane,
>  			 const struct intel_crtc_state *crtc_state);
>  struct intel_plane *intel_plane_alloc(void);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 490f09264c7f..e51cbf6b4159 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11911,6 +11911,24 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
>  		crtc_state->active_planes |= BIT(linked->id);
>  		crtc_state->update_planes |= BIT(linked->id);
>  		DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
> +
> +		/* Copy parameters to slave plane */
> +		linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
> +		linked_state->color_ctl = plane_state->color_ctl;
> +		linked_state->color_plane[0] = plane_state->color_plane[0];
> +
> +		intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
> +		linked_state->uapi.src = plane_state->uapi.src;
> +		linked_state->uapi.dst = plane_state->uapi.dst;
> +
> +		if (icl_is_hdr_plane(dev_priv, plane->id)) {
> +			if (linked->id == PLANE_SPRITE5)
> +				plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
> +			else if (linked->id == PLANE_SPRITE4)
> +				plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
> +			else
> +				MISSING_CASE(linked->id);
> +		}

That stuff looks like it deserves a function of its own. Also a bit
annoying to copy if piecemeal like that. I guess don't have a
convenient way to just copy the whole thing in one go.

The use of intel_plane_copy_uapi_to_hw_state() also seems wrong
for the bigjoiner slave case. Shouldn't we just copy the hw state
and ignore uapi state here entirely?

>  	}
>  
>  	return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index a38d0f20ef2b..ff481af2b24b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -555,6 +555,9 @@ struct intel_plane_state {
>  	/* plane color control register */
>  	u32 color_ctl;
>  
> +	/* chroma upsampler control register */
> +	u32 cus_ctl;
> +
>  	/*
>  	 * scaler_id
>  	 *    = -1 : not using a scaler
> @@ -1112,9 +1115,6 @@ struct intel_plane {
>  	void (*update_plane)(struct intel_plane *plane,
>  			     const struct intel_crtc_state *crtc_state,
>  			     const struct intel_plane_state *plane_state);
> -	void (*update_slave)(struct intel_plane *plane,
> -			     const struct intel_crtc_state *crtc_state,
> -			     const struct intel_plane_state *plane_state);
>  	void (*disable_plane)(struct intel_plane *plane,
>  			      const struct intel_crtc_state *crtc_state);
>  	bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 00f83d37abcf..0036ca6c1aba 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -526,7 +526,7 @@ static void
>  skl_program_plane(struct intel_plane *plane,
>  		  const struct intel_crtc_state *crtc_state,
>  		  const struct intel_plane_state *plane_state,
> -		  int color_plane, bool slave, u32 plane_ctl)
> +		  int color_plane)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	enum plane_id plane_id = plane->id;
> @@ -541,12 +541,12 @@ skl_program_plane(struct intel_plane *plane,
>  	u32 y = plane_state->color_plane[color_plane].y;
>  	u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
>  	u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> -	struct intel_plane *linked = plane_state->planar_linked_plane;
>  	const struct drm_framebuffer *fb = plane_state->hw.fb;
>  	u8 alpha = plane_state->hw.alpha >> 8;
>  	u32 plane_color_ctl = 0;
>  	unsigned long irqflags;
>  	u32 keymsk, keymax;
> +	u32 plane_ctl = plane_state->ctl;
>  
>  	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
>  
> @@ -578,26 +578,8 @@ skl_program_plane(struct intel_plane *plane,
>  	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
>  		      (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
>  
> -	if (icl_is_hdr_plane(dev_priv, plane_id)) {
> -		u32 cus_ctl = 0;
> -
> -		if (linked) {
> -			/* Enable and use MPEG-2 chroma siting */
> -			cus_ctl = PLANE_CUS_ENABLE |
> -				PLANE_CUS_HPHASE_0 |
> -				PLANE_CUS_VPHASE_SIGN_NEGATIVE |
> -				PLANE_CUS_VPHASE_0_25;
> -
> -			if (linked->id == PLANE_SPRITE5)
> -				cus_ctl |= PLANE_CUS_PLANE_7;
> -			else if (linked->id == PLANE_SPRITE4)
> -				cus_ctl |= PLANE_CUS_PLANE_6;
> -			else
> -				MISSING_CASE(linked->id);
> -		}
> -
> -		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), cus_ctl);
> -	}
> +	if (icl_is_hdr_plane(dev_priv, plane_id))
> +		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), plane_state->cus_ctl);
>  
>  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>  		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
> @@ -627,7 +609,7 @@ skl_program_plane(struct intel_plane *plane,
>  	I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
>  		      intel_plane_ggtt_offset(plane_state) + surf_addr);
>  
> -	if (!slave && plane_state->scaler_id >= 0)
> +	if (plane_state->scaler_id >= 0)
>  		skl_program_scaler(plane, crtc_state, plane_state);
>  
>  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> @@ -640,24 +622,12 @@ skl_update_plane(struct intel_plane *plane,
>  {
>  	int color_plane = 0;
>  
> -	if (plane_state->planar_linked_plane) {
> -		/* Program the UV plane */
> +	if (plane_state->planar_linked_plane && !plane_state->planar_slave)
> +		/* Program the UV plane on planar master */
>  		color_plane = 1;
> -	}
> -
> -	skl_program_plane(plane, crtc_state, plane_state,
> -			  color_plane, false, plane_state->ctl);
> -}
>  
> -static void
> -icl_update_slave(struct intel_plane *plane,
> -		 const struct intel_crtc_state *crtc_state,
> -		 const struct intel_plane_state *plane_state)
> -{
> -	skl_program_plane(plane, crtc_state, plane_state, 0, true,
> -			  plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE);
> +	skl_program_plane(plane, crtc_state, plane_state, color_plane);
>  }
> -
>  static void
>  skl_disable_plane(struct intel_plane *plane,
>  		  const struct intel_crtc_state *crtc_state)
> @@ -1844,6 +1814,15 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
>  		plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
>  							     plane_state);
>  
> +	if (drm_format_info_is_yuv_semiplanar(fb->format) &&
> +	    icl_is_hdr_plane(dev_priv, plane->id))
> +		/* Enable and use MPEG-2 chroma siting */
> +		plane_state->cus_ctl = PLANE_CUS_ENABLE |
> +			PLANE_CUS_HPHASE_0 |
> +			PLANE_CUS_VPHASE_SIGN_NEGATIVE | PLANE_CUS_VPHASE_0_25;
> +	else
> +		plane_state->cus_ctl = 0;
> +
>  	return 0;
>  }
>  
> @@ -2512,8 +2491,6 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>  	plane->disable_plane = skl_disable_plane;
>  	plane->get_hw_state = skl_plane_get_hw_state;
>  	plane->check_plane = skl_plane_check;
> -	if (icl_is_nv12_y_plane(plane_id))
> -		plane->update_slave = icl_update_slave;
>  
>  	if (INTEL_GEN(dev_priv) >= 11)
>  		formats = icl_get_plane_formats(dev_priv, pipe,
> -- 
> 2.23.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH] drm/i915: Perform manual conversions for crtc uapi/hw split, v2.
  2019-10-18  8:13   ` [PATCH] drm/i915: Perform manual conversions for crtc uapi/hw split, v2 Maarten Lankhorst
@ 2019-10-22 18:16     ` Ville Syrjälä
  2019-10-24 12:12         ` [Intel-gfx] " Maarten Lankhorst
  0 siblings, 1 reply; 49+ messages in thread
From: Ville Syrjälä @ 2019-10-22 18:16 UTC (permalink / raw)
  To: Maarten Lankhorst; +Cc: intel-gfx

On Fri, Oct 18, 2019 at 10:13:23AM +0200, Maarten Lankhorst wrote:
> intel_get_load_detect_pipe() needs to set uapi active,
> uapi enable is set by the call to drm_atomic_set_mode_for_crtc(),
> so we can remove it.
> 
> intel_pipe_config_compare() needs to look at hw state, but I didn't
> change spatch to look at it. It's easy enough to do manually.
> 
> intel_atomic_check() definitely needs to check for uapi enable,
> otherwise intel_modeset_pipe_config cannot copy uapi state to hw.

We seem to have three totally separate things in this one patch.

> 
> Changes since v1:
> - Actually set uapi.active in get_load_detect_pipe().
> 
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 42 ++++++++++----------
>  1 file changed, 21 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index fa0abfdff2ae..bbac6b764d92 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11214,7 +11214,7 @@ int intel_get_load_detect_pipe(struct drm_connector *connector,
>  		goto fail;
>  	}
>  
> -	crtc_state->base.active = crtc_state->base.enable = true;
> +	crtc_state->uapi.active = true;
>  
>  	if (!mode)
>  		mode = &load_detect_mode;
> @@ -12754,19 +12754,19 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  
>  	PIPE_CONF_CHECK_X(output_types);
>  
> -	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
> -	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
> -	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
> -	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
> -	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
> -	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
> +	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> +	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> +	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> +	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> +	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> +	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
>  
> -	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
> -	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
> -	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
> -	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
> -	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
> -	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
> +	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> +	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> +	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> +	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> +	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> +	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
>  
>  	PIPE_CONF_CHECK_I(pixel_multiplier);
>  	PIPE_CONF_CHECK_I(output_format);
> @@ -12783,17 +12783,17 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  
>  	PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
>  
> -	PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
> +	PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
>  			      DRM_MODE_FLAG_INTERLACE);
>  
>  	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
> -		PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
> +		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
>  				      DRM_MODE_FLAG_PHSYNC);
> -		PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
> +		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
>  				      DRM_MODE_FLAG_NHSYNC);
> -		PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
> +		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
>  				      DRM_MODE_FLAG_PVSYNC);
> -		PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
> +		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
>  				      DRM_MODE_FLAG_NVSYNC);
>  	}
>  
> @@ -12832,7 +12832,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  
>  		bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
>  		if (bp_gamma)
> -			PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, base.gamma_lut, bp_gamma);
> +			PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
>  
>  	}
>  
> @@ -12877,7 +12877,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
>  		PIPE_CONF_CHECK_I(pipe_bpp);
>  
> -	PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
> +	PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
>  	PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
>  
>  	PIPE_CONF_CHECK_I(min_voltage_level);
> @@ -13572,7 +13572,7 @@ static int intel_atomic_check(struct drm_device *dev,
>  		if (!needs_modeset(new_crtc_state))
>  			continue;
>  
> -		if (!new_crtc_state->base.enable) {
> +		if (!new_crtc_state->uapi.enable) {
>  			any_ms = true;
>  			continue;
>  		}
> -- 
> 2.23.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH 07/14] drm/i915: Perform automated conversions for crtc uapi/hw split, base -> uapi.
  2019-10-17 13:20 ` [PATCH 07/14] drm/i915: Perform automated conversions for crtc uapi/hw split, base -> uapi Maarten Lankhorst
@ 2019-10-22 18:24   ` Ville Syrjälä
  0 siblings, 0 replies; 49+ messages in thread
From: Ville Syrjälä @ 2019-10-22 18:24 UTC (permalink / raw)
  To: Maarten Lankhorst; +Cc: intel-gfx

On Thu, Oct 17, 2019 at 03:20:58PM +0200, Maarten Lankhorst wrote:
> Split up crtc_state->base to uapi. This is done using the following patch,
> ran after the previous commit that splits out any hw references:
> 
> @@
> struct intel_crtc_state *T;
> @@
> -T->base
> +T->uapi
> 
> @@
> struct intel_crtc_state *T;
> identifier x =~ "^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
> @@
> -T->base.x
> +T->uapi.x
> 
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

Can't see any functional issues with this one. Slightly disgusting how
many places end up saying "uapi" when not actually dealing with uapi
stuff, but can't really do anyhting about that unless we want to start
playing super fragile tricks with unions.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c        |   6 +-
>  drivers/gpu/drm/i915/display/intel_atomic.c   |   8 +-
>  .../gpu/drm/i915/display/intel_atomic_plane.c |   6 +-
>  drivers/gpu/drm/i915/display/intel_audio.c    |   8 +-
>  drivers/gpu/drm/i915/display/intel_bw.c       |   4 +-
>  drivers/gpu/drm/i915/display/intel_cdclk.c    |  10 +-
>  drivers/gpu/drm/i915/display/intel_color.c    |  70 ++---
>  drivers/gpu/drm/i915/display/intel_crt.c      |   6 +-
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  32 +--
>  drivers/gpu/drm/i915/display/intel_display.c  | 241 +++++++++---------
>  drivers/gpu/drm/i915/display/intel_dp.c       |  20 +-
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   |   2 +-
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c |  14 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  20 +-
>  drivers/gpu/drm/i915/display/intel_dvo.c      |   2 +-
>  drivers/gpu/drm/i915/display/intel_hdmi.c     |  44 ++--
>  drivers/gpu/drm/i915/display/intel_lvds.c     |   4 +-
>  drivers/gpu/drm/i915/display/intel_panel.c    |   6 +-
>  drivers/gpu/drm/i915/display/intel_pipe_crc.c |   4 +-
>  drivers/gpu/drm/i915/display/intel_psr.c      |   6 +-
>  drivers/gpu/drm/i915/display/intel_sdvo.c     |   6 +-
>  drivers/gpu/drm/i915/display/intel_sprite.c   |  17 +-
>  drivers/gpu/drm/i915/display/intel_tv.c       |   4 +-
>  drivers/gpu/drm/i915/display/intel_vdsc.c     |   8 +-
>  drivers/gpu/drm/i915/display/vlv_dsi.c        |  10 +-
>  drivers/gpu/drm/i915/i915_debugfs.c           |   6 +-
>  drivers/gpu/drm/i915/intel_pm.c               | 112 ++++----
>  27 files changed, 339 insertions(+), 337 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 4ec493e4755b..0e24b8e257e5 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -625,7 +625,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	enum pipe pipe = intel_crtc->pipe;
>  	u32 tmp;
>  	enum port port;
> @@ -1242,7 +1242,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
>  				 struct intel_crtc_state *pipe_config)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  
>  	/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
> @@ -1265,7 +1265,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
>  	struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
>  						   base);
>  	struct intel_connector *intel_connector = intel_dsi->attached_connector;
> -	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	const struct drm_display_mode *fixed_mode =
>  					intel_connector->panel.fixed_mode;
>  	struct drm_display_mode *adjusted_mode =
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 2cdc92897abd..7cf13b9c7d38 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -193,7 +193,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
>  	if (!crtc_state)
>  		return NULL;
>  
> -	__drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->base);
> +	__drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);
>  
>  	crtc_state->update_pipe = false;
>  	crtc_state->disable_lp_wm = false;
> @@ -205,7 +205,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
>  	crtc_state->fb_bits = 0;
>  	crtc_state->update_planes = 0;
>  
> -	return &crtc_state->base;
> +	return &crtc_state->uapi;
>  }
>  
>  /**
> @@ -222,7 +222,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
>  {
>  	struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
>  
> -	__drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
> +	__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
>  	kfree(crtc_state);
>  }
>  
> @@ -319,7 +319,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>  {
>  	struct intel_crtc_scaler_state *scaler_state =
>  		&crtc_state->scaler_state;
> -	struct drm_atomic_state *drm_state = crtc_state->base.state;
> +	struct drm_atomic_state *drm_state = crtc_state->uapi.state;
>  	struct intel_atomic_state *state = to_intel_atomic_state(drm_state);
>  	int num_scalers_need;
>  	int i;
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 847f9c4ecbbd..d92c185d4b4a 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -268,7 +268,7 @@ void intel_update_plane(struct intel_plane *plane,
>  			const struct intel_crtc_state *crtc_state,
>  			const struct intel_plane_state *plane_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  
>  	trace_intel_update_plane(&plane->base, crtc);
>  	plane->update_plane(plane, crtc_state, plane_state);
> @@ -278,7 +278,7 @@ void intel_update_slave(struct intel_plane *plane,
>  			const struct intel_crtc_state *crtc_state,
>  			const struct intel_plane_state *plane_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  
>  	trace_intel_update_plane(&plane->base, crtc);
>  	plane->update_slave(plane, crtc_state, plane_state);
> @@ -287,7 +287,7 @@ void intel_update_slave(struct intel_plane *plane,
>  void intel_disable_plane(struct intel_plane *plane,
>  			 const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  
>  	trace_intel_disable_plane(&plane->base, crtc);
>  	plane->disable_plane(plane, crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index 6a58e8ad86f8..5680eed9c71f 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -554,7 +554,7 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder,
>  				    const struct drm_connector_state *old_conn_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>  	enum pipe pipe = crtc->pipe;
>  	enum port port = encoder->port;
>  	u32 tmp, eldv;
> @@ -601,7 +601,7 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder,
>  				   const struct drm_connector_state *conn_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_connector *connector = conn_state->connector;
>  	enum pipe pipe = crtc->pipe;
>  	enum port port = encoder->port;
> @@ -691,7 +691,7 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct i915_audio_component *acomp = dev_priv->audio_component;
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_connector *connector = conn_state->connector;
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
> @@ -752,7 +752,7 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct i915_audio_component *acomp = dev_priv->audio_component;
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>  	enum port port = encoder->port;
>  	enum pipe pipe = crtc->pipe;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 22e83f857de8..3f6e29f61323 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -297,7 +297,7 @@ static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_stat
>  
>  static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	unsigned int data_rate = 0;
>  	enum plane_id plane_id;
>  
> @@ -318,7 +318,7 @@ static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_
>  void intel_bw_crtc_update(struct intel_bw_state *bw_state,
>  			  const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  
>  	bw_state->data_rate[crtc->pipe] =
>  		intel_bw_crtc_data_rate(crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index fd1ed0fb8748..931f19dbd4dd 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1902,7 +1902,7 @@ intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv,
>  
>  static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	int pixel_rate = crtc_state->pixel_rate;
>  
>  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> @@ -1921,7 +1921,7 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
>  int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv =
> -		to_i915(crtc_state->base.crtc->dev);
> +		to_i915(crtc_state->uapi.crtc->dev);
>  	int min_cdclk;
>  
>  	if (!crtc_state->hw.enable)
> @@ -2261,10 +2261,10 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
>  			return PTR_ERR(crtc_state);
>  
>  		if (!crtc_state->hw.active ||
> -		    drm_atomic_crtc_needs_modeset(&crtc_state->base))
> +		    drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
>  			continue;
>  
> -		crtc_state->base.mode_changed = true;
> +		crtc_state->uapi.mode_changed = true;
>  
>  		ret = drm_atomic_add_affected_connectors(&state->base,
>  							 &crtc->base);
> @@ -2330,7 +2330,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
>  		crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
>  		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
>  		if (crtc_state &&
> -		    drm_atomic_crtc_needs_modeset(&crtc_state->base))
> +		    drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
>  			pipe = INVALID_PIPE;
>  	} else {
>  		pipe = INVALID_PIPE;
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 65e1b18bd7e3..52712bb9ed15 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -205,7 +205,7 @@ static void icl_update_output_csc(struct intel_crtc *crtc,
>  
>  static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
>  	/*
>  	 * FIXME if there's a gamma LUT after the CSC, we should
> @@ -270,7 +270,7 @@ static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
>  
>  static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	bool limited_color_range = ilk_csc_limited_range(crtc_state);
>  
> @@ -309,7 +309,7 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
>  
>  static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>  	if (crtc_state->hw.ctm) {
> @@ -338,7 +338,7 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
>   */
>  static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  
> @@ -404,7 +404,7 @@ static u32 ilk_lut_10(const struct drm_color_lut *color)
>  static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
>  				    const struct drm_property_blob *blob)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  	int i;
> @@ -440,7 +440,7 @@ static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
>  
>  static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  	u32 val;
> @@ -453,7 +453,7 @@ static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
>  
>  static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  	u32 val;
> @@ -468,7 +468,7 @@ static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
>  
>  static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>  	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
> @@ -478,7 +478,7 @@ static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
>  
>  static void skl_color_commit(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  	u32 val = 0;
> @@ -524,7 +524,7 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc,
>  
>  static void i965_load_luts(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
>  
>  	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> @@ -547,7 +547,7 @@ static void ilk_load_lut_10(struct intel_crtc *crtc,
>  
>  static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
>  
>  	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> @@ -654,7 +654,7 @@ static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
>  
>  static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
>  	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
>  
> @@ -677,7 +677,7 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
>  
>  static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
>  	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
>  
> @@ -700,7 +700,7 @@ static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
>  
>  static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  	const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> @@ -739,7 +739,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
>  
>  static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  	const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> @@ -767,7 +767,7 @@ static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_stat
>  static void glk_load_luts(const struct intel_crtc_state *crtc_state)
>  {
>  	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  
>  	/*
>  	 * On GLK+ both pipe CSC and degamma LUT are controlled
> @@ -808,7 +808,7 @@ static void
>  icl_load_gcmax(const struct intel_crtc_state *crtc_state,
>  	       const struct drm_color_lut *color)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct intel_dsb *dsb = intel_dsb_get(crtc);
>  	enum pipe pipe = crtc->pipe;
>  
> @@ -822,7 +822,7 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
>  static void
>  icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
>  	const struct drm_color_lut *lut = blob->data;
>  	struct intel_dsb *dsb = intel_dsb_get(crtc);
> @@ -854,7 +854,7 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
>  static void
>  icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
>  	const struct drm_color_lut *lut = blob->data;
>  	const struct drm_color_lut *entry;
> @@ -911,7 +911,7 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
>  static void icl_load_luts(const struct intel_crtc_state *crtc_state)
>  {
>  	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct intel_dsb *dsb = intel_dsb_get(crtc);
>  
>  	if (crtc_state->hw.degamma_lut)
> @@ -990,7 +990,7 @@ static void chv_load_cgm_gamma(struct intel_crtc *crtc,
>  
>  static void chv_load_luts(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
>  	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
>  
> @@ -1010,28 +1010,28 @@ static void chv_load_luts(const struct intel_crtc_state *crtc_state)
>  
>  void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
>  	dev_priv->display.load_luts(crtc_state);
>  }
>  
>  void intel_color_commit(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
>  	dev_priv->display.color_commit(crtc_state);
>  }
>  
>  int intel_color_check(struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
>  	return dev_priv->display.color_check(crtc_state);
>  }
>  
>  void intel_color_get_config(struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
>  	if (dev_priv->display.read_luts)
>  		dev_priv->display.read_luts(crtc_state);
> @@ -1055,16 +1055,16 @@ static bool need_plane_update(struct intel_plane *plane,
>  static int
>  intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_atomic_state *state =
> -		to_intel_atomic_state(new_crtc_state->base.state);
> +		to_intel_atomic_state(new_crtc_state->uapi.state);
>  	const struct intel_crtc_state *old_crtc_state =
>  		intel_atomic_get_old_crtc_state(state, crtc);
>  	struct intel_plane *plane;
>  
>  	if (!new_crtc_state->hw.active ||
> -	    drm_atomic_crtc_needs_modeset(&new_crtc_state->base))
> +	    drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
>  		return 0;
>  
>  	if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
> @@ -1107,7 +1107,7 @@ static int check_lut_size(const struct drm_property_blob *lut, int expected)
>  
>  static int check_luts(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
>  	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
>  	int gamma_length, degamma_length;
> @@ -1480,7 +1480,7 @@ static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
>  
>  int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>  	if (HAS_GMCH(dev_priv)) {
> @@ -1586,7 +1586,7 @@ static u32 intel_color_lut_pack(u32 val, u32 bit_precision)
>  static struct drm_property_blob *
>  i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  	struct drm_property_blob *blob;
> @@ -1629,7 +1629,7 @@ static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
>  static struct drm_property_blob *
>  i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>  	enum pipe pipe = crtc->pipe;
> @@ -1681,7 +1681,7 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
>  static struct drm_property_blob *
>  chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>  	enum pipe pipe = crtc->pipe;
> @@ -1723,7 +1723,7 @@ static void chv_read_luts(struct intel_crtc_state *crtc_state)
>  static struct drm_property_blob *
>  ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>  	enum pipe pipe = crtc->pipe;
> @@ -1770,7 +1770,7 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
>  static struct drm_property_blob *
>  glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	int hw_lut_size = ivb_lut_10_size(prec_index);
>  	enum pipe pipe = crtc->pipe;
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index 399abc3d521e..164af1936d38 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -161,7 +161,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_crt *crt = intel_encoder_to_crt(encoder);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>  	u32 adpa;
>  
> @@ -271,7 +271,7 @@ static void hsw_pre_enable_crt(struct intel_encoder *encoder,
>  			       const struct drm_connector_state *conn_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum pipe pipe = crtc->pipe;
>  
>  	WARN_ON(!crtc_state->has_pch_encoder);
> @@ -288,7 +288,7 @@ static void hsw_enable_crt(struct intel_encoder *encoder,
>  			   const struct drm_connector_state *conn_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum pipe pipe = crtc->pipe;
>  
>  	WARN_ON(!crtc_state->has_pch_encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c8639b92a6da..1b9f68d4c566 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1744,7 +1744,7 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
>  void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
>  			  const struct drm_connector_state *conn_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	u32 temp;
> @@ -1806,7 +1806,7 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
>  void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
>  				    bool state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	u32 temp;
> @@ -1828,7 +1828,7 @@ void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
>  static u32
>  intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
> @@ -1915,7 +1915,7 @@ intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
>  
>  void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	u32 temp;
> @@ -1931,7 +1931,7 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
>  static void
>  intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	u32 temp;
> @@ -1943,7 +1943,7 @@ intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
>  
>  void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
> @@ -2241,7 +2241,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
>  
>  void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
>  	enum port port = encoder->port;
> @@ -2259,7 +2259,7 @@ void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
>  
>  void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  
>  	if (cpu_transcoder != TRANSCODER_EDP) {
> @@ -3337,7 +3337,7 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
>  static void
>  tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
>  	u32 val;
>  
>  	if (!cstate->dc3co_exitline)
> @@ -3352,7 +3352,7 @@ static void
>  tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
>  {
>  	u32 val, exit_scanlines;
> -	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
>  
>  	if (!cstate->dc3co_exitline)
>  		return;
> @@ -3370,7 +3370,7 @@ static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
>  					      struct intel_crtc_state *cstate)
>  {
>  	u32 exit_scanlines;
> -	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
>  	u32 crtc_vdisplay = cstate->hw.adjusted_mode.crtc_vdisplay;
>  
>  	cstate->dc3co_exitline = 0;
> @@ -3379,7 +3379,7 @@ static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
>  		return;
>  
>  	/* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
> -	if (to_intel_crtc(cstate->base.crtc)->pipe != PIPE_A ||
> +	if (to_intel_crtc(cstate->uapi.crtc)->pipe != PIPE_A ||
>  	    encoder->port != PORT_A)
>  		return;
>  
> @@ -3403,7 +3403,7 @@ static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
>  static void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state)
>  {
>  	u32 val;
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
>  	if (INTEL_GEN(dev_priv) < 12)
>  		return;
> @@ -3649,7 +3649,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *encoder,
>  				 const struct intel_crtc_state *crtc_state,
>  				 const struct drm_connector_state *conn_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  
> @@ -4206,7 +4206,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>  			  struct intel_crtc_state *pipe_config)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
>  	u32 temp, flags = 0;
>  
> @@ -4373,7 +4373,7 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder,
>  				    struct intel_crtc_state *pipe_config,
>  				    struct drm_connector_state *conn_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = encoder->port;
>  	int ret;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 3106aaf55f17..06c593d56d92 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -516,7 +516,7 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
>  static bool
>  needs_modeset(const struct intel_crtc_state *state)
>  {
> -	return drm_atomic_crtc_needs_modeset(&state->base);
> +	return drm_atomic_crtc_needs_modeset(&state->uapi);
>  }
>  
>  /*
> @@ -630,7 +630,7 @@ i9xx_select_p2_div(const struct intel_limit *limit,
>  		   const struct intel_crtc_state *crtc_state,
>  		   int target)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
>  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
>  		/*
> @@ -666,7 +666,7 @@ i9xx_find_best_dpll(const struct intel_limit *limit,
>  		    int target, int refclk, struct dpll *match_clock,
>  		    struct dpll *best_clock)
>  {
> -	struct drm_device *dev = crtc_state->base.crtc->dev;
> +	struct drm_device *dev = crtc_state->uapi.crtc->dev;
>  	struct dpll clock;
>  	int err = target;
>  
> @@ -724,7 +724,7 @@ pnv_find_best_dpll(const struct intel_limit *limit,
>  		   int target, int refclk, struct dpll *match_clock,
>  		   struct dpll *best_clock)
>  {
> -	struct drm_device *dev = crtc_state->base.crtc->dev;
> +	struct drm_device *dev = crtc_state->uapi.crtc->dev;
>  	struct dpll clock;
>  	int err = target;
>  
> @@ -780,7 +780,7 @@ g4x_find_best_dpll(const struct intel_limit *limit,
>  		   int target, int refclk, struct dpll *match_clock,
>  		   struct dpll *best_clock)
>  {
> -	struct drm_device *dev = crtc_state->base.crtc->dev;
> +	struct drm_device *dev = crtc_state->uapi.crtc->dev;
>  	struct dpll clock;
>  	int max_n;
>  	bool found = false;
> @@ -874,7 +874,7 @@ vlv_find_best_dpll(const struct intel_limit *limit,
>  		   int target, int refclk, struct dpll *match_clock,
>  		   struct dpll *best_clock)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_device *dev = crtc->base.dev;
>  	struct dpll clock;
>  	unsigned int bestppm = 1000000;
> @@ -934,7 +934,7 @@ chv_find_best_dpll(const struct intel_limit *limit,
>  		   int target, int refclk, struct dpll *match_clock,
>  		   struct dpll *best_clock)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_device *dev = crtc->base.dev;
>  	unsigned int best_error_ppm;
>  	struct dpll clock;
> @@ -1067,7 +1067,7 @@ static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
>  static void
>  intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>  	if (INTEL_GEN(dev_priv) >= 4) {
> @@ -1526,7 +1526,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc,
>  
>  static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  
> @@ -1617,7 +1617,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
>  
>  static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  	i915_reg_t reg;
> @@ -1761,7 +1761,7 @@ enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
>  
>  static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
>  	/*
>  	 * On i965gm the hardware frame counter reads
> @@ -1781,7 +1781,7 @@ static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state
>  
>  static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  
>  	drm_crtc_set_max_vblank_count(&crtc->base,
>  				      intel_crtc_max_vblank_count(crtc_state));
> @@ -1790,7 +1790,7 @@ static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
>  
>  static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
>  	enum pipe pipe = crtc->pipe;
> @@ -1848,7 +1848,7 @@ static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
>  
>  static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
>  	enum pipe pipe = crtc->pipe;
> @@ -3103,14 +3103,14 @@ intel_set_plane_visible(struct intel_crtc_state *crtc_state,
>  	plane_state->base.visible = visible;
>  
>  	if (visible)
> -		crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);
> +		crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
>  	else
> -		crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);
> +		crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
>  }
>  
>  static void fixup_active_planes(struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	struct drm_plane *plane;
>  
>  	/*
> @@ -3121,7 +3121,7 @@ static void fixup_active_planes(struct intel_crtc_state *crtc_state)
>  	crtc_state->active_planes = 0;
>  
>  	drm_for_each_plane_mask(plane, &dev_priv->drm,
> -				crtc_state->base.plane_mask)
> +				crtc_state->uapi.plane_mask)
>  		crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
>  }
>  
> @@ -3592,7 +3592,7 @@ i9xx_plane_max_stride(struct intel_plane *plane,
>  
>  static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	u32 dspcntr = 0;
>  
> @@ -3745,7 +3745,7 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
>  		return ret;
>  
>  	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> -						  &crtc_state->base,
> +						  &crtc_state->uapi,
>  						  DRM_PLANE_HELPER_NO_SCALING,
>  						  DRM_PLANE_HELPER_NO_SCALING,
>  						  i9xx_plane_has_windowing(plane),
> @@ -3921,7 +3921,7 @@ static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
>   */
>  static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	const struct intel_crtc_scaler_state *scaler_state =
>  		&crtc_state->scaler_state;
>  	int i;
> @@ -4116,7 +4116,7 @@ static u32 cnl_plane_ctl_flip(unsigned int reflect)
>  
>  u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	u32 plane_ctl = 0;
>  
>  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> @@ -4172,7 +4172,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>  
>  u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	u32 plane_color_ctl = 0;
>  
>  	if (INTEL_GEN(dev_priv) >= 11)
> @@ -4788,7 +4788,7 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
>  
>  static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
>  	enum pipe pipe = intel_crtc->pipe;
>  	i915_reg_t reg;
> @@ -4949,7 +4949,7 @@ void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
>  /* Program iCLKIP clock to the desired frequency */
>  static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
>  	u32 divsel, phaseinc, auxdiv, phasedir = 0;
> @@ -5065,7 +5065,7 @@ int lpt_get_iclkip(struct drm_i915_private *dev_priv)
>  static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
>  						enum pipe pch_transcoder)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  
> @@ -5108,7 +5108,7 @@ static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool e
>  
>  static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>  	switch (crtc->pipe) {
> @@ -5138,7 +5138,7 @@ static struct intel_encoder *
>  intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
>  			   const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	const struct drm_connector_state *connector_state;
>  	const struct drm_connector *connector;
>  	struct intel_encoder *encoder = NULL;
> @@ -5170,7 +5170,7 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
>  static void ironlake_pch_enable(const struct intel_atomic_state *state,
>  				const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	enum pipe pipe = crtc->pipe;
> @@ -5254,7 +5254,7 @@ static void ironlake_pch_enable(const struct intel_atomic_state *state,
>  static void lpt_pch_enable(const struct intel_atomic_state *state,
>  			   const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  
> @@ -5371,7 +5371,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>  	struct intel_crtc_scaler_state *scaler_state =
>  		&crtc_state->scaler_state;
>  	struct intel_crtc *intel_crtc =
> -		to_intel_crtc(crtc_state->base.crtc);
> +		to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
> @@ -5568,7 +5568,7 @@ static void skylake_scaler_disable(struct intel_crtc *crtc)
>  
>  static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  	const struct intel_crtc_scaler_state *scaler_state =
> @@ -5605,7 +5605,7 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
>  
>  static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  
> @@ -5626,7 +5626,7 @@ static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
>  
>  void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
> @@ -5662,7 +5662,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
>  
>  void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
> @@ -5767,7 +5767,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
>  static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
>  				       const struct intel_crtc_state *new_crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>  	if (!old_crtc_state->ips_enabled)
> @@ -5783,7 +5783,7 @@ static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_s
>  	 * Disable IPS before we program the LUT.
>  	 */
>  	if (IS_HASWELL(dev_priv) &&
> -	    (new_crtc_state->base.color_mgmt_changed ||
> +	    (new_crtc_state->uapi.color_mgmt_changed ||
>  	     new_crtc_state->update_pipe) &&
>  	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
>  		return true;
> @@ -5794,7 +5794,7 @@ static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_s
>  static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
>  				       const struct intel_crtc_state *new_crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>  	if (!new_crtc_state->ips_enabled)
> @@ -5810,7 +5810,7 @@ static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_s
>  	 * Re-enable IPS after the LUT has been programmed.
>  	 */
>  	if (IS_HASWELL(dev_priv) &&
> -	    (new_crtc_state->base.color_mgmt_changed ||
> +	    (new_crtc_state->uapi.color_mgmt_changed ||
>  	     new_crtc_state->update_pipe) &&
>  	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
>  		return true;
> @@ -5851,10 +5851,10 @@ static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv,
>  
>  static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct drm_atomic_state *state = old_crtc_state->base.state;
> +	struct drm_atomic_state *state = old_crtc_state->uapi.state;
>  	struct intel_crtc_state *pipe_config =
>  		intel_atomic_get_new_crtc_state(to_intel_atomic_state(state),
>  						crtc);
> @@ -5894,10 +5894,10 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
>  static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
>  				   struct intel_crtc_state *pipe_config)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct drm_atomic_state *state = old_crtc_state->base.state;
> +	struct drm_atomic_state *state = old_crtc_state->uapi.state;
>  	struct drm_plane *primary = crtc->base.primary;
>  	struct drm_plane_state *old_primary_state =
>  		drm_atomic_get_old_plane_state(state, primary);
> @@ -6249,7 +6249,7 @@ static void intel_encoders_update_pipe(struct intel_crtc *crtc,
>  
>  static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
>  
>  	plane->disable_plane(plane, crtc_state);
> @@ -6258,7 +6258,7 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
>  static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
>  				 struct intel_atomic_state *state)
>  {
> -	struct drm_crtc *crtc = pipe_config->base.crtc;
> +	struct drm_crtc *crtc = pipe_config->uapi.crtc;
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -6392,7 +6392,7 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
>  static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>  				struct intel_atomic_state *state)
>  {
> -	struct drm_crtc *crtc = pipe_config->base.crtc;
> +	struct drm_crtc *crtc = pipe_config->uapi.crtc;
>  	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	enum pipe pipe = intel_crtc->pipe, hsw_workaround_pipe;
> @@ -6500,7 +6500,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>  
>  static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  
> @@ -6516,7 +6516,7 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
>  static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
>  				  struct intel_atomic_state *state)
>  {
> -	struct drm_crtc *crtc = old_crtc_state->base.crtc;
> +	struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -6575,7 +6575,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
>  static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
>  				 struct intel_atomic_state *state)
>  {
> -	struct drm_crtc *crtc = old_crtc_state->base.crtc;
> +	struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
>  	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> @@ -6609,7 +6609,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
>  
>  static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>  	if (!crtc_state->gmch_pfit.control)
> @@ -6745,7 +6745,7 @@ intel_aux_power_domain(struct intel_digital_port *dig_port)
>  
>  static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct drm_encoder *encoder;
>  	enum pipe pipe = crtc->pipe;
> @@ -6762,7 +6762,7 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
>  		mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
>  
>  	drm_for_each_encoder_mask(encoder, &dev_priv->drm,
> -				  crtc_state->base.encoder_mask) {
> +				  crtc_state->uapi.encoder_mask) {
>  		struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
>  
>  		mask |= BIT_ULL(intel_encoder->power_domain);
> @@ -6780,7 +6780,7 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
>  static u64
>  modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum intel_display_power_domain domain;
>  	u64 domains, new_domains, old_domains;
> @@ -6809,7 +6809,7 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
>  static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>  				   struct intel_atomic_state *state)
>  {
> -	struct drm_crtc *crtc = pipe_config->base.crtc;
> +	struct drm_crtc *crtc = pipe_config->uapi.crtc;
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -6865,7 +6865,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>  
>  static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>  	I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
> @@ -6875,7 +6875,7 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
>  static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
>  			     struct intel_atomic_state *state)
>  {
> -	struct drm_crtc *crtc = pipe_config->base.crtc;
> +	struct drm_crtc *crtc = pipe_config->uapi.crtc;
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -6925,7 +6925,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
>  
>  static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>  	if (!old_crtc_state->gmch_pfit.control)
> @@ -6941,7 +6941,7 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
>  static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
>  			      struct intel_atomic_state *state)
>  {
> -	struct drm_crtc *crtc = old_crtc_state->base.crtc;
> +	struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -7140,7 +7140,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
>  				     struct intel_crtc_state *pipe_config)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct drm_atomic_state *state = pipe_config->base.state;
> +	struct drm_atomic_state *state = pipe_config->uapi.state;
>  	struct intel_crtc *other_crtc;
>  	struct intel_crtc_state *other_crtc_state;
>  
> @@ -7259,7 +7259,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
>  
>  bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>  	/* IPS only exists on ULT machines and is tied to pipe A. */
> @@ -7289,9 +7289,9 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
>  static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv =
> -		to_i915(crtc_state->base.crtc->dev);
> +		to_i915(crtc_state->uapi.crtc->dev);
>  	struct intel_atomic_state *intel_state =
> -		to_intel_atomic_state(crtc_state->base.state);
> +		to_intel_atomic_state(crtc_state->uapi.state);
>  
>  	if (!hsw_crtc_state_ips_capable(crtc_state))
>  		return false;
> @@ -7363,7 +7363,7 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
>  
>  static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
>  	if (HAS_GMCH(dev_priv))
>  		/* FIXME calculate proper pipe pixel rate for GMCH pfit */
> @@ -7598,7 +7598,7 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
>  static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
>  					 const struct intel_link_m_n *m_n)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  
> @@ -7625,7 +7625,7 @@ static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta
>  					 const struct intel_link_m_n *m_n,
>  					 const struct intel_link_m_n *m2_n2)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  	enum transcoder transcoder = crtc_state->cpu_transcoder;
> @@ -7938,7 +7938,7 @@ int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
>  	if (!pipe_config)
>  		return -ENOMEM;
>  
> -	pipe_config->base.crtc = &crtc->base;
> +	pipe_config->uapi.crtc = &crtc->base;
>  	pipe_config->pixel_multiplier = 1;
>  	pipe_config->dpll = *dpll;
>  
> @@ -8098,7 +8098,7 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
>  
>  static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> @@ -8160,7 +8160,7 @@ static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
>  
>  static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  
> @@ -8174,7 +8174,7 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
>  
>  static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  
>  	if (IS_GEN(dev_priv, 2))
> @@ -8272,7 +8272,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
>  
>  static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	u32 pipeconf;
>  
> @@ -8718,7 +8718,7 @@ bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
>  
>  static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> @@ -9356,7 +9356,7 @@ void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
>  
>  static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  	u32 val;
> @@ -9410,7 +9410,7 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
>  
>  static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	u32 val = 0;
> @@ -9433,7 +9433,7 @@ static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
>  
>  static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	u32 val = 0;
>  
> @@ -9619,7 +9619,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_atomic_state *state =
> -		to_intel_atomic_state(crtc_state->base.state);
> +		to_intel_atomic_state(crtc_state->uapi.state);
>  	const struct intel_limit *limit;
>  	int refclk = 120000;
>  
> @@ -10044,7 +10044,7 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_atomic_state *state =
> -		to_intel_atomic_state(crtc_state->base.state);
> +		to_intel_atomic_state(crtc_state->uapi.state);
>  
>  	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
>  	    INTEL_GEN(dev_priv) >= 11) {
> @@ -10615,7 +10615,7 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
>  	}
>  
>  	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> -						  &crtc_state->base,
> +						  &crtc_state->uapi,
>  						  DRM_PLANE_HELPER_NO_SCALING,
>  						  DRM_PLANE_HELPER_NO_SCALING,
>  						  true, true);
> @@ -10802,7 +10802,7 @@ i9xx_cursor_max_stride(struct intel_plane *plane,
>  
>  static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	u32 cntl = 0;
>  
> @@ -11219,7 +11219,7 @@ int intel_get_load_detect_pipe(struct drm_connector *connector,
>  	if (!mode)
>  		mode = &load_detect_mode;
>  
> -	ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
> +	ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, mode);
>  	if (ret)
>  		goto fail;
>  
> @@ -11457,7 +11457,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
>  		return NULL;
>  	}
>  
> -	crtc_state->base.crtc = &crtc->base;
> +	crtc_state->uapi.crtc = &crtc->base;
>  
>  	if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
>  		kfree(crtc_state);
> @@ -11528,7 +11528,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
>  				    const struct intel_plane_state *old_plane_state,
>  				    struct intel_plane_state *plane_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	bool mode_changed = needs_modeset(crtc_state);
> @@ -11700,9 +11700,9 @@ static int icl_add_linked_planes(struct intel_atomic_state *state)
>  
>  static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->base.state);
> +	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
>  	struct intel_plane *plane, *linked;
>  	struct intel_plane_state *plane_state;
>  	int i;
> @@ -11772,9 +11772,9 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
>  
>  static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
>  	struct intel_atomic_state *state =
> -		to_intel_atomic_state(new_crtc_state->base.state);
> +		to_intel_atomic_state(new_crtc_state->uapi.state);
>  	const struct intel_crtc_state *old_crtc_state =
>  		intel_atomic_get_old_crtc_state(state, crtc);
>  
> @@ -11807,10 +11807,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>  	 * when C8 planes are getting enabled/disabled.
>  	 */
>  	if (c8_planes_changed(crtc_state))
> -		crtc_state->base.color_mgmt_changed = true;
> +		crtc_state->uapi.color_mgmt_changed = true;
>  
>  	if (mode_changed || crtc_state->update_pipe ||
> -	    crtc_state->base.color_mgmt_changed) {
> +	    crtc_state->uapi.color_mgmt_changed) {
>  		ret = intel_color_check(crtc_state);
>  		if (ret)
>  			return ret;
> @@ -11928,7 +11928,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
>  			  struct intel_crtc_state *pipe_config)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	struct drm_atomic_state *state = pipe_config->base.state;
> +	struct drm_atomic_state *state = pipe_config->uapi.state;
>  	struct drm_connector *connector;
>  	struct drm_connector_state *connector_state;
>  	int bpp, i;
> @@ -12081,7 +12081,7 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
>  				   struct intel_atomic_state *state,
>  				   const char *context)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	const struct intel_plane_state *plane_state;
>  	struct intel_plane *plane;
> @@ -12258,7 +12258,7 @@ static int
>  clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv =
> -		to_i915(crtc_state->base.crtc->dev);
> +		to_i915(crtc_state->uapi.crtc->dev);
>  	struct intel_crtc_state *saved_state;
>  
>  	saved_state = kzalloc(sizeof(*saved_state), GFP_KERNEL);
> @@ -12284,8 +12284,8 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
>  	BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
>  	BUILD_BUG_ON(offsetof(struct intel_crtc_state, uapi));
>  	BUILD_BUG_ON(offsetof(struct intel_crtc_state, hw));
> -	memcpy(&crtc_state->base + 1, &saved_state->base + 1,
> -	       sizeof(*crtc_state) - sizeof(crtc_state->base));
> +	memcpy(&crtc_state->uapi + 1, &saved_state->uapi + 1,
> +	       sizeof(*crtc_state) - sizeof(crtc_state->uapi));
>  
>  	kfree(saved_state);
>  	return 0;
> @@ -12294,8 +12294,8 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
>  static int
>  intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
>  {
> -	struct drm_crtc *crtc = pipe_config->base.crtc;
> -	struct drm_atomic_state *state = pipe_config->base.state;
> +	struct drm_crtc *crtc = pipe_config->uapi.crtc;
> +	struct drm_atomic_state *state = pipe_config->uapi.state;
>  	struct intel_encoder *encoder;
>  	struct drm_connector *connector;
>  	struct drm_connector_state *connector_state;
> @@ -12560,7 +12560,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  			  const struct intel_crtc_state *pipe_config,
>  			  bool fastset)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(current_config->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
>  	bool ret = true;
>  	u32 bp_gamma = 0;
>  	bool fixup_inherited = fastset &&
> @@ -13108,12 +13108,12 @@ verify_crtc_state(struct intel_crtc *crtc,
>  	struct drm_atomic_state *state;
>  	bool active;
>  
> -	state = old_crtc_state->base.state;
> -	__drm_atomic_helper_crtc_destroy_state(&old_crtc_state->base);
> +	state = old_crtc_state->uapi.state;
> +	__drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
>  	pipe_config = old_crtc_state;
>  	memset(pipe_config, 0, sizeof(*pipe_config));
> -	pipe_config->base.crtc = &crtc->base;
> -	pipe_config->base.state = state;
> +	pipe_config->uapi.crtc = &crtc->base;
> +	pipe_config->uapi.state = state;
>  
>  	DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.base.id, crtc->base.name);
>  
> @@ -13293,7 +13293,7 @@ intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
>  static void
>  intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
> @@ -13490,7 +13490,7 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
>  	if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
>  		return;
>  
> -	new_crtc_state->base.mode_changed = false;
> +	new_crtc_state->uapi.mode_changed = false;
>  	new_crtc_state->update_pipe = true;
>  
>  	/*
> @@ -13563,7 +13563,7 @@ static int intel_atomic_check(struct drm_device *dev,
>  					    new_crtc_state, i) {
>  		if (new_crtc_state->hw.mode.private_flags !=
>  		    old_crtc_state->hw.mode.private_flags)
> -			new_crtc_state->base.mode_changed = true;
> +			new_crtc_state->uapi.mode_changed = true;
>  	}
>  
>  	ret = drm_atomic_helper_check_modeset(dev, &state->base);
> @@ -13687,7 +13687,7 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
>  static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
>  			       const struct intel_crtc_state *new_crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>  	/* drm_atomic_helper_update_legacy_modeset_state might not be called. */
> @@ -13732,7 +13732,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
>  	 * CRTC was enabled.
>  	 */
>  	if (!modeset) {
> -		if (new_crtc_state->base.color_mgmt_changed ||
> +		if (new_crtc_state->uapi.color_mgmt_changed ||
>  		    new_crtc_state->update_pipe)
>  			intel_color_commit(new_crtc_state);
>  
> @@ -13938,7 +13938,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
>  			 */
>  			if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
>  						 &old_crtc_state->wm.skl.ddb) &&
> -			    !new_crtc_state->base.active_changed &&
> +			    !new_crtc_state->uapi.active_changed &&
>  			    state->wm_results.dirty_pipes != updated)
>  				vbl_wait = true;
>  
> @@ -14071,12 +14071,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  		bool modeset = needs_modeset(new_crtc_state);
>  
>  		/* Complete events for now disable pipes here. */
> -		if (modeset && !new_crtc_state->hw.active && new_crtc_state->base.event) {
> +		if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
>  			spin_lock_irq(&dev->event_lock);
> -			drm_crtc_send_vblank_event(&crtc->base, new_crtc_state->base.event);
> +			drm_crtc_send_vblank_event(&crtc->base,
> +						   new_crtc_state->uapi.event);
>  			spin_unlock_irq(&dev->event_lock);
>  
> -			new_crtc_state->base.event = NULL;
> +			new_crtc_state->uapi.event = NULL;
>  		}
>  	}
>  
> @@ -14109,7 +14110,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>  		if (new_crtc_state->hw.active &&
>  		    !needs_modeset(new_crtc_state) &&
> -		    (new_crtc_state->base.color_mgmt_changed ||
> +		    (new_crtc_state->uapi.color_mgmt_changed ||
>  		     new_crtc_state->update_pipe))
>  			intel_color_load_luts(new_crtc_state);
>  	}
> @@ -14557,7 +14558,7 @@ int
>  skl_max_scale(const struct intel_crtc_state *crtc_state,
>  	      const struct drm_format_info *format)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	int max_scale;
>  	int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
> @@ -14566,7 +14567,7 @@ skl_max_scale(const struct intel_crtc_state *crtc_state,
>  		return DRM_PLANE_HELPER_NO_SCALING;
>  
>  	crtc_clock = crtc_state->hw.adjusted_mode.crtc_clock;
> -	max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
> +	max_dotclk = to_intel_atomic_state(crtc_state->uapi.state)->cdclk.logical.cdclk;
>  
>  	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
>  		max_dotclk *= 2;
> @@ -14786,7 +14787,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
>  
>  out_free:
>  	if (new_crtc_state)
> -		intel_crtc_destroy_state(&crtc->base, &new_crtc_state->base);
> +		intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
>  	if (ret)
>  		intel_plane_destroy_state(&plane->base, &new_plane_state->base);
>  	else
> @@ -15112,7 +15113,7 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		ret = -ENOMEM;
>  		goto fail;
>  	}
> -	__drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->base);
> +	__drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->uapi);
>  	intel_crtc->config = crtc_state;
>  
>  	primary = intel_primary_plane_create(dev_priv, pipe);
> @@ -16128,7 +16129,7 @@ static int intel_initial_commit(struct drm_device *dev)
>  			 * having a proper LUT loaded. Remove once we
>  			 * have readout for pipe gamma enable.
>  			 */
> -			crtc_state->base.color_mgmt_changed = true;
> +			crtc_state->uapi.color_mgmt_changed = true;
>  		}
>  	}
>  
> @@ -16526,7 +16527,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
>  
>  static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
>  	/*
>  	 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
> @@ -16660,9 +16661,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>  		struct intel_crtc_state *crtc_state =
>  			to_intel_crtc_state(crtc->base.state);
>  
> -		__drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
> +		__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
>  		memset(crtc_state, 0, sizeof(*crtc_state));
> -		__drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->base);
> +		__drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->uapi);
>  
>  		crtc_state->hw.active = crtc_state->hw.enable =
>  			dev_priv->display.get_pipe_config(crtc, crtc_state);
> @@ -16748,9 +16749,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>  				 * because anything calling .crtc_disable may
>  				 * rely on the connector_mask being accurate.
>  				 */
> -				crtc_state->base.connector_mask |=
> +				crtc_state->uapi.connector_mask |=
>  					drm_connector_mask(&connector->base);
> -				crtc_state->base.encoder_mask |=
> +				crtc_state->uapi.encoder_mask |=
>  					drm_encoder_mask(&encoder->base);
>  			}
>  		} else {
> @@ -16778,7 +16779,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>  			crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
>  			intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
>  						    crtc_state);
> -			WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->base, &crtc->base.mode));
> +			WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc->base.mode));
>  
>  			/*
>  			 * The initial mode needs to be set in order to keep
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 213b0c0cdd67..7d691f6fc369 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2222,7 +2222,7 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
>  	const struct drm_display_info *info = &connector->display_info;
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	int ret;
>  
>  	if (!drm_mode_is_420_only(info, adjusted_mode) ||
> @@ -2287,7 +2287,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>  	struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
>  	enum port port = encoder->port;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	struct intel_connector *intel_connector = intel_dp->attached_connector;
>  	struct intel_digital_connector_state *intel_conn_state =
>  		to_intel_digital_connector_state(conn_state);
> @@ -2402,7 +2402,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>  	enum port port = encoder->port;
> -	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  
>  	intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
> @@ -3000,7 +3000,7 @@ static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
>  static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
>  				const struct intel_crtc_state *pipe_config)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>  	assert_pipe_disabled(dev_priv, crtc->pipe);
> @@ -3040,7 +3040,7 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
>  static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
>  				 const struct intel_crtc_state *old_crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>  	assert_pipe_disabled(dev_priv, crtc->pipe);
> @@ -3200,7 +3200,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>  	u32 tmp, flags = 0;
>  	enum port port = encoder->port;
> -	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  
>  	if (encoder->type == INTEL_OUTPUT_EDP)
>  		pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
> @@ -3467,7 +3467,7 @@ static void intel_enable_dp(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> -	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	u32 dp_reg = I915_READ(intel_dp->output_reg);
>  	enum pipe pipe = crtc->pipe;
>  	intel_wakeref_t wakeref;
> @@ -3600,7 +3600,7 @@ static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  
>  	lockdep_assert_held(&dev_priv->pps_mutex);
>  
> @@ -4122,7 +4122,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>  	enum port port = encoder->port;
>  	u32 DP = intel_dp->DP;
>  
> @@ -6874,7 +6874,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
>  				    int refresh_rate)
>  {
>  	struct intel_dp *intel_dp = dev_priv->drrs.dp;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
>  
>  	if (refresh_rate <= 0) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 7d63f0a79ca1..adf1d3895419 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -42,7 +42,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
>  					    struct drm_connector_state *conn_state,
>  					    struct link_config_limits *limits)
>  {
> -	struct drm_atomic_state *state = crtc_state->base.state;
> +	struct drm_atomic_state *state = crtc_state->uapi.state;
>  	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
>  	struct intel_dp *intel_dp = &intel_mst->primary->dp;
>  	struct intel_connector *connector =
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 556d1b30f06a..704f38681c4b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -739,7 +739,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum pipe pipe = crtc->pipe;
>  	u32 val;
>  
> @@ -783,7 +783,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
>  {
>  	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum dpio_channel ch = vlv_dport_to_channel(dport);
>  	enum pipe pipe = crtc->pipe;
>  	unsigned int lane_mask =
> @@ -864,7 +864,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>  	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum dpio_channel ch = vlv_dport_to_channel(dport);
>  	enum pipe pipe = crtc->pipe;
>  	int data, i, stagger;
> @@ -953,7 +953,7 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
>  			      const struct intel_crtc_state *old_crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	enum pipe pipe = to_intel_crtc(old_crtc_state->base.crtc)->pipe;
> +	enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe;
>  	u32 val;
>  
>  	vlv_dpio_get(dev_priv);
> @@ -1016,7 +1016,7 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
>  {
>  	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum dpio_channel port = vlv_dport_to_channel(dport);
>  	enum pipe pipe = crtc->pipe;
>  
> @@ -1046,7 +1046,7 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>  	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum dpio_channel port = vlv_dport_to_channel(dport);
>  	enum pipe pipe = crtc->pipe;
>  	u32 val;
> @@ -1075,7 +1075,7 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
>  {
>  	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>  	enum dpio_channel port = vlv_dport_to_channel(dport);
>  	enum pipe pipe = crtc->pipe;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index ec10fa7d3c69..33db1f59b406 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -136,7 +136,7 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
>   */
>  void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>  
> @@ -163,7 +163,7 @@ void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)
>   */
>  void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>  	unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
> @@ -208,7 +208,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
>   */
>  void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>  	unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
> @@ -827,7 +827,7 @@ hsw_ddi_hdmi_get_dpll(struct intel_atomic_state *state,
>  static struct intel_shared_dpll *
>  hsw_ddi_dp_get_dpll(struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	struct intel_shared_dpll *pll;
>  	enum intel_dpll_id pll_id;
>  	int clock = crtc_state->port_clock;
> @@ -1736,7 +1736,7 @@ static bool
>  bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
>  			  struct bxt_clk_div *clk_div)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct dpll best_clock;
>  
>  	/* Calculate HDMI div */
> @@ -2259,7 +2259,7 @@ static bool
>  cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
>  			struct skl_wrpll_params *wrpll_params)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	u32 afe_clock = crtc_state->port_clock * 5;
>  	u32 ref_clock;
>  	u32 dco_min = 7998000;
> @@ -2538,7 +2538,7 @@ static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
>  static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
>  				  struct skl_wrpll_params *pll_params)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	const struct icl_combo_pll_params *params =
>  		dev_priv->cdclk.hw.ref == 24000 ?
>  		icl_dp_combo_pll_24MHz_values :
> @@ -2560,7 +2560,7 @@ static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
>  static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
>  			     struct skl_wrpll_params *pll_params)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
>  	if (INTEL_GEN(dev_priv) >= 12) {
>  		switch (dev_priv->cdclk.hw.ref) {
> @@ -2597,7 +2597,7 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
>  				struct intel_encoder *encoder,
>  				struct intel_dpll_hw_state *pll_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	u32 cfgcr0, cfgcr1;
>  	struct skl_wrpll_params pll_params = { 0 };
>  	bool ret;
> @@ -2729,7 +2729,7 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
>  static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
>  				  struct intel_dpll_hw_state *pll_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	int refclk_khz = dev_priv->cdclk.hw.ref;
>  	int clock = crtc_state->port_clock;
>  	u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
> index a68e5c5b91b4..28770c5765ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -277,7 +277,7 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder,
>  				 const struct drm_connector_state *conn_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
>  	enum pipe pipe = crtc->pipe;
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 2f5fc71ac9a0..357ad459bfbc 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -285,7 +285,7 @@ static void ibx_write_infoframe(struct intel_encoder *encoder,
>  {
>  	const u32 *data = frame;
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
>  	u32 val = I915_READ(reg);
>  	int i;
> @@ -321,7 +321,7 @@ static void ibx_read_infoframe(struct intel_encoder *encoder,
>  			       void *frame, ssize_t len)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	u32 val, *data = frame;
>  	int i;
>  
> @@ -340,7 +340,7 @@ static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
>  				  const struct intel_crtc_state *pipe_config)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
> +	enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
>  	i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
>  	u32 val = I915_READ(reg);
>  
> @@ -362,7 +362,7 @@ static void cpt_write_infoframe(struct intel_encoder *encoder,
>  {
>  	const u32 *data = frame;
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
>  	u32 val = I915_READ(reg);
>  	int i;
> @@ -401,7 +401,7 @@ static void cpt_read_infoframe(struct intel_encoder *encoder,
>  			       void *frame, ssize_t len)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	u32 val, *data = frame;
>  	int i;
>  
> @@ -420,7 +420,7 @@ static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
>  				  const struct intel_crtc_state *pipe_config)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
> +	enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
>  	u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
>  
>  	if ((val & VIDEO_DIP_ENABLE) == 0)
> @@ -438,7 +438,7 @@ static void vlv_write_infoframe(struct intel_encoder *encoder,
>  {
>  	const u32 *data = frame;
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
>  	u32 val = I915_READ(reg);
>  	int i;
> @@ -474,7 +474,7 @@ static void vlv_read_infoframe(struct intel_encoder *encoder,
>  			       void *frame, ssize_t len)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	u32 val, *data = frame;
>  	int i;
>  
> @@ -493,7 +493,7 @@ static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
>  				  const struct intel_crtc_state *pipe_config)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
> +	enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
>  	u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
>  
>  	if ((val & VIDEO_DIP_ENABLE) == 0)
> @@ -965,7 +965,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
>  					 const struct drm_connector_state *conn_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	i915_reg_t reg;
>  
>  	if ((crtc_state->infoframes.enable &
> @@ -990,7 +990,7 @@ void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
>  				   struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	i915_reg_t reg;
>  
>  	if ((crtc_state->infoframes.enable &
> @@ -1037,7 +1037,7 @@ static void ibx_set_infoframes(struct intel_encoder *encoder,
>  			       const struct drm_connector_state *conn_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
>  	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
>  	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
> @@ -1096,7 +1096,7 @@ static void cpt_set_infoframes(struct intel_encoder *encoder,
>  			       const struct drm_connector_state *conn_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
>  	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
>  	u32 val = I915_READ(reg);
> @@ -1145,7 +1145,7 @@ static void vlv_set_infoframes(struct intel_encoder *encoder,
>  			       const struct drm_connector_state *conn_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
>  	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
>  	u32 val = I915_READ(reg);
> @@ -1741,7 +1741,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder,
>  {
>  	struct drm_device *dev = encoder->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
>  	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>  	u32 hdmi_val;
> @@ -1865,7 +1865,7 @@ static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
>  				    const struct intel_crtc_state *pipe_config,
>  				    const struct drm_connector_state *conn_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  
>  	WARN_ON(!pipe_config->has_hdmi_sink);
>  	DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
> @@ -1951,7 +1951,7 @@ static void cpt_enable_hdmi(struct intel_encoder *encoder,
>  {
>  	struct drm_device *dev = encoder->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
>  	enum pipe pipe = crtc->pipe;
>  	u32 temp;
> @@ -2015,7 +2015,7 @@ static void intel_disable_hdmi(struct intel_encoder *encoder,
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
>  	struct intel_digital_port *intel_dig_port =
>  		hdmi_to_dig_port(intel_hdmi);
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>  	u32 temp;
>  
>  	temp = I915_READ(intel_hdmi->hdmi_reg);
> @@ -2215,8 +2215,8 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
>  				     int bpc)
>  {
>  	struct drm_i915_private *dev_priv =
> -		to_i915(crtc_state->base.crtc->dev);
> -	struct drm_atomic_state *state = crtc_state->base.state;
> +		to_i915(crtc_state->uapi.crtc->dev);
> +	struct drm_atomic_state *state = crtc_state->uapi.state;
>  	struct drm_connector_state *connector_state;
>  	struct drm_connector *connector;
>  	const struct drm_display_mode *adjusted_mode =
> @@ -2245,7 +2245,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
>  	for_each_new_connector_in_state(state, connector, connector_state, i) {
>  		const struct drm_display_info *info = &connector->display_info;
>  
> -		if (connector_state->crtc != crtc_state->base.crtc)
> +		if (connector_state->crtc != crtc_state->uapi.crtc)
>  			continue;
>  
>  		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
> @@ -2286,7 +2286,7 @@ static bool
>  intel_hdmi_ycbcr420_config(struct drm_connector *connector,
>  			   struct intel_crtc_state *config)
>  {
> -	struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(config->uapi.crtc);
>  
>  	if (!connector->ycbcr_420_allowed) {
>  		DRM_ERROR("Platform doesn't support YCBCR420 output\n");
> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
> index f17d6e02460f..ca4ebb0f2230 100644
> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> @@ -230,7 +230,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder,
>  {
>  	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	enum pipe pipe = crtc->pipe;
>  	u32 temp;
> @@ -393,7 +393,7 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
>  	struct intel_connector *intel_connector =
>  		lvds_encoder->attached_connector;
>  	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	unsigned int lvds_bpp;
>  
>  	/* Should never happen!! */
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
> index 5e3fd37d9471..6f3eaae3761f 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.c
> +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> @@ -1047,7 +1047,7 @@ static void vlv_enable_backlight(const struct intel_crtc_state *crtc_state,
>  	struct intel_connector *connector = to_intel_connector(conn_state->connector);
>  	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>  	struct intel_panel *panel = &connector->panel;
> -	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> +	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
>  	u32 ctl, ctl2;
>  
>  	ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe));
> @@ -1077,7 +1077,7 @@ static void bxt_enable_backlight(const struct intel_crtc_state *crtc_state,
>  	struct intel_connector *connector = to_intel_connector(conn_state->connector);
>  	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>  	struct intel_panel *panel = &connector->panel;
> -	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> +	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
>  	u32 pwm_ctl, val;
>  
>  	/* Controller 1 uses the utility pin. */
> @@ -1189,7 +1189,7 @@ void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
>  	struct intel_connector *connector = to_intel_connector(conn_state->connector);
>  	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>  	struct intel_panel *panel = &connector->panel;
> -	enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> +	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
>  
>  	if (!panel->backlight.present)
>  		return;
> diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> index fc602533a602..2746512f4466 100644
> --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> @@ -309,13 +309,13 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
>  		goto put_state;
>  	}
>  
> -	pipe_config->base.mode_changed = pipe_config->has_psr;
> +	pipe_config->uapi.mode_changed = pipe_config->has_psr;
>  	pipe_config->crc_enabled = enable;
>  
>  	if (IS_HASWELL(dev_priv) &&
>  	    pipe_config->hw.active && crtc->pipe == PIPE_A &&
>  	    pipe_config->cpu_transcoder == TRANSCODER_EDP)
> -		pipe_config->base.mode_changed = true;
> +		pipe_config->uapi.mode_changed = true;
>  
>  	ret = drm_atomic_commit(state);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 347004981cff..9c76ad5383b9 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -812,7 +812,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
>  
>  	dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
>  	dev_priv->psr.busy_frontbuffer_bits = 0;
> -	dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> +	dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
>  	dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
>  	dev_priv->psr.dc3co_exit_delay = intel_get_frame_time_us(crtc_state);
>  	dev_priv->psr.transcoder = crtc_state->cpu_transcoder;
> @@ -1059,7 +1059,7 @@ void intel_psr_update(struct intel_dp *intel_dp,
>  int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
>  			    u32 *out_value)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>  	if (!dev_priv->psr.enabled || !new_crtc_state->has_psr)
> @@ -1141,7 +1141,7 @@ static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
>  
>  		if (intel_crtc_state->hw.active && intel_crtc_state->has_psr) {
>  			/* Mark mode as changed to trigger a pipe->update() */
> -			intel_crtc_state->base.mode_changed = true;
> +			intel_crtc_state->uapi.mode_changed = true;
>  			break;
>  		}
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
> index 97ae8cc1314e..1047357c15c4 100644
> --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> @@ -1429,7 +1429,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
>  				  const struct drm_connector_state *conn_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>  	const struct intel_sdvo_connector_state *sdvo_state =
>  		to_intel_sdvo_connector_state(conn_state);
> @@ -1723,7 +1723,7 @@ static void intel_disable_sdvo(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>  	u32 temp;
>  
>  	if (old_crtc_state->has_audio)
> @@ -1785,7 +1785,7 @@ static void intel_enable_sdvo(struct intel_encoder *encoder,
>  	struct drm_device *dev = encoder->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	u32 temp;
>  	bool input1, input2;
>  	int i;
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index ef0ca7c6d11f..fa687c05b1ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -81,7 +81,7 @@ int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
>   */
>  void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
>  	long timeout = msecs_to_jiffies_timeout(1);
> @@ -190,7 +190,7 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
>   */
>  void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
>  	enum pipe pipe = crtc->pipe;
>  	int scanline_end = intel_get_crtc_scanline(crtc);
>  	u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
> @@ -203,14 +203,15 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
>  	 * Would be slightly nice to just grab the vblank count and arm the
>  	 * event outside of the critical section - the spinlock might spin for a
>  	 * while ... */
> -	if (new_crtc_state->base.event) {
> +	if (new_crtc_state->uapi.event) {
>  		WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
>  
>  		spin_lock(&crtc->base.dev->event_lock);
> -		drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
> +		drm_crtc_arm_vblank_event(&crtc->base,
> +				          new_crtc_state->uapi.event);
>  		spin_unlock(&crtc->base.dev->event_lock);
>  
> -		new_crtc_state->base.event = NULL;
> +		new_crtc_state->uapi.event = NULL;
>  	}
>  
>  	local_irq_enable();
> @@ -1586,7 +1587,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
>  	}
>  
>  	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> -						  &crtc_state->base,
> +						  &crtc_state->uapi,
>  						  min_scale, max_scale,
>  						  true, true);
>  	if (ret)
> @@ -1643,7 +1644,7 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
>  		return ret;
>  
>  	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> -						  &crtc_state->base,
> +						  &crtc_state->uapi,
>  						  DRM_PLANE_HELPER_NO_SCALING,
>  						  DRM_PLANE_HELPER_NO_SCALING,
>  						  true, true);
> @@ -1808,7 +1809,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
>  	}
>  
>  	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> -						  &crtc_state->base,
> +						  &crtc_state->uapi,
>  						  min_scale, max_scale,
>  						  true, true);
>  	if (ret)
> diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
> index e800d45b813d..4499d402c316 100644
> --- a/drivers/gpu/drm/i915/display/intel_tv.c
> +++ b/drivers/gpu/drm/i915/display/intel_tv.c
> @@ -924,7 +924,7 @@ intel_enable_tv(struct intel_encoder *encoder,
>  
>  	/* Prevents vblank waits from timing out in intel_tv_detect_type() */
>  	intel_wait_for_vblank(dev_priv,
> -			      to_intel_crtc(pipe_config->base.crtc)->pipe);
> +			      to_intel_crtc(pipe_config->uapi.crtc)->pipe);
>  
>  	I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
>  }
> @@ -1417,7 +1417,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder,
>  				const struct drm_connector_state *conn_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	struct intel_tv *intel_tv = enc_to_tv(encoder);
>  	const struct intel_tv_connector_state *tv_conn_state =
>  		to_intel_tv_connector_state(conn_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 6a338a83aaed..38c181499505 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -459,7 +459,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
>  enum intel_display_power_domain
>  intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  
>  	/*
> @@ -483,7 +483,7 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
>  static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
>  						const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
>  	enum pipe pipe = crtc->pipe;
> @@ -902,7 +902,7 @@ static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
>  void intel_dsc_enable(struct intel_encoder *encoder,
>  		      const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
> @@ -938,7 +938,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
>  
>  void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index 3bf838279fc2..16f93d1e71e5 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -261,7 +261,7 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
>  	struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
>  						   base);
>  	struct intel_connector *intel_connector = intel_dsi->attached_connector;
> -	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
>  	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	int ret;
> @@ -624,7 +624,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder,
>  				  const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	enum port port;
>  
> @@ -746,7 +746,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
>  				 const struct drm_connector_state *conn_state)
>  {
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> -	struct drm_crtc *crtc = pipe_config->base.crtc;
> +	struct drm_crtc *crtc = pipe_config->uapi.crtc;
>  	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	enum pipe pipe = intel_crtc->pipe;
> @@ -1034,7 +1034,7 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
>  	struct drm_display_mode *adjusted_mode =
>  					&pipe_config->hw.adjusted_mode;
>  	struct drm_display_mode *adjusted_mode_sw;
> -	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	unsigned int lane_count = intel_dsi->lane_count;
>  	unsigned int bpp, fmt;
> @@ -1315,7 +1315,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
>  	struct drm_encoder *encoder = &intel_encoder->base;
>  	struct drm_device *dev = encoder->dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
>  	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	enum port port;
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 51e83da21738..bdace2f14cde 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -4222,7 +4222,7 @@ static int i915_drrs_ctl_set(void *data, u64 val)
>  		    !crtc_state->has_drrs)
>  			goto out;
>  
> -		commit = crtc_state->base.commit;
> +		commit = crtc_state->uapi.commit;
>  		if (commit) {
>  			ret = wait_for_completion_interruptible(&commit->hw_done);
>  			if (ret)
> @@ -4234,7 +4234,7 @@ static int i915_drrs_ctl_set(void *data, u64 val)
>  			struct intel_encoder *encoder;
>  			struct intel_dp *intel_dp;
>  
> -			if (!(crtc_state->base.connector_mask &
> +			if (!(crtc_state->uapi.connector_mask &
>  			      drm_connector_mask(connector)))
>  				continue;
>  
> @@ -4293,7 +4293,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
>  			return ret;
>  
>  		crtc_state = to_intel_crtc_state(intel_crtc->base.state);
> -		commit = crtc_state->base.commit;
> +		commit = crtc_state->uapi.commit;
>  		if (commit) {
>  			ret = wait_for_completion_interruptible(&commit->hw_done);
>  			if (!ret)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9671ff29c25f..76f8eea15ddf 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -464,7 +464,7 @@ static const int pessimal_latency_ns = 5000;
>  
>  static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
>  	enum pipe pipe = crtc->pipe;
> @@ -1144,7 +1144,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
>  static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
>  				 int level, enum plane_id plane_id, u16 value)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	bool dirty = false;
>  
>  	for (; level < intel_wm_num_levels(dev_priv); level++) {
> @@ -1160,7 +1160,7 @@ static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
>  static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
>  			       int level, u16 value)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	bool dirty = false;
>  
>  	/* NORMAL level doesn't have an FBC watermark */
> @@ -1262,7 +1262,7 @@ static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
>  static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
>  				     int level)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
>  	if (level > dev_priv->wm.max_level)
>  		return false;
> @@ -1300,9 +1300,9 @@ static void g4x_invalidate_wms(struct intel_crtc *crtc,
>  
>  static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct intel_atomic_state *state =
> -		to_intel_atomic_state(crtc_state->base.state);
> +		to_intel_atomic_state(crtc_state->uapi.state);
>  	struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
>  	int num_active_planes = hweight8(crtc_state->active_planes &
>  					 ~BIT(PLANE_CURSOR));
> @@ -1389,17 +1389,17 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
>  
>  static int g4x_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
>  	struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;
>  	const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;
>  	struct intel_atomic_state *intel_state =
> -		to_intel_atomic_state(new_crtc_state->base.state);
> +		to_intel_atomic_state(new_crtc_state->uapi.state);
>  	const struct intel_crtc_state *old_crtc_state =
>  		intel_atomic_get_old_crtc_state(intel_state, crtc);
>  	const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
>  	enum plane_id plane_id;
>  
> -	if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
> +	if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
>  		*intermediate = *optimal;
>  
>  		intermediate->cxsr = false;
> @@ -1531,8 +1531,8 @@ static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
>  static void g4x_initial_watermarks(struct intel_atomic_state *state,
>  				   struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  
>  	mutex_lock(&dev_priv->wm.wm_mutex);
>  	crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
> @@ -1543,8 +1543,8 @@ static void g4x_initial_watermarks(struct intel_atomic_state *state,
>  static void g4x_optimize_watermarks(struct intel_atomic_state *state,
>  				    struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  
>  	if (!crtc_state->wm.need_postvbl_update)
>  		return;
> @@ -1631,7 +1631,7 @@ static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
>  
>  static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	const struct g4x_pipe_wm *raw =
>  		&crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
>  	struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
> @@ -1743,7 +1743,7 @@ static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
>  static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
>  				 int level, enum plane_id plane_id, u16 value)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	int num_levels = intel_wm_num_levels(dev_priv);
>  	bool dirty = false;
>  
> @@ -1818,16 +1818,16 @@ static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
>  
>  static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_atomic_state *state =
> -		to_intel_atomic_state(crtc_state->base.state);
> +		to_intel_atomic_state(crtc_state->uapi.state);
>  	struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
>  	const struct vlv_fifo_state *fifo_state =
>  		&crtc_state->wm.vlv.fifo_state;
>  	int num_active_planes = hweight8(crtc_state->active_planes &
>  					 ~BIT(PLANE_CURSOR));
> -	bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base);
> +	bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
>  	const struct intel_plane_state *old_plane_state;
>  	const struct intel_plane_state *new_plane_state;
>  	struct intel_plane *plane;
> @@ -1926,7 +1926,7 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
>  static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>  				   struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_uncore *uncore = &dev_priv->uncore;
>  	const struct vlv_fifo_state *fifo_state =
> @@ -2022,17 +2022,17 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>  
>  static int vlv_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
>  	struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate;
>  	const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;
>  	struct intel_atomic_state *intel_state =
> -		to_intel_atomic_state(new_crtc_state->base.state);
> +		to_intel_atomic_state(new_crtc_state->uapi.state);
>  	const struct intel_crtc_state *old_crtc_state =
>  		intel_atomic_get_old_crtc_state(intel_state, crtc);
>  	const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
>  	int level;
>  
> -	if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
> +	if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
>  		*intermediate = *optimal;