* [CI] drm/i915/gt: Introduce barrier pulses along engines
@ 2019-10-21 16:08 Chris Wilson
2019-10-21 16:24 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Introduce barrier pulses along engines (rev3) Patchwork
2019-10-21 16:48 ` ✗ Fi.CI.BAT: failure " Patchwork
0 siblings, 2 replies; 6+ messages in thread
From: Chris Wilson @ 2019-10-21 16:08 UTC (permalink / raw)
To: intel-gfx
To flush idle barriers, and even inflight requests, we want to send a
preemptive 'pulse' along an engine. We use a no-op request along the
pinned kernel_context at high priority so that it should run or else
kick off the stuck requests. We can use this to ensure idle barriers are
immediately flushed, as part of a context cancellation mechanism, or as
part of a heartbeat mechanism to detect and reset a stuck GPU.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +-
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 77 +++++++++
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 15 ++
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
.../drm/i915/gt/selftest_engine_heartbeat.c | 150 ++++++++++++++++++
drivers/gpu/drm/i915/i915_priolist_types.h | 1 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
7 files changed, 247 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
create mode 100644 drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a16a2daef977..2fd4bed188e5 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -78,8 +78,9 @@ gt-y += \
gt/intel_breadcrumbs.o \
gt/intel_context.o \
gt/intel_engine_cs.o \
- gt/intel_engine_pool.o \
+ gt/intel_engine_heartbeat.o \
gt/intel_engine_pm.o \
+ gt/intel_engine_pool.o \
gt/intel_engine_user.o \
gt/intel_gt.o \
gt/intel_gt_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
new file mode 100644
index 000000000000..4b9ab7813d54
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -0,0 +1,77 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "i915_request.h"
+
+#include "intel_context.h"
+#include "intel_engine_heartbeat.h"
+#include "intel_engine_pm.h"
+#include "intel_engine.h"
+#include "intel_gt.h"
+
+static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq)
+{
+ engine->wakeref_serial = READ_ONCE(engine->serial) + 1;
+ i915_request_add_active_barriers(rq);
+}
+
+int intel_engine_pulse(struct intel_engine_cs *engine)
+{
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_BARRIER };
+ struct intel_context *ce = engine->kernel_context;
+ struct i915_request *rq;
+ int err = 0;
+
+ if (!intel_engine_has_preemption(engine))
+ return -ENODEV;
+
+ if (!intel_engine_pm_get_if_awake(engine))
+ return 0;
+
+ if (mutex_lock_interruptible(&ce->timeline->mutex))
+ goto out_rpm;
+
+ intel_context_enter(ce);
+ rq = __i915_request_create(ce, GFP_NOWAIT | __GFP_NOWARN);
+ intel_context_exit(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_unlock;
+ }
+
+ rq->flags |= I915_REQUEST_SENTINEL;
+ idle_pulse(engine, rq);
+
+ __i915_request_commit(rq);
+ __i915_request_queue(rq, &attr);
+
+out_unlock:
+ mutex_unlock(&ce->timeline->mutex);
+out_rpm:
+ intel_engine_pm_put(engine);
+ return err;
+}
+
+int intel_engine_flush_barriers(struct intel_engine_cs *engine)
+{
+ struct i915_request *rq;
+
+ if (llist_empty(&engine->barrier_tasks))
+ return 0;
+
+ rq = i915_request_create(engine->kernel_context);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ idle_pulse(engine, rq);
+ i915_request_add(rq);
+
+ return 0;
+}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_engine_heartbeat.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
new file mode 100644
index 000000000000..b334e5aaf78d
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef INTEL_ENGINE_HEARTBEAT_H
+#define INTEL_ENGINE_HEARTBEAT_H
+
+struct intel_engine_cs;
+
+int intel_engine_pulse(struct intel_engine_cs *engine);
+int intel_engine_flush_barriers(struct intel_engine_cs *engine);
+
+#endif /* INTEL_ENGINE_HEARTBEAT_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 67eb6183648a..7d76611d9df1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -111,7 +111,7 @@ static bool switch_to_kernel_context(struct intel_engine_cs *engine)
i915_request_add_active_barriers(rq);
/* Install ourselves as a preemption barrier */
- rq->sched.attr.priority = I915_PRIORITY_UNPREEMPTABLE;
+ rq->sched.attr.priority = I915_PRIORITY_BARRIER;
__i915_request_commit(rq);
/* Release our exclusive hold on the engine */
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
new file mode 100644
index 000000000000..ad2f0543cbda
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
@@ -0,0 +1,150 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#include "i915_drv.h"
+
+#include "intel_gt_requests.h"
+#include "i915_selftest.h"
+
+struct pulse {
+ struct i915_active active;
+ struct kref kref;
+};
+
+static int pulse_active(struct i915_active *active)
+{
+ kref_get(&container_of(active, struct pulse, active)->kref);
+ return 0;
+}
+
+static void pulse_free(struct kref *kref)
+{
+ kfree(container_of(kref, struct pulse, kref));
+}
+
+static void pulse_put(struct pulse *p)
+{
+ kref_put(&p->kref, pulse_free);
+}
+
+static void pulse_retire(struct i915_active *active)
+{
+ pulse_put(container_of(active, struct pulse, active));
+}
+
+static struct pulse *pulse_create(void)
+{
+ struct pulse *p;
+
+ p = kmalloc(sizeof(*p), GFP_KERNEL);
+ if (!p)
+ return p;
+
+ kref_init(&p->kref);
+ i915_active_init(&p->active, pulse_active, pulse_retire);
+
+ return p;
+}
+
+static int __live_idle_pulse(struct intel_engine_cs *engine,
+ int (*fn)(struct intel_engine_cs *cs))
+{
+ struct pulse *p;
+ int err;
+
+ p = pulse_create();
+ if (!p)
+ return -ENOMEM;
+
+ err = i915_active_acquire_preallocate_barrier(&p->active, engine);
+ if (err)
+ goto out;
+
+ i915_active_acquire_barrier(&p->active);
+
+ err = fn(engine);
+ if (err)
+ goto out;
+
+ if (intel_gt_retire_requests_timeout(engine->gt, HZ / 5)) {
+ err = -ETIME;
+ goto out;
+ }
+
+ if (atomic_read(&p->active.count)) {
+ pr_err("%s: heartbeat pulse did not flush idle tasks\n",
+ engine->name);
+ err = -EINVAL;
+ goto out;
+ }
+
+out:
+ pulse_put(p);
+ return err;
+}
+
+static int live_idle_flush(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /* Check that we can flush the idle barriers */
+
+ for_each_engine(engine, gt, id) {
+ intel_engine_pm_get(engine);
+ err = __live_idle_pulse(engine, intel_engine_flush_barriers);
+ intel_engine_pm_put(engine);
+ if (err)
+ break;
+ }
+
+ return err;
+}
+
+static int live_idle_pulse(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /* Check that heartbeat pulses flush the idle barriers */
+
+ for_each_engine(engine, gt, id) {
+ intel_engine_pm_get(engine);
+ err = __live_idle_pulse(engine, intel_engine_pulse);
+ intel_engine_pm_put(engine);
+ if (err && err != -ENODEV)
+ break;
+
+ err = 0;
+ }
+
+ return err;
+}
+
+int intel_heartbeat_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(live_idle_flush),
+ SUBTEST(live_idle_pulse),
+ };
+ int saved_hangcheck;
+ int err;
+
+ if (intel_gt_is_wedged(&i915->gt))
+ return 0;
+
+ saved_hangcheck = i915_modparams.enable_hangcheck;
+ i915_modparams.enable_hangcheck = INT_MAX;
+
+ err = intel_gt_live_subtests(tests, &i915->gt);
+
+ i915_modparams.enable_hangcheck = saved_hangcheck;
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h b/drivers/gpu/drm/i915/i915_priolist_types.h
index 21037a2e2038..ae8bb3cb627e 100644
--- a/drivers/gpu/drm/i915/i915_priolist_types.h
+++ b/drivers/gpu/drm/i915/i915_priolist_types.h
@@ -39,6 +39,7 @@ enum {
* active request.
*/
#define I915_PRIORITY_UNPREEMPTABLE INT_MAX
+#define I915_PRIORITY_BARRIER INT_MAX
#define __NO_PREEMPTION (I915_PRIORITY_WAIT)
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 6daf6599ec79..00a063730bc3 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -17,6 +17,7 @@ selftest(gt_timelines, intel_timeline_live_selftests)
selftest(gt_contexts, intel_context_live_selftests)
selftest(gt_lrc, intel_lrc_live_selftests)
selftest(gt_pm, intel_gt_pm_live_selftests)
+selftest(gt_heartbeat, intel_heartbeat_live_selftests)
selftest(requests, i915_request_live_selftests)
selftest(active, i915_active_live_selftests)
selftest(objects, i915_gem_object_live_selftests)
--
2.24.0.rc0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Introduce barrier pulses along engines (rev3)
2019-10-21 16:08 [CI] drm/i915/gt: Introduce barrier pulses along engines Chris Wilson
@ 2019-10-21 16:24 ` Patchwork
2019-10-21 16:48 ` ✗ Fi.CI.BAT: failure " Patchwork
1 sibling, 0 replies; 6+ messages in thread
From: Patchwork @ 2019-10-21 16:24 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt: Introduce barrier pulses along engines (rev3)
URL : https://patchwork.freedesktop.org/series/68309/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
420dc8e008a2 drm/i915/gt: Introduce barrier pulses along engines
-:32: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#32:
new file mode 100644
-:37: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#37: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:1:
+/*
-:38: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#38: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:2:
+ * SPDX-License-Identifier: MIT
-:120: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#120: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h:1:
+/*
-:121: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#121: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h:2:
+ * SPDX-License-Identifier: MIT
-:154: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#154: FILE: drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c:1:
+/*
-:155: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#155: FILE: drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c:2:
+ * SPDX-License-Identifier: MIT
total: 0 errors, 7 warnings, 0 checks, 274 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/gt: Introduce barrier pulses along engines (rev3)
2019-10-21 16:08 [CI] drm/i915/gt: Introduce barrier pulses along engines Chris Wilson
2019-10-21 16:24 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Introduce barrier pulses along engines (rev3) Patchwork
@ 2019-10-21 16:48 ` Patchwork
1 sibling, 0 replies; 6+ messages in thread
From: Patchwork @ 2019-10-21 16:48 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt: Introduce barrier pulses along engines (rev3)
URL : https://patchwork.freedesktop.org/series/68309/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7141 -> Patchwork_14904
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14904 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14904, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14904:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_active:
- fi-byt-n2820: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7141/fi-byt-n2820/igt@i915_selftest@live_active.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-byt-n2820/igt@i915_selftest@live_active.html
* igt@i915_selftest@live_coherency:
- fi-snb-2600: [PASS][3] -> [DMESG-WARN][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7141/fi-snb-2600/igt@i915_selftest@live_coherency.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-snb-2600/igt@i915_selftest@live_coherency.html
* igt@i915_selftest@live_dmabuf:
- fi-ivb-3770: [PASS][5] -> [DMESG-WARN][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7141/fi-ivb-3770/igt@i915_selftest@live_dmabuf.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-ivb-3770/igt@i915_selftest@live_dmabuf.html
* {igt@i915_selftest@live_gt_heartbeat} (NEW):
- fi-kbl-x1275: NOTRUN -> [DMESG-FAIL][7]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-kbl-x1275/igt@i915_selftest@live_gt_heartbeat.html
- fi-bsw-kefka: NOTRUN -> [DMESG-FAIL][8]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-bsw-kefka/igt@i915_selftest@live_gt_heartbeat.html
- {fi-icl-dsi}: NOTRUN -> [DMESG-FAIL][9]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-icl-dsi/igt@i915_selftest@live_gt_heartbeat.html
- fi-cfl-8700k: NOTRUN -> [DMESG-FAIL][10]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-cfl-8700k/igt@i915_selftest@live_gt_heartbeat.html
- fi-skl-6600u: NOTRUN -> [DMESG-FAIL][11]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-skl-6600u/igt@i915_selftest@live_gt_heartbeat.html
- fi-kbl-8809g: NOTRUN -> [DMESG-FAIL][12]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
- {fi-icl-u4}: NOTRUN -> [DMESG-FAIL][13]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-icl-u4/igt@i915_selftest@live_gt_heartbeat.html
- fi-skl-lmem: NOTRUN -> [DMESG-FAIL][14]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-skl-lmem/igt@i915_selftest@live_gt_heartbeat.html
- fi-apl-guc: NOTRUN -> [DMESG-FAIL][15]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-apl-guc/igt@i915_selftest@live_gt_heartbeat.html
- fi-kbl-r: NOTRUN -> [DMESG-FAIL][16]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-kbl-r/igt@i915_selftest@live_gt_heartbeat.html
- fi-bdw-5557u: NOTRUN -> [DMESG-FAIL][17]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-bdw-5557u/igt@i915_selftest@live_gt_heartbeat.html
- fi-bwr-2160: NOTRUN -> [DMESG-FAIL][18]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-bwr-2160/igt@i915_selftest@live_gt_heartbeat.html
- fi-byt-n2820: NOTRUN -> [DMESG-FAIL][19]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-byt-n2820/igt@i915_selftest@live_gt_heartbeat.html
- fi-skl-6770hq: NOTRUN -> [DMESG-FAIL][20]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-skl-6770hq/igt@i915_selftest@live_gt_heartbeat.html
- fi-kbl-guc: NOTRUN -> [DMESG-FAIL][21]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-kbl-guc/igt@i915_selftest@live_gt_heartbeat.html
- fi-snb-2600: NOTRUN -> [DMESG-FAIL][22]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-snb-2600/igt@i915_selftest@live_gt_heartbeat.html
- fi-elk-e7500: NOTRUN -> [DMESG-FAIL][23]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-elk-e7500/igt@i915_selftest@live_gt_heartbeat.html
- {fi-tgl-u2}: NOTRUN -> [DMESG-FAIL][24]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-tgl-u2/igt@i915_selftest@live_gt_heartbeat.html
- fi-ilk-650: NOTRUN -> [DMESG-FAIL][25]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-ilk-650/igt@i915_selftest@live_gt_heartbeat.html
- fi-pnv-d510: NOTRUN -> [DMESG-FAIL][26]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-pnv-d510/igt@i915_selftest@live_gt_heartbeat.html
- fi-bdw-gvtdvm: NOTRUN -> [DMESG-FAIL][27]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-bdw-gvtdvm/igt@i915_selftest@live_gt_heartbeat.html
- fi-cfl-8109u: NOTRUN -> [DMESG-FAIL][28]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-cfl-8109u/igt@i915_selftest@live_gt_heartbeat.html
- fi-hsw-peppy: NOTRUN -> [DMESG-FAIL][29]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-hsw-peppy/igt@i915_selftest@live_gt_heartbeat.html
- fi-icl-u2: NOTRUN -> [DMESG-FAIL][30]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-icl-u2/igt@i915_selftest@live_gt_heartbeat.html
- fi-gdg-551: NOTRUN -> [DMESG-FAIL][31]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-gdg-551/igt@i915_selftest@live_gt_heartbeat.html
- fi-glk-dsi: NOTRUN -> [DMESG-FAIL][32]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-glk-dsi/igt@i915_selftest@live_gt_heartbeat.html
- fi-snb-2520m: NOTRUN -> [DMESG-FAIL][33]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-snb-2520m/igt@i915_selftest@live_gt_heartbeat.html
- {fi-icl-guc}: NOTRUN -> [DMESG-FAIL][34]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-icl-guc/igt@i915_selftest@live_gt_heartbeat.html
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][35]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-kbl-soraka/igt@i915_selftest@live_gt_heartbeat.html
- fi-hsw-4770: NOTRUN -> [DMESG-FAIL][36]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-hsw-4770/igt@i915_selftest@live_gt_heartbeat.html
- fi-kbl-7500u: NOTRUN -> [DMESG-FAIL][37]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-kbl-7500u/igt@i915_selftest@live_gt_heartbeat.html
- fi-whl-u: NOTRUN -> [DMESG-FAIL][38]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-whl-u/igt@i915_selftest@live_gt_heartbeat.html
- fi-cml-u2: NOTRUN -> [DMESG-FAIL][39]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-cml-u2/igt@i915_selftest@live_gt_heartbeat.html
- fi-icl-u3: NOTRUN -> [DMESG-FAIL][40]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-icl-u3/igt@i915_selftest@live_gt_heartbeat.html
- fi-cml-u: NOTRUN -> [DMESG-FAIL][41]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-cml-u/igt@i915_selftest@live_gt_heartbeat.html
- fi-ivb-3770: NOTRUN -> [DMESG-FAIL][42]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-ivb-3770/igt@i915_selftest@live_gt_heartbeat.html
- fi-bxt-dsi: NOTRUN -> [DMESG-FAIL][43]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-bxt-dsi/igt@i915_selftest@live_gt_heartbeat.html
- fi-byt-j1900: NOTRUN -> [DMESG-FAIL][44]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-byt-j1900/igt@i915_selftest@live_gt_heartbeat.html
- fi-skl-iommu: NOTRUN -> [DMESG-FAIL][45]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-skl-iommu/igt@i915_selftest@live_gt_heartbeat.html
- {fi-cml-s}: NOTRUN -> [DMESG-FAIL][46]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-cml-s/igt@i915_selftest@live_gt_heartbeat.html
- fi-cfl-guc: NOTRUN -> [DMESG-FAIL][47]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-cfl-guc/igt@i915_selftest@live_gt_heartbeat.html
- fi-skl-guc: NOTRUN -> [DMESG-FAIL][48]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-skl-guc/igt@i915_selftest@live_gt_heartbeat.html
- fi-skl-6700k2: NOTRUN -> [DMESG-FAIL][49]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-skl-6700k2/igt@i915_selftest@live_gt_heartbeat.html
- fi-bsw-n3050: NOTRUN -> [DMESG-FAIL][50]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-bsw-n3050/igt@i915_selftest@live_gt_heartbeat.html
- fi-blb-e6850: NOTRUN -> [DMESG-FAIL][51]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-blb-e6850/igt@i915_selftest@live_gt_heartbeat.html
* igt@i915_selftest@live_objects:
- fi-ilk-650: [PASS][52] -> [DMESG-WARN][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7141/fi-ilk-650/igt@i915_selftest@live_objects.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-ilk-650/igt@i915_selftest@live_objects.html
* igt@i915_selftest@live_requests:
- fi-skl-6700k2: [PASS][54] -> [DMESG-WARN][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7141/fi-skl-6700k2/igt@i915_selftest@live_requests.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-skl-6700k2/igt@i915_selftest@live_requests.html
- fi-bxt-dsi: [PASS][56] -> [DMESG-WARN][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7141/fi-bxt-dsi/igt@i915_selftest@live_requests.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-bxt-dsi/igt@i915_selftest@live_requests.html
- fi-kbl-8809g: [PASS][58] -> [DMESG-WARN][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7141/fi-kbl-8809g/igt@i915_selftest@live_requests.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-kbl-8809g/igt@i915_selftest@live_requests.html
- fi-skl-iommu: [PASS][60] -> [DMESG-WARN][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7141/fi-skl-iommu/igt@i915_selftest@live_requests.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-skl-iommu/igt@i915_selftest@live_requests.html
- fi-skl-guc: [PASS][62] -> [DMESG-WARN][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7141/fi-skl-guc/igt@i915_selftest@live_requests.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-skl-guc/igt@i915_selftest@live_requests.html
* igt@runner@aborted:
- fi-ilk-650: NOTRUN -> [FAIL][64]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-ilk-650/igt@runner@aborted.html
- fi-pnv-d510: NOTRUN -> [FAIL][65]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-pnv-d510/igt@runner@aborted.html
- fi-bdw-gvtdvm: NOTRUN -> [FAIL][66]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-bdw-gvtdvm/igt@runner@aborted.html
- fi-cfl-8109u: NOTRUN -> [FAIL][67]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-cfl-8109u/igt@runner@aborted.html
- fi-gdg-551: NOTRUN -> [FAIL][68]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-gdg-551/igt@runner@aborted.html
- fi-kbl-soraka: NOTRUN -> [FAIL][69]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-kbl-soraka/igt@runner@aborted.html
- fi-kbl-7500u: NOTRUN -> [FAIL][70]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-kbl-7500u/igt@runner@aborted.html
- fi-whl-u: NOTRUN -> [FAIL][71]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-whl-u/igt@runner@aborted.html
- fi-cml-u2: NOTRUN -> [FAIL][72]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-cml-u2/igt@runner@aborted.html
- fi-cml-u: NOTRUN -> [FAIL][73]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-cml-u/igt@runner@aborted.html
- fi-bsw-n3050: NOTRUN -> [FAIL][74]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-bsw-n3050/igt@runner@aborted.html
- fi-blb-e6850: NOTRUN -> [FAIL][75]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-blb-e6850/igt@runner@aborted.html
- fi-kbl-x1275: NOTRUN -> [FAIL][76]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-kbl-x1275/igt@runner@aborted.html
- fi-bsw-kefka: NOTRUN -> [FAIL][77]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-bsw-kefka/igt@runner@aborted.html
- fi-cfl-8700k: NOTRUN -> [FAIL][78]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-cfl-8700k/igt@runner@aborted.html
- fi-kbl-r: NOTRUN -> [FAIL][79]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-kbl-r/igt@runner@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][80]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-bdw-5557u/igt@runner@aborted.html
- fi-elk-e7500: NOTRUN -> [FAIL][81]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-elk-e7500/igt@runner@aborted.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {fi-cml-s}: NOTRUN -> [FAIL][82]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-cml-s/igt@runner@aborted.html
- {fi-tgl-u2}: NOTRUN -> [FAIL][83]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-tgl-u2/igt@runner@aborted.html
New tests
---------
New tests have been introduced between CI_DRM_7141 and Patchwork_14904:
### New IGT tests (1) ###
* igt@i915_selftest@live_gt_heartbeat:
- Statuses : 45 dmesg-fail(s)
- Exec time: [0.37, 2.87] s
Known issues
------------
Here are the changes found in Patchwork_14904 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap@basic-small-bo:
- fi-icl-u3: [PASS][84] -> [DMESG-WARN][85] ([fdo#107724])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7141/fi-icl-u3/igt@gem_mmap@basic-small-bo.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-icl-u3/igt@gem_mmap@basic-small-bo.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][86] -> [FAIL][87] ([fdo#111407])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7141/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- {fi-icl-dsi}: [INCOMPLETE][88] ([fdo#107713] / [fdo#109100]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7141/fi-icl-dsi/igt@gem_ctx_create@basic-files.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-icl-dsi/igt@gem_ctx_create@basic-files.html
* igt@gem_ctx_switch@rcs0:
- {fi-icl-guc}: [INCOMPLETE][90] ([fdo#107713]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7141/fi-icl-guc/igt@gem_ctx_switch@rcs0.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-icl-guc/igt@gem_ctx_switch@rcs0.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-kbl-7500u: [DMESG-WARN][92] ([fdo#105128] / [fdo#107139]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7141/fi-kbl-7500u/igt@gem_exec_suspend@basic-s4-devices.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-kbl-7500u/igt@gem_exec_suspend@basic-s4-devices.html
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [DMESG-WARN][94] ([fdo#107724]) -> [PASS][95] +2 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7141/fi-icl-u3/igt@gem_flink_basic@double-flink.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-icl-u3/igt@gem_flink_basic@double-flink.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][96] ([fdo#102614]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7141/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#105128]: https://bugs.freedesktop.org/show_bug.cgi?id=105128
[fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109644]: https://bugs.freedesktop.org/show_bug.cgi?id=109644
[fdo#110464]: https://bugs.freedesktop.org/show_bug.cgi?id=110464
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (53 -> 46)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7141 -> Patchwork_14904
CI-20190529: 20190529
CI_DRM_7141: a109221528d0b9d4f24065aed372c6b45e251bd6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5235: da9abbab69be80dd00812a4607a4ea2dffcc4544 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14904: 420dc8e008a2f016ac1578584f40108e3d37b835 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
420dc8e008a2 drm/i915/gt: Introduce barrier pulses along engines
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14904/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [CI] drm/i915/gt: Introduce barrier pulses along engines
@ 2019-10-21 17:43 Chris Wilson
0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2019-10-21 17:43 UTC (permalink / raw)
To: intel-gfx
To flush idle barriers, and even inflight requests, we want to send a
preemptive 'pulse' along an engine. We use a no-op request along the
pinned kernel_context at high priority so that it should run or else
kick off the stuck requests. We can use this to ensure idle barriers are
immediately flushed, as part of a context cancellation mechanism, or as
part of a heartbeat mechanism to detect and reset a stuck GPU.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +-
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 77 +++++++++
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 15 ++
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
.../drm/i915/gt/selftest_engine_heartbeat.c | 159 ++++++++++++++++++
drivers/gpu/drm/i915/i915_active.c | 1 +
drivers/gpu/drm/i915/i915_priolist_types.h | 1 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
8 files changed, 257 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
create mode 100644 drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a16a2daef977..2fd4bed188e5 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -78,8 +78,9 @@ gt-y += \
gt/intel_breadcrumbs.o \
gt/intel_context.o \
gt/intel_engine_cs.o \
- gt/intel_engine_pool.o \
+ gt/intel_engine_heartbeat.o \
gt/intel_engine_pm.o \
+ gt/intel_engine_pool.o \
gt/intel_engine_user.o \
gt/intel_gt.o \
gt/intel_gt_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
new file mode 100644
index 000000000000..4b9ab7813d54
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -0,0 +1,77 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "i915_request.h"
+
+#include "intel_context.h"
+#include "intel_engine_heartbeat.h"
+#include "intel_engine_pm.h"
+#include "intel_engine.h"
+#include "intel_gt.h"
+
+static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq)
+{
+ engine->wakeref_serial = READ_ONCE(engine->serial) + 1;
+ i915_request_add_active_barriers(rq);
+}
+
+int intel_engine_pulse(struct intel_engine_cs *engine)
+{
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_BARRIER };
+ struct intel_context *ce = engine->kernel_context;
+ struct i915_request *rq;
+ int err = 0;
+
+ if (!intel_engine_has_preemption(engine))
+ return -ENODEV;
+
+ if (!intel_engine_pm_get_if_awake(engine))
+ return 0;
+
+ if (mutex_lock_interruptible(&ce->timeline->mutex))
+ goto out_rpm;
+
+ intel_context_enter(ce);
+ rq = __i915_request_create(ce, GFP_NOWAIT | __GFP_NOWARN);
+ intel_context_exit(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_unlock;
+ }
+
+ rq->flags |= I915_REQUEST_SENTINEL;
+ idle_pulse(engine, rq);
+
+ __i915_request_commit(rq);
+ __i915_request_queue(rq, &attr);
+
+out_unlock:
+ mutex_unlock(&ce->timeline->mutex);
+out_rpm:
+ intel_engine_pm_put(engine);
+ return err;
+}
+
+int intel_engine_flush_barriers(struct intel_engine_cs *engine)
+{
+ struct i915_request *rq;
+
+ if (llist_empty(&engine->barrier_tasks))
+ return 0;
+
+ rq = i915_request_create(engine->kernel_context);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ idle_pulse(engine, rq);
+ i915_request_add(rq);
+
+ return 0;
+}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_engine_heartbeat.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
new file mode 100644
index 000000000000..b334e5aaf78d
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef INTEL_ENGINE_HEARTBEAT_H
+#define INTEL_ENGINE_HEARTBEAT_H
+
+struct intel_engine_cs;
+
+int intel_engine_pulse(struct intel_engine_cs *engine);
+int intel_engine_flush_barriers(struct intel_engine_cs *engine);
+
+#endif /* INTEL_ENGINE_HEARTBEAT_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 67eb6183648a..7d76611d9df1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -111,7 +111,7 @@ static bool switch_to_kernel_context(struct intel_engine_cs *engine)
i915_request_add_active_barriers(rq);
/* Install ourselves as a preemption barrier */
- rq->sched.attr.priority = I915_PRIORITY_UNPREEMPTABLE;
+ rq->sched.attr.priority = I915_PRIORITY_BARRIER;
__i915_request_commit(rq);
/* Release our exclusive hold on the engine */
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
new file mode 100644
index 000000000000..1f5ab59ad6e7
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
@@ -0,0 +1,159 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#include "i915_drv.h"
+
+#include "intel_gt_requests.h"
+#include "i915_selftest.h"
+
+struct pulse {
+ struct i915_active active;
+ struct kref kref;
+};
+
+static int pulse_active(struct i915_active *active)
+{
+ kref_get(&container_of(active, struct pulse, active)->kref);
+ return 0;
+}
+
+static void pulse_free(struct kref *kref)
+{
+ kfree(container_of(kref, struct pulse, kref));
+}
+
+static void pulse_put(struct pulse *p)
+{
+ kref_put(&p->kref, pulse_free);
+}
+
+static void pulse_retire(struct i915_active *active)
+{
+ pulse_put(container_of(active, struct pulse, active));
+}
+
+static struct pulse *pulse_create(void)
+{
+ struct pulse *p;
+
+ p = kmalloc(sizeof(*p), GFP_KERNEL);
+ if (!p)
+ return p;
+
+ kref_init(&p->kref);
+ i915_active_init(&p->active, pulse_active, pulse_retire);
+
+ return p;
+}
+
+static int __live_idle_pulse(struct intel_engine_cs *engine,
+ int (*fn)(struct intel_engine_cs *cs))
+{
+ struct pulse *p;
+ int err;
+
+ p = pulse_create();
+ if (!p)
+ return -ENOMEM;
+
+ err = i915_active_acquire(&p->active);
+ if (err)
+ goto out;
+
+ err = i915_active_acquire_preallocate_barrier(&p->active, engine);
+ if (err) {
+ i915_active_release(&p->active);
+ goto out;
+ }
+
+ i915_active_acquire_barrier(&p->active);
+ i915_active_release(&p->active);
+
+ GEM_BUG_ON(i915_active_is_idle(&p->active));
+
+ err = fn(engine);
+ if (err)
+ goto out;
+
+ if (intel_gt_retire_requests_timeout(engine->gt, HZ / 5)) {
+ err = -ETIME;
+ goto out;
+ }
+
+ if (!i915_active_is_idle(&p->active)) {
+ pr_err("%s: heartbeat pulse did not flush idle tasks\n",
+ engine->name);
+ err = -EINVAL;
+ goto out;
+ }
+
+out:
+ pulse_put(p);
+ return err;
+}
+
+static int live_idle_flush(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /* Check that we can flush the idle barriers */
+
+ for_each_engine(engine, gt, id) {
+ intel_engine_pm_get(engine);
+ err = __live_idle_pulse(engine, intel_engine_flush_barriers);
+ intel_engine_pm_put(engine);
+ if (err)
+ break;
+ }
+
+ return err;
+}
+
+static int live_idle_pulse(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /* Check that heartbeat pulses flush the idle barriers */
+
+ for_each_engine(engine, gt, id) {
+ intel_engine_pm_get(engine);
+ err = __live_idle_pulse(engine, intel_engine_pulse);
+ intel_engine_pm_put(engine);
+ if (err && err != -ENODEV)
+ break;
+
+ err = 0;
+ }
+
+ return err;
+}
+
+int intel_heartbeat_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(live_idle_flush),
+ SUBTEST(live_idle_pulse),
+ };
+ int saved_hangcheck;
+ int err;
+
+ if (intel_gt_is_wedged(&i915->gt))
+ return 0;
+
+ saved_hangcheck = i915_modparams.enable_hangcheck;
+ i915_modparams.enable_hangcheck = INT_MAX;
+
+ err = intel_gt_live_subtests(tests, &i915->gt);
+
+ i915_modparams.enable_hangcheck = saved_hangcheck;
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/i915_active.c b/drivers/gpu/drm/i915/i915_active.c
index 7927b1a0c7a6..07d39f22a2c3 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -595,6 +595,7 @@ int i915_active_acquire_preallocate_barrier(struct i915_active *ref,
struct llist_node *pos, *next;
int err;
+ GEM_BUG_ON(i915_active_is_idle(ref));
GEM_BUG_ON(!llist_empty(&ref->preallocated_barriers));
/*
diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h b/drivers/gpu/drm/i915/i915_priolist_types.h
index 21037a2e2038..ae8bb3cb627e 100644
--- a/drivers/gpu/drm/i915/i915_priolist_types.h
+++ b/drivers/gpu/drm/i915/i915_priolist_types.h
@@ -39,6 +39,7 @@ enum {
* active request.
*/
#define I915_PRIORITY_UNPREEMPTABLE INT_MAX
+#define I915_PRIORITY_BARRIER INT_MAX
#define __NO_PREEMPTION (I915_PRIORITY_WAIT)
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 6daf6599ec79..00a063730bc3 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -17,6 +17,7 @@ selftest(gt_timelines, intel_timeline_live_selftests)
selftest(gt_contexts, intel_context_live_selftests)
selftest(gt_lrc, intel_lrc_live_selftests)
selftest(gt_pm, intel_gt_pm_live_selftests)
+selftest(gt_heartbeat, intel_heartbeat_live_selftests)
selftest(requests, i915_request_live_selftests)
selftest(active, i915_active_live_selftests)
selftest(objects, i915_gem_object_live_selftests)
--
2.24.0.rc0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [CI] drm/i915/gt: Introduce barrier pulses along engines
@ 2019-10-21 15:56 Chris Wilson
0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2019-10-21 15:56 UTC (permalink / raw)
To: intel-gfx
To flush idle barriers, and even inflight requests, we want to send a
preemptive 'pulse' along an engine. We use a no-op request along the
pinned kernel_context at high priority so that it should run or else
kick off the stuck requests. We can use this to ensure idle barriers are
immediately flushed, as part of a context cancellation mechanism, or as
part of a heartbeat mechanism to detect and reset a stuck GPU.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +-
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 77 +++++++++
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 15 ++
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
.../drm/i915/gt/selftest_engine_heartbeat.c | 154 ++++++++++++++++++
drivers/gpu/drm/i915/i915_priolist_types.h | 1 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
7 files changed, 251 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
create mode 100644 drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a16a2daef977..2fd4bed188e5 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -78,8 +78,9 @@ gt-y += \
gt/intel_breadcrumbs.o \
gt/intel_context.o \
gt/intel_engine_cs.o \
- gt/intel_engine_pool.o \
+ gt/intel_engine_heartbeat.o \
gt/intel_engine_pm.o \
+ gt/intel_engine_pool.o \
gt/intel_engine_user.o \
gt/intel_gt.o \
gt/intel_gt_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
new file mode 100644
index 000000000000..4b9ab7813d54
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -0,0 +1,77 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "i915_request.h"
+
+#include "intel_context.h"
+#include "intel_engine_heartbeat.h"
+#include "intel_engine_pm.h"
+#include "intel_engine.h"
+#include "intel_gt.h"
+
+static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq)
+{
+ engine->wakeref_serial = READ_ONCE(engine->serial) + 1;
+ i915_request_add_active_barriers(rq);
+}
+
+int intel_engine_pulse(struct intel_engine_cs *engine)
+{
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_BARRIER };
+ struct intel_context *ce = engine->kernel_context;
+ struct i915_request *rq;
+ int err = 0;
+
+ if (!intel_engine_has_preemption(engine))
+ return -ENODEV;
+
+ if (!intel_engine_pm_get_if_awake(engine))
+ return 0;
+
+ if (mutex_lock_interruptible(&ce->timeline->mutex))
+ goto out_rpm;
+
+ intel_context_enter(ce);
+ rq = __i915_request_create(ce, GFP_NOWAIT | __GFP_NOWARN);
+ intel_context_exit(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_unlock;
+ }
+
+ rq->flags |= I915_REQUEST_SENTINEL;
+ idle_pulse(engine, rq);
+
+ __i915_request_commit(rq);
+ __i915_request_queue(rq, &attr);
+
+out_unlock:
+ mutex_unlock(&ce->timeline->mutex);
+out_rpm:
+ intel_engine_pm_put(engine);
+ return err;
+}
+
+int intel_engine_flush_barriers(struct intel_engine_cs *engine)
+{
+ struct i915_request *rq;
+
+ if (llist_empty(&engine->barrier_tasks))
+ return 0;
+
+ rq = i915_request_create(engine->kernel_context);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ idle_pulse(engine, rq);
+ i915_request_add(rq);
+
+ return 0;
+}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_engine_heartbeat.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
new file mode 100644
index 000000000000..b334e5aaf78d
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef INTEL_ENGINE_HEARTBEAT_H
+#define INTEL_ENGINE_HEARTBEAT_H
+
+struct intel_engine_cs;
+
+int intel_engine_pulse(struct intel_engine_cs *engine);
+int intel_engine_flush_barriers(struct intel_engine_cs *engine);
+
+#endif /* INTEL_ENGINE_HEARTBEAT_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 67eb6183648a..7d76611d9df1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -111,7 +111,7 @@ static bool switch_to_kernel_context(struct intel_engine_cs *engine)
i915_request_add_active_barriers(rq);
/* Install ourselves as a preemption barrier */
- rq->sched.attr.priority = I915_PRIORITY_UNPREEMPTABLE;
+ rq->sched.attr.priority = I915_PRIORITY_BARRIER;
__i915_request_commit(rq);
/* Release our exclusive hold on the engine */
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
new file mode 100644
index 000000000000..10724d98e796
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
@@ -0,0 +1,154 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#include "i915_drv.h"
+
+#include "intel_gt_requests.h"
+#include "i915_selftest.h"
+
+struct pulse {
+ struct i915_active active;
+ struct kref kref;
+};
+
+static int pulse_active(struct i915_active *active)
+{
+ kref_get(&container_of(active, struct pulse, active)->kref);
+ return 0;
+}
+
+static void pulse_free(struct kref *kref)
+{
+ kfree(container_of(kref, struct pulse, kref));
+}
+
+static void pulse_put(struct pulse *p)
+{
+ kref_put(&p->kref, pulse_free);
+}
+
+static void pulse_retire(struct i915_active *active)
+{
+ pulse_put(container_of(active, struct pulse, active));
+}
+
+static struct pulse *pulse_create(void)
+{
+ struct pulse *p;
+
+ p = kmalloc(sizeof(*p), GFP_KERNEL);
+ if (!p)
+ return p;
+
+ kref_init(&p->kref);
+ i915_active_init(&p->active, pulse_active, pulse_retire);
+
+ return p;
+}
+
+static int __live_idle_pulse(struct intel_engine_cs *engine,
+ int (*fn)(struct intel_engine_cs *cs))
+{
+ struct pulse *p;
+ int err;
+
+ GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
+
+ p = pulse_create();
+ if (!p)
+ return -ENOMEM;
+
+ err = i915_active_acquire_preallocate_barrier(&p->active, engine);
+ if (err)
+ goto out;
+
+ i915_active_acquire_barrier(&p->active);
+
+ err = fn(engine);
+ if (err) {
+ llist_del_all(&engine->barrier_tasks);
+ goto out;
+ }
+
+ if (intel_gt_retire_requests_timeout(engine->gt, HZ / 5)) {
+ err = -ETIME;
+ goto out;
+ }
+
+ if (atomic_read(&p->active.count)) {
+ pr_err("%s: heartbeat pulse did not flush idle tasks\n",
+ engine->name);
+ err = -EINVAL;
+ goto out;
+ }
+
+out:
+ pulse_put(p);
+ return err;
+}
+
+static int live_idle_flush(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /* Check that we can flush the idle barriers */
+
+ for_each_engine(engine, gt, id) {
+ intel_engine_pm_get(engine);
+ err = __live_idle_pulse(engine, intel_engine_flush_barriers);
+ intel_engine_pm_put(engine);
+ if (err)
+ break;
+ }
+
+ return err;
+}
+
+static int live_idle_pulse(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /* Check that heartbeat pulses flush the idle barriers */
+
+ for_each_engine(engine, gt, id) {
+ intel_engine_pm_get(engine);
+ err = __live_idle_pulse(engine, intel_engine_pulse);
+ intel_engine_pm_put(engine);
+ if (err && err != -ENODEV)
+ break;
+
+ err = 0;
+ }
+
+ return err;
+}
+
+int intel_heartbeat_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(live_idle_flush),
+ SUBTEST(live_idle_pulse),
+ };
+ int saved_hangcheck;
+ int err;
+
+ if (intel_gt_is_wedged(&i915->gt))
+ return 0;
+
+ saved_hangcheck = i915_modparams.enable_hangcheck;
+ i915_modparams.enable_hangcheck = INT_MAX;
+
+ err = intel_gt_live_subtests(tests, &i915->gt);
+
+ i915_modparams.enable_hangcheck = saved_hangcheck;
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h b/drivers/gpu/drm/i915/i915_priolist_types.h
index 21037a2e2038..ae8bb3cb627e 100644
--- a/drivers/gpu/drm/i915/i915_priolist_types.h
+++ b/drivers/gpu/drm/i915/i915_priolist_types.h
@@ -39,6 +39,7 @@ enum {
* active request.
*/
#define I915_PRIORITY_UNPREEMPTABLE INT_MAX
+#define I915_PRIORITY_BARRIER INT_MAX
#define __NO_PREEMPTION (I915_PRIORITY_WAIT)
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 6daf6599ec79..00a063730bc3 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -17,6 +17,7 @@ selftest(gt_timelines, intel_timeline_live_selftests)
selftest(gt_contexts, intel_context_live_selftests)
selftest(gt_lrc, intel_lrc_live_selftests)
selftest(gt_pm, intel_gt_pm_live_selftests)
+selftest(gt_heartbeat, intel_heartbeat_live_selftests)
selftest(requests, i915_request_live_selftests)
selftest(active, i915_active_live_selftests)
selftest(objects, i915_gem_object_live_selftests)
--
2.24.0.rc0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [CI] drm/i915/gt: Introduce barrier pulses along engines
@ 2019-10-21 14:13 Chris Wilson
0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2019-10-21 14:13 UTC (permalink / raw)
To: intel-gfx
To flush idle barriers, and even inflight requests, we want to send a
preemptive 'pulse' along an engine. We use a no-op request along the
pinned kernel_context at high priority so that it should run or else
kick off the stuck requests. We can use this to ensure idle barriers are
immediately flushed, as part of a context cancellation mechanism, or as
part of a heartbeat mechanism to detect and reset a stuck GPU.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +-
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 77 ++++++++++++
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 15 +++
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
.../drm/i915/gt/selftest_engine_heartbeat.c | 110 ++++++++++++++++++
drivers/gpu/drm/i915/i915_priolist_types.h | 1 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
7 files changed, 207 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
create mode 100644 drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a16a2daef977..2fd4bed188e5 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -78,8 +78,9 @@ gt-y += \
gt/intel_breadcrumbs.o \
gt/intel_context.o \
gt/intel_engine_cs.o \
- gt/intel_engine_pool.o \
+ gt/intel_engine_heartbeat.o \
gt/intel_engine_pm.o \
+ gt/intel_engine_pool.o \
gt/intel_engine_user.o \
gt/intel_gt.o \
gt/intel_gt_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
new file mode 100644
index 000000000000..4b9ab7813d54
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -0,0 +1,77 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "i915_request.h"
+
+#include "intel_context.h"
+#include "intel_engine_heartbeat.h"
+#include "intel_engine_pm.h"
+#include "intel_engine.h"
+#include "intel_gt.h"
+
+static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq)
+{
+ engine->wakeref_serial = READ_ONCE(engine->serial) + 1;
+ i915_request_add_active_barriers(rq);
+}
+
+int intel_engine_pulse(struct intel_engine_cs *engine)
+{
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_BARRIER };
+ struct intel_context *ce = engine->kernel_context;
+ struct i915_request *rq;
+ int err = 0;
+
+ if (!intel_engine_has_preemption(engine))
+ return -ENODEV;
+
+ if (!intel_engine_pm_get_if_awake(engine))
+ return 0;
+
+ if (mutex_lock_interruptible(&ce->timeline->mutex))
+ goto out_rpm;
+
+ intel_context_enter(ce);
+ rq = __i915_request_create(ce, GFP_NOWAIT | __GFP_NOWARN);
+ intel_context_exit(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_unlock;
+ }
+
+ rq->flags |= I915_REQUEST_SENTINEL;
+ idle_pulse(engine, rq);
+
+ __i915_request_commit(rq);
+ __i915_request_queue(rq, &attr);
+
+out_unlock:
+ mutex_unlock(&ce->timeline->mutex);
+out_rpm:
+ intel_engine_pm_put(engine);
+ return err;
+}
+
+int intel_engine_flush_barriers(struct intel_engine_cs *engine)
+{
+ struct i915_request *rq;
+
+ if (llist_empty(&engine->barrier_tasks))
+ return 0;
+
+ rq = i915_request_create(engine->kernel_context);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ idle_pulse(engine, rq);
+ i915_request_add(rq);
+
+ return 0;
+}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_engine_heartbeat.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
new file mode 100644
index 000000000000..b334e5aaf78d
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef INTEL_ENGINE_HEARTBEAT_H
+#define INTEL_ENGINE_HEARTBEAT_H
+
+struct intel_engine_cs;
+
+int intel_engine_pulse(struct intel_engine_cs *engine);
+int intel_engine_flush_barriers(struct intel_engine_cs *engine);
+
+#endif /* INTEL_ENGINE_HEARTBEAT_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 67eb6183648a..7d76611d9df1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -111,7 +111,7 @@ static bool switch_to_kernel_context(struct intel_engine_cs *engine)
i915_request_add_active_barriers(rq);
/* Install ourselves as a preemption barrier */
- rq->sched.attr.priority = I915_PRIORITY_UNPREEMPTABLE;
+ rq->sched.attr.priority = I915_PRIORITY_BARRIER;
__i915_request_commit(rq);
/* Release our exclusive hold on the engine */
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
new file mode 100644
index 000000000000..49c683d3b244
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
@@ -0,0 +1,110 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#include "i915_drv.h"
+
+#include "intel_gt_requests.h"
+#include "i915_selftest.h"
+
+static int __live_idle_pulse(struct intel_engine_cs *engine,
+ int (*fn)(struct intel_engine_cs *cs))
+{
+ struct i915_active ref;
+ int err;
+
+ GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
+
+ i915_active_init(&ref, NULL, NULL);
+
+ err = i915_active_acquire_preallocate_barrier(&ref, engine);
+ if (err)
+ return err;
+
+ i915_active_acquire_barrier(&ref);
+
+ err = fn(engine);
+ if (err) {
+ llist_del_all(&engine->barrier_tasks);
+ return err;
+ }
+
+ if (intel_gt_retire_requests_timeout(engine->gt, HZ / 5)) {
+ intel_gt_set_wedged(engine->gt);
+ return -ETIME; /* leaking struct i915_active!!! */
+ }
+
+ if (atomic_read(&ref.count)) {
+ pr_err("%s: heartbeat pulse did not flush idle tasks\n",
+ engine->name);
+ intel_gt_set_wedged(engine->gt);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int live_idle_flush(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /* Check that we can flush the idle barriers */
+
+ for_each_engine(engine, gt, id) {
+ intel_engine_pm_get(engine);
+ err = __live_idle_pulse(engine, intel_engine_flush_barriers);
+ intel_engine_pm_put(engine);
+ if (err)
+ break;
+ }
+
+ return err;
+}
+
+static int live_idle_pulse(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /* Check that heartbeat pulses flush the idle barriers */
+
+ for_each_engine(engine, gt, id) {
+ intel_engine_pm_get(engine);
+ err = __live_idle_pulse(engine, intel_engine_pulse);
+ intel_engine_pm_put(engine);
+ if (err && err != -ENODEV)
+ break;
+
+ err = 0;
+ }
+
+ return err;
+}
+
+int intel_heartbeat_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(live_idle_flush),
+ SUBTEST(live_idle_pulse),
+ };
+ int saved_hangcheck;
+ int err;
+
+ if (intel_gt_is_wedged(&i915->gt))
+ return 0;
+
+ saved_hangcheck = i915_modparams.enable_hangcheck;
+ i915_modparams.enable_hangcheck = INT_MAX;
+
+ err = intel_gt_live_subtests(tests, &i915->gt);
+
+ i915_modparams.enable_hangcheck = saved_hangcheck;
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h b/drivers/gpu/drm/i915/i915_priolist_types.h
index 21037a2e2038..ae8bb3cb627e 100644
--- a/drivers/gpu/drm/i915/i915_priolist_types.h
+++ b/drivers/gpu/drm/i915/i915_priolist_types.h
@@ -39,6 +39,7 @@ enum {
* active request.
*/
#define I915_PRIORITY_UNPREEMPTABLE INT_MAX
+#define I915_PRIORITY_BARRIER INT_MAX
#define __NO_PREEMPTION (I915_PRIORITY_WAIT)
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 6daf6599ec79..00a063730bc3 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -17,6 +17,7 @@ selftest(gt_timelines, intel_timeline_live_selftests)
selftest(gt_contexts, intel_context_live_selftests)
selftest(gt_lrc, intel_lrc_live_selftests)
selftest(gt_pm, intel_gt_pm_live_selftests)
+selftest(gt_heartbeat, intel_heartbeat_live_selftests)
selftest(requests, i915_request_live_selftests)
selftest(active, i915_active_live_selftests)
selftest(objects, i915_gem_object_live_selftests)
--
2.24.0.rc0
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^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-10-21 17:43 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-21 16:08 [CI] drm/i915/gt: Introduce barrier pulses along engines Chris Wilson
2019-10-21 16:24 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Introduce barrier pulses along engines (rev3) Patchwork
2019-10-21 16:48 ` ✗ Fi.CI.BAT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2019-10-21 17:43 [CI] drm/i915/gt: Introduce barrier pulses along engines Chris Wilson
2019-10-21 15:56 Chris Wilson
2019-10-21 14:13 Chris Wilson
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