* [CI] drm/i915/gt: Introduce barrier pulses along engines
@ 2019-10-21 17:43 Chris Wilson
2019-10-21 19:13 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Introduce barrier pulses along engines (rev4) Patchwork
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Chris Wilson @ 2019-10-21 17:43 UTC (permalink / raw)
To: intel-gfx
To flush idle barriers, and even inflight requests, we want to send a
preemptive 'pulse' along an engine. We use a no-op request along the
pinned kernel_context at high priority so that it should run or else
kick off the stuck requests. We can use this to ensure idle barriers are
immediately flushed, as part of a context cancellation mechanism, or as
part of a heartbeat mechanism to detect and reset a stuck GPU.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +-
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 77 +++++++++
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 15 ++
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
.../drm/i915/gt/selftest_engine_heartbeat.c | 159 ++++++++++++++++++
drivers/gpu/drm/i915/i915_active.c | 1 +
drivers/gpu/drm/i915/i915_priolist_types.h | 1 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
8 files changed, 257 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
create mode 100644 drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a16a2daef977..2fd4bed188e5 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -78,8 +78,9 @@ gt-y += \
gt/intel_breadcrumbs.o \
gt/intel_context.o \
gt/intel_engine_cs.o \
- gt/intel_engine_pool.o \
+ gt/intel_engine_heartbeat.o \
gt/intel_engine_pm.o \
+ gt/intel_engine_pool.o \
gt/intel_engine_user.o \
gt/intel_gt.o \
gt/intel_gt_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
new file mode 100644
index 000000000000..4b9ab7813d54
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -0,0 +1,77 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "i915_request.h"
+
+#include "intel_context.h"
+#include "intel_engine_heartbeat.h"
+#include "intel_engine_pm.h"
+#include "intel_engine.h"
+#include "intel_gt.h"
+
+static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq)
+{
+ engine->wakeref_serial = READ_ONCE(engine->serial) + 1;
+ i915_request_add_active_barriers(rq);
+}
+
+int intel_engine_pulse(struct intel_engine_cs *engine)
+{
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_BARRIER };
+ struct intel_context *ce = engine->kernel_context;
+ struct i915_request *rq;
+ int err = 0;
+
+ if (!intel_engine_has_preemption(engine))
+ return -ENODEV;
+
+ if (!intel_engine_pm_get_if_awake(engine))
+ return 0;
+
+ if (mutex_lock_interruptible(&ce->timeline->mutex))
+ goto out_rpm;
+
+ intel_context_enter(ce);
+ rq = __i915_request_create(ce, GFP_NOWAIT | __GFP_NOWARN);
+ intel_context_exit(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_unlock;
+ }
+
+ rq->flags |= I915_REQUEST_SENTINEL;
+ idle_pulse(engine, rq);
+
+ __i915_request_commit(rq);
+ __i915_request_queue(rq, &attr);
+
+out_unlock:
+ mutex_unlock(&ce->timeline->mutex);
+out_rpm:
+ intel_engine_pm_put(engine);
+ return err;
+}
+
+int intel_engine_flush_barriers(struct intel_engine_cs *engine)
+{
+ struct i915_request *rq;
+
+ if (llist_empty(&engine->barrier_tasks))
+ return 0;
+
+ rq = i915_request_create(engine->kernel_context);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ idle_pulse(engine, rq);
+ i915_request_add(rq);
+
+ return 0;
+}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_engine_heartbeat.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
new file mode 100644
index 000000000000..b334e5aaf78d
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef INTEL_ENGINE_HEARTBEAT_H
+#define INTEL_ENGINE_HEARTBEAT_H
+
+struct intel_engine_cs;
+
+int intel_engine_pulse(struct intel_engine_cs *engine);
+int intel_engine_flush_barriers(struct intel_engine_cs *engine);
+
+#endif /* INTEL_ENGINE_HEARTBEAT_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 67eb6183648a..7d76611d9df1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -111,7 +111,7 @@ static bool switch_to_kernel_context(struct intel_engine_cs *engine)
i915_request_add_active_barriers(rq);
/* Install ourselves as a preemption barrier */
- rq->sched.attr.priority = I915_PRIORITY_UNPREEMPTABLE;
+ rq->sched.attr.priority = I915_PRIORITY_BARRIER;
__i915_request_commit(rq);
/* Release our exclusive hold on the engine */
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
new file mode 100644
index 000000000000..1f5ab59ad6e7
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
@@ -0,0 +1,159 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#include "i915_drv.h"
+
+#include "intel_gt_requests.h"
+#include "i915_selftest.h"
+
+struct pulse {
+ struct i915_active active;
+ struct kref kref;
+};
+
+static int pulse_active(struct i915_active *active)
+{
+ kref_get(&container_of(active, struct pulse, active)->kref);
+ return 0;
+}
+
+static void pulse_free(struct kref *kref)
+{
+ kfree(container_of(kref, struct pulse, kref));
+}
+
+static void pulse_put(struct pulse *p)
+{
+ kref_put(&p->kref, pulse_free);
+}
+
+static void pulse_retire(struct i915_active *active)
+{
+ pulse_put(container_of(active, struct pulse, active));
+}
+
+static struct pulse *pulse_create(void)
+{
+ struct pulse *p;
+
+ p = kmalloc(sizeof(*p), GFP_KERNEL);
+ if (!p)
+ return p;
+
+ kref_init(&p->kref);
+ i915_active_init(&p->active, pulse_active, pulse_retire);
+
+ return p;
+}
+
+static int __live_idle_pulse(struct intel_engine_cs *engine,
+ int (*fn)(struct intel_engine_cs *cs))
+{
+ struct pulse *p;
+ int err;
+
+ p = pulse_create();
+ if (!p)
+ return -ENOMEM;
+
+ err = i915_active_acquire(&p->active);
+ if (err)
+ goto out;
+
+ err = i915_active_acquire_preallocate_barrier(&p->active, engine);
+ if (err) {
+ i915_active_release(&p->active);
+ goto out;
+ }
+
+ i915_active_acquire_barrier(&p->active);
+ i915_active_release(&p->active);
+
+ GEM_BUG_ON(i915_active_is_idle(&p->active));
+
+ err = fn(engine);
+ if (err)
+ goto out;
+
+ if (intel_gt_retire_requests_timeout(engine->gt, HZ / 5)) {
+ err = -ETIME;
+ goto out;
+ }
+
+ if (!i915_active_is_idle(&p->active)) {
+ pr_err("%s: heartbeat pulse did not flush idle tasks\n",
+ engine->name);
+ err = -EINVAL;
+ goto out;
+ }
+
+out:
+ pulse_put(p);
+ return err;
+}
+
+static int live_idle_flush(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /* Check that we can flush the idle barriers */
+
+ for_each_engine(engine, gt, id) {
+ intel_engine_pm_get(engine);
+ err = __live_idle_pulse(engine, intel_engine_flush_barriers);
+ intel_engine_pm_put(engine);
+ if (err)
+ break;
+ }
+
+ return err;
+}
+
+static int live_idle_pulse(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /* Check that heartbeat pulses flush the idle barriers */
+
+ for_each_engine(engine, gt, id) {
+ intel_engine_pm_get(engine);
+ err = __live_idle_pulse(engine, intel_engine_pulse);
+ intel_engine_pm_put(engine);
+ if (err && err != -ENODEV)
+ break;
+
+ err = 0;
+ }
+
+ return err;
+}
+
+int intel_heartbeat_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(live_idle_flush),
+ SUBTEST(live_idle_pulse),
+ };
+ int saved_hangcheck;
+ int err;
+
+ if (intel_gt_is_wedged(&i915->gt))
+ return 0;
+
+ saved_hangcheck = i915_modparams.enable_hangcheck;
+ i915_modparams.enable_hangcheck = INT_MAX;
+
+ err = intel_gt_live_subtests(tests, &i915->gt);
+
+ i915_modparams.enable_hangcheck = saved_hangcheck;
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/i915_active.c b/drivers/gpu/drm/i915/i915_active.c
index 7927b1a0c7a6..07d39f22a2c3 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -595,6 +595,7 @@ int i915_active_acquire_preallocate_barrier(struct i915_active *ref,
struct llist_node *pos, *next;
int err;
+ GEM_BUG_ON(i915_active_is_idle(ref));
GEM_BUG_ON(!llist_empty(&ref->preallocated_barriers));
/*
diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h b/drivers/gpu/drm/i915/i915_priolist_types.h
index 21037a2e2038..ae8bb3cb627e 100644
--- a/drivers/gpu/drm/i915/i915_priolist_types.h
+++ b/drivers/gpu/drm/i915/i915_priolist_types.h
@@ -39,6 +39,7 @@ enum {
* active request.
*/
#define I915_PRIORITY_UNPREEMPTABLE INT_MAX
+#define I915_PRIORITY_BARRIER INT_MAX
#define __NO_PREEMPTION (I915_PRIORITY_WAIT)
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 6daf6599ec79..00a063730bc3 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -17,6 +17,7 @@ selftest(gt_timelines, intel_timeline_live_selftests)
selftest(gt_contexts, intel_context_live_selftests)
selftest(gt_lrc, intel_lrc_live_selftests)
selftest(gt_pm, intel_gt_pm_live_selftests)
+selftest(gt_heartbeat, intel_heartbeat_live_selftests)
selftest(requests, i915_request_live_selftests)
selftest(active, i915_active_live_selftests)
selftest(objects, i915_gem_object_live_selftests)
--
2.24.0.rc0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Introduce barrier pulses along engines (rev4)
2019-10-21 17:43 [CI] drm/i915/gt: Introduce barrier pulses along engines Chris Wilson
@ 2019-10-21 19:13 ` Patchwork
2019-10-21 19:55 ` ✓ Fi.CI.BAT: success " Patchwork
2019-10-22 1:24 ` ✗ Fi.CI.IGT: failure " Patchwork
2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2019-10-21 19:13 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt: Introduce barrier pulses along engines (rev4)
URL : https://patchwork.freedesktop.org/series/68309/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1b7f5f7aef7e drm/i915/gt: Introduce barrier pulses along engines
-:32: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#32:
new file mode 100644
-:37: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#37: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:1:
+/*
-:38: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#38: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:2:
+ * SPDX-License-Identifier: MIT
-:120: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#120: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h:1:
+/*
-:121: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#121: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h:2:
+ * SPDX-License-Identifier: MIT
-:154: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#154: FILE: drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c:1:
+/*
-:155: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#155: FILE: drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c:2:
+ * SPDX-License-Identifier: MIT
total: 0 errors, 7 warnings, 0 checks, 290 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/gt: Introduce barrier pulses along engines (rev4)
2019-10-21 17:43 [CI] drm/i915/gt: Introduce barrier pulses along engines Chris Wilson
2019-10-21 19:13 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Introduce barrier pulses along engines (rev4) Patchwork
@ 2019-10-21 19:55 ` Patchwork
2019-10-22 1:24 ` ✗ Fi.CI.IGT: failure " Patchwork
2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2019-10-21 19:55 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt: Introduce barrier pulses along engines (rev4)
URL : https://patchwork.freedesktop.org/series/68309/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7142 -> Patchwork_14906
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/index.html
New tests
---------
New tests have been introduced between CI_DRM_7142 and Patchwork_14906:
### New IGT tests (1) ###
* igt@i915_selftest@live_gt_heartbeat:
- Statuses : 45 pass(s)
- Exec time: [0.38, 2.35] s
Known issues
------------
Here are the changes found in Patchwork_14906 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
* igt@i915_selftest@live_hangcheck:
- fi-bsw-n3050: [PASS][3] -> [INCOMPLETE][4] ([fdo#105876])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/fi-bsw-n3050/igt@i915_selftest@live_hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/fi-bsw-n3050/igt@i915_selftest@live_hangcheck.html
#### Possible fixes ####
* igt@gem_basic@create-close:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/fi-icl-u3/igt@gem_basic@create-close.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/fi-icl-u3/igt@gem_basic@create-close.html
* igt@gem_ctx_create@basic-files:
- fi-bdw-gvtdvm: [DMESG-WARN][7] ([fdo#112064]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/fi-bdw-gvtdvm/igt@gem_ctx_create@basic-files.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/fi-bdw-gvtdvm/igt@gem_ctx_create@basic-files.html
- {fi-icl-guc}: [INCOMPLETE][9] ([fdo#107713] / [fdo#109100]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/fi-icl-guc/igt@gem_ctx_create@basic-files.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/fi-icl-guc/igt@gem_ctx_create@basic-files.html
* igt@gem_ctx_switch@rcs0:
- fi-cml-u: [INCOMPLETE][11] ([fdo#110566]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/fi-cml-u/igt@gem_ctx_switch@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/fi-cml-u/igt@gem_ctx_switch@rcs0.html
* igt@gem_exec_gttfill@basic:
- {fi-icl-dsi}: [DMESG-WARN][13] ([fdo#106107]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/fi-icl-dsi/igt@gem_exec_gttfill@basic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/fi-icl-dsi/igt@gem_exec_gttfill@basic.html
* igt@i915_selftest@live_coherency:
- fi-cfl-8109u: [TIMEOUT][15] -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/fi-cfl-8109u/igt@i915_selftest@live_coherency.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/fi-cfl-8109u/igt@i915_selftest@live_coherency.html
#### Warnings ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#111407]) -> [FAIL][18] ([fdo#111045] / [fdo#111096])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#105876]: https://bugs.freedesktop.org/show_bug.cgi?id=105876
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#112064]: https://bugs.freedesktop.org/show_bug.cgi?id=112064
Participating hosts (52 -> 46)
------------------------------
Additional (1): fi-icl-u2
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7142 -> Patchwork_14906
CI-20190529: 20190529
CI_DRM_7142: 639c81d1ccbabfd8421709509bf5052213198307 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5235: da9abbab69be80dd00812a4607a4ea2dffcc4544 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14906: 1b7f5f7aef7e0168dd500756bbd2bfd2bfd58341 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1b7f5f7aef7e drm/i915/gt: Introduce barrier pulses along engines
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915/gt: Introduce barrier pulses along engines (rev4)
2019-10-21 17:43 [CI] drm/i915/gt: Introduce barrier pulses along engines Chris Wilson
2019-10-21 19:13 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Introduce barrier pulses along engines (rev4) Patchwork
2019-10-21 19:55 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-10-22 1:24 ` Patchwork
2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2019-10-22 1:24 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt: Introduce barrier pulses along engines (rev4)
URL : https://patchwork.freedesktop.org/series/68309/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7142_full -> Patchwork_14906_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14906_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14906_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14906_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_eio@in-flight-contexts-10ms:
- shard-snb: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-snb1/igt@gem_eio@in-flight-contexts-10ms.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-snb2/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive:
- shard-apl: NOTRUN -> [TIMEOUT][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-apl3/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_ctx_shared@exec-single-timeline-bsd2:
- {shard-tglb}: [PASS][4] -> [INCOMPLETE][5] +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-tglb5/igt@gem_ctx_shared@exec-single-timeline-bsd2.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-tglb8/igt@gem_ctx_shared@exec-single-timeline-bsd2.html
* igt@gem_ctx_switch@legacy-default-queue:
- {shard-tglb}: NOTRUN -> [INCOMPLETE][6]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-tglb8/igt@gem_ctx_switch@legacy-default-queue.html
Known issues
------------
Here are the changes found in Patchwork_14906_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@vcs1-none:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [fdo#112080]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-iclb1/igt@gem_ctx_isolation@vcs1-none.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-iclb5/igt@gem_ctx_isolation@vcs1-none.html
* igt@gem_ctx_shared@q-smoketest-bsd2:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +10 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-iclb4/igt@gem_ctx_shared@q-smoketest-bsd2.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-iclb8/igt@gem_ctx_shared@q-smoketest-bsd2.html
* igt@gem_ctx_switch@vcs1:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112080]) +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-iclb1/igt@gem_ctx_switch@vcs1.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-iclb5/igt@gem_ctx_switch@vcs1.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-hsw: [PASS][13] -> [INCOMPLETE][14] ([fdo#103540])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-hsw7/igt@gem_eio@in-flight-contexts-10ms.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-hsw5/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_exec_schedule@independent-bsd:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#111325]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-iclb8/igt@gem_exec_schedule@independent-bsd.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-iclb2/igt@gem_exec_schedule@independent-bsd.html
* igt@gem_linear_blits@interruptible:
- shard-apl: [PASS][17] -> [INCOMPLETE][18] ([fdo#103927] / [fdo#112067])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-apl3/igt@gem_linear_blits@interruptible.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-apl5/igt@gem_linear_blits@interruptible.html
* igt@gem_tiled_swapping@non-threaded:
- shard-apl: [PASS][19] -> [INCOMPLETE][20] ([fdo#103927]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-apl3/igt@gem_tiled_swapping@non-threaded.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-apl5/igt@gem_tiled_swapping@non-threaded.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-snb: [PASS][21] -> [DMESG-WARN][22] ([fdo#111870])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-snb7/igt@gem_userptr_blits@dmabuf-unsync.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-snb6/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-hsw: [PASS][23] -> [DMESG-WARN][24] ([fdo#111870]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-hsw5/igt@gem_userptr_blits@sync-unmap-cycles.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-hsw5/igt@gem_userptr_blits@sync-unmap-cycles.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [PASS][25] -> [INCOMPLETE][26] ([fdo#103665])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-kbl2/igt@gem_workarounds@suspend-resume-fd.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [PASS][27] -> [DMESG-WARN][28] ([fdo#108566]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-apl5/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: [PASS][29] -> [FAIL][30] ([fdo#105363])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][31] -> [FAIL][32] ([fdo#105363])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-skl6/igt@kms_flip@flip-vs-expired-vblank.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-skl4/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip_tiling@flip-changes-tiling-y:
- shard-skl: [PASS][33] -> [FAIL][34] ([fdo#107931] / [fdo#108303])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-skl3/igt@kms_flip_tiling@flip-changes-tiling-y.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-skl2/igt@kms_flip_tiling@flip-changes-tiling-y.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: [PASS][35] -> [FAIL][36] ([fdo#103167]) +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][37] -> [FAIL][38] ([fdo#108145]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#109441])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][41] -> [FAIL][42] ([fdo#99912])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-apl7/igt@kms_setmode@basic.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-apl6/igt@kms_setmode@basic.html
- shard-hsw: [PASS][43] -> [FAIL][44] ([fdo#99912])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-hsw6/igt@kms_setmode@basic.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-hsw5/igt@kms_setmode@basic.html
* igt@prime_vgem@basic-sync-default:
- shard-iclb: [PASS][45] -> [INCOMPLETE][46] ([fdo#107713]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-iclb5/igt@prime_vgem@basic-sync-default.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-iclb7/igt@prime_vgem@basic-sync-default.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [SKIP][47] ([fdo#109276] / [fdo#112080]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-iclb8/igt@gem_ctx_isolation@vcs1-dirty-create.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-iclb2/igt@gem_ctx_isolation@vcs1-dirty-create.html
* igt@gem_ctx_shared@q-smoketest-render:
- {shard-tglb}: [INCOMPLETE][49] ([fdo# 111852 ]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-tglb4/igt@gem_ctx_shared@q-smoketest-render.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-tglb3/igt@gem_ctx_shared@q-smoketest-render.html
* igt@gem_ctx_switch@vcs1-heavy:
- shard-iclb: [SKIP][51] ([fdo#112080]) -> [PASS][52] +9 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-iclb8/igt@gem_ctx_switch@vcs1-heavy.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-iclb2/igt@gem_ctx_switch@vcs1-heavy.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-snb: [FAIL][53] ([fdo#111925]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-snb4/igt@gem_eio@in-flight-contexts-immediate.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-snb1/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [SKIP][55] ([fdo#109276]) -> [PASS][56] +15 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd1.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [SKIP][57] ([fdo#111325]) -> [PASS][58] +4 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-iclb6/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@gem_request_retire@retire-vma-not-inactive:
- shard-iclb: [INCOMPLETE][59] ([fdo#107713]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-iclb7/igt@gem_request_retire@retire-vma-not-inactive.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-iclb1/igt@gem_request_retire@retire-vma-not-inactive.html
* igt@gem_tiled_blits@interruptible:
- shard-glk: [DMESG-WARN][61] -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-glk4/igt@gem_tiled_blits@interruptible.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-glk1/igt@gem_tiled_blits@interruptible.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-snb: [DMESG-WARN][63] ([fdo#111870]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-hsw: [DMESG-WARN][65] ([fdo#111870]) -> [PASS][66] +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-hsw5/igt@gem_userptr_blits@sync-unmap-after-close.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-hsw7/igt@gem_userptr_blits@sync-unmap-after-close.html
* {igt@i915_pm_dc@dc6-dpms}:
- shard-iclb: [FAIL][67] ([fdo#110548]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-iclb4/igt@i915_pm_dc@dc6-dpms.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-iclb8/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_selftest@live_hangcheck:
- {shard-tglb}: [INCOMPLETE][69] ([fdo#111747]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-tglb6/igt@i915_selftest@live_hangcheck.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-tglb4/igt@i915_selftest@live_hangcheck.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- {shard-tglb}: [INCOMPLETE][71] ([fdo#111832] / [fdo#111850]) -> [PASS][72] +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-tglb1/igt@i915_suspend@fence-restore-tiled2untiled.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-tglb4/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_flip@dpms-vs-vblank-race:
- shard-glk: [FAIL][73] ([fdo#111609]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-glk4/igt@kms_flip@dpms-vs-vblank-race.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-glk1/igt@kms_flip@dpms-vs-vblank-race.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [FAIL][75] ([fdo#105363]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@modeset-vs-vblank-race-interruptible:
- shard-apl: [FAIL][77] ([fdo#111609]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-apl7/igt@kms_flip@modeset-vs-vblank-race-interruptible.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-apl8/igt@kms_flip@modeset-vs-vblank-race-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
- shard-iclb: [FAIL][79] ([fdo#103167]) -> [PASS][80] +4 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-kbl: [DMESG-WARN][81] ([fdo#103313] / [fdo#103558]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- {shard-tglb}: [INCOMPLETE][83] ([fdo#111832] / [fdo#111850] / [fdo#111884]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-suspend.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
- {shard-tglb}: [FAIL][85] ([fdo#103167]) -> [PASS][86] +8 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
* igt@kms_plane_cursor@pipe-a-primary-size-256:
- shard-kbl: [DMESG-WARN][87] ([fdo#103313] / [fdo#103558] / [fdo#105602]) -> [PASS][88] +9 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-kbl4/igt@kms_plane_cursor@pipe-a-primary-size-256.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-kbl1/igt@kms_plane_cursor@pipe-a-primary-size-256.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [FAIL][89] ([fdo#103166]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [SKIP][91] ([fdo#109441]) -> [PASS][92] +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-iclb8/igt@kms_psr@psr2_cursor_plane_move.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][93] ([fdo#108566]) -> [PASS][94] +5 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-apl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-b-wait-idle-hang:
- shard-apl: [INCOMPLETE][95] ([fdo#103927]) -> [PASS][96] +5 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-apl7/igt@kms_vblank@pipe-b-wait-idle-hang.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-apl3/igt@kms_vblank@pipe-b-wait-idle-hang.html
* igt@kms_vblank@pipe-d-ts-continuation-suspend:
- {shard-tglb}: [INCOMPLETE][97] ([fdo#111850]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-tglb4/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-tglb3/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
* igt@perf_pmu@busy-no-semaphores-vecs0:
- shard-apl: [DMESG-WARN][99] ([fdo#111626]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-apl7/igt@perf_pmu@busy-no-semaphores-vecs0.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-apl6/igt@perf_pmu@busy-no-semaphores-vecs0.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-isolation-bsd2:
- shard-iclb: [SKIP][101] ([fdo#109276]) -> [FAIL][102] ([fdo#111330])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7142/shard-iclb5/igt@gem_mocs_settings@mocs-isolation-bsd2.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/shard-iclb4/igt@gem_mocs_settings@mocs-isolation-bsd2.html
* igt@gem_mocs_settings@mocs-settings-bsd2:
- shard-iclb: [FAIL][103] ([fdo#111330]) -> [SKIP][104] ([fdo#109276])
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14906/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* [CI] drm/i915/gt: Introduce barrier pulses along engines
@ 2019-10-21 16:08 Chris Wilson
0 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2019-10-21 16:08 UTC (permalink / raw)
To: intel-gfx
To flush idle barriers, and even inflight requests, we want to send a
preemptive 'pulse' along an engine. We use a no-op request along the
pinned kernel_context at high priority so that it should run or else
kick off the stuck requests. We can use this to ensure idle barriers are
immediately flushed, as part of a context cancellation mechanism, or as
part of a heartbeat mechanism to detect and reset a stuck GPU.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +-
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 77 +++++++++
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 15 ++
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
.../drm/i915/gt/selftest_engine_heartbeat.c | 150 ++++++++++++++++++
drivers/gpu/drm/i915/i915_priolist_types.h | 1 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
7 files changed, 247 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
create mode 100644 drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a16a2daef977..2fd4bed188e5 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -78,8 +78,9 @@ gt-y += \
gt/intel_breadcrumbs.o \
gt/intel_context.o \
gt/intel_engine_cs.o \
- gt/intel_engine_pool.o \
+ gt/intel_engine_heartbeat.o \
gt/intel_engine_pm.o \
+ gt/intel_engine_pool.o \
gt/intel_engine_user.o \
gt/intel_gt.o \
gt/intel_gt_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
new file mode 100644
index 000000000000..4b9ab7813d54
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -0,0 +1,77 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "i915_request.h"
+
+#include "intel_context.h"
+#include "intel_engine_heartbeat.h"
+#include "intel_engine_pm.h"
+#include "intel_engine.h"
+#include "intel_gt.h"
+
+static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq)
+{
+ engine->wakeref_serial = READ_ONCE(engine->serial) + 1;
+ i915_request_add_active_barriers(rq);
+}
+
+int intel_engine_pulse(struct intel_engine_cs *engine)
+{
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_BARRIER };
+ struct intel_context *ce = engine->kernel_context;
+ struct i915_request *rq;
+ int err = 0;
+
+ if (!intel_engine_has_preemption(engine))
+ return -ENODEV;
+
+ if (!intel_engine_pm_get_if_awake(engine))
+ return 0;
+
+ if (mutex_lock_interruptible(&ce->timeline->mutex))
+ goto out_rpm;
+
+ intel_context_enter(ce);
+ rq = __i915_request_create(ce, GFP_NOWAIT | __GFP_NOWARN);
+ intel_context_exit(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_unlock;
+ }
+
+ rq->flags |= I915_REQUEST_SENTINEL;
+ idle_pulse(engine, rq);
+
+ __i915_request_commit(rq);
+ __i915_request_queue(rq, &attr);
+
+out_unlock:
+ mutex_unlock(&ce->timeline->mutex);
+out_rpm:
+ intel_engine_pm_put(engine);
+ return err;
+}
+
+int intel_engine_flush_barriers(struct intel_engine_cs *engine)
+{
+ struct i915_request *rq;
+
+ if (llist_empty(&engine->barrier_tasks))
+ return 0;
+
+ rq = i915_request_create(engine->kernel_context);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ idle_pulse(engine, rq);
+ i915_request_add(rq);
+
+ return 0;
+}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_engine_heartbeat.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
new file mode 100644
index 000000000000..b334e5aaf78d
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef INTEL_ENGINE_HEARTBEAT_H
+#define INTEL_ENGINE_HEARTBEAT_H
+
+struct intel_engine_cs;
+
+int intel_engine_pulse(struct intel_engine_cs *engine);
+int intel_engine_flush_barriers(struct intel_engine_cs *engine);
+
+#endif /* INTEL_ENGINE_HEARTBEAT_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 67eb6183648a..7d76611d9df1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -111,7 +111,7 @@ static bool switch_to_kernel_context(struct intel_engine_cs *engine)
i915_request_add_active_barriers(rq);
/* Install ourselves as a preemption barrier */
- rq->sched.attr.priority = I915_PRIORITY_UNPREEMPTABLE;
+ rq->sched.attr.priority = I915_PRIORITY_BARRIER;
__i915_request_commit(rq);
/* Release our exclusive hold on the engine */
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
new file mode 100644
index 000000000000..ad2f0543cbda
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
@@ -0,0 +1,150 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#include "i915_drv.h"
+
+#include "intel_gt_requests.h"
+#include "i915_selftest.h"
+
+struct pulse {
+ struct i915_active active;
+ struct kref kref;
+};
+
+static int pulse_active(struct i915_active *active)
+{
+ kref_get(&container_of(active, struct pulse, active)->kref);
+ return 0;
+}
+
+static void pulse_free(struct kref *kref)
+{
+ kfree(container_of(kref, struct pulse, kref));
+}
+
+static void pulse_put(struct pulse *p)
+{
+ kref_put(&p->kref, pulse_free);
+}
+
+static void pulse_retire(struct i915_active *active)
+{
+ pulse_put(container_of(active, struct pulse, active));
+}
+
+static struct pulse *pulse_create(void)
+{
+ struct pulse *p;
+
+ p = kmalloc(sizeof(*p), GFP_KERNEL);
+ if (!p)
+ return p;
+
+ kref_init(&p->kref);
+ i915_active_init(&p->active, pulse_active, pulse_retire);
+
+ return p;
+}
+
+static int __live_idle_pulse(struct intel_engine_cs *engine,
+ int (*fn)(struct intel_engine_cs *cs))
+{
+ struct pulse *p;
+ int err;
+
+ p = pulse_create();
+ if (!p)
+ return -ENOMEM;
+
+ err = i915_active_acquire_preallocate_barrier(&p->active, engine);
+ if (err)
+ goto out;
+
+ i915_active_acquire_barrier(&p->active);
+
+ err = fn(engine);
+ if (err)
+ goto out;
+
+ if (intel_gt_retire_requests_timeout(engine->gt, HZ / 5)) {
+ err = -ETIME;
+ goto out;
+ }
+
+ if (atomic_read(&p->active.count)) {
+ pr_err("%s: heartbeat pulse did not flush idle tasks\n",
+ engine->name);
+ err = -EINVAL;
+ goto out;
+ }
+
+out:
+ pulse_put(p);
+ return err;
+}
+
+static int live_idle_flush(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /* Check that we can flush the idle barriers */
+
+ for_each_engine(engine, gt, id) {
+ intel_engine_pm_get(engine);
+ err = __live_idle_pulse(engine, intel_engine_flush_barriers);
+ intel_engine_pm_put(engine);
+ if (err)
+ break;
+ }
+
+ return err;
+}
+
+static int live_idle_pulse(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /* Check that heartbeat pulses flush the idle barriers */
+
+ for_each_engine(engine, gt, id) {
+ intel_engine_pm_get(engine);
+ err = __live_idle_pulse(engine, intel_engine_pulse);
+ intel_engine_pm_put(engine);
+ if (err && err != -ENODEV)
+ break;
+
+ err = 0;
+ }
+
+ return err;
+}
+
+int intel_heartbeat_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(live_idle_flush),
+ SUBTEST(live_idle_pulse),
+ };
+ int saved_hangcheck;
+ int err;
+
+ if (intel_gt_is_wedged(&i915->gt))
+ return 0;
+
+ saved_hangcheck = i915_modparams.enable_hangcheck;
+ i915_modparams.enable_hangcheck = INT_MAX;
+
+ err = intel_gt_live_subtests(tests, &i915->gt);
+
+ i915_modparams.enable_hangcheck = saved_hangcheck;
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h b/drivers/gpu/drm/i915/i915_priolist_types.h
index 21037a2e2038..ae8bb3cb627e 100644
--- a/drivers/gpu/drm/i915/i915_priolist_types.h
+++ b/drivers/gpu/drm/i915/i915_priolist_types.h
@@ -39,6 +39,7 @@ enum {
* active request.
*/
#define I915_PRIORITY_UNPREEMPTABLE INT_MAX
+#define I915_PRIORITY_BARRIER INT_MAX
#define __NO_PREEMPTION (I915_PRIORITY_WAIT)
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 6daf6599ec79..00a063730bc3 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -17,6 +17,7 @@ selftest(gt_timelines, intel_timeline_live_selftests)
selftest(gt_contexts, intel_context_live_selftests)
selftest(gt_lrc, intel_lrc_live_selftests)
selftest(gt_pm, intel_gt_pm_live_selftests)
+selftest(gt_heartbeat, intel_heartbeat_live_selftests)
selftest(requests, i915_request_live_selftests)
selftest(active, i915_active_live_selftests)
selftest(objects, i915_gem_object_live_selftests)
--
2.24.0.rc0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [CI] drm/i915/gt: Introduce barrier pulses along engines
@ 2019-10-21 15:56 Chris Wilson
0 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2019-10-21 15:56 UTC (permalink / raw)
To: intel-gfx
To flush idle barriers, and even inflight requests, we want to send a
preemptive 'pulse' along an engine. We use a no-op request along the
pinned kernel_context at high priority so that it should run or else
kick off the stuck requests. We can use this to ensure idle barriers are
immediately flushed, as part of a context cancellation mechanism, or as
part of a heartbeat mechanism to detect and reset a stuck GPU.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +-
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 77 +++++++++
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 15 ++
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
.../drm/i915/gt/selftest_engine_heartbeat.c | 154 ++++++++++++++++++
drivers/gpu/drm/i915/i915_priolist_types.h | 1 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
7 files changed, 251 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
create mode 100644 drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a16a2daef977..2fd4bed188e5 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -78,8 +78,9 @@ gt-y += \
gt/intel_breadcrumbs.o \
gt/intel_context.o \
gt/intel_engine_cs.o \
- gt/intel_engine_pool.o \
+ gt/intel_engine_heartbeat.o \
gt/intel_engine_pm.o \
+ gt/intel_engine_pool.o \
gt/intel_engine_user.o \
gt/intel_gt.o \
gt/intel_gt_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
new file mode 100644
index 000000000000..4b9ab7813d54
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -0,0 +1,77 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "i915_request.h"
+
+#include "intel_context.h"
+#include "intel_engine_heartbeat.h"
+#include "intel_engine_pm.h"
+#include "intel_engine.h"
+#include "intel_gt.h"
+
+static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq)
+{
+ engine->wakeref_serial = READ_ONCE(engine->serial) + 1;
+ i915_request_add_active_barriers(rq);
+}
+
+int intel_engine_pulse(struct intel_engine_cs *engine)
+{
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_BARRIER };
+ struct intel_context *ce = engine->kernel_context;
+ struct i915_request *rq;
+ int err = 0;
+
+ if (!intel_engine_has_preemption(engine))
+ return -ENODEV;
+
+ if (!intel_engine_pm_get_if_awake(engine))
+ return 0;
+
+ if (mutex_lock_interruptible(&ce->timeline->mutex))
+ goto out_rpm;
+
+ intel_context_enter(ce);
+ rq = __i915_request_create(ce, GFP_NOWAIT | __GFP_NOWARN);
+ intel_context_exit(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_unlock;
+ }
+
+ rq->flags |= I915_REQUEST_SENTINEL;
+ idle_pulse(engine, rq);
+
+ __i915_request_commit(rq);
+ __i915_request_queue(rq, &attr);
+
+out_unlock:
+ mutex_unlock(&ce->timeline->mutex);
+out_rpm:
+ intel_engine_pm_put(engine);
+ return err;
+}
+
+int intel_engine_flush_barriers(struct intel_engine_cs *engine)
+{
+ struct i915_request *rq;
+
+ if (llist_empty(&engine->barrier_tasks))
+ return 0;
+
+ rq = i915_request_create(engine->kernel_context);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ idle_pulse(engine, rq);
+ i915_request_add(rq);
+
+ return 0;
+}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_engine_heartbeat.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
new file mode 100644
index 000000000000..b334e5aaf78d
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef INTEL_ENGINE_HEARTBEAT_H
+#define INTEL_ENGINE_HEARTBEAT_H
+
+struct intel_engine_cs;
+
+int intel_engine_pulse(struct intel_engine_cs *engine);
+int intel_engine_flush_barriers(struct intel_engine_cs *engine);
+
+#endif /* INTEL_ENGINE_HEARTBEAT_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 67eb6183648a..7d76611d9df1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -111,7 +111,7 @@ static bool switch_to_kernel_context(struct intel_engine_cs *engine)
i915_request_add_active_barriers(rq);
/* Install ourselves as a preemption barrier */
- rq->sched.attr.priority = I915_PRIORITY_UNPREEMPTABLE;
+ rq->sched.attr.priority = I915_PRIORITY_BARRIER;
__i915_request_commit(rq);
/* Release our exclusive hold on the engine */
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
new file mode 100644
index 000000000000..10724d98e796
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
@@ -0,0 +1,154 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#include "i915_drv.h"
+
+#include "intel_gt_requests.h"
+#include "i915_selftest.h"
+
+struct pulse {
+ struct i915_active active;
+ struct kref kref;
+};
+
+static int pulse_active(struct i915_active *active)
+{
+ kref_get(&container_of(active, struct pulse, active)->kref);
+ return 0;
+}
+
+static void pulse_free(struct kref *kref)
+{
+ kfree(container_of(kref, struct pulse, kref));
+}
+
+static void pulse_put(struct pulse *p)
+{
+ kref_put(&p->kref, pulse_free);
+}
+
+static void pulse_retire(struct i915_active *active)
+{
+ pulse_put(container_of(active, struct pulse, active));
+}
+
+static struct pulse *pulse_create(void)
+{
+ struct pulse *p;
+
+ p = kmalloc(sizeof(*p), GFP_KERNEL);
+ if (!p)
+ return p;
+
+ kref_init(&p->kref);
+ i915_active_init(&p->active, pulse_active, pulse_retire);
+
+ return p;
+}
+
+static int __live_idle_pulse(struct intel_engine_cs *engine,
+ int (*fn)(struct intel_engine_cs *cs))
+{
+ struct pulse *p;
+ int err;
+
+ GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
+
+ p = pulse_create();
+ if (!p)
+ return -ENOMEM;
+
+ err = i915_active_acquire_preallocate_barrier(&p->active, engine);
+ if (err)
+ goto out;
+
+ i915_active_acquire_barrier(&p->active);
+
+ err = fn(engine);
+ if (err) {
+ llist_del_all(&engine->barrier_tasks);
+ goto out;
+ }
+
+ if (intel_gt_retire_requests_timeout(engine->gt, HZ / 5)) {
+ err = -ETIME;
+ goto out;
+ }
+
+ if (atomic_read(&p->active.count)) {
+ pr_err("%s: heartbeat pulse did not flush idle tasks\n",
+ engine->name);
+ err = -EINVAL;
+ goto out;
+ }
+
+out:
+ pulse_put(p);
+ return err;
+}
+
+static int live_idle_flush(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /* Check that we can flush the idle barriers */
+
+ for_each_engine(engine, gt, id) {
+ intel_engine_pm_get(engine);
+ err = __live_idle_pulse(engine, intel_engine_flush_barriers);
+ intel_engine_pm_put(engine);
+ if (err)
+ break;
+ }
+
+ return err;
+}
+
+static int live_idle_pulse(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /* Check that heartbeat pulses flush the idle barriers */
+
+ for_each_engine(engine, gt, id) {
+ intel_engine_pm_get(engine);
+ err = __live_idle_pulse(engine, intel_engine_pulse);
+ intel_engine_pm_put(engine);
+ if (err && err != -ENODEV)
+ break;
+
+ err = 0;
+ }
+
+ return err;
+}
+
+int intel_heartbeat_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(live_idle_flush),
+ SUBTEST(live_idle_pulse),
+ };
+ int saved_hangcheck;
+ int err;
+
+ if (intel_gt_is_wedged(&i915->gt))
+ return 0;
+
+ saved_hangcheck = i915_modparams.enable_hangcheck;
+ i915_modparams.enable_hangcheck = INT_MAX;
+
+ err = intel_gt_live_subtests(tests, &i915->gt);
+
+ i915_modparams.enable_hangcheck = saved_hangcheck;
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h b/drivers/gpu/drm/i915/i915_priolist_types.h
index 21037a2e2038..ae8bb3cb627e 100644
--- a/drivers/gpu/drm/i915/i915_priolist_types.h
+++ b/drivers/gpu/drm/i915/i915_priolist_types.h
@@ -39,6 +39,7 @@ enum {
* active request.
*/
#define I915_PRIORITY_UNPREEMPTABLE INT_MAX
+#define I915_PRIORITY_BARRIER INT_MAX
#define __NO_PREEMPTION (I915_PRIORITY_WAIT)
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 6daf6599ec79..00a063730bc3 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -17,6 +17,7 @@ selftest(gt_timelines, intel_timeline_live_selftests)
selftest(gt_contexts, intel_context_live_selftests)
selftest(gt_lrc, intel_lrc_live_selftests)
selftest(gt_pm, intel_gt_pm_live_selftests)
+selftest(gt_heartbeat, intel_heartbeat_live_selftests)
selftest(requests, i915_request_live_selftests)
selftest(active, i915_active_live_selftests)
selftest(objects, i915_gem_object_live_selftests)
--
2.24.0.rc0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [CI] drm/i915/gt: Introduce barrier pulses along engines
@ 2019-10-21 14:13 Chris Wilson
0 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2019-10-21 14:13 UTC (permalink / raw)
To: intel-gfx
To flush idle barriers, and even inflight requests, we want to send a
preemptive 'pulse' along an engine. We use a no-op request along the
pinned kernel_context at high priority so that it should run or else
kick off the stuck requests. We can use this to ensure idle barriers are
immediately flushed, as part of a context cancellation mechanism, or as
part of a heartbeat mechanism to detect and reset a stuck GPU.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +-
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 77 ++++++++++++
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 15 +++
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
.../drm/i915/gt/selftest_engine_heartbeat.c | 110 ++++++++++++++++++
drivers/gpu/drm/i915/i915_priolist_types.h | 1 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
7 files changed, 207 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
create mode 100644 drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a16a2daef977..2fd4bed188e5 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -78,8 +78,9 @@ gt-y += \
gt/intel_breadcrumbs.o \
gt/intel_context.o \
gt/intel_engine_cs.o \
- gt/intel_engine_pool.o \
+ gt/intel_engine_heartbeat.o \
gt/intel_engine_pm.o \
+ gt/intel_engine_pool.o \
gt/intel_engine_user.o \
gt/intel_gt.o \
gt/intel_gt_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
new file mode 100644
index 000000000000..4b9ab7813d54
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -0,0 +1,77 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "i915_request.h"
+
+#include "intel_context.h"
+#include "intel_engine_heartbeat.h"
+#include "intel_engine_pm.h"
+#include "intel_engine.h"
+#include "intel_gt.h"
+
+static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq)
+{
+ engine->wakeref_serial = READ_ONCE(engine->serial) + 1;
+ i915_request_add_active_barriers(rq);
+}
+
+int intel_engine_pulse(struct intel_engine_cs *engine)
+{
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_BARRIER };
+ struct intel_context *ce = engine->kernel_context;
+ struct i915_request *rq;
+ int err = 0;
+
+ if (!intel_engine_has_preemption(engine))
+ return -ENODEV;
+
+ if (!intel_engine_pm_get_if_awake(engine))
+ return 0;
+
+ if (mutex_lock_interruptible(&ce->timeline->mutex))
+ goto out_rpm;
+
+ intel_context_enter(ce);
+ rq = __i915_request_create(ce, GFP_NOWAIT | __GFP_NOWARN);
+ intel_context_exit(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_unlock;
+ }
+
+ rq->flags |= I915_REQUEST_SENTINEL;
+ idle_pulse(engine, rq);
+
+ __i915_request_commit(rq);
+ __i915_request_queue(rq, &attr);
+
+out_unlock:
+ mutex_unlock(&ce->timeline->mutex);
+out_rpm:
+ intel_engine_pm_put(engine);
+ return err;
+}
+
+int intel_engine_flush_barriers(struct intel_engine_cs *engine)
+{
+ struct i915_request *rq;
+
+ if (llist_empty(&engine->barrier_tasks))
+ return 0;
+
+ rq = i915_request_create(engine->kernel_context);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ idle_pulse(engine, rq);
+ i915_request_add(rq);
+
+ return 0;
+}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_engine_heartbeat.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
new file mode 100644
index 000000000000..b334e5aaf78d
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef INTEL_ENGINE_HEARTBEAT_H
+#define INTEL_ENGINE_HEARTBEAT_H
+
+struct intel_engine_cs;
+
+int intel_engine_pulse(struct intel_engine_cs *engine);
+int intel_engine_flush_barriers(struct intel_engine_cs *engine);
+
+#endif /* INTEL_ENGINE_HEARTBEAT_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 67eb6183648a..7d76611d9df1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -111,7 +111,7 @@ static bool switch_to_kernel_context(struct intel_engine_cs *engine)
i915_request_add_active_barriers(rq);
/* Install ourselves as a preemption barrier */
- rq->sched.attr.priority = I915_PRIORITY_UNPREEMPTABLE;
+ rq->sched.attr.priority = I915_PRIORITY_BARRIER;
__i915_request_commit(rq);
/* Release our exclusive hold on the engine */
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
new file mode 100644
index 000000000000..49c683d3b244
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
@@ -0,0 +1,110 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#include "i915_drv.h"
+
+#include "intel_gt_requests.h"
+#include "i915_selftest.h"
+
+static int __live_idle_pulse(struct intel_engine_cs *engine,
+ int (*fn)(struct intel_engine_cs *cs))
+{
+ struct i915_active ref;
+ int err;
+
+ GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
+
+ i915_active_init(&ref, NULL, NULL);
+
+ err = i915_active_acquire_preallocate_barrier(&ref, engine);
+ if (err)
+ return err;
+
+ i915_active_acquire_barrier(&ref);
+
+ err = fn(engine);
+ if (err) {
+ llist_del_all(&engine->barrier_tasks);
+ return err;
+ }
+
+ if (intel_gt_retire_requests_timeout(engine->gt, HZ / 5)) {
+ intel_gt_set_wedged(engine->gt);
+ return -ETIME; /* leaking struct i915_active!!! */
+ }
+
+ if (atomic_read(&ref.count)) {
+ pr_err("%s: heartbeat pulse did not flush idle tasks\n",
+ engine->name);
+ intel_gt_set_wedged(engine->gt);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int live_idle_flush(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /* Check that we can flush the idle barriers */
+
+ for_each_engine(engine, gt, id) {
+ intel_engine_pm_get(engine);
+ err = __live_idle_pulse(engine, intel_engine_flush_barriers);
+ intel_engine_pm_put(engine);
+ if (err)
+ break;
+ }
+
+ return err;
+}
+
+static int live_idle_pulse(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /* Check that heartbeat pulses flush the idle barriers */
+
+ for_each_engine(engine, gt, id) {
+ intel_engine_pm_get(engine);
+ err = __live_idle_pulse(engine, intel_engine_pulse);
+ intel_engine_pm_put(engine);
+ if (err && err != -ENODEV)
+ break;
+
+ err = 0;
+ }
+
+ return err;
+}
+
+int intel_heartbeat_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(live_idle_flush),
+ SUBTEST(live_idle_pulse),
+ };
+ int saved_hangcheck;
+ int err;
+
+ if (intel_gt_is_wedged(&i915->gt))
+ return 0;
+
+ saved_hangcheck = i915_modparams.enable_hangcheck;
+ i915_modparams.enable_hangcheck = INT_MAX;
+
+ err = intel_gt_live_subtests(tests, &i915->gt);
+
+ i915_modparams.enable_hangcheck = saved_hangcheck;
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h b/drivers/gpu/drm/i915/i915_priolist_types.h
index 21037a2e2038..ae8bb3cb627e 100644
--- a/drivers/gpu/drm/i915/i915_priolist_types.h
+++ b/drivers/gpu/drm/i915/i915_priolist_types.h
@@ -39,6 +39,7 @@ enum {
* active request.
*/
#define I915_PRIORITY_UNPREEMPTABLE INT_MAX
+#define I915_PRIORITY_BARRIER INT_MAX
#define __NO_PREEMPTION (I915_PRIORITY_WAIT)
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 6daf6599ec79..00a063730bc3 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -17,6 +17,7 @@ selftest(gt_timelines, intel_timeline_live_selftests)
selftest(gt_contexts, intel_context_live_selftests)
selftest(gt_lrc, intel_lrc_live_selftests)
selftest(gt_pm, intel_gt_pm_live_selftests)
+selftest(gt_heartbeat, intel_heartbeat_live_selftests)
selftest(requests, i915_request_live_selftests)
selftest(active, i915_active_live_selftests)
selftest(objects, i915_gem_object_live_selftests)
--
2.24.0.rc0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-10-22 1:24 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-21 17:43 [CI] drm/i915/gt: Introduce barrier pulses along engines Chris Wilson
2019-10-21 19:13 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Introduce barrier pulses along engines (rev4) Patchwork
2019-10-21 19:55 ` ✓ Fi.CI.BAT: success " Patchwork
2019-10-22 1:24 ` ✗ Fi.CI.IGT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2019-10-21 16:08 [CI] drm/i915/gt: Introduce barrier pulses along engines Chris Wilson
2019-10-21 15:56 Chris Wilson
2019-10-21 14:13 Chris Wilson
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