[PATCH 1/5] drm/i915/psr: Add bits per pixel limitation

[PATCH 1/5] drm/i915/psr: Add bits per pixel limitation

[José Roberto de Souza]

PSR2 HW only support a limited number of bits per pixel, if mode has
more than supported PSR2 should not be enabled.

BSpec: 50422
BSpec: 7713
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index c1d133362b76..0d84ea28bc6f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -608,7 +608,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 	int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
-	int psr_max_h = 0, psr_max_v = 0;
+	int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
 
 	if (!dev_priv->psr.sink_psr2_support)
 		return false;
@@ -632,12 +632,15 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 	if (INTEL_GEN(dev_priv) >= 12) {
 		psr_max_h = 5120;
 		psr_max_v = 3200;
+		max_bpp = 30;
 	} else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 		psr_max_h = 4096;
 		psr_max_v = 2304;
+		max_bpp = 24;
 	} else if (IS_GEN(dev_priv, 9)) {
 		psr_max_h = 3640;
 		psr_max_v = 2304;
+		max_bpp = 24;
 	}
 
 	if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) {
@@ -647,6 +650,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
+	if (crtc_state->pipe_bpp > max_bpp) {
+		DRM_DEBUG_KMS("PSR2 not enabled, pipe bpp %d > max supported %d\n",
+			      crtc_state->pipe_bpp, max_bpp);
+		return false;
+	}
+
 	/*
 	 * HW sends SU blocks of size four scan lines, which means the starting
 	 * X coordinate and Y granularity requirements will always be met. We
-- 
2.24.0

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[Intel-gfx] [PATCH 1/5] drm/i915/psr: Add bits per pixel limitation

[José Roberto de Souza]

PSR2 HW only support a limited number of bits per pixel, if mode has
more than supported PSR2 should not be enabled.

BSpec: 50422
BSpec: 7713
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index c1d133362b76..0d84ea28bc6f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -608,7 +608,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 	int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
-	int psr_max_h = 0, psr_max_v = 0;
+	int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
 
 	if (!dev_priv->psr.sink_psr2_support)
 		return false;
@@ -632,12 +632,15 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 	if (INTEL_GEN(dev_priv) >= 12) {
 		psr_max_h = 5120;
 		psr_max_v = 3200;
+		max_bpp = 30;
 	} else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 		psr_max_h = 4096;
 		psr_max_v = 2304;
+		max_bpp = 24;
 	} else if (IS_GEN(dev_priv, 9)) {
 		psr_max_h = 3640;
 		psr_max_v = 2304;
+		max_bpp = 24;
 	}
 
 	if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) {
@@ -647,6 +650,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
+	if (crtc_state->pipe_bpp > max_bpp) {
+		DRM_DEBUG_KMS("PSR2 not enabled, pipe bpp %d > max supported %d\n",
+			      crtc_state->pipe_bpp, max_bpp);
+		return false;
+	}
+
 	/*
 	 * HW sends SU blocks of size four scan lines, which means the starting
 	 * X coordinate and Y granularity requirements will always be met. We
-- 
2.24.0

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[PATCH 2/5] drm/i915/psr: Refactor psr short pulse handler

[José Roberto de Souza]

eDP spec states that when sink enconters a problem that prevents it
to keep PSR running it should set PSR status to internal error and
set the reason why it happen to PSR_ERROR_STATUS but it is not how it
was implemented.
But also I don't want to change this behavior, who knows if there is
a panel out there that only set the PSR_ERROR_STATUS.

So here refactoring the code a bit to make more easy to read what was
state above as more checks will be added to this function.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 51 ++++++++++++++----------
 1 file changed, 31 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 0d84ea28bc6f..f38da1b9b323 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1386,11 +1386,30 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
 	mutex_init(&dev_priv->psr.lock);
 }
 
+static bool psr_get_status_and_error_status(struct intel_dp *intel_dp,
+					    u8 *status, u8 *error_status)
+{
+	struct drm_dp_aux *aux = &intel_dp->aux;
+	int r;
+
+	r = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status);
+	if (r != 1)
+		return false;
+
+	r = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status);
+	if (r != 1)
+		return false;
+
+	*status = *status & DP_PSR_SINK_STATE_MASK;
+
+	return true;
+}
+
 void intel_psr_short_pulse(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	struct i915_psr *psr = &dev_priv->psr;
-	u8 val;
+	u8 status, error_status;
 	const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
 			  DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
 			  DP_PSR_LINK_CRC_ERROR;
@@ -1403,38 +1422,30 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
 	if (!psr->enabled || psr->dp != intel_dp)
 		goto exit;
 
-	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) != 1) {
-		DRM_ERROR("PSR_STATUS dpcd read failed\n");
+	if (!psr_get_status_and_error_status(intel_dp, &status, &error_status)) {
+		DRM_ERROR("Error reading PSR status or error status\n");
 		goto exit;
 	}
 
-	if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR) {
-		DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n");
+	if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) {
 		intel_psr_disable_locked(intel_dp);
 		psr->sink_not_reliable = true;
 	}
 
-	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) {
-		DRM_ERROR("PSR_ERROR_STATUS dpcd read failed\n");
-		goto exit;
-	}
-
-	if (val & DP_PSR_RFB_STORAGE_ERROR)
+	if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status)
+		DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n");
+	if (error_status & DP_PSR_RFB_STORAGE_ERROR)
 		DRM_DEBUG_KMS("PSR RFB storage error, disabling PSR\n");
-	if (val & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
+	if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
 		DRM_DEBUG_KMS("PSR VSC SDP uncorrectable error, disabling PSR\n");
-	if (val & DP_PSR_LINK_CRC_ERROR)
+	if (error_status & DP_PSR_LINK_CRC_ERROR)
 		DRM_DEBUG_KMS("PSR Link CRC error, disabling PSR\n");
 
-	if (val & ~errors)
+	if (error_status & ~errors)
 		DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n",
-			  val & ~errors);
-	if (val & errors) {
-		intel_psr_disable_locked(intel_dp);
-		psr->sink_not_reliable = true;
-	}
+			  error_status & ~errors);
 	/* clear status register */
-	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
 exit:
 	mutex_unlock(&psr->lock);
 }
-- 
2.24.0

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[Intel-gfx] [PATCH 2/5] drm/i915/psr: Refactor psr short pulse handler

[José Roberto de Souza]

eDP spec states that when sink enconters a problem that prevents it
to keep PSR running it should set PSR status to internal error and
set the reason why it happen to PSR_ERROR_STATUS but it is not how it
was implemented.
But also I don't want to change this behavior, who knows if there is
a panel out there that only set the PSR_ERROR_STATUS.

So here refactoring the code a bit to make more easy to read what was
state above as more checks will be added to this function.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 51 ++++++++++++++----------
 1 file changed, 31 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 0d84ea28bc6f..f38da1b9b323 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1386,11 +1386,30 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
 	mutex_init(&dev_priv->psr.lock);
 }
 
+static bool psr_get_status_and_error_status(struct intel_dp *intel_dp,
+					    u8 *status, u8 *error_status)
+{
+	struct drm_dp_aux *aux = &intel_dp->aux;
+	int r;
+
+	r = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status);
+	if (r != 1)
+		return false;
+
+	r = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status);
+	if (r != 1)
+		return false;
+
+	*status = *status & DP_PSR_SINK_STATE_MASK;
+
+	return true;
+}
+
 void intel_psr_short_pulse(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	struct i915_psr *psr = &dev_priv->psr;
-	u8 val;
+	u8 status, error_status;
 	const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
 			  DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
 			  DP_PSR_LINK_CRC_ERROR;
@@ -1403,38 +1422,30 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
 	if (!psr->enabled || psr->dp != intel_dp)
 		goto exit;
 
-	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) != 1) {
-		DRM_ERROR("PSR_STATUS dpcd read failed\n");
+	if (!psr_get_status_and_error_status(intel_dp, &status, &error_status)) {
+		DRM_ERROR("Error reading PSR status or error status\n");
 		goto exit;
 	}
 
-	if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR) {
-		DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n");
+	if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) {
 		intel_psr_disable_locked(intel_dp);
 		psr->sink_not_reliable = true;
 	}
 
-	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) {
-		DRM_ERROR("PSR_ERROR_STATUS dpcd read failed\n");
-		goto exit;
-	}
-
-	if (val & DP_PSR_RFB_STORAGE_ERROR)
+	if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status)
+		DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n");
+	if (error_status & DP_PSR_RFB_STORAGE_ERROR)
 		DRM_DEBUG_KMS("PSR RFB storage error, disabling PSR\n");
-	if (val & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
+	if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
 		DRM_DEBUG_KMS("PSR VSC SDP uncorrectable error, disabling PSR\n");
-	if (val & DP_PSR_LINK_CRC_ERROR)
+	if (error_status & DP_PSR_LINK_CRC_ERROR)
 		DRM_DEBUG_KMS("PSR Link CRC error, disabling PSR\n");
 
-	if (val & ~errors)
+	if (error_status & ~errors)
 		DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n",
-			  val & ~errors);
-	if (val & errors) {
-		intel_psr_disable_locked(intel_dp);
-		psr->sink_not_reliable = true;
-	}
+			  error_status & ~errors);
 	/* clear status register */
-	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
 exit:
 	mutex_unlock(&psr->lock);
 }
-- 
2.24.0

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Re: [PATCH 2/5] drm/i915/psr: Refactor psr short pulse handler

[Matt Roper]

On Tue, Nov 05, 2019 at 05:45:01PM -0800, José Roberto de Souza wrote:
> eDP spec states that when sink enconters a problem that prevents it
> to keep PSR running it should set PSR status to internal error and
> set the reason why it happen to PSR_ERROR_STATUS but it is not how it
> was implemented.
> But also I don't want to change this behavior, who knows if there is
> a panel out there that only set the PSR_ERROR_STATUS.
> 
> So here refactoring the code a bit to make more easy to read what was
> state above as more checks will be added to this function.
> 
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 51 ++++++++++++++----------
>  1 file changed, 31 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 0d84ea28bc6f..f38da1b9b323 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1386,11 +1386,30 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
>  	mutex_init(&dev_priv->psr.lock);
>  }
>  
> +static bool psr_get_status_and_error_status(struct intel_dp *intel_dp,
> +					    u8 *status, u8 *error_status)

This should probably return an integer rather than a bool to match the
kernel coding style guidelines:

        """
        If the name of a function is an action or an imperative command,
        the function should return an error-code integer.  If the name
        is a predicate, the function should return a "succeeded"
        boolean.
        """


Matt

> +{
> +	struct drm_dp_aux *aux = &intel_dp->aux;
> +	int r;
> +
> +	r = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status);
> +	if (r != 1)
> +		return false;
> +
> +	r = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status);
> +	if (r != 1)
> +		return false;
> +
> +	*status = *status & DP_PSR_SINK_STATE_MASK;
> +
> +	return true;
> +}
> +
>  void intel_psr_short_pulse(struct intel_dp *intel_dp)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	struct i915_psr *psr = &dev_priv->psr;
> -	u8 val;
> +	u8 status, error_status;
>  	const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
>  			  DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
>  			  DP_PSR_LINK_CRC_ERROR;
> @@ -1403,38 +1422,30 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
>  	if (!psr->enabled || psr->dp != intel_dp)
>  		goto exit;
>  
> -	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) != 1) {
> -		DRM_ERROR("PSR_STATUS dpcd read failed\n");
> +	if (!psr_get_status_and_error_status(intel_dp, &status, &error_status)) {
> +		DRM_ERROR("Error reading PSR status or error status\n");
>  		goto exit;
>  	}
>  
> -	if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR) {
> -		DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n");
> +	if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) {
>  		intel_psr_disable_locked(intel_dp);
>  		psr->sink_not_reliable = true;
>  	}
>  
> -	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) {
> -		DRM_ERROR("PSR_ERROR_STATUS dpcd read failed\n");
> -		goto exit;
> -	}
> -
> -	if (val & DP_PSR_RFB_STORAGE_ERROR)
> +	if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status)
> +		DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n");
> +	if (error_status & DP_PSR_RFB_STORAGE_ERROR)
>  		DRM_DEBUG_KMS("PSR RFB storage error, disabling PSR\n");
> -	if (val & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
> +	if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
>  		DRM_DEBUG_KMS("PSR VSC SDP uncorrectable error, disabling PSR\n");
> -	if (val & DP_PSR_LINK_CRC_ERROR)
> +	if (error_status & DP_PSR_LINK_CRC_ERROR)
>  		DRM_DEBUG_KMS("PSR Link CRC error, disabling PSR\n");
>  
> -	if (val & ~errors)
> +	if (error_status & ~errors)
>  		DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n",
> -			  val & ~errors);
> -	if (val & errors) {
> -		intel_psr_disable_locked(intel_dp);
> -		psr->sink_not_reliable = true;
> -	}
> +			  error_status & ~errors);
>  	/* clear status register */
> -	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
> +	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
>  exit:
>  	mutex_unlock(&psr->lock);
>  }
> -- 
> 2.24.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH 2/5] drm/i915/psr: Refactor psr short pulse handler

[Matt Roper]

On Tue, Nov 05, 2019 at 05:45:01PM -0800, José Roberto de Souza wrote:
> eDP spec states that when sink enconters a problem that prevents it
> to keep PSR running it should set PSR status to internal error and
> set the reason why it happen to PSR_ERROR_STATUS but it is not how it
> was implemented.
> But also I don't want to change this behavior, who knows if there is
> a panel out there that only set the PSR_ERROR_STATUS.
> 
> So here refactoring the code a bit to make more easy to read what was
> state above as more checks will be added to this function.
> 
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 51 ++++++++++++++----------
>  1 file changed, 31 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 0d84ea28bc6f..f38da1b9b323 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1386,11 +1386,30 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
>  	mutex_init(&dev_priv->psr.lock);
>  }
>  
> +static bool psr_get_status_and_error_status(struct intel_dp *intel_dp,
> +					    u8 *status, u8 *error_status)

This should probably return an integer rather than a bool to match the
kernel coding style guidelines:

        """
        If the name of a function is an action or an imperative command,
        the function should return an error-code integer.  If the name
        is a predicate, the function should return a "succeeded"
        boolean.
        """


Matt

> +{
> +	struct drm_dp_aux *aux = &intel_dp->aux;
> +	int r;
> +
> +	r = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status);
> +	if (r != 1)
> +		return false;
> +
> +	r = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status);
> +	if (r != 1)
> +		return false;
> +
> +	*status = *status & DP_PSR_SINK_STATE_MASK;
> +
> +	return true;
> +}
> +
>  void intel_psr_short_pulse(struct intel_dp *intel_dp)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	struct i915_psr *psr = &dev_priv->psr;
> -	u8 val;
> +	u8 status, error_status;
>  	const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
>  			  DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
>  			  DP_PSR_LINK_CRC_ERROR;
> @@ -1403,38 +1422,30 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
>  	if (!psr->enabled || psr->dp != intel_dp)
>  		goto exit;
>  
> -	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) != 1) {
> -		DRM_ERROR("PSR_STATUS dpcd read failed\n");
> +	if (!psr_get_status_and_error_status(intel_dp, &status, &error_status)) {
> +		DRM_ERROR("Error reading PSR status or error status\n");
>  		goto exit;
>  	}
>  
> -	if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR) {
> -		DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n");
> +	if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) {
>  		intel_psr_disable_locked(intel_dp);
>  		psr->sink_not_reliable = true;
>  	}
>  
> -	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) {
> -		DRM_ERROR("PSR_ERROR_STATUS dpcd read failed\n");
> -		goto exit;
> -	}
> -
> -	if (val & DP_PSR_RFB_STORAGE_ERROR)
> +	if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status)
> +		DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n");
> +	if (error_status & DP_PSR_RFB_STORAGE_ERROR)
>  		DRM_DEBUG_KMS("PSR RFB storage error, disabling PSR\n");
> -	if (val & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
> +	if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
>  		DRM_DEBUG_KMS("PSR VSC SDP uncorrectable error, disabling PSR\n");
> -	if (val & DP_PSR_LINK_CRC_ERROR)
> +	if (error_status & DP_PSR_LINK_CRC_ERROR)
>  		DRM_DEBUG_KMS("PSR Link CRC error, disabling PSR\n");
>  
> -	if (val & ~errors)
> +	if (error_status & ~errors)
>  		DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n",
> -			  val & ~errors);
> -	if (val & errors) {
> -		intel_psr_disable_locked(intel_dp);
> -		psr->sink_not_reliable = true;
> -	}
> +			  error_status & ~errors);
>  	/* clear status register */
> -	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
> +	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
>  exit:
>  	mutex_unlock(&psr->lock);
>  }
> -- 
> 2.24.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[PATCH 3/5] drm/i915/psr: Enable ALPM lock timeout error interruption

[José Roberto de Souza]

When this error happens sink link is not stable after the required
FW_EXIT_LATENCY period so it will miss the selective update.
As the other PSR errors, for now we are not trying to recover from
it.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 37 +++++++++++++++++++++++-
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index f38da1b9b323..c703a10d2fd7 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -402,7 +402,9 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 	/* Enable ALPM at sink for psr2 */
 	if (dev_priv->psr.psr2_enabled) {
 		drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
-				   DP_ALPM_ENABLE);
+				   DP_ALPM_ENABLE |
+				   DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
+
 		dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
 	} else {
 		if (dev_priv->psr.link_standby)
@@ -934,6 +936,9 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 	/* Disable PSR on Sink */
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
 
+	if (dev_priv->psr.psr2_enabled)
+		drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);
+
 	dev_priv->psr.enabled = false;
 }
 
@@ -1405,6 +1410,33 @@ static bool psr_get_status_and_error_status(struct intel_dp *intel_dp,
 	return true;
 }
 
+static void psr_alpm_check(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct drm_dp_aux *aux = &intel_dp->aux;
+	struct i915_psr *psr = &dev_priv->psr;
+	u8 val;
+	int r;
+
+	if (!psr->psr2_enabled)
+		return;
+
+	r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val);
+	if (r != 1) {
+		DRM_ERROR("Error reading ALPM status\n");
+		return;
+	}
+
+	if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) {
+		intel_psr_disable_locked(intel_dp);
+		psr->sink_not_reliable = true;
+		DRM_DEBUG_KMS("ALPM lock timeout error, disabling PSR\n");
+
+		/* Clearing error */
+		drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val);
+	}
+}
+
 void intel_psr_short_pulse(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1446,6 +1478,9 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
 			  error_status & ~errors);
 	/* clear status register */
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
+
+	psr_alpm_check(intel_dp);
+
 exit:
 	mutex_unlock(&psr->lock);
 }
-- 
2.24.0

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[Intel-gfx] [PATCH 3/5] drm/i915/psr: Enable ALPM lock timeout error interruption

[José Roberto de Souza]

When this error happens sink link is not stable after the required
FW_EXIT_LATENCY period so it will miss the selective update.
As the other PSR errors, for now we are not trying to recover from
it.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 37 +++++++++++++++++++++++-
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index f38da1b9b323..c703a10d2fd7 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -402,7 +402,9 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 	/* Enable ALPM at sink for psr2 */
 	if (dev_priv->psr.psr2_enabled) {
 		drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
-				   DP_ALPM_ENABLE);
+				   DP_ALPM_ENABLE |
+				   DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
+
 		dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
 	} else {
 		if (dev_priv->psr.link_standby)
@@ -934,6 +936,9 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 	/* Disable PSR on Sink */
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
 
+	if (dev_priv->psr.psr2_enabled)
+		drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);
+
 	dev_priv->psr.enabled = false;
 }
 
@@ -1405,6 +1410,33 @@ static bool psr_get_status_and_error_status(struct intel_dp *intel_dp,
 	return true;
 }
 
+static void psr_alpm_check(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct drm_dp_aux *aux = &intel_dp->aux;
+	struct i915_psr *psr = &dev_priv->psr;
+	u8 val;
+	int r;
+
+	if (!psr->psr2_enabled)
+		return;
+
+	r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val);
+	if (r != 1) {
+		DRM_ERROR("Error reading ALPM status\n");
+		return;
+	}
+
+	if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) {
+		intel_psr_disable_locked(intel_dp);
+		psr->sink_not_reliable = true;
+		DRM_DEBUG_KMS("ALPM lock timeout error, disabling PSR\n");
+
+		/* Clearing error */
+		drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val);
+	}
+}
+
 void intel_psr_short_pulse(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1446,6 +1478,9 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
 			  error_status & ~errors);
 	/* clear status register */
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
+
+	psr_alpm_check(intel_dp);
+
 exit:
 	mutex_unlock(&psr->lock);
 }
-- 
2.24.0

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[PATCH 4/5] drm/i915/psr: Check if sink PSR capability changed

[José Roberto de Souza]

eDP specification states that sink can have its PSR capability
changed, I have never found any panel doing that but lets add that
for completeness.
For now it is not reading back the PSR capabilities and if possible
re-enabling PSR, this will be added if a panel is found using this
feature.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index c703a10d2fd7..cdd9c270b42c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1437,6 +1437,26 @@ static void psr_alpm_check(struct intel_dp *intel_dp)
 	}
 }
 
+static void psr_capability_changed_check(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct i915_psr *psr = &dev_priv->psr;
+	u8 val;
+	int r;
+
+	r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val);
+	if (r != 1) {
+		DRM_ERROR("Error reading DP_PSR_ESI\n");
+		return;
+	}
+
+	if (val & DP_PSR_CAPS_CHANGE) {
+		intel_psr_disable_locked(intel_dp);
+		psr->sink_not_reliable = true;
+		DRM_DEBUG_KMS("Sink PSR capability changed, disabling PSR\n");
+	}
+}
+
 void intel_psr_short_pulse(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1480,6 +1500,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
 
 	psr_alpm_check(intel_dp);
+	psr_capability_changed_check(intel_dp);
 
 exit:
 	mutex_unlock(&psr->lock);
-- 
2.24.0

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[Intel-gfx] [PATCH 4/5] drm/i915/psr: Check if sink PSR capability changed

[José Roberto de Souza]

eDP specification states that sink can have its PSR capability
changed, I have never found any panel doing that but lets add that
for completeness.
For now it is not reading back the PSR capabilities and if possible
re-enabling PSR, this will be added if a panel is found using this
feature.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index c703a10d2fd7..cdd9c270b42c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1437,6 +1437,26 @@ static void psr_alpm_check(struct intel_dp *intel_dp)
 	}
 }
 
+static void psr_capability_changed_check(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct i915_psr *psr = &dev_priv->psr;
+	u8 val;
+	int r;
+
+	r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val);
+	if (r != 1) {
+		DRM_ERROR("Error reading DP_PSR_ESI\n");
+		return;
+	}
+
+	if (val & DP_PSR_CAPS_CHANGE) {
+		intel_psr_disable_locked(intel_dp);
+		psr->sink_not_reliable = true;
+		DRM_DEBUG_KMS("Sink PSR capability changed, disabling PSR\n");
+	}
+}
+
 void intel_psr_short_pulse(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1480,6 +1500,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
 
 	psr_alpm_check(intel_dp);
+	psr_capability_changed_check(intel_dp);
 
 exit:
 	mutex_unlock(&psr->lock);
-- 
2.24.0

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[PATCH 5/5] drm/i915/vbt: Parse power conservation features block

[José Roberto de Souza]

Since VBT 228 is from this block that PSR and other power saving
features configuration should be read from.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 19 +++++++++++-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 29 +++++++++++++++++++
 2 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index a03f56b7b4ef..bf79e9858bd8 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -561,7 +561,23 @@ parse_driver_features(struct drm_i915_private *dev_priv,
 	 */
 	if (!driver->drrs_enabled)
 		dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
-	dev_priv->vbt.psr.enable = driver->psr_enabled;
+	if (bdb->version < 228)
+		dev_priv->vbt.psr.enable = driver->psr_enabled;
+}
+
+static void
+parse_power_conservation_features(struct drm_i915_private *dev_priv,
+				  const struct bdb_header *bdb)
+{
+	const struct bdb_lfp_power *power;
+	u8 panel_type = dev_priv->vbt.panel_type;
+
+	power = find_section(bdb, BDB_LVDS_POWER);
+	if (!power)
+		return;
+
+	if (bdb->version >= 228)
+		dev_priv->vbt.psr.enable = power->psr & (1 << panel_type);
 }
 
 static void
@@ -1878,6 +1894,7 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
 	parse_lfp_backlight(dev_priv, bdb);
 	parse_sdvo_panel_data(dev_priv, bdb);
 	parse_driver_features(dev_priv, bdb);
+	parse_power_conservation_features(dev_priv, bdb);
 	parse_edp(dev_priv, bdb);
 	parse_psr(dev_priv, bdb);
 	parse_mipi_config(dev_priv, bdb);
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 69a7cb1fa121..31f47ce56587 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -792,6 +792,35 @@ struct bdb_lfp_backlight_data {
 	struct lfp_backlight_control_method backlight_control[16];
 } __packed;
 
+/*
+ * Block 44 - LFP Power Conservation Features Block
+ */
+
+struct als_data_entry {
+	u16 backlight_adjust;
+	u16 lux;
+} __packed;
+
+struct agressiveness_profile_entry {
+	u8 dpst_agressiveness : 4;
+	u8 lace_agressiveness : 4;
+} __packed;
+
+struct bdb_lfp_power {
+	u8 lfp_feature_bits;
+	struct als_data_entry als[5];
+	u8 lace_aggressiveness_profile;
+	u16 dpst;
+	u16 psr;
+	u16 drrs;
+	u16 lace_support;
+	u16 adt;
+	u16 dmrrs;
+	u16 adb;
+	u16 lace_enabled_status;
+	struct agressiveness_profile_entry aggressivenes[16];
+} __packed;
+
 /*
  * Block 52 - MIPI Configuration Block
  */
-- 
2.24.0

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[Intel-gfx] [PATCH 5/5] drm/i915/vbt: Parse power conservation features block

[José Roberto de Souza]

Since VBT 228 is from this block that PSR and other power saving
features configuration should be read from.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 19 +++++++++++-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 29 +++++++++++++++++++
 2 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index a03f56b7b4ef..bf79e9858bd8 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -561,7 +561,23 @@ parse_driver_features(struct drm_i915_private *dev_priv,
 	 */
 	if (!driver->drrs_enabled)
 		dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
-	dev_priv->vbt.psr.enable = driver->psr_enabled;
+	if (bdb->version < 228)
+		dev_priv->vbt.psr.enable = driver->psr_enabled;
+}
+
+static void
+parse_power_conservation_features(struct drm_i915_private *dev_priv,
+				  const struct bdb_header *bdb)
+{
+	const struct bdb_lfp_power *power;
+	u8 panel_type = dev_priv->vbt.panel_type;
+
+	power = find_section(bdb, BDB_LVDS_POWER);
+	if (!power)
+		return;
+
+	if (bdb->version >= 228)
+		dev_priv->vbt.psr.enable = power->psr & (1 << panel_type);
 }
 
 static void
@@ -1878,6 +1894,7 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
 	parse_lfp_backlight(dev_priv, bdb);
 	parse_sdvo_panel_data(dev_priv, bdb);
 	parse_driver_features(dev_priv, bdb);
+	parse_power_conservation_features(dev_priv, bdb);
 	parse_edp(dev_priv, bdb);
 	parse_psr(dev_priv, bdb);
 	parse_mipi_config(dev_priv, bdb);
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 69a7cb1fa121..31f47ce56587 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -792,6 +792,35 @@ struct bdb_lfp_backlight_data {
 	struct lfp_backlight_control_method backlight_control[16];
 } __packed;
 
+/*
+ * Block 44 - LFP Power Conservation Features Block
+ */
+
+struct als_data_entry {
+	u16 backlight_adjust;
+	u16 lux;
+} __packed;
+
+struct agressiveness_profile_entry {
+	u8 dpst_agressiveness : 4;
+	u8 lace_agressiveness : 4;
+} __packed;
+
+struct bdb_lfp_power {
+	u8 lfp_feature_bits;
+	struct als_data_entry als[5];
+	u8 lace_aggressiveness_profile;
+	u16 dpst;
+	u16 psr;
+	u16 drrs;
+	u16 lace_support;
+	u16 adt;
+	u16 dmrrs;
+	u16 adb;
+	u16 lace_enabled_status;
+	struct agressiveness_profile_entry aggressivenes[16];
+} __packed;
+
 /*
  * Block 52 - MIPI Configuration Block
  */
-- 
2.24.0

_______________________________________________
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Re: [PATCH 5/5] drm/i915/vbt: Parse power conservation features block

[Matt Roper]

On Tue, Nov 05, 2019 at 05:45:04PM -0800, José Roberto de Souza wrote:
> Since VBT 228 is from this block that PSR and other power saving
> features configuration should be read from.
> 
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c     | 19 +++++++++++-
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 29 +++++++++++++++++++
>  2 files changed, 47 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index a03f56b7b4ef..bf79e9858bd8 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -561,7 +561,23 @@ parse_driver_features(struct drm_i915_private *dev_priv,
>  	 */
>  	if (!driver->drrs_enabled)
>  		dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
> -	dev_priv->vbt.psr.enable = driver->psr_enabled;
> +	if (bdb->version < 228)
> +		dev_priv->vbt.psr.enable = driver->psr_enabled;
> +}
> +
> +static void
> +parse_power_conservation_features(struct drm_i915_private *dev_priv,
> +				  const struct bdb_header *bdb)
> +{
> +	const struct bdb_lfp_power *power;
> +	u8 panel_type = dev_priv->vbt.panel_type;
> +
> +	power = find_section(bdb, BDB_LVDS_POWER);
> +	if (!power)
> +		return;
> +
> +	if (bdb->version >= 228)
> +		dev_priv->vbt.psr.enable = power->psr & (1 << panel_type);

Should we also be setting dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED
if block 44 tells us it isn't valid on this panel?


Matt

>  }
>  
>  static void
> @@ -1878,6 +1894,7 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
>  	parse_lfp_backlight(dev_priv, bdb);
>  	parse_sdvo_panel_data(dev_priv, bdb);
>  	parse_driver_features(dev_priv, bdb);
> +	parse_power_conservation_features(dev_priv, bdb);
>  	parse_edp(dev_priv, bdb);
>  	parse_psr(dev_priv, bdb);
>  	parse_mipi_config(dev_priv, bdb);
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 69a7cb1fa121..31f47ce56587 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -792,6 +792,35 @@ struct bdb_lfp_backlight_data {
>  	struct lfp_backlight_control_method backlight_control[16];
>  } __packed;
>  
> +/*
> + * Block 44 - LFP Power Conservation Features Block
> + */
> +
> +struct als_data_entry {
> +	u16 backlight_adjust;
> +	u16 lux;
> +} __packed;
> +
> +struct agressiveness_profile_entry {
> +	u8 dpst_agressiveness : 4;
> +	u8 lace_agressiveness : 4;
> +} __packed;
> +
> +struct bdb_lfp_power {
> +	u8 lfp_feature_bits;
> +	struct als_data_entry als[5];
> +	u8 lace_aggressiveness_profile;
> +	u16 dpst;
> +	u16 psr;
> +	u16 drrs;
> +	u16 lace_support;
> +	u16 adt;
> +	u16 dmrrs;
> +	u16 adb;
> +	u16 lace_enabled_status;
> +	struct agressiveness_profile_entry aggressivenes[16];
> +} __packed;
> +
>  /*
>   * Block 52 - MIPI Configuration Block
>   */
> -- 
> 2.24.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 5/5] drm/i915/vbt: Parse power conservation features block

[Matt Roper]

On Tue, Nov 05, 2019 at 05:45:04PM -0800, José Roberto de Souza wrote:
> Since VBT 228 is from this block that PSR and other power saving
> features configuration should be read from.
> 
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c     | 19 +++++++++++-
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 29 +++++++++++++++++++
>  2 files changed, 47 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index a03f56b7b4ef..bf79e9858bd8 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -561,7 +561,23 @@ parse_driver_features(struct drm_i915_private *dev_priv,
>  	 */
>  	if (!driver->drrs_enabled)
>  		dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
> -	dev_priv->vbt.psr.enable = driver->psr_enabled;
> +	if (bdb->version < 228)
> +		dev_priv->vbt.psr.enable = driver->psr_enabled;
> +}
> +
> +static void
> +parse_power_conservation_features(struct drm_i915_private *dev_priv,
> +				  const struct bdb_header *bdb)
> +{
> +	const struct bdb_lfp_power *power;
> +	u8 panel_type = dev_priv->vbt.panel_type;
> +
> +	power = find_section(bdb, BDB_LVDS_POWER);
> +	if (!power)
> +		return;
> +
> +	if (bdb->version >= 228)
> +		dev_priv->vbt.psr.enable = power->psr & (1 << panel_type);

Should we also be setting dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED
if block 44 tells us it isn't valid on this panel?


Matt

>  }
>  
>  static void
> @@ -1878,6 +1894,7 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
>  	parse_lfp_backlight(dev_priv, bdb);
>  	parse_sdvo_panel_data(dev_priv, bdb);
>  	parse_driver_features(dev_priv, bdb);
> +	parse_power_conservation_features(dev_priv, bdb);
>  	parse_edp(dev_priv, bdb);
>  	parse_psr(dev_priv, bdb);
>  	parse_mipi_config(dev_priv, bdb);
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 69a7cb1fa121..31f47ce56587 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -792,6 +792,35 @@ struct bdb_lfp_backlight_data {
>  	struct lfp_backlight_control_method backlight_control[16];
>  } __packed;
>  
> +/*
> + * Block 44 - LFP Power Conservation Features Block
> + */
> +
> +struct als_data_entry {
> +	u16 backlight_adjust;
> +	u16 lux;
> +} __packed;
> +
> +struct agressiveness_profile_entry {
> +	u8 dpst_agressiveness : 4;
> +	u8 lace_agressiveness : 4;
> +} __packed;
> +
> +struct bdb_lfp_power {
> +	u8 lfp_feature_bits;
> +	struct als_data_entry als[5];
> +	u8 lace_aggressiveness_profile;
> +	u16 dpst;
> +	u16 psr;
> +	u16 drrs;
> +	u16 lace_support;
> +	u16 adt;
> +	u16 dmrrs;
> +	u16 adb;
> +	u16 lace_enabled_status;
> +	struct agressiveness_profile_entry aggressivenes[16];
> +} __packed;
> +
>  /*
>   * Block 52 - MIPI Configuration Block
>   */
> -- 
> 2.24.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 5/5] drm/i915/vbt: Parse power conservation features block

[Souza, Jose]

On Tue, 2019-11-12 at 13:21 -0800, Matt Roper wrote:
> On Tue, Nov 05, 2019 at 05:45:04PM -0800, José Roberto de Souza
> wrote:
> > Since VBT 228 is from this block that PSR and other power saving
> > features configuration should be read from.
> > 
> > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_bios.c     | 19 +++++++++++-
> >  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 29
> > +++++++++++++++++++
> >  2 files changed, 47 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > b/drivers/gpu/drm/i915/display/intel_bios.c
> > index a03f56b7b4ef..bf79e9858bd8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -561,7 +561,23 @@ parse_driver_features(struct drm_i915_private
> > *dev_priv,
> >  	 */
> >  	if (!driver->drrs_enabled)
> >  		dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
> > -	dev_priv->vbt.psr.enable = driver->psr_enabled;
> > +	if (bdb->version < 228)
> > +		dev_priv->vbt.psr.enable = driver->psr_enabled;
> > +}
> > +
> > +static void
> > +parse_power_conservation_features(struct drm_i915_private
> > *dev_priv,
> > +				  const struct bdb_header *bdb)
> > +{
> > +	const struct bdb_lfp_power *power;
> > +	u8 panel_type = dev_priv->vbt.panel_type;
> > +
> > +	power = find_section(bdb, BDB_LVDS_POWER);
> > +	if (!power)
> > +		return;
> > +
> > +	if (bdb->version >= 228)
> > +		dev_priv->vbt.psr.enable = power->psr & (1 <<
> > panel_type);
> 
> Should we also be setting dev_priv->vbt.drrs_type =
> DRRS_NOT_SUPPORTED
> if block 44 tells us it isn't valid on this panel?
> 

Yep, it should.
Thanks for catching this.

> 
> Matt
> 
> >  }
> >  
> >  static void
> > @@ -1878,6 +1894,7 @@ void intel_bios_init(struct drm_i915_private
> > *dev_priv)
> >  	parse_lfp_backlight(dev_priv, bdb);
> >  	parse_sdvo_panel_data(dev_priv, bdb);
> >  	parse_driver_features(dev_priv, bdb);
> > +	parse_power_conservation_features(dev_priv, bdb);
> >  	parse_edp(dev_priv, bdb);
> >  	parse_psr(dev_priv, bdb);
> >  	parse_mipi_config(dev_priv, bdb);
> > diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > index 69a7cb1fa121..31f47ce56587 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > @@ -792,6 +792,35 @@ struct bdb_lfp_backlight_data {
> >  	struct lfp_backlight_control_method backlight_control[16];
> >  } __packed;
> >  
> > +/*
> > + * Block 44 - LFP Power Conservation Features Block
> > + */
> > +
> > +struct als_data_entry {
> > +	u16 backlight_adjust;
> > +	u16 lux;
> > +} __packed;
> > +
> > +struct agressiveness_profile_entry {
> > +	u8 dpst_agressiveness : 4;
> > +	u8 lace_agressiveness : 4;
> > +} __packed;
> > +
> > +struct bdb_lfp_power {
> > +	u8 lfp_feature_bits;
> > +	struct als_data_entry als[5];
> > +	u8 lace_aggressiveness_profile;
> > +	u16 dpst;
> > +	u16 psr;
> > +	u16 drrs;
> > +	u16 lace_support;
> > +	u16 adt;
> > +	u16 dmrrs;
> > +	u16 adb;
> > +	u16 lace_enabled_status;
> > +	struct agressiveness_profile_entry aggressivenes[16];
> > +} __packed;
> > +
> >  /*
> >   * Block 52 - MIPI Configuration Block
> >   */
> > -- 
> > 2.24.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Re: [Intel-gfx] [PATCH 5/5] drm/i915/vbt: Parse power conservation features block

[Souza, Jose]

On Tue, 2019-11-12 at 13:21 -0800, Matt Roper wrote:
> On Tue, Nov 05, 2019 at 05:45:04PM -0800, José Roberto de Souza
> wrote:
> > Since VBT 228 is from this block that PSR and other power saving
> > features configuration should be read from.
> > 
> > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_bios.c     | 19 +++++++++++-
> >  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 29
> > +++++++++++++++++++
> >  2 files changed, 47 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > b/drivers/gpu/drm/i915/display/intel_bios.c
> > index a03f56b7b4ef..bf79e9858bd8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -561,7 +561,23 @@ parse_driver_features(struct drm_i915_private
> > *dev_priv,
> >  	 */
> >  	if (!driver->drrs_enabled)
> >  		dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
> > -	dev_priv->vbt.psr.enable = driver->psr_enabled;
> > +	if (bdb->version < 228)
> > +		dev_priv->vbt.psr.enable = driver->psr_enabled;
> > +}
> > +
> > +static void
> > +parse_power_conservation_features(struct drm_i915_private
> > *dev_priv,
> > +				  const struct bdb_header *bdb)
> > +{
> > +	const struct bdb_lfp_power *power;
> > +	u8 panel_type = dev_priv->vbt.panel_type;
> > +
> > +	power = find_section(bdb, BDB_LVDS_POWER);
> > +	if (!power)
> > +		return;
> > +
> > +	if (bdb->version >= 228)
> > +		dev_priv->vbt.psr.enable = power->psr & (1 <<
> > panel_type);
> 
> Should we also be setting dev_priv->vbt.drrs_type =
> DRRS_NOT_SUPPORTED
> if block 44 tells us it isn't valid on this panel?
> 

Yep, it should.
Thanks for catching this.

> 
> Matt
> 
> >  }
> >  
> >  static void
> > @@ -1878,6 +1894,7 @@ void intel_bios_init(struct drm_i915_private
> > *dev_priv)
> >  	parse_lfp_backlight(dev_priv, bdb);
> >  	parse_sdvo_panel_data(dev_priv, bdb);
> >  	parse_driver_features(dev_priv, bdb);
> > +	parse_power_conservation_features(dev_priv, bdb);
> >  	parse_edp(dev_priv, bdb);
> >  	parse_psr(dev_priv, bdb);
> >  	parse_mipi_config(dev_priv, bdb);
> > diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > index 69a7cb1fa121..31f47ce56587 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > @@ -792,6 +792,35 @@ struct bdb_lfp_backlight_data {
> >  	struct lfp_backlight_control_method backlight_control[16];
> >  } __packed;
> >  
> > +/*
> > + * Block 44 - LFP Power Conservation Features Block
> > + */
> > +
> > +struct als_data_entry {
> > +	u16 backlight_adjust;
> > +	u16 lux;
> > +} __packed;
> > +
> > +struct agressiveness_profile_entry {
> > +	u8 dpst_agressiveness : 4;
> > +	u8 lace_agressiveness : 4;
> > +} __packed;
> > +
> > +struct bdb_lfp_power {
> > +	u8 lfp_feature_bits;
> > +	struct als_data_entry als[5];
> > +	u8 lace_aggressiveness_profile;
> > +	u16 dpst;
> > +	u16 psr;
> > +	u16 drrs;
> > +	u16 lace_support;
> > +	u16 adt;
> > +	u16 dmrrs;
> > +	u16 adb;
> > +	u16 lace_enabled_status;
> > +	struct agressiveness_profile_entry aggressivenes[16];
> > +} __packed;
> > +
> >  /*
> >   * Block 52 - MIPI Configuration Block
> >   */
> > -- 
> > 2.24.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Re: [PATCH 5/5] drm/i915/vbt: Parse power conservation features block

[Souza, Jose]

On Tue, 2019-11-12 at 23:56 +0000, Souza, Jose wrote:
> On Tue, 2019-11-12 at 13:21 -0800, Matt Roper wrote:
> > On Tue, Nov 05, 2019 at 05:45:04PM -0800, José Roberto de Souza
> > wrote:
> > > Since VBT 228 is from this block that PSR and other power saving
> > > features configuration should be read from.
> > > 
> > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_bios.c     | 19 +++++++++++-
> > >  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 29
> > > +++++++++++++++++++
> > >  2 files changed, 47 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > > b/drivers/gpu/drm/i915/display/intel_bios.c
> > > index a03f56b7b4ef..bf79e9858bd8 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > > @@ -561,7 +561,23 @@ parse_driver_features(struct
> > > drm_i915_private
> > > *dev_priv,
> > >  	 */
> > >  	if (!driver->drrs_enabled)
> > >  		dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
> > > -	dev_priv->vbt.psr.enable = driver->psr_enabled;
> > > +	if (bdb->version < 228)
> > > +		dev_priv->vbt.psr.enable = driver->psr_enabled;
> > > +}
> > > +
> > > +static void
> > > +parse_power_conservation_features(struct drm_i915_private
> > > *dev_priv,
> > > +				  const struct bdb_header *bdb)
> > > +{
> > > +	const struct bdb_lfp_power *power;
> > > +	u8 panel_type = dev_priv->vbt.panel_type;
> > > +
> > > +	power = find_section(bdb, BDB_LVDS_POWER);
> > > +	if (!power)
> > > +		return;
> > > +
> > > +	if (bdb->version >= 228)
> > > +		dev_priv->vbt.psr.enable = power->psr & (1 <<
> > > panel_type);
> > 
> > Should we also be setting dev_priv->vbt.drrs_type =
> > DRRS_NOT_SUPPORTED
> > if block 44 tells us it isn't valid on this panel?
> > 
> 
> Yep, it should.
> Thanks for catching this.

Nothing from block 40 is obsolete, it has the information about the
DRRS type of all the 16 possible panels so is better keep relying on it
as block 44 only have only the information if DRRS is supported or not.

I also checked the other features but we don't implement those.


> 
> > Matt
> > 
> > >  }
> > >  
> > >  static void
> > > @@ -1878,6 +1894,7 @@ void intel_bios_init(struct
> > > drm_i915_private
> > > *dev_priv)
> > >  	parse_lfp_backlight(dev_priv, bdb);
> > >  	parse_sdvo_panel_data(dev_priv, bdb);
> > >  	parse_driver_features(dev_priv, bdb);
> > > +	parse_power_conservation_features(dev_priv, bdb);
> > >  	parse_edp(dev_priv, bdb);
> > >  	parse_psr(dev_priv, bdb);
> > >  	parse_mipi_config(dev_priv, bdb);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > index 69a7cb1fa121..31f47ce56587 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > @@ -792,6 +792,35 @@ struct bdb_lfp_backlight_data {
> > >  	struct lfp_backlight_control_method backlight_control[16];
> > >  } __packed;
> > >  
> > > +/*
> > > + * Block 44 - LFP Power Conservation Features Block
> > > + */
> > > +
> > > +struct als_data_entry {
> > > +	u16 backlight_adjust;
> > > +	u16 lux;
> > > +} __packed;
> > > +
> > > +struct agressiveness_profile_entry {
> > > +	u8 dpst_agressiveness : 4;
> > > +	u8 lace_agressiveness : 4;
> > > +} __packed;
> > > +
> > > +struct bdb_lfp_power {
> > > +	u8 lfp_feature_bits;
> > > +	struct als_data_entry als[5];
> > > +	u8 lace_aggressiveness_profile;
> > > +	u16 dpst;
> > > +	u16 psr;
> > > +	u16 drrs;
> > > +	u16 lace_support;
> > > +	u16 adt;
> > > +	u16 dmrrs;
> > > +	u16 adb;
> > > +	u16 lace_enabled_status;
> > > +	struct agressiveness_profile_entry aggressivenes[16];
> > > +} __packed;
> > > +
> > >  /*
> > >   * Block 52 - MIPI Configuration Block
> > >   */
> > > -- 
> > > 2.24.0
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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Re: [Intel-gfx] [PATCH 5/5] drm/i915/vbt: Parse power conservation features block

[Souza, Jose]

On Tue, 2019-11-12 at 23:56 +0000, Souza, Jose wrote:
> On Tue, 2019-11-12 at 13:21 -0800, Matt Roper wrote:
> > On Tue, Nov 05, 2019 at 05:45:04PM -0800, José Roberto de Souza
> > wrote:
> > > Since VBT 228 is from this block that PSR and other power saving
> > > features configuration should be read from.
> > > 
> > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_bios.c     | 19 +++++++++++-
> > >  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 29
> > > +++++++++++++++++++
> > >  2 files changed, 47 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > > b/drivers/gpu/drm/i915/display/intel_bios.c
> > > index a03f56b7b4ef..bf79e9858bd8 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > > @@ -561,7 +561,23 @@ parse_driver_features(struct
> > > drm_i915_private
> > > *dev_priv,
> > >  	 */
> > >  	if (!driver->drrs_enabled)
> > >  		dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
> > > -	dev_priv->vbt.psr.enable = driver->psr_enabled;
> > > +	if (bdb->version < 228)
> > > +		dev_priv->vbt.psr.enable = driver->psr_enabled;
> > > +}
> > > +
> > > +static void
> > > +parse_power_conservation_features(struct drm_i915_private
> > > *dev_priv,
> > > +				  const struct bdb_header *bdb)
> > > +{
> > > +	const struct bdb_lfp_power *power;
> > > +	u8 panel_type = dev_priv->vbt.panel_type;
> > > +
> > > +	power = find_section(bdb, BDB_LVDS_POWER);
> > > +	if (!power)
> > > +		return;
> > > +
> > > +	if (bdb->version >= 228)
> > > +		dev_priv->vbt.psr.enable = power->psr & (1 <<
> > > panel_type);
> > 
> > Should we also be setting dev_priv->vbt.drrs_type =
> > DRRS_NOT_SUPPORTED
> > if block 44 tells us it isn't valid on this panel?
> > 
> 
> Yep, it should.
> Thanks for catching this.

Nothing from block 40 is obsolete, it has the information about the
DRRS type of all the 16 possible panels so is better keep relying on it
as block 44 only have only the information if DRRS is supported or not.

I also checked the other features but we don't implement those.


> 
> > Matt
> > 
> > >  }
> > >  
> > >  static void
> > > @@ -1878,6 +1894,7 @@ void intel_bios_init(struct
> > > drm_i915_private
> > > *dev_priv)
> > >  	parse_lfp_backlight(dev_priv, bdb);
> > >  	parse_sdvo_panel_data(dev_priv, bdb);
> > >  	parse_driver_features(dev_priv, bdb);
> > > +	parse_power_conservation_features(dev_priv, bdb);
> > >  	parse_edp(dev_priv, bdb);
> > >  	parse_psr(dev_priv, bdb);
> > >  	parse_mipi_config(dev_priv, bdb);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > index 69a7cb1fa121..31f47ce56587 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > @@ -792,6 +792,35 @@ struct bdb_lfp_backlight_data {
> > >  	struct lfp_backlight_control_method backlight_control[16];
> > >  } __packed;
> > >  
> > > +/*
> > > + * Block 44 - LFP Power Conservation Features Block
> > > + */
> > > +
> > > +struct als_data_entry {
> > > +	u16 backlight_adjust;
> > > +	u16 lux;
> > > +} __packed;
> > > +
> > > +struct agressiveness_profile_entry {
> > > +	u8 dpst_agressiveness : 4;
> > > +	u8 lace_agressiveness : 4;
> > > +} __packed;
> > > +
> > > +struct bdb_lfp_power {
> > > +	u8 lfp_feature_bits;
> > > +	struct als_data_entry als[5];
> > > +	u8 lace_aggressiveness_profile;
> > > +	u16 dpst;
> > > +	u16 psr;
> > > +	u16 drrs;
> > > +	u16 lace_support;
> > > +	u16 adt;
> > > +	u16 dmrrs;
> > > +	u16 adb;
> > > +	u16 lace_enabled_status;
> > > +	struct agressiveness_profile_entry aggressivenes[16];
> > > +} __packed;
> > > +
> > >  /*
> > >   * Block 52 - MIPI Configuration Block
> > >   */
> > > -- 
> > > 2.24.0
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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Re: [PATCH 5/5] drm/i915/vbt: Parse power conservation features block

[Matt Roper]

On Mon, Nov 25, 2019 at 04:47:39PM -0800, Souza, Jose wrote:
> On Tue, 2019-11-12 at 23:56 +0000, Souza, Jose wrote:
> > On Tue, 2019-11-12 at 13:21 -0800, Matt Roper wrote:
> > > On Tue, Nov 05, 2019 at 05:45:04PM -0800, José Roberto de Souza
> > > wrote:
> > > > Since VBT 228 is from this block that PSR and other power saving
> > > > features configuration should be read from.
> > > > 
> > > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_bios.c     | 19 +++++++++++-
> > > >  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 29
> > > > +++++++++++++++++++
> > > >  2 files changed, 47 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > > > b/drivers/gpu/drm/i915/display/intel_bios.c
> > > > index a03f56b7b4ef..bf79e9858bd8 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > > > @@ -561,7 +561,23 @@ parse_driver_features(struct
> > > > drm_i915_private
> > > > *dev_priv,
> > > >  	 */
> > > >  	if (!driver->drrs_enabled)
> > > >  		dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
> > > > -	dev_priv->vbt.psr.enable = driver->psr_enabled;
> > > > +	if (bdb->version < 228)
> > > > +		dev_priv->vbt.psr.enable = driver->psr_enabled;
> > > > +}
> > > > +
> > > > +static void
> > > > +parse_power_conservation_features(struct drm_i915_private
> > > > *dev_priv,
> > > > +				  const struct bdb_header *bdb)
> > > > +{
> > > > +	const struct bdb_lfp_power *power;
> > > > +	u8 panel_type = dev_priv->vbt.panel_type;
> > > > +
> > > > +	power = find_section(bdb, BDB_LVDS_POWER);
> > > > +	if (!power)
> > > > +		return;
> > > > +
> > > > +	if (bdb->version >= 228)
> > > > +		dev_priv->vbt.psr.enable = power->psr & (1 <<
> > > > panel_type);
> > > 
> > > Should we also be setting dev_priv->vbt.drrs_type =
> > > DRRS_NOT_SUPPORTED
> > > if block 44 tells us it isn't valid on this panel?
> > > 
> > 
> > Yep, it should.
> > Thanks for catching this.
> 
> Nothing from block 40 is obsolete, it has the information about the
> DRRS type of all the 16 possible panels so is better keep relying on it
> as block 44 only have only the information if DRRS is supported or not.
> 
> I also checked the other features but we don't implement those.

I think the DRRS_NOT_SUPPORTED is currently being set based on the
contents of block 12 (in parse_driver_features).  Block 12 does list the
bit we're looking at as obsolete in version 228 (moved to block 44).


Matt

> 
> 
> > 
> > > Matt
> > > 
> > > >  }
> > > >  
> > > >  static void
> > > > @@ -1878,6 +1894,7 @@ void intel_bios_init(struct
> > > > drm_i915_private
> > > > *dev_priv)
> > > >  	parse_lfp_backlight(dev_priv, bdb);
> > > >  	parse_sdvo_panel_data(dev_priv, bdb);
> > > >  	parse_driver_features(dev_priv, bdb);
> > > > +	parse_power_conservation_features(dev_priv, bdb);
> > > >  	parse_edp(dev_priv, bdb);
> > > >  	parse_psr(dev_priv, bdb);
> > > >  	parse_mipi_config(dev_priv, bdb);
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > > b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > > index 69a7cb1fa121..31f47ce56587 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > > @@ -792,6 +792,35 @@ struct bdb_lfp_backlight_data {
> > > >  	struct lfp_backlight_control_method backlight_control[16];
> > > >  } __packed;
> > > >  
> > > > +/*
> > > > + * Block 44 - LFP Power Conservation Features Block
> > > > + */
> > > > +
> > > > +struct als_data_entry {
> > > > +	u16 backlight_adjust;
> > > > +	u16 lux;
> > > > +} __packed;
> > > > +
> > > > +struct agressiveness_profile_entry {
> > > > +	u8 dpst_agressiveness : 4;
> > > > +	u8 lace_agressiveness : 4;
> > > > +} __packed;
> > > > +
> > > > +struct bdb_lfp_power {
> > > > +	u8 lfp_feature_bits;
> > > > +	struct als_data_entry als[5];
> > > > +	u8 lace_aggressiveness_profile;
> > > > +	u16 dpst;
> > > > +	u16 psr;
> > > > +	u16 drrs;
> > > > +	u16 lace_support;
> > > > +	u16 adt;
> > > > +	u16 dmrrs;
> > > > +	u16 adb;
> > > > +	u16 lace_enabled_status;
> > > > +	struct agressiveness_profile_entry aggressivenes[16];
> > > > +} __packed;
> > > > +
> > > >  /*
> > > >   * Block 52 - MIPI Configuration Block
> > > >   */
> > > > -- 
> > > > 2.24.0
> > > > 
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 5/5] drm/i915/vbt: Parse power conservation features block

[Matt Roper]

On Mon, Nov 25, 2019 at 04:47:39PM -0800, Souza, Jose wrote:
> On Tue, 2019-11-12 at 23:56 +0000, Souza, Jose wrote:
> > On Tue, 2019-11-12 at 13:21 -0800, Matt Roper wrote:
> > > On Tue, Nov 05, 2019 at 05:45:04PM -0800, José Roberto de Souza
> > > wrote:
> > > > Since VBT 228 is from this block that PSR and other power saving
> > > > features configuration should be read from.
> > > > 
> > > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_bios.c     | 19 +++++++++++-
> > > >  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 29
> > > > +++++++++++++++++++
> > > >  2 files changed, 47 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > > > b/drivers/gpu/drm/i915/display/intel_bios.c
> > > > index a03f56b7b4ef..bf79e9858bd8 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > > > @@ -561,7 +561,23 @@ parse_driver_features(struct
> > > > drm_i915_private
> > > > *dev_priv,
> > > >  	 */
> > > >  	if (!driver->drrs_enabled)
> > > >  		dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
> > > > -	dev_priv->vbt.psr.enable = driver->psr_enabled;
> > > > +	if (bdb->version < 228)
> > > > +		dev_priv->vbt.psr.enable = driver->psr_enabled;
> > > > +}
> > > > +
> > > > +static void
> > > > +parse_power_conservation_features(struct drm_i915_private
> > > > *dev_priv,
> > > > +				  const struct bdb_header *bdb)
> > > > +{
> > > > +	const struct bdb_lfp_power *power;
> > > > +	u8 panel_type = dev_priv->vbt.panel_type;
> > > > +
> > > > +	power = find_section(bdb, BDB_LVDS_POWER);
> > > > +	if (!power)
> > > > +		return;
> > > > +
> > > > +	if (bdb->version >= 228)
> > > > +		dev_priv->vbt.psr.enable = power->psr & (1 <<
> > > > panel_type);
> > > 
> > > Should we also be setting dev_priv->vbt.drrs_type =
> > > DRRS_NOT_SUPPORTED
> > > if block 44 tells us it isn't valid on this panel?
> > > 
> > 
> > Yep, it should.
> > Thanks for catching this.
> 
> Nothing from block 40 is obsolete, it has the information about the
> DRRS type of all the 16 possible panels so is better keep relying on it
> as block 44 only have only the information if DRRS is supported or not.
> 
> I also checked the other features but we don't implement those.

I think the DRRS_NOT_SUPPORTED is currently being set based on the
contents of block 12 (in parse_driver_features).  Block 12 does list the
bit we're looking at as obsolete in version 228 (moved to block 44).


Matt

> 
> 
> > 
> > > Matt
> > > 
> > > >  }
> > > >  
> > > >  static void
> > > > @@ -1878,6 +1894,7 @@ void intel_bios_init(struct
> > > > drm_i915_private
> > > > *dev_priv)
> > > >  	parse_lfp_backlight(dev_priv, bdb);
> > > >  	parse_sdvo_panel_data(dev_priv, bdb);
> > > >  	parse_driver_features(dev_priv, bdb);
> > > > +	parse_power_conservation_features(dev_priv, bdb);
> > > >  	parse_edp(dev_priv, bdb);
> > > >  	parse_psr(dev_priv, bdb);
> > > >  	parse_mipi_config(dev_priv, bdb);
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > > b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > > index 69a7cb1fa121..31f47ce56587 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > > @@ -792,6 +792,35 @@ struct bdb_lfp_backlight_data {
> > > >  	struct lfp_backlight_control_method backlight_control[16];
> > > >  } __packed;
> > > >  
> > > > +/*
> > > > + * Block 44 - LFP Power Conservation Features Block
> > > > + */
> > > > +
> > > > +struct als_data_entry {
> > > > +	u16 backlight_adjust;
> > > > +	u16 lux;
> > > > +} __packed;
> > > > +
> > > > +struct agressiveness_profile_entry {
> > > > +	u8 dpst_agressiveness : 4;
> > > > +	u8 lace_agressiveness : 4;
> > > > +} __packed;
> > > > +
> > > > +struct bdb_lfp_power {
> > > > +	u8 lfp_feature_bits;
> > > > +	struct als_data_entry als[5];
> > > > +	u8 lace_aggressiveness_profile;
> > > > +	u16 dpst;
> > > > +	u16 psr;
> > > > +	u16 drrs;
> > > > +	u16 lace_support;
> > > > +	u16 adt;
> > > > +	u16 dmrrs;
> > > > +	u16 adb;
> > > > +	u16 lace_enabled_status;
> > > > +	struct agressiveness_profile_entry aggressivenes[16];
> > > > +} __packed;
> > > > +
> > > >  /*
> > > >   * Block 52 - MIPI Configuration Block
> > > >   */
> > > > -- 
> > > > 2.24.0
> > > > 
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 5/5] drm/i915/vbt: Parse power conservation features block

[Souza, Jose]

On Wed, 2019-11-27 at 10:02 -0800, Matt Roper wrote:
> On Mon, Nov 25, 2019 at 04:47:39PM -0800, Souza, Jose wrote:
> > On Tue, 2019-11-12 at 23:56 +0000, Souza, Jose wrote:
> > > On Tue, 2019-11-12 at 13:21 -0800, Matt Roper wrote:
> > > > On Tue, Nov 05, 2019 at 05:45:04PM -0800, José Roberto de Souza
> > > > wrote:
> > > > > Since VBT 228 is from this block that PSR and other power
> > > > > saving
> > > > > features configuration should be read from.
> > > > > 
> > > > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/display/intel_bios.c     | 19
> > > > > +++++++++++-
> > > > >  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 29
> > > > > +++++++++++++++++++
> > > > >  2 files changed, 47 insertions(+), 1 deletion(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > > > > b/drivers/gpu/drm/i915/display/intel_bios.c
> > > > > index a03f56b7b4ef..bf79e9858bd8 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > > > > @@ -561,7 +561,23 @@ parse_driver_features(struct
> > > > > drm_i915_private
> > > > > *dev_priv,
> > > > >  	 */
> > > > >  	if (!driver->drrs_enabled)
> > > > >  		dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
> > > > > -	dev_priv->vbt.psr.enable = driver->psr_enabled;
> > > > > +	if (bdb->version < 228)
> > > > > +		dev_priv->vbt.psr.enable = driver->psr_enabled;
> > > > > +}
> > > > > +
> > > > > +static void
> > > > > +parse_power_conservation_features(struct drm_i915_private
> > > > > *dev_priv,
> > > > > +				  const struct bdb_header *bdb)
> > > > > +{
> > > > > +	const struct bdb_lfp_power *power;
> > > > > +	u8 panel_type = dev_priv->vbt.panel_type;
> > > > > +
> > > > > +	power = find_section(bdb, BDB_LVDS_POWER);
> > > > > +	if (!power)
> > > > > +		return;
> > > > > +
> > > > > +	if (bdb->version >= 228)
> > > > > +		dev_priv->vbt.psr.enable = power->psr & (1 <<
> > > > > panel_type);
> > > > 
> > > > Should we also be setting dev_priv->vbt.drrs_type =
> > > > DRRS_NOT_SUPPORTED
> > > > if block 44 tells us it isn't valid on this panel?
> > > > 
> > > 
> > > Yep, it should.
> > > Thanks for catching this.
> > 
> > Nothing from block 40 is obsolete, it has the information about the
> > DRRS type of all the 16 possible panels so is better keep relying
> > on it
> > as block 44 only have only the information if DRRS is supported or
> > not.
> > 
> > I also checked the other features but we don't implement those.
> 
> I think the DRRS_NOT_SUPPORTED is currently being set based on the
> contents of block 12 (in parse_driver_features).  Block 12 does list
> the
> bit we're looking at as obsolete in version 228 (moved to block 44).

Now I got it.
Thanks I will fix that.

> 
> 
> Matt
> 
> > 
> > > > Matt
> > > > 
> > > > >  }
> > > > >  
> > > > >  static void
> > > > > @@ -1878,6 +1894,7 @@ void intel_bios_init(struct
> > > > > drm_i915_private
> > > > > *dev_priv)
> > > > >  	parse_lfp_backlight(dev_priv, bdb);
> > > > >  	parse_sdvo_panel_data(dev_priv, bdb);
> > > > >  	parse_driver_features(dev_priv, bdb);
> > > > > +	parse_power_conservation_features(dev_priv, bdb);
> > > > >  	parse_edp(dev_priv, bdb);
> > > > >  	parse_psr(dev_priv, bdb);
> > > > >  	parse_mipi_config(dev_priv, bdb);
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > > > b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > > > index 69a7cb1fa121..31f47ce56587 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > > > @@ -792,6 +792,35 @@ struct bdb_lfp_backlight_data {
> > > > >  	struct lfp_backlight_control_method
> > > > > backlight_control[16];
> > > > >  } __packed;
> > > > >  
> > > > > +/*
> > > > > + * Block 44 - LFP Power Conservation Features Block
> > > > > + */
> > > > > +
> > > > > +struct als_data_entry {
> > > > > +	u16 backlight_adjust;
> > > > > +	u16 lux;
> > > > > +} __packed;
> > > > > +
> > > > > +struct agressiveness_profile_entry {
> > > > > +	u8 dpst_agressiveness : 4;
> > > > > +	u8 lace_agressiveness : 4;
> > > > > +} __packed;
> > > > > +
> > > > > +struct bdb_lfp_power {
> > > > > +	u8 lfp_feature_bits;
> > > > > +	struct als_data_entry als[5];
> > > > > +	u8 lace_aggressiveness_profile;
> > > > > +	u16 dpst;
> > > > > +	u16 psr;
> > > > > +	u16 drrs;
> > > > > +	u16 lace_support;
> > > > > +	u16 adt;
> > > > > +	u16 dmrrs;
> > > > > +	u16 adb;
> > > > > +	u16 lace_enabled_status;
> > > > > +	struct agressiveness_profile_entry aggressivenes[16];
> > > > > +} __packed;
> > > > > +
> > > > >  /*
> > > > >   * Block 52 - MIPI Configuration Block
> > > > >   */
> > > > > -- 
> > > > > 2.24.0
> > > > > 
> > > > > _______________________________________________
> > > > > Intel-gfx mailing list
> > > > > Intel-gfx@lists.freedesktop.org
> > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 5/5] drm/i915/vbt: Parse power conservation features block

[Souza, Jose]

On Wed, 2019-11-27 at 10:02 -0800, Matt Roper wrote:
> On Mon, Nov 25, 2019 at 04:47:39PM -0800, Souza, Jose wrote:
> > On Tue, 2019-11-12 at 23:56 +0000, Souza, Jose wrote:
> > > On Tue, 2019-11-12 at 13:21 -0800, Matt Roper wrote:
> > > > On Tue, Nov 05, 2019 at 05:45:04PM -0800, José Roberto de Souza
> > > > wrote:
> > > > > Since VBT 228 is from this block that PSR and other power
> > > > > saving
> > > > > features configuration should be read from.
> > > > > 
> > > > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/display/intel_bios.c     | 19
> > > > > +++++++++++-
> > > > >  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 29
> > > > > +++++++++++++++++++
> > > > >  2 files changed, 47 insertions(+), 1 deletion(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > > > > b/drivers/gpu/drm/i915/display/intel_bios.c
> > > > > index a03f56b7b4ef..bf79e9858bd8 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > > > > @@ -561,7 +561,23 @@ parse_driver_features(struct
> > > > > drm_i915_private
> > > > > *dev_priv,
> > > > >  	 */
> > > > >  	if (!driver->drrs_enabled)
> > > > >  		dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
> > > > > -	dev_priv->vbt.psr.enable = driver->psr_enabled;
> > > > > +	if (bdb->version < 228)
> > > > > +		dev_priv->vbt.psr.enable = driver->psr_enabled;
> > > > > +}
> > > > > +
> > > > > +static void
> > > > > +parse_power_conservation_features(struct drm_i915_private
> > > > > *dev_priv,
> > > > > +				  const struct bdb_header *bdb)
> > > > > +{
> > > > > +	const struct bdb_lfp_power *power;
> > > > > +	u8 panel_type = dev_priv->vbt.panel_type;
> > > > > +
> > > > > +	power = find_section(bdb, BDB_LVDS_POWER);
> > > > > +	if (!power)
> > > > > +		return;
> > > > > +
> > > > > +	if (bdb->version >= 228)
> > > > > +		dev_priv->vbt.psr.enable = power->psr & (1 <<
> > > > > panel_type);
> > > > 
> > > > Should we also be setting dev_priv->vbt.drrs_type =
> > > > DRRS_NOT_SUPPORTED
> > > > if block 44 tells us it isn't valid on this panel?
> > > > 
> > > 
> > > Yep, it should.
> > > Thanks for catching this.
> > 
> > Nothing from block 40 is obsolete, it has the information about the
> > DRRS type of all the 16 possible panels so is better keep relying
> > on it
> > as block 44 only have only the information if DRRS is supported or
> > not.
> > 
> > I also checked the other features but we don't implement those.
> 
> I think the DRRS_NOT_SUPPORTED is currently being set based on the
> contents of block 12 (in parse_driver_features).  Block 12 does list
> the
> bit we're looking at as obsolete in version 228 (moved to block 44).

Now I got it.
Thanks I will fix that.

> 
> 
> Matt
> 
> > 
> > > > Matt
> > > > 
> > > > >  }
> > > > >  
> > > > >  static void
> > > > > @@ -1878,6 +1894,7 @@ void intel_bios_init(struct
> > > > > drm_i915_private
> > > > > *dev_priv)
> > > > >  	parse_lfp_backlight(dev_priv, bdb);
> > > > >  	parse_sdvo_panel_data(dev_priv, bdb);
> > > > >  	parse_driver_features(dev_priv, bdb);
> > > > > +	parse_power_conservation_features(dev_priv, bdb);
> > > > >  	parse_edp(dev_priv, bdb);
> > > > >  	parse_psr(dev_priv, bdb);
> > > > >  	parse_mipi_config(dev_priv, bdb);
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > > > b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > > > index 69a7cb1fa121..31f47ce56587 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > > > > @@ -792,6 +792,35 @@ struct bdb_lfp_backlight_data {
> > > > >  	struct lfp_backlight_control_method
> > > > > backlight_control[16];
> > > > >  } __packed;
> > > > >  
> > > > > +/*
> > > > > + * Block 44 - LFP Power Conservation Features Block
> > > > > + */
> > > > > +
> > > > > +struct als_data_entry {
> > > > > +	u16 backlight_adjust;
> > > > > +	u16 lux;
> > > > > +} __packed;
> > > > > +
> > > > > +struct agressiveness_profile_entry {
> > > > > +	u8 dpst_agressiveness : 4;
> > > > > +	u8 lace_agressiveness : 4;
> > > > > +} __packed;
> > > > > +
> > > > > +struct bdb_lfp_power {
> > > > > +	u8 lfp_feature_bits;
> > > > > +	struct als_data_entry als[5];
> > > > > +	u8 lace_aggressiveness_profile;
> > > > > +	u16 dpst;
> > > > > +	u16 psr;
> > > > > +	u16 drrs;
> > > > > +	u16 lace_support;
> > > > > +	u16 adt;
> > > > > +	u16 dmrrs;
> > > > > +	u16 adb;
> > > > > +	u16 lace_enabled_status;
> > > > > +	struct agressiveness_profile_entry aggressivenes[16];
> > > > > +} __packed;
> > > > > +
> > > > >  /*
> > > > >   * Block 52 - MIPI Configuration Block
> > > > >   */
> > > > > -- 
> > > > > 2.24.0
> > > > > 
> > > > > _______________________________________________
> > > > > Intel-gfx mailing list
> > > > > Intel-gfx@lists.freedesktop.org
> > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/psr: Add bits per pixel limitation

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915/psr: Add bits per pixel limitation
URL   : https://patchwork.freedesktop.org/series/69025/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7264 -> Patchwork_15142
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/index.html

Known issues
------------

  Here are the changes found in Patchwork_15142 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7500u:       [PASS][3] -> [FAIL][4] ([fdo#109635 ] / [fdo#110387])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html

  
#### Possible fixes ####

  * igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
    - fi-icl-u3:          [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html

  * igt@i915_module_load@reload:
    - {fi-icl-dsi}:       [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/fi-icl-dsi/igt@i915_module_load@reload.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/fi-icl-dsi/igt@i915_module_load@reload.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 
  [fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387


Participating hosts (51 -> 43)
------------------------------

  Additional (1): fi-tgl-u 
  Missing    (9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-ctg-p8600 fi-gdg-551 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7264 -> Patchwork_15142

  CI-20190529: 20190529
  CI_DRM_7264: f5cfd96ad87b58bf3b5dfa5365f8beb8bac15a38 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5263: 8a5d44dc5e51622cd43f23c2cf24d44c24a0564d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15142: 195205377ead3b57d89c7bbe84e8c8b2a6674aed @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

195205377ead drm/i915/vbt: Parse power conservation features block
e32f36a265ce drm/i915/psr: Check if sink PSR capability changed
599cc781b5d5 drm/i915/psr: Enable ALPM lock timeout error interruption
06234ff23d8f drm/i915/psr: Refactor psr short pulse handler
dd7008d4828a drm/i915/psr: Add bits per pixel limitation

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/psr: Add bits per pixel limitation

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915/psr: Add bits per pixel limitation
URL   : https://patchwork.freedesktop.org/series/69025/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7264 -> Patchwork_15142
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/index.html

Known issues
------------

  Here are the changes found in Patchwork_15142 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7500u:       [PASS][3] -> [FAIL][4] ([fdo#109635 ] / [fdo#110387])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html

  
#### Possible fixes ####

  * igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
    - fi-icl-u3:          [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html

  * igt@i915_module_load@reload:
    - {fi-icl-dsi}:       [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/fi-icl-dsi/igt@i915_module_load@reload.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/fi-icl-dsi/igt@i915_module_load@reload.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 
  [fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387


Participating hosts (51 -> 43)
------------------------------

  Additional (1): fi-tgl-u 
  Missing    (9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-ctg-p8600 fi-gdg-551 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7264 -> Patchwork_15142

  CI-20190529: 20190529
  CI_DRM_7264: f5cfd96ad87b58bf3b5dfa5365f8beb8bac15a38 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5263: 8a5d44dc5e51622cd43f23c2cf24d44c24a0564d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15142: 195205377ead3b57d89c7bbe84e8c8b2a6674aed @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

195205377ead drm/i915/vbt: Parse power conservation features block
e32f36a265ce drm/i915/psr: Check if sink PSR capability changed
599cc781b5d5 drm/i915/psr: Enable ALPM lock timeout error interruption
06234ff23d8f drm/i915/psr: Refactor psr short pulse handler
dd7008d4828a drm/i915/psr: Add bits per pixel limitation

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915/psr: Add bits per pixel limitation

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915/psr: Add bits per pixel limitation
URL   : https://patchwork.freedesktop.org/series/69025/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7264_full -> Patchwork_15142_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_15142_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#112080]) +13 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb2/igt@gem_busy@busy-vcs1.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb7/igt@gem_busy@busy-vcs1.html

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-kbl:          [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +7 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-kbl3/igt@gem_ctx_isolation@rcs0-s3.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-kbl7/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_ctx_isolation@vcs1-s3:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#109276] / [fdo#112080])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb1/igt@gem_ctx_isolation@vcs1-s3.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb7/igt@gem_ctx_isolation@vcs1-s3.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#110841])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb5/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_exec_schedule@preempt-contexts-bsd2:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#109276]) +19 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb1/igt@gem_exec_schedule@preempt-contexts-bsd2.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb3/igt@gem_exec_schedule@preempt-contexts-bsd2.html

  * igt@gem_exec_schedule@reorder-wide-bsd:
    - shard-iclb:         [PASS][11] -> [SKIP][12] ([fdo#112146]) +7 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb7/igt@gem_exec_schedule@reorder-wide-bsd.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html

  * igt@gem_userptr_blits@sync-unmap:
    - shard-snb:          [PASS][13] -> [DMESG-WARN][14] ([fdo#111870])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-snb1/igt@gem_userptr_blits@sync-unmap.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-snb2/igt@gem_userptr_blits@sync-unmap.html

  * igt@i915_selftest@mock_requests:
    - shard-skl:          [PASS][15] -> [DMESG-WARN][16] ([fdo#111086])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-skl6/igt@i915_selftest@mock_requests.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-skl7/igt@i915_selftest@mock_requests.html
    - shard-glk:          [PASS][17] -> [INCOMPLETE][18] ([fdo#103359] / [k.org#198133])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-glk9/igt@i915_selftest@mock_requests.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-glk4/igt@i915_selftest@mock_requests.html

  * igt@kms_color@pipe-b-ctm-0-5:
    - shard-skl:          [PASS][19] -> [DMESG-WARN][20] ([fdo#106107])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-skl4/igt@kms_color@pipe-b-ctm-0-5.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-skl9/igt@kms_color@pipe-b-ctm-0-5.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-glk:          [PASS][21] -> [FAIL][22] ([fdo#104873])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#102670])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic:
    - shard-skl:          [PASS][25] -> [DMESG-WARN][26] ([fdo#105541])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-skl9/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-skl5/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_draw_crc@draw-method-rgb565-blt-xtiled:
    - shard-skl:          [PASS][27] -> [FAIL][28] ([fdo#103184] / [fdo#103232])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-skl8/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-skl6/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-iclb:         [PASS][29] -> [FAIL][30] ([fdo#103167]) +10 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-apl:          [PASS][31] -> [DMESG-WARN][32] ([fdo#108566]) +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][33] -> [FAIL][34] ([fdo#108145] / [fdo#110403])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [PASS][35] -> [SKIP][36] ([fdo#109441]) +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb7/igt@kms_psr@psr2_primary_page_flip.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@vcs0-s3:
    - {shard-tglb}:       [INCOMPLETE][37] ([fdo#111832]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb5/igt@gem_ctx_isolation@vcs0-s3.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-tglb3/igt@gem_ctx_isolation@vcs0-s3.html

  * {igt@gem_ctx_persistence@vcs1-mixed-process}:
    - shard-iclb:         [SKIP][39] ([fdo#109276] / [fdo#112080]) -> [PASS][40] +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb7/igt@gem_ctx_persistence@vcs1-mixed-process.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb4/igt@gem_ctx_persistence@vcs1-mixed-process.html

  * igt@gem_ctx_switch@vcs1-heavy-queue:
    - shard-iclb:         [SKIP][41] ([fdo#112080]) -> [PASS][42] +13 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb7/igt@gem_ctx_switch@vcs1-heavy-queue.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb4/igt@gem_ctx_switch@vcs1-heavy-queue.html

  * igt@gem_exec_gttfill@basic:
    - {shard-tglb}:       [INCOMPLETE][43] ([fdo#111593]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb4/igt@gem_exec_gttfill@basic.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-tglb4/igt@gem_exec_gttfill@basic.html

  * igt@gem_exec_schedule@preemptive-hang-bsd:
    - shard-iclb:         [SKIP][45] ([fdo#112146]) -> [PASS][46] +7 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb6/igt@gem_exec_schedule@preemptive-hang-bsd.html

  * igt@gem_exec_schedule@smoketest-all:
    - {shard-tglb}:       [INCOMPLETE][47] ([fdo#111855]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb3/igt@gem_exec_schedule@smoketest-all.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-tglb8/igt@gem_exec_schedule@smoketest-all.html

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
    - shard-hsw:          [FAIL][49] ([fdo#112037]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-hsw8/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-hsw6/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [DMESG-WARN][51] ([fdo#108566]) -> [PASS][52] +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-apl4/igt@gem_workarounds@suspend-resume-context.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-apl4/igt@gem_workarounds@suspend-resume-context.html

  * {igt@i915_pm_dc@dc6-dpms}:
    - shard-iclb:         [FAIL][53] ([fdo#110548]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb8/igt@i915_pm_dc@dc6-dpms.html

  * {igt@i915_selftest@live_gt_timelines}:
    - {shard-tglb}:       [INCOMPLETE][55] ([fdo#111831]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb6/igt@i915_selftest@live_gt_timelines.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-tglb5/igt@i915_selftest@live_gt_timelines.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][57] ([fdo#108566]) -> [PASS][58] +2 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - {shard-tglb}:       [INCOMPLETE][59] ([fdo#111747] / [fdo#111832] / [fdo#111850]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb8/igt@kms_fbcon_fbt@fbc-suspend.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-tglb1/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [FAIL][61] ([fdo#105363]) -> [PASS][62] +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-skl5/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@plain-flip-fb-recreate:
    - shard-skl:          [FAIL][63] ([fdo#100368]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-skl9/igt@kms_flip@plain-flip-fb-recreate.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-skl4/igt@kms_flip@plain-flip-fb-recreate.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-iclb:         [FAIL][65] ([fdo#103167]) -> [PASS][66] +3 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
    - {shard-tglb}:       [FAIL][67] ([fdo#103167]) -> [PASS][68] +2 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          [FAIL][69] ([fdo#108145]) -> [PASS][70] +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  * igt@kms_psr@no_drrs:
    - shard-iclb:         [FAIL][71] ([fdo#108341]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb1/igt@kms_psr@no_drrs.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb3/igt@kms_psr@no_drrs.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [SKIP][73] ([fdo#109441]) -> [PASS][74] +2 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_psr@suspend:
    - {shard-tglb}:       [INCOMPLETE][75] ([fdo#111832] / [fdo#111850]) -> [PASS][76] +3 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb4/igt@kms_psr@suspend.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-tglb6/igt@kms_psr@suspend.html

  * igt@kms_vblank@pipe-d-ts-continuation-suspend:
    - {shard-tglb}:       [INCOMPLETE][77] ([fdo#111850]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb3/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-tglb5/igt@kms_vblank@pipe-d-ts-continuation-suspend.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-skl:          [TIMEOUT][79] ([fdo#111732 ]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-skl7/igt@perf@gen8-unprivileged-single-ctx-counters.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-skl2/igt@perf@gen8-unprivileged-single-ctx-counters.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [SKIP][81] ([fdo#109276]) -> [PASS][82] +22 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb7/igt@prime_vgem@fence-wait-bsd2.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html

  * igt@tools_test@tools_test:
    - shard-snb:          [SKIP][83] ([fdo#109271]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-snb5/igt@tools_test@tools_test.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-snb4/igt@tools_test@tools_test.html

  
#### Warnings ####

  * igt@gem_mocs_settings@mocs-reset-bsd2:
    - shard-iclb:         [SKIP][85] ([fdo#109276]) -> [FAIL][86] ([fdo#111330]) +1 similar issue
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb7/igt@gem_mocs_settings@mocs-reset-bsd2.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb4/igt@gem_mocs_settings@mocs-reset-bsd2.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
  [fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110548]: https://bugs.freedesktop.org/show_bug.cgi?id=110548
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#111086]: https://bugs.freedesktop.org/show_bug.cgi?id=111086
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
  [fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
  [fdo#111646]: https://bugs.freedesktop.org/show_bug.cgi?id=111646
  [fdo#111671]: https://bugs.freedesktop.org/show_bug.cgi?id=111671
  [fdo#111732 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111732 
  [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
  [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
  [fdo#111795 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111795 
  [fdo#111830 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111830 
  [fdo#111831]: https://bugs.freedesktop.org/show_bug.cgi?id=111831
  [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
  [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
  [fdo#111855]: https://bugs.freedesktop.org/show_bug.cgi?id=111855
  [fdo#111865]: https://bugs.freedesktop.org/show_bug.cgi?id=111865
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#111912]: https://bugs.freedesktop.org/show_bug.cgi?id=111912
  [fdo#111998]: https://bugs.freedesktop.org/show_bug.cgi?id=111998
  [fdo#112016 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112016 
  [fdo#112021 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112021 
  [fdo#112037]: https://bugs.freedesktop.org/show_bug.cgi?id=112037
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7264 -> Patchwork_15142

  CI-20190529: 20190529
  CI_DRM_7264: f5cfd96ad87b58bf3b5dfa5365f8beb8bac15a38 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5263: 8a5d44dc5e51622cd43f23c2cf24d44c24a0564d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15142: 195205377ead3b57d89c7bbe84e8c8b2a6674aed @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915/psr: Add bits per pixel limitation

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915/psr: Add bits per pixel limitation
URL   : https://patchwork.freedesktop.org/series/69025/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7264_full -> Patchwork_15142_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_15142_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#112080]) +13 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb2/igt@gem_busy@busy-vcs1.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb7/igt@gem_busy@busy-vcs1.html

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-kbl:          [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +7 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-kbl3/igt@gem_ctx_isolation@rcs0-s3.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-kbl7/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_ctx_isolation@vcs1-s3:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#109276] / [fdo#112080])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb1/igt@gem_ctx_isolation@vcs1-s3.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb7/igt@gem_ctx_isolation@vcs1-s3.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#110841])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb5/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_exec_schedule@preempt-contexts-bsd2:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#109276]) +19 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb1/igt@gem_exec_schedule@preempt-contexts-bsd2.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb3/igt@gem_exec_schedule@preempt-contexts-bsd2.html

  * igt@gem_exec_schedule@reorder-wide-bsd:
    - shard-iclb:         [PASS][11] -> [SKIP][12] ([fdo#112146]) +7 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb7/igt@gem_exec_schedule@reorder-wide-bsd.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html

  * igt@gem_userptr_blits@sync-unmap:
    - shard-snb:          [PASS][13] -> [DMESG-WARN][14] ([fdo#111870])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-snb1/igt@gem_userptr_blits@sync-unmap.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-snb2/igt@gem_userptr_blits@sync-unmap.html

  * igt@i915_selftest@mock_requests:
    - shard-skl:          [PASS][15] -> [DMESG-WARN][16] ([fdo#111086])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-skl6/igt@i915_selftest@mock_requests.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-skl7/igt@i915_selftest@mock_requests.html
    - shard-glk:          [PASS][17] -> [INCOMPLETE][18] ([fdo#103359] / [k.org#198133])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-glk9/igt@i915_selftest@mock_requests.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-glk4/igt@i915_selftest@mock_requests.html

  * igt@kms_color@pipe-b-ctm-0-5:
    - shard-skl:          [PASS][19] -> [DMESG-WARN][20] ([fdo#106107])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-skl4/igt@kms_color@pipe-b-ctm-0-5.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-skl9/igt@kms_color@pipe-b-ctm-0-5.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-glk:          [PASS][21] -> [FAIL][22] ([fdo#104873])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#102670])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic:
    - shard-skl:          [PASS][25] -> [DMESG-WARN][26] ([fdo#105541])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-skl9/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-skl5/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_draw_crc@draw-method-rgb565-blt-xtiled:
    - shard-skl:          [PASS][27] -> [FAIL][28] ([fdo#103184] / [fdo#103232])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-skl8/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-skl6/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-iclb:         [PASS][29] -> [FAIL][30] ([fdo#103167]) +10 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-apl:          [PASS][31] -> [DMESG-WARN][32] ([fdo#108566]) +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][33] -> [FAIL][34] ([fdo#108145] / [fdo#110403])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [PASS][35] -> [SKIP][36] ([fdo#109441]) +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb7/igt@kms_psr@psr2_primary_page_flip.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@vcs0-s3:
    - {shard-tglb}:       [INCOMPLETE][37] ([fdo#111832]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb5/igt@gem_ctx_isolation@vcs0-s3.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-tglb3/igt@gem_ctx_isolation@vcs0-s3.html

  * {igt@gem_ctx_persistence@vcs1-mixed-process}:
    - shard-iclb:         [SKIP][39] ([fdo#109276] / [fdo#112080]) -> [PASS][40] +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb7/igt@gem_ctx_persistence@vcs1-mixed-process.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb4/igt@gem_ctx_persistence@vcs1-mixed-process.html

  * igt@gem_ctx_switch@vcs1-heavy-queue:
    - shard-iclb:         [SKIP][41] ([fdo#112080]) -> [PASS][42] +13 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb7/igt@gem_ctx_switch@vcs1-heavy-queue.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb4/igt@gem_ctx_switch@vcs1-heavy-queue.html

  * igt@gem_exec_gttfill@basic:
    - {shard-tglb}:       [INCOMPLETE][43] ([fdo#111593]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb4/igt@gem_exec_gttfill@basic.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-tglb4/igt@gem_exec_gttfill@basic.html

  * igt@gem_exec_schedule@preemptive-hang-bsd:
    - shard-iclb:         [SKIP][45] ([fdo#112146]) -> [PASS][46] +7 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb6/igt@gem_exec_schedule@preemptive-hang-bsd.html

  * igt@gem_exec_schedule@smoketest-all:
    - {shard-tglb}:       [INCOMPLETE][47] ([fdo#111855]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb3/igt@gem_exec_schedule@smoketest-all.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-tglb8/igt@gem_exec_schedule@smoketest-all.html

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
    - shard-hsw:          [FAIL][49] ([fdo#112037]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-hsw8/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-hsw6/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [DMESG-WARN][51] ([fdo#108566]) -> [PASS][52] +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-apl4/igt@gem_workarounds@suspend-resume-context.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-apl4/igt@gem_workarounds@suspend-resume-context.html

  * {igt@i915_pm_dc@dc6-dpms}:
    - shard-iclb:         [FAIL][53] ([fdo#110548]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb8/igt@i915_pm_dc@dc6-dpms.html

  * {igt@i915_selftest@live_gt_timelines}:
    - {shard-tglb}:       [INCOMPLETE][55] ([fdo#111831]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb6/igt@i915_selftest@live_gt_timelines.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-tglb5/igt@i915_selftest@live_gt_timelines.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][57] ([fdo#108566]) -> [PASS][58] +2 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - {shard-tglb}:       [INCOMPLETE][59] ([fdo#111747] / [fdo#111832] / [fdo#111850]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb8/igt@kms_fbcon_fbt@fbc-suspend.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-tglb1/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [FAIL][61] ([fdo#105363]) -> [PASS][62] +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-skl5/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@plain-flip-fb-recreate:
    - shard-skl:          [FAIL][63] ([fdo#100368]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-skl9/igt@kms_flip@plain-flip-fb-recreate.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-skl4/igt@kms_flip@plain-flip-fb-recreate.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-iclb:         [FAIL][65] ([fdo#103167]) -> [PASS][66] +3 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
    - {shard-tglb}:       [FAIL][67] ([fdo#103167]) -> [PASS][68] +2 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          [FAIL][69] ([fdo#108145]) -> [PASS][70] +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  * igt@kms_psr@no_drrs:
    - shard-iclb:         [FAIL][71] ([fdo#108341]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb1/igt@kms_psr@no_drrs.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb3/igt@kms_psr@no_drrs.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [SKIP][73] ([fdo#109441]) -> [PASS][74] +2 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_psr@suspend:
    - {shard-tglb}:       [INCOMPLETE][75] ([fdo#111832] / [fdo#111850]) -> [PASS][76] +3 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb4/igt@kms_psr@suspend.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-tglb6/igt@kms_psr@suspend.html

  * igt@kms_vblank@pipe-d-ts-continuation-suspend:
    - {shard-tglb}:       [INCOMPLETE][77] ([fdo#111850]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-tglb3/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-tglb5/igt@kms_vblank@pipe-d-ts-continuation-suspend.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-skl:          [TIMEOUT][79] ([fdo#111732 ]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-skl7/igt@perf@gen8-unprivileged-single-ctx-counters.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-skl2/igt@perf@gen8-unprivileged-single-ctx-counters.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [SKIP][81] ([fdo#109276]) -> [PASS][82] +22 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb7/igt@prime_vgem@fence-wait-bsd2.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html

  * igt@tools_test@tools_test:
    - shard-snb:          [SKIP][83] ([fdo#109271]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-snb5/igt@tools_test@tools_test.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-snb4/igt@tools_test@tools_test.html

  
#### Warnings ####

  * igt@gem_mocs_settings@mocs-reset-bsd2:
    - shard-iclb:         [SKIP][85] ([fdo#109276]) -> [FAIL][86] ([fdo#111330]) +1 similar issue
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb7/igt@gem_mocs_settings@mocs-reset-bsd2.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/shard-iclb4/igt@gem_mocs_settings@mocs-reset-bsd2.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
  [fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110548]: https://bugs.freedesktop.org/show_bug.cgi?id=110548
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#111086]: https://bugs.freedesktop.org/show_bug.cgi?id=111086
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
  [fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
  [fdo#111646]: https://bugs.freedesktop.org/show_bug.cgi?id=111646
  [fdo#111671]: https://bugs.freedesktop.org/show_bug.cgi?id=111671
  [fdo#111732 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111732 
  [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
  [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
  [fdo#111795 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111795 
  [fdo#111830 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111830 
  [fdo#111831]: https://bugs.freedesktop.org/show_bug.cgi?id=111831
  [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
  [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
  [fdo#111855]: https://bugs.freedesktop.org/show_bug.cgi?id=111855
  [fdo#111865]: https://bugs.freedesktop.org/show_bug.cgi?id=111865
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#111912]: https://bugs.freedesktop.org/show_bug.cgi?id=111912
  [fdo#111998]: https://bugs.freedesktop.org/show_bug.cgi?id=111998
  [fdo#112016 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112016 
  [fdo#112021 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112021 
  [fdo#112037]: https://bugs.freedesktop.org/show_bug.cgi?id=112037
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7264 -> Patchwork_15142

  CI-20190529: 20190529
  CI_DRM_7264: f5cfd96ad87b58bf3b5dfa5365f8beb8bac15a38 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5263: 8a5d44dc5e51622cd43f23c2cf24d44c24a0564d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15142: 195205377ead3b57d89c7bbe84e8c8b2a6674aed @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15142/index.html
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/5] drm/i915/psr: Add bits per pixel limitation

[Matt Roper]

On Tue, Nov 05, 2019 at 05:45:00PM -0800, José Roberto de Souza wrote:
> PSR2 HW only support a limited number of bits per pixel, if mode has
> more than supported PSR2 should not be enabled.
> 
> BSpec: 50422
> BSpec: 7713
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index c1d133362b76..0d84ea28bc6f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -608,7 +608,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
>  	int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> -	int psr_max_h = 0, psr_max_v = 0;
> +	int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
>  
>  	if (!dev_priv->psr.sink_psr2_support)
>  		return false;
> @@ -632,12 +632,15 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  	if (INTEL_GEN(dev_priv) >= 12) {
>  		psr_max_h = 5120;
>  		psr_max_v = 3200;
> +		max_bpp = 30;
>  	} else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
>  		psr_max_h = 4096;
>  		psr_max_v = 2304;
> +		max_bpp = 24;
>  	} else if (IS_GEN(dev_priv, 9)) {
>  		psr_max_h = 3640;
>  		psr_max_v = 2304;
> +		max_bpp = 24;
>  	}
>  
>  	if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) {
> @@ -647,6 +650,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  		return false;
>  	}
>  
> +	if (crtc_state->pipe_bpp > max_bpp) {
> +		DRM_DEBUG_KMS("PSR2 not enabled, pipe bpp %d > max supported %d\n",
> +			      crtc_state->pipe_bpp, max_bpp);
> +		return false;
> +	}

The wording of the bspec is "PSR2 is limited to 30bpp 10:10:10" and
"PSR2 is limited to 24bpp 8:8:8" --- that wording makes it sound like
you need to use that one specific mode rather than it being an upper
limit?  I.e., do we need an == test here rather than >?


Matt

> +
>  	/*
>  	 * HW sends SU blocks of size four scan lines, which means the starting
>  	 * X coordinate and Y granularity requirements will always be met. We
> -- 
> 2.24.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/5] drm/i915/psr: Add bits per pixel limitation

[Matt Roper]

On Tue, Nov 05, 2019 at 05:45:00PM -0800, José Roberto de Souza wrote:
> PSR2 HW only support a limited number of bits per pixel, if mode has
> more than supported PSR2 should not be enabled.
> 
> BSpec: 50422
> BSpec: 7713
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index c1d133362b76..0d84ea28bc6f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -608,7 +608,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
>  	int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> -	int psr_max_h = 0, psr_max_v = 0;
> +	int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
>  
>  	if (!dev_priv->psr.sink_psr2_support)
>  		return false;
> @@ -632,12 +632,15 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  	if (INTEL_GEN(dev_priv) >= 12) {
>  		psr_max_h = 5120;
>  		psr_max_v = 3200;
> +		max_bpp = 30;
>  	} else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
>  		psr_max_h = 4096;
>  		psr_max_v = 2304;
> +		max_bpp = 24;
>  	} else if (IS_GEN(dev_priv, 9)) {
>  		psr_max_h = 3640;
>  		psr_max_v = 2304;
> +		max_bpp = 24;
>  	}
>  
>  	if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) {
> @@ -647,6 +650,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  		return false;
>  	}
>  
> +	if (crtc_state->pipe_bpp > max_bpp) {
> +		DRM_DEBUG_KMS("PSR2 not enabled, pipe bpp %d > max supported %d\n",
> +			      crtc_state->pipe_bpp, max_bpp);
> +		return false;
> +	}

The wording of the bspec is "PSR2 is limited to 30bpp 10:10:10" and
"PSR2 is limited to 24bpp 8:8:8" --- that wording makes it sound like
you need to use that one specific mode rather than it being an upper
limit?  I.e., do we need an == test here rather than >?


Matt

> +
>  	/*
>  	 * HW sends SU blocks of size four scan lines, which means the starting
>  	 * X coordinate and Y granularity requirements will always be met. We
> -- 
> 2.24.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/5] drm/i915/psr: Add bits per pixel limitation

[Souza, Jose]

On Tue, 2019-11-12 at 09:16 -0800, Matt Roper wrote:
> On Tue, Nov 05, 2019 at 05:45:00PM -0800, José Roberto de Souza
> wrote:
> > PSR2 HW only support a limited number of bits per pixel, if mode
> > has
> > more than supported PSR2 should not be enabled.
> > 
> > BSpec: 50422
> > BSpec: 7713
> > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++++-
> >  1 file changed, 10 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index c1d133362b76..0d84ea28bc6f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -608,7 +608,7 @@ static bool intel_psr2_config_valid(struct
> > intel_dp *intel_dp,
> >  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >  	int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> >  	int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> > -	int psr_max_h = 0, psr_max_v = 0;
> > +	int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
> >  
> >  	if (!dev_priv->psr.sink_psr2_support)
> >  		return false;
> > @@ -632,12 +632,15 @@ static bool intel_psr2_config_valid(struct
> > intel_dp *intel_dp,
> >  	if (INTEL_GEN(dev_priv) >= 12) {
> >  		psr_max_h = 5120;
> >  		psr_max_v = 3200;
> > +		max_bpp = 30;
> >  	} else if (INTEL_GEN(dev_priv) >= 10 ||
> > IS_GEMINILAKE(dev_priv)) {
> >  		psr_max_h = 4096;
> >  		psr_max_v = 2304;
> > +		max_bpp = 24;
> >  	} else if (IS_GEN(dev_priv, 9)) {
> >  		psr_max_h = 3640;
> >  		psr_max_v = 2304;
> > +		max_bpp = 24;
> >  	}
> >  
> >  	if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) {
> > @@ -647,6 +650,12 @@ static bool intel_psr2_config_valid(struct
> > intel_dp *intel_dp,
> >  		return false;
> >  	}
> >  
> > +	if (crtc_state->pipe_bpp > max_bpp) {
> > +		DRM_DEBUG_KMS("PSR2 not enabled, pipe bpp %d > max
> > supported %d\n",
> > +			      crtc_state->pipe_bpp, max_bpp);
> > +		return false;
> > +	}
> 
> The wording of the bspec is "PSR2 is limited to 30bpp 10:10:10" and
> "PSR2 is limited to 24bpp 8:8:8" --- that wording makes it sound like
> you need to use that one specific mode rather than it being an upper
> limit?  I.e., do we need an == test here rather than >?

It works with lower than the limit:

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7312/shard-tglb4/igt@kms_psr2_su@frontbuffer.html

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7309/shard-iclb2/igt@kms_psr@psr2_basic.html

But I agree with you, BSpec should have "limited up to Xbpp", going toopen a issue. 

> 
> 
> Matt
> 
> > +
> >  	/*
> >  	 * HW sends SU blocks of size four scan lines, which means the
> > starting
> >  	 * X coordinate and Y granularity requirements will always be
> > met. We
> > -- 
> > 2.24.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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Re: [Intel-gfx] [PATCH 1/5] drm/i915/psr: Add bits per pixel limitation

[Souza, Jose]

On Tue, 2019-11-12 at 09:16 -0800, Matt Roper wrote:
> On Tue, Nov 05, 2019 at 05:45:00PM -0800, José Roberto de Souza
> wrote:
> > PSR2 HW only support a limited number of bits per pixel, if mode
> > has
> > more than supported PSR2 should not be enabled.
> > 
> > BSpec: 50422
> > BSpec: 7713
> > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++++-
> >  1 file changed, 10 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index c1d133362b76..0d84ea28bc6f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -608,7 +608,7 @@ static bool intel_psr2_config_valid(struct
> > intel_dp *intel_dp,
> >  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >  	int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> >  	int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> > -	int psr_max_h = 0, psr_max_v = 0;
> > +	int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
> >  
> >  	if (!dev_priv->psr.sink_psr2_support)
> >  		return false;
> > @@ -632,12 +632,15 @@ static bool intel_psr2_config_valid(struct
> > intel_dp *intel_dp,
> >  	if (INTEL_GEN(dev_priv) >= 12) {
> >  		psr_max_h = 5120;
> >  		psr_max_v = 3200;
> > +		max_bpp = 30;
> >  	} else if (INTEL_GEN(dev_priv) >= 10 ||
> > IS_GEMINILAKE(dev_priv)) {
> >  		psr_max_h = 4096;
> >  		psr_max_v = 2304;
> > +		max_bpp = 24;
> >  	} else if (IS_GEN(dev_priv, 9)) {
> >  		psr_max_h = 3640;
> >  		psr_max_v = 2304;
> > +		max_bpp = 24;
> >  	}
> >  
> >  	if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) {
> > @@ -647,6 +650,12 @@ static bool intel_psr2_config_valid(struct
> > intel_dp *intel_dp,
> >  		return false;
> >  	}
> >  
> > +	if (crtc_state->pipe_bpp > max_bpp) {
> > +		DRM_DEBUG_KMS("PSR2 not enabled, pipe bpp %d > max
> > supported %d\n",
> > +			      crtc_state->pipe_bpp, max_bpp);
> > +		return false;
> > +	}
> 
> The wording of the bspec is "PSR2 is limited to 30bpp 10:10:10" and
> "PSR2 is limited to 24bpp 8:8:8" --- that wording makes it sound like
> you need to use that one specific mode rather than it being an upper
> limit?  I.e., do we need an == test here rather than >?

It works with lower than the limit:

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7312/shard-tglb4/igt@kms_psr2_su@frontbuffer.html

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7309/shard-iclb2/igt@kms_psr@psr2_basic.html

But I agree with you, BSpec should have "limited up to Xbpp", going toopen a issue. 

> 
> 
> Matt
> 
> > +
> >  	/*
> >  	 * HW sends SU blocks of size four scan lines, which means the
> > starting
> >  	 * X coordinate and Y granularity requirements will always be
> > met. We
> > -- 
> > 2.24.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/5] drm/i915/psr: Add bits per pixel limitation

[Lucas De Marchi]

On Tue, Nov 12, 2019 at 09:16:57AM -0800, Matt Roper wrote:
>On Tue, Nov 05, 2019 at 05:45:00PM -0800, José Roberto de Souza wrote:
>> PSR2 HW only support a limited number of bits per pixel, if mode has
>> more than supported PSR2 should not be enabled.
>>
>> BSpec: 50422
>> BSpec: 7713
>> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++++-
>>  1 file changed, 10 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index c1d133362b76..0d84ea28bc6f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -608,7 +608,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>>  	int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
>>  	int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
>> -	int psr_max_h = 0, psr_max_v = 0;
>> +	int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
>>
>>  	if (!dev_priv->psr.sink_psr2_support)
>>  		return false;
>> @@ -632,12 +632,15 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>>  	if (INTEL_GEN(dev_priv) >= 12) {
>>  		psr_max_h = 5120;
>>  		psr_max_v = 3200;
>> +		max_bpp = 30;
>>  	} else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
>>  		psr_max_h = 4096;
>>  		psr_max_v = 2304;
>> +		max_bpp = 24;
>>  	} else if (IS_GEN(dev_priv, 9)) {
>>  		psr_max_h = 3640;
>>  		psr_max_v = 2304;
>> +		max_bpp = 24;
>>  	}
>>
>>  	if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) {
>> @@ -647,6 +650,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>>  		return false;
>>  	}
>>
>> +	if (crtc_state->pipe_bpp > max_bpp) {
>> +		DRM_DEBUG_KMS("PSR2 not enabled, pipe bpp %d > max supported %d\n",
>> +			      crtc_state->pipe_bpp, max_bpp);
>> +		return false;
>> +	}
>
>The wording of the bspec is "PSR2 is limited to 30bpp 10:10:10" and
>"PSR2 is limited to 24bpp 8:8:8" --- that wording makes it sound like
>you need to use that one specific mode rather than it being an upper
>limit?  I.e., do we need an == test here rather than >?

I understand "limited" here rather as a limit, not as the only mode it
works in. Yes, it's confusing, but I don't think it makes much sense to
support just one bpp.

Lucas De Marchi

>
>
>Matt
>
>> +
>>  	/*
>>  	 * HW sends SU blocks of size four scan lines, which means the starting
>>  	 * X coordinate and Y granularity requirements will always be met. We
>> --
>> 2.24.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>-- 
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
>(916) 356-2795
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Re: [Intel-gfx] [PATCH 1/5] drm/i915/psr: Add bits per pixel limitation

[Lucas De Marchi]

On Tue, Nov 12, 2019 at 09:16:57AM -0800, Matt Roper wrote:
>On Tue, Nov 05, 2019 at 05:45:00PM -0800, José Roberto de Souza wrote:
>> PSR2 HW only support a limited number of bits per pixel, if mode has
>> more than supported PSR2 should not be enabled.
>>
>> BSpec: 50422
>> BSpec: 7713
>> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++++-
>>  1 file changed, 10 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index c1d133362b76..0d84ea28bc6f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -608,7 +608,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>>  	int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
>>  	int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
>> -	int psr_max_h = 0, psr_max_v = 0;
>> +	int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
>>
>>  	if (!dev_priv->psr.sink_psr2_support)
>>  		return false;
>> @@ -632,12 +632,15 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>>  	if (INTEL_GEN(dev_priv) >= 12) {
>>  		psr_max_h = 5120;
>>  		psr_max_v = 3200;
>> +		max_bpp = 30;
>>  	} else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
>>  		psr_max_h = 4096;
>>  		psr_max_v = 2304;
>> +		max_bpp = 24;
>>  	} else if (IS_GEN(dev_priv, 9)) {
>>  		psr_max_h = 3640;
>>  		psr_max_v = 2304;
>> +		max_bpp = 24;
>>  	}
>>
>>  	if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) {
>> @@ -647,6 +650,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>>  		return false;
>>  	}
>>
>> +	if (crtc_state->pipe_bpp > max_bpp) {
>> +		DRM_DEBUG_KMS("PSR2 not enabled, pipe bpp %d > max supported %d\n",
>> +			      crtc_state->pipe_bpp, max_bpp);
>> +		return false;
>> +	}
>
>The wording of the bspec is "PSR2 is limited to 30bpp 10:10:10" and
>"PSR2 is limited to 24bpp 8:8:8" --- that wording makes it sound like
>you need to use that one specific mode rather than it being an upper
>limit?  I.e., do we need an == test here rather than >?

I understand "limited" here rather as a limit, not as the only mode it
works in. Yes, it's confusing, but I don't think it makes much sense to
support just one bpp.

Lucas De Marchi

>
>
>Matt
>
>> +
>>  	/*
>>  	 * HW sends SU blocks of size four scan lines, which means the starting
>>  	 * X coordinate and Y granularity requirements will always be met. We
>> --
>> 2.24.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>-- 
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
>(916) 356-2795
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/5] drm/i915/psr: Add bits per pixel limitation

[Lucas De Marchi]

On Tue, Nov 05, 2019 at 05:45:00PM -0800, Jose Souza wrote:
>PSR2 HW only support a limited number of bits per pixel, if mode has
>more than supported PSR2 should not be enabled.
>
>BSpec: 50422
>BSpec: 7713

matches both specs


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>index c1d133362b76..0d84ea28bc6f 100644
>--- a/drivers/gpu/drm/i915/display/intel_psr.c
>+++ b/drivers/gpu/drm/i915/display/intel_psr.c
>@@ -608,7 +608,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> 	int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> 	int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
>-	int psr_max_h = 0, psr_max_v = 0;
>+	int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
>
> 	if (!dev_priv->psr.sink_psr2_support)
> 		return false;
>@@ -632,12 +632,15 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> 	if (INTEL_GEN(dev_priv) >= 12) {
> 		psr_max_h = 5120;
> 		psr_max_v = 3200;
>+		max_bpp = 30;
> 	} else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> 		psr_max_h = 4096;
> 		psr_max_v = 2304;
>+		max_bpp = 24;
> 	} else if (IS_GEN(dev_priv, 9)) {
> 		psr_max_h = 3640;
> 		psr_max_v = 2304;
>+		max_bpp = 24;
> 	}
>
> 	if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) {
>@@ -647,6 +650,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> 		return false;
> 	}
>
>+	if (crtc_state->pipe_bpp > max_bpp) {
>+		DRM_DEBUG_KMS("PSR2 not enabled, pipe bpp %d > max supported %d\n",
>+			      crtc_state->pipe_bpp, max_bpp);
>+		return false;
>+	}
>+
> 	/*
> 	 * HW sends SU blocks of size four scan lines, which means the starting
> 	 * X coordinate and Y granularity requirements will always be met. We
>-- 
>2.24.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Re: [Intel-gfx] [PATCH 1/5] drm/i915/psr: Add bits per pixel limitation

[Lucas De Marchi]

On Tue, Nov 05, 2019 at 05:45:00PM -0800, Jose Souza wrote:
>PSR2 HW only support a limited number of bits per pixel, if mode has
>more than supported PSR2 should not be enabled.
>
>BSpec: 50422
>BSpec: 7713

matches both specs


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>index c1d133362b76..0d84ea28bc6f 100644
>--- a/drivers/gpu/drm/i915/display/intel_psr.c
>+++ b/drivers/gpu/drm/i915/display/intel_psr.c
>@@ -608,7 +608,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> 	int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> 	int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
>-	int psr_max_h = 0, psr_max_v = 0;
>+	int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
>
> 	if (!dev_priv->psr.sink_psr2_support)
> 		return false;
>@@ -632,12 +632,15 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> 	if (INTEL_GEN(dev_priv) >= 12) {
> 		psr_max_h = 5120;
> 		psr_max_v = 3200;
>+		max_bpp = 30;
> 	} else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> 		psr_max_h = 4096;
> 		psr_max_v = 2304;
>+		max_bpp = 24;
> 	} else if (IS_GEN(dev_priv, 9)) {
> 		psr_max_h = 3640;
> 		psr_max_v = 2304;
>+		max_bpp = 24;
> 	}
>
> 	if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) {
>@@ -647,6 +650,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> 		return false;
> 	}
>
>+	if (crtc_state->pipe_bpp > max_bpp) {
>+		DRM_DEBUG_KMS("PSR2 not enabled, pipe bpp %d > max supported %d\n",
>+			      crtc_state->pipe_bpp, max_bpp);
>+		return false;
>+	}
>+
> 	/*
> 	 * HW sends SU blocks of size four scan lines, which means the starting
> 	 * X coordinate and Y granularity requirements will always be met. We
>-- 
>2.24.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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