From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> To: Andrew Murray <andrew.murray@arm.com>, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Eric Anholt <eric@anholt.net>, Stefan Wahren <wahrenst@gmx.net> Cc: james.quinlan@broadcom.com, mbrugger@suse.com, f.fainelli@gmail.com, phil@raspberrypi.org, Nicolas Saenz Julienne <nsaenzjulienne@suse.de>, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] ARM: dts: bcm2711: Enable PCIe controller Date: Wed, 6 Nov 2019 22:45:24 +0100 [thread overview] Message-ID: <20191106214527.18736-3-nsaenzjulienne@suse.de> (raw) In-Reply-To: <20191106214527.18736-1-nsaenzjulienne@suse.de> This enables bcm2711's PCIe bus, wich is hardwired to a VIA Technologies XHCI USB 3.0 controller. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> --- arch/arm/boot/dts/bcm2711.dtsi | 47 ++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index a9d84e28f245..c7b2e7b57da6 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -288,6 +288,53 @@ arm,cpu-registers-not-fw-configured; }; + scb { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, + <0x6 0x00000000 0x6 0x00000000 0x40000000>; + + pcie_0: pcie@7d500000 { + compatible = "brcm,bcm2711-pcie"; + reg = <0x0 0x7d500000 0x9310>; + msi-controller; + msi-parent = <&pcie_0>; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + linux,pci-domain = <0>; + brcm,enable-ssc; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 + IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &gicv2 GIC_SPI 144 + IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &gicv2 GIC_SPI 145 + IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &gicv2 GIC_SPI 146 + IRQ_TYPE_LEVEL_HIGH>; + + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 + 0x0 0x04000000>; + /* + * The wrapper around the PCIe block has a bug + * preventing it from accessing beyond the first 3GB of + * memory. As the bus DMA mask is rounded up to the + * closest power of two of the dma-range size, we're + * forced to set the limit at 2GB. This can be + * harmlessly changed in the future once the DMA code + * handles non power of two DMA limits. + */ + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 + 0x0 0x80000000>; + }; + }; + cpus: cpus { #address-cells = <1>; #size-cells = <0>; -- 2.23.0
WARNING: multiple messages have this Message-ID (diff)
From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> To: Andrew Murray <andrew.murray@arm.com>, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Eric Anholt <eric@anholt.net>, Stefan Wahren <wahrenst@gmx.net> Cc: f.fainelli@gmail.com, phil@raspberrypi.org, linux-kernel@vger.kernel.org, mbrugger@suse.com, james.quinlan@broadcom.com, Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Subject: [PATCH 2/4] ARM: dts: bcm2711: Enable PCIe controller Date: Wed, 6 Nov 2019 22:45:24 +0100 [thread overview] Message-ID: <20191106214527.18736-3-nsaenzjulienne@suse.de> (raw) In-Reply-To: <20191106214527.18736-1-nsaenzjulienne@suse.de> This enables bcm2711's PCIe bus, wich is hardwired to a VIA Technologies XHCI USB 3.0 controller. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> --- arch/arm/boot/dts/bcm2711.dtsi | 47 ++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index a9d84e28f245..c7b2e7b57da6 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -288,6 +288,53 @@ arm,cpu-registers-not-fw-configured; }; + scb { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, + <0x6 0x00000000 0x6 0x00000000 0x40000000>; + + pcie_0: pcie@7d500000 { + compatible = "brcm,bcm2711-pcie"; + reg = <0x0 0x7d500000 0x9310>; + msi-controller; + msi-parent = <&pcie_0>; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + linux,pci-domain = <0>; + brcm,enable-ssc; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 + IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &gicv2 GIC_SPI 144 + IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &gicv2 GIC_SPI 145 + IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &gicv2 GIC_SPI 146 + IRQ_TYPE_LEVEL_HIGH>; + + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 + 0x0 0x04000000>; + /* + * The wrapper around the PCIe block has a bug + * preventing it from accessing beyond the first 3GB of + * memory. As the bus DMA mask is rounded up to the + * closest power of two of the dma-range size, we're + * forced to set the limit at 2GB. This can be + * harmlessly changed in the future once the DMA code + * handles non power of two DMA limits. + */ + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 + 0x0 0x80000000>; + }; + }; + cpus: cpus { #address-cells = <1>; #size-cells = <0>; -- 2.23.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-11-06 21:45 UTC|newest] Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-06 21:45 [PATCH 0/4] Raspberry Pi 4 PCIe support Nicolas Saenz Julienne 2019-11-06 21:45 ` Nicolas Saenz Julienne 2019-11-06 21:45 ` [PATCH 1/4] dt-bindings: pci: add bindings for brcmstb's PCIe device Nicolas Saenz Julienne 2019-11-06 21:45 ` Nicolas Saenz Julienne 2019-11-07 10:32 ` Andrew Murray 2019-11-07 10:32 ` Andrew Murray 2019-11-07 10:53 ` Nicolas Saenz Julienne 2019-11-07 10:53 ` Nicolas Saenz Julienne 2019-11-13 4:15 ` Rob Herring 2019-11-13 4:15 ` Rob Herring 2019-11-14 13:15 ` Nicolas Saenz Julienne 2019-11-14 13:15 ` Nicolas Saenz Julienne 2019-11-06 21:45 ` Nicolas Saenz Julienne [this message] 2019-11-06 21:45 ` [PATCH 2/4] ARM: dts: bcm2711: Enable PCIe controller Nicolas Saenz Julienne 2019-11-07 10:37 ` Andrew Murray 2019-11-07 10:37 ` Andrew Murray 2019-11-12 9:18 ` Nicolas Saenz Julienne 2019-11-12 9:18 ` Nicolas Saenz Julienne 2019-11-07 17:44 ` Stefan Wahren 2019-11-07 17:44 ` Stefan Wahren 2019-11-07 18:24 ` Nicolas Saenz Julienne 2019-11-07 18:24 ` Nicolas Saenz Julienne 2019-11-06 21:45 ` [PATCH 3/4] PCI: brcmstb: add Broadcom STB PCIe host controller driver Nicolas Saenz Julienne 2019-11-06 21:45 ` Nicolas Saenz Julienne 2019-11-07 15:00 ` Andrew Murray 2019-11-07 15:00 ` Andrew Murray 2019-11-07 16:12 ` Jim Quinlan 2019-11-07 16:12 ` Jim Quinlan 2019-11-08 10:52 ` Andrew Murray 2019-11-08 10:52 ` Andrew Murray 2019-11-08 16:33 ` Jim Quinlan 2019-11-08 16:33 ` Jim Quinlan 2019-11-07 17:30 ` Nicolas Saenz Julienne 2019-11-07 17:30 ` Nicolas Saenz Julienne 2019-11-08 10:51 ` Andrew Murray 2019-11-08 10:51 ` Andrew Murray 2019-11-07 17:50 ` Stefan Wahren 2019-11-07 17:50 ` Stefan Wahren 2019-11-08 11:13 ` Nicolas Saenz Julienne 2019-11-08 11:13 ` Nicolas Saenz Julienne 2019-11-11 7:10 ` Jeremy Linton 2019-11-11 7:10 ` Jeremy Linton 2019-11-11 15:29 ` Nicolas Saenz Julienne 2019-11-11 15:29 ` Nicolas Saenz Julienne 2019-11-11 16:40 ` Florian Fainelli 2019-11-11 16:40 ` Florian Fainelli 2019-11-11 20:00 ` Jeremy Linton 2019-11-11 20:00 ` Jeremy Linton 2019-11-11 21:27 ` Florian Fainelli 2019-11-11 21:27 ` Florian Fainelli 2019-11-06 21:45 ` [PATCH 4/4] PCI: brcmstb: add MSI capability Nicolas Saenz Julienne 2019-11-06 21:45 ` Nicolas Saenz Julienne 2019-11-07 15:40 ` Marc Zyngier 2019-11-07 15:40 ` Marc Zyngier 2019-11-11 11:21 ` Nicolas Saenz Julienne 2019-11-11 11:21 ` Nicolas Saenz Julienne 2019-11-11 13:29 ` Marc Zyngier 2019-11-11 13:29 ` Marc Zyngier 2019-11-06 21:51 ` [PATCH 0/4] Raspberry Pi 4 PCIe support Florian Fainelli 2019-11-06 21:51 ` Florian Fainelli 2019-11-07 9:58 ` Nicolas Saenz Julienne 2019-11-07 9:58 ` Nicolas Saenz Julienne
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