From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> To: Rob Herring <robh@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com>, devicetree@vger.kernel.org, mbrugger@suse.com, linux-pci@vger.kernel.org, phil@raspberrypi.org, linux-kernel@vger.kernel.org, f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, james.quinlan@broadcom.com, Bjorn Helgaas <bhelgaas@google.com>, Andrew Murray <andrew.murray@arm.com>, linux-arm-kernel@lists.infradead.org, wahrenst@gmx.net Subject: Re: [PATCH 1/4] dt-bindings: pci: add bindings for brcmstb's PCIe device Date: Thu, 14 Nov 2019 14:15:13 +0100 [thread overview] Message-ID: <5d706b02fb23c2dd6422306ff8d43a90910e36b8.camel@suse.de> (raw) In-Reply-To: <20191113041533.GA25497@bogus> [-- Attachment #1: Type: text/plain, Size: 5899 bytes --] On Tue, 2019-11-12 at 22:15 -0600, Rob Herring wrote: > On Wed, Nov 06, 2019 at 10:45:23PM +0100, Nicolas Saenz Julienne wrote: > > From: Jim Quinlan <james.quinlan@broadcom.com> > > > > The DT bindings description of the brcmstb PCIe device is described. > > This node can only be used for now on the Raspberry Pi 4. > > > > This was based on Jim's original submission[1], converted to yaml and > > adapted to the RPi4 case. > > > > [1] https://patchwork.kernel.org/patch/10605937/ > > > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> > > Co-developed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> > > Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> > > --- > > .../bindings/pci/brcm,stb-pcie.yaml | 116 ++++++++++++++++++ > > 1 file changed, 116 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > > I'm working on a common PCI host schema that should cut down some of the > standard props. Is there a way for me to have a look at it so I can rebase the binding on top of it? > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > > b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > > new file mode 100644 > > index 000000000000..0b81c26f8568 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > > @@ -0,0 +1,116 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > Dual license new bindings please: > > # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) Noted > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Brcmstb PCIe Host Controller Device Tree Bindings > > + > > +maintainers: > > + - Nicolas Saenz Julienne <nsaenzjulienne@suse.de> > > + > > +properties: > > + compatible: > > + const: brcm,bcm2711-pcie # The Raspberry Pi 4 > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + minItems: 1 > > + maxItems: 2 > > + items: > > + - description: PCIe host controller > > + - description: builtin MSI controller > > + > > + interrupt-names: > > + minItems: 1 > > + maxItems: 2 > > + items: > > + - const: pcie > > + - const: msi > > + > > + "#address-cells": > > + const: 3 > > + > > + "#size-cells": > > + const: 2 > > + > > + "#interrupt-cells": > > + const: 1 > > + > > + interrupt-map-mask: true > > + > > + interrupt-map: true > > 4 entries? You're right, for this specific case, as XHCI is hardwired and only uses one irq, we'd only need the first entry. Although who knows, maybe they are wired nonetheless. I guess it's safer to assume they aren't for now. > You'll need to bracket <> each entry in the example and dts. Ok > > + > > + ranges: true > > How many entries? One, I'll update it. > > + > > + dma-ranges: true > > How many entries? One, I'll update it. > > + > > + clocks: > > + maxItems: 1 > > + > > + clock-names: > > + items: > > + - const: sw_pcie > > + > > + msi-controller: > > + description: Identifies the node as an MSI controller. > > + type: boolean > > + > > + msi-parent: > > + description: MSI controller the device is capable of using. > > + $ref: /schemas/types.yaml#/definitions/phandle > > + > > + linux,pci-domain: > > + description: PCI domain ID. Should be unique for each host controller. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + > > + brcm,enable-ssc: > > + description: Indicates usage of spread-spectrum clocking. > > + type: boolean > > + > > +required: > > + - compatible > > + - reg > > + - "#address-cells" > > + - "#size-cells" > > + - "#interrupt-cells" > > + - interrupt-map-mask > > + - interrupt-map > > + - ranges > > + - dma-ranges > > + - linux,pci-domain > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/irq.h> > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + > > + scb { > > + #address-cells = <2>; > > + #size-cells = <1>; > > + pcie0: pcie@7d500000 { > > + compatible = "brcm,bcm2711-pcie"; > > + reg = <0x0 0x7d500000 0x9310>; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + #interrupt-cells = <1>; > > + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "pcie", "msi"; > > + interrupt-map-mask = <0x0 0x0 0x0 0x7>; > > + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 > > IRQ_TYPE_LEVEL_HIGH > > + 0 0 0 2 &gicv2 GIC_SPI 144 > > IRQ_TYPE_LEVEL_HIGH > > + 0 0 0 3 &gicv2 GIC_SPI 145 > > IRQ_TYPE_LEVEL_HIGH > > + 0 0 0 4 &gicv2 GIC_SPI 146 > > IRQ_TYPE_LEVEL_HIGH>; > > + msi-parent = <&pcie0>; > > + msi-controller; > > + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 > > 0x04000000>; > > + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 > > 0x0 0x80000000>; > > + linux,pci-domain = <0>; > > + brcm,enable-ssc; > > + }; > > + }; > > -- > > 2.23.0 > > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel [-- Attachment #2: This is a digitally signed message part --] [-- Type: application/pgp-signature, Size: 488 bytes --]
WARNING: multiple messages have this Message-ID (diff)
From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> To: Rob Herring <robh@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com>, devicetree@vger.kernel.org, mbrugger@suse.com, linux-pci@vger.kernel.org, phil@raspberrypi.org, linux-kernel@vger.kernel.org, f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, james.quinlan@broadcom.com, Bjorn Helgaas <bhelgaas@google.com>, Andrew Murray <andrew.murray@arm.com>, linux-arm-kernel@lists.infradead.org, wahrenst@gmx.net Subject: Re: [PATCH 1/4] dt-bindings: pci: add bindings for brcmstb's PCIe device Date: Thu, 14 Nov 2019 14:15:13 +0100 [thread overview] Message-ID: <5d706b02fb23c2dd6422306ff8d43a90910e36b8.camel@suse.de> (raw) In-Reply-To: <20191113041533.GA25497@bogus> [-- Attachment #1.1: Type: text/plain, Size: 5899 bytes --] On Tue, 2019-11-12 at 22:15 -0600, Rob Herring wrote: > On Wed, Nov 06, 2019 at 10:45:23PM +0100, Nicolas Saenz Julienne wrote: > > From: Jim Quinlan <james.quinlan@broadcom.com> > > > > The DT bindings description of the brcmstb PCIe device is described. > > This node can only be used for now on the Raspberry Pi 4. > > > > This was based on Jim's original submission[1], converted to yaml and > > adapted to the RPi4 case. > > > > [1] https://patchwork.kernel.org/patch/10605937/ > > > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> > > Co-developed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> > > Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> > > --- > > .../bindings/pci/brcm,stb-pcie.yaml | 116 ++++++++++++++++++ > > 1 file changed, 116 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > > I'm working on a common PCI host schema that should cut down some of the > standard props. Is there a way for me to have a look at it so I can rebase the binding on top of it? > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > > b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > > new file mode 100644 > > index 000000000000..0b81c26f8568 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > > @@ -0,0 +1,116 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > Dual license new bindings please: > > # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) Noted > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Brcmstb PCIe Host Controller Device Tree Bindings > > + > > +maintainers: > > + - Nicolas Saenz Julienne <nsaenzjulienne@suse.de> > > + > > +properties: > > + compatible: > > + const: brcm,bcm2711-pcie # The Raspberry Pi 4 > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + minItems: 1 > > + maxItems: 2 > > + items: > > + - description: PCIe host controller > > + - description: builtin MSI controller > > + > > + interrupt-names: > > + minItems: 1 > > + maxItems: 2 > > + items: > > + - const: pcie > > + - const: msi > > + > > + "#address-cells": > > + const: 3 > > + > > + "#size-cells": > > + const: 2 > > + > > + "#interrupt-cells": > > + const: 1 > > + > > + interrupt-map-mask: true > > + > > + interrupt-map: true > > 4 entries? You're right, for this specific case, as XHCI is hardwired and only uses one irq, we'd only need the first entry. Although who knows, maybe they are wired nonetheless. I guess it's safer to assume they aren't for now. > You'll need to bracket <> each entry in the example and dts. Ok > > + > > + ranges: true > > How many entries? One, I'll update it. > > + > > + dma-ranges: true > > How many entries? One, I'll update it. > > + > > + clocks: > > + maxItems: 1 > > + > > + clock-names: > > + items: > > + - const: sw_pcie > > + > > + msi-controller: > > + description: Identifies the node as an MSI controller. > > + type: boolean > > + > > + msi-parent: > > + description: MSI controller the device is capable of using. > > + $ref: /schemas/types.yaml#/definitions/phandle > > + > > + linux,pci-domain: > > + description: PCI domain ID. Should be unique for each host controller. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + > > + brcm,enable-ssc: > > + description: Indicates usage of spread-spectrum clocking. > > + type: boolean > > + > > +required: > > + - compatible > > + - reg > > + - "#address-cells" > > + - "#size-cells" > > + - "#interrupt-cells" > > + - interrupt-map-mask > > + - interrupt-map > > + - ranges > > + - dma-ranges > > + - linux,pci-domain > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/irq.h> > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + > > + scb { > > + #address-cells = <2>; > > + #size-cells = <1>; > > + pcie0: pcie@7d500000 { > > + compatible = "brcm,bcm2711-pcie"; > > + reg = <0x0 0x7d500000 0x9310>; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + #interrupt-cells = <1>; > > + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "pcie", "msi"; > > + interrupt-map-mask = <0x0 0x0 0x0 0x7>; > > + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 > > IRQ_TYPE_LEVEL_HIGH > > + 0 0 0 2 &gicv2 GIC_SPI 144 > > IRQ_TYPE_LEVEL_HIGH > > + 0 0 0 3 &gicv2 GIC_SPI 145 > > IRQ_TYPE_LEVEL_HIGH > > + 0 0 0 4 &gicv2 GIC_SPI 146 > > IRQ_TYPE_LEVEL_HIGH>; > > + msi-parent = <&pcie0>; > > + msi-controller; > > + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 > > 0x04000000>; > > + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 > > 0x0 0x80000000>; > > + linux,pci-domain = <0>; > > + brcm,enable-ssc; > > + }; > > + }; > > -- > > 2.23.0 > > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel [-- Attachment #1.2: This is a digitally signed message part --] [-- Type: application/pgp-signature, Size: 488 bytes --] [-- Attachment #2: Type: text/plain, Size: 176 bytes --] _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-11-14 13:15 UTC|newest] Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-06 21:45 [PATCH 0/4] Raspberry Pi 4 PCIe support Nicolas Saenz Julienne 2019-11-06 21:45 ` Nicolas Saenz Julienne 2019-11-06 21:45 ` [PATCH 1/4] dt-bindings: pci: add bindings for brcmstb's PCIe device Nicolas Saenz Julienne 2019-11-06 21:45 ` Nicolas Saenz Julienne 2019-11-07 10:32 ` Andrew Murray 2019-11-07 10:32 ` Andrew Murray 2019-11-07 10:53 ` Nicolas Saenz Julienne 2019-11-07 10:53 ` Nicolas Saenz Julienne 2019-11-13 4:15 ` Rob Herring 2019-11-13 4:15 ` Rob Herring 2019-11-14 13:15 ` Nicolas Saenz Julienne [this message] 2019-11-14 13:15 ` Nicolas Saenz Julienne 2019-11-06 21:45 ` [PATCH 2/4] ARM: dts: bcm2711: Enable PCIe controller Nicolas Saenz Julienne 2019-11-06 21:45 ` Nicolas Saenz Julienne 2019-11-07 10:37 ` Andrew Murray 2019-11-07 10:37 ` Andrew Murray 2019-11-12 9:18 ` Nicolas Saenz Julienne 2019-11-12 9:18 ` Nicolas Saenz Julienne 2019-11-07 17:44 ` Stefan Wahren 2019-11-07 17:44 ` Stefan Wahren 2019-11-07 18:24 ` Nicolas Saenz Julienne 2019-11-07 18:24 ` Nicolas Saenz Julienne 2019-11-06 21:45 ` [PATCH 3/4] PCI: brcmstb: add Broadcom STB PCIe host controller driver Nicolas Saenz Julienne 2019-11-06 21:45 ` Nicolas Saenz Julienne 2019-11-07 15:00 ` Andrew Murray 2019-11-07 15:00 ` Andrew Murray 2019-11-07 16:12 ` Jim Quinlan 2019-11-07 16:12 ` Jim Quinlan 2019-11-08 10:52 ` Andrew Murray 2019-11-08 10:52 ` Andrew Murray 2019-11-08 16:33 ` Jim Quinlan 2019-11-08 16:33 ` Jim Quinlan 2019-11-07 17:30 ` Nicolas Saenz Julienne 2019-11-07 17:30 ` Nicolas Saenz Julienne 2019-11-08 10:51 ` Andrew Murray 2019-11-08 10:51 ` Andrew Murray 2019-11-07 17:50 ` Stefan Wahren 2019-11-07 17:50 ` Stefan Wahren 2019-11-08 11:13 ` Nicolas Saenz Julienne 2019-11-08 11:13 ` Nicolas Saenz Julienne 2019-11-11 7:10 ` Jeremy Linton 2019-11-11 7:10 ` Jeremy Linton 2019-11-11 15:29 ` Nicolas Saenz Julienne 2019-11-11 15:29 ` Nicolas Saenz Julienne 2019-11-11 16:40 ` Florian Fainelli 2019-11-11 16:40 ` Florian Fainelli 2019-11-11 20:00 ` Jeremy Linton 2019-11-11 20:00 ` Jeremy Linton 2019-11-11 21:27 ` Florian Fainelli 2019-11-11 21:27 ` Florian Fainelli 2019-11-06 21:45 ` [PATCH 4/4] PCI: brcmstb: add MSI capability Nicolas Saenz Julienne 2019-11-06 21:45 ` Nicolas Saenz Julienne 2019-11-07 15:40 ` Marc Zyngier 2019-11-07 15:40 ` Marc Zyngier 2019-11-11 11:21 ` Nicolas Saenz Julienne 2019-11-11 11:21 ` Nicolas Saenz Julienne 2019-11-11 13:29 ` Marc Zyngier 2019-11-11 13:29 ` Marc Zyngier 2019-11-06 21:51 ` [PATCH 0/4] Raspberry Pi 4 PCIe support Florian Fainelli 2019-11-06 21:51 ` Florian Fainelli 2019-11-07 9:58 ` Nicolas Saenz Julienne 2019-11-07 9:58 ` Nicolas Saenz Julienne
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