* [PATCH v10 0/2] Refactor Gen11+ SAGV support
@ 2019-11-07 15:30 ` Stanislav Lisovskiy
0 siblings, 0 replies; 25+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-07 15:30 UTC (permalink / raw)
To: intel-gfx
For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.
Stanislav Lisovskiy (2):
drm/i915: Refactor intel_can_enable_sagv
drm/i915: Restrict qgv points which don't have enough bandwidth.
drivers/gpu/drm/i915/display/intel_atomic.h | 3 +
drivers/gpu/drm/i915/display/intel_bw.c | 137 ++++++--
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 108 +++++-
.../drm/i915/display/intel_display_types.h | 12 +
drivers/gpu/drm/i915/i915_drv.h | 10 +-
drivers/gpu/drm/i915/i915_reg.h | 8 +
drivers/gpu/drm/i915/intel_pm.c | 307 +++++++++++++++++-
drivers/gpu/drm/i915/intel_pm.h | 1 +
drivers/gpu/drm/i915/intel_sideband.c | 27 +-
drivers/gpu/drm/i915/intel_sideband.h | 1 -
11 files changed, 565 insertions(+), 51 deletions(-)
--
2.17.1
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v10 0/2] Refactor Gen11+ SAGV support
@ 2019-11-07 15:30 ` Stanislav Lisovskiy
0 siblings, 0 replies; 25+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-07 15:30 UTC (permalink / raw)
To: intel-gfx
For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.
Stanislav Lisovskiy (2):
drm/i915: Refactor intel_can_enable_sagv
drm/i915: Restrict qgv points which don't have enough bandwidth.
drivers/gpu/drm/i915/display/intel_atomic.h | 3 +
drivers/gpu/drm/i915/display/intel_bw.c | 137 ++++++--
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 108 +++++-
.../drm/i915/display/intel_display_types.h | 12 +
drivers/gpu/drm/i915/i915_drv.h | 10 +-
drivers/gpu/drm/i915/i915_reg.h | 8 +
drivers/gpu/drm/i915/intel_pm.c | 307 +++++++++++++++++-
drivers/gpu/drm/i915/intel_pm.h | 1 +
drivers/gpu/drm/i915/intel_sideband.c | 27 +-
drivers/gpu/drm/i915/intel_sideband.h | 1 -
11 files changed, 565 insertions(+), 51 deletions(-)
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v10 1/2] drm/i915: Refactor intel_can_enable_sagv
@ 2019-11-07 15:30 ` Stanislav Lisovskiy
0 siblings, 0 replies; 25+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-07 15:30 UTC (permalink / raw)
To: intel-gfx
Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.
v2:
- Rework watermark calculation algorithm to
attempt to calculate Level 0 watermark
with added sagv block time latency and
check if it fits in DBuf in order to
determine if SAGV can be enabled already
at this stage, just as BSpec 49325 states.
if that fails rollback to usual Level 0
latency and disable SAGV.
- Remove unneeded tabs(James Ausmus)
v3: Rebased the patch
v4: - Added back interlaced check for Gen12 and
added separate function for TGL SAGV check
(thanks to James Ausmus for spotting)
- Removed unneeded gen check
- Extracted Gen12 SAGV decision making code
to a separate function from skl_compute_wm
v5: - Added SAGV global state to dev_priv, because
we need to track all pipes, not only those
in atomic state. Each pipe has now correspondent
bit mask reflecting, whether it can tolerate
SAGV or not(thanks to Ville Syrjala for suggestions).
- Now using active flag instead of enable in crc
usage check.
v6: - Fixed rebase conflicts
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +
.../drm/i915/display/intel_display_types.h | 9 +
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/intel_pm.c | 296 +++++++++++++++++-
4 files changed, 303 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 876fc25968bf..7ea1e7518ab6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14855,6 +14855,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (dev_priv->display.optimize_watermarks)
dev_priv->display.optimize_watermarks(state,
new_crtc_state);
+ if (state->crtc_sagv_mask & BIT(crtc->pipe))
+ dev_priv->crtc_sagv_mask |= BIT(crtc->pipe);
+ else
+ dev_priv->crtc_sagv_mask &= ~BIT(crtc->pipe);
}
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index fadd9853f966..fb274538af23 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -490,6 +490,14 @@ struct intel_atomic_state {
*/
u8 active_pipe_changes;
+ /*
+ * Contains a mask which reflects whether correspondent pipe
+ * can tolerate SAGV or not, so that we can make a decision
+ * at atomic_commit_tail stage, whether we enable it or not
+ * based on global state in dev_priv.
+ */
+ u32 crtc_sagv_mask;
+
u8 active_pipes;
/* minimum acceptable cdclk for each pipe */
int min_cdclk[I915_MAX_PIPES];
@@ -670,6 +678,7 @@ struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
+ struct skl_wm_level sagv_wm0;
bool is_planar;
};
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7e0f67babe20..4f4e2e839513 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1176,6 +1176,12 @@ struct drm_i915_private {
u32 sagv_block_time_us;
+ /*
+ * Contains a bit mask, whether correspondent
+ * pipe allows SAGV or not.
+ */
+ u32 crtc_sagv_mask;
+
struct {
/*
* Raw watermark latency values:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2d389e437e87..c792dd168742 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3740,7 +3740,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+static void skl_set_sagv_mask(struct intel_atomic_state *state)
{
struct drm_device *dev = state->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -3750,21 +3750,23 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
enum pipe pipe;
int level, latency;
+ state->crtc_sagv_mask = 0;
+
if (!intel_has_sagv(dev_priv))
- return false;
+ return;
/*
* If there are no active CRTCs, no additional checks need be performed
*/
if (hweight8(state->active_pipes) == 0)
- return true;
+ return;
/*
* SKL+ workaround: bspec recommends we disable SAGV when we have
* more then one pipe enabled
*/
if (hweight8(state->active_pipes) > 1)
- return false;
+ return;
/* Since we're now guaranteed to only have one active CRTC... */
pipe = ffs(state->active_pipes) - 1;
@@ -3772,7 +3774,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
crtc_state = to_intel_crtc_state(crtc->base.state);
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
- return false;
+ return;
for_each_intel_plane_on_crtc(dev, crtc, plane) {
struct skl_plane_wm *wm =
@@ -3800,9 +3802,127 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
* can't enable SAGV.
*/
if (latency < dev_priv->sagv_block_time_us)
- return false;
+ return;
}
+ state->crtc_sagv_mask |= BIT(crtc->pipe);
+}
+
+static void tgl_set_sagv_mask(struct intel_atomic_state *state);
+
+static void icl_set_sagv_mask(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ int level, latency;
+ int i;
+ int plane_id;
+
+ state->crtc_sagv_mask = 0;
+
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ /*
+ * If there are no active CRTCs, no additional checks need be performed
+ */
+ if (hweight8(state->active_pipes) == 0)
+ return;
+
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ unsigned int flags = crtc->base.state->adjusted_mode.flags;
+ bool can_sagv;
+
+ if (flags & DRM_MODE_FLAG_INTERLACE)
+ continue;
+
+ if (!new_crtc_state->base.active)
+ continue;
+
+ can_sagv = true;
+ for_each_plane_id_on_crtc(crtc, plane_id) {
+ struct skl_plane_wm *wm =
+ &new_crtc_state->wm.skl.optimal.planes[plane_id];
+
+ /* Skip this plane if it's not enabled */
+ if (!wm->wm[0].plane_en)
+ continue;
+
+ /* Find the highest enabled wm level for this plane */
+ for (level = ilk_wm_max_level(dev_priv);
+ !wm->wm[level].plane_en; --level) {
+ }
+
+ latency = dev_priv->wm.skl_latency[level];
+
+ /*
+ * If any of the planes on this pipe don't enable
+ * wm levels that incur memory latencies higher than
+ * sagv_block_time_us we can't enable SAGV.
+ */
+ if (latency < dev_priv->sagv_block_time_us) {
+ can_sagv = false;
+ break;
+ }
+ }
+ if (can_sagv)
+ state->crtc_sagv_mask |= BIT(crtc->pipe);
+ }
+}
+
+bool intel_can_enable_sagv(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum pipe pipe;
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ tgl_set_sagv_mask(state);
+ else if (INTEL_GEN(dev_priv) == 11)
+ icl_set_sagv_mask(state);
+ else
+ skl_set_sagv_mask(state);
+
+ /*
+ * For SAGV we need to account all the pipes,
+ * not only the ones which are in state currently.
+ */
+ for_each_pipe(dev_priv, pipe) {
+ unsigned int active_pipes;
+ /*
+ * Figure out if we are changing active pipes here
+ * then after commit dev_priv->active_pipes will
+ * anyway be assigned to state->active_pipes.
+ */
+ if (state->active_pipe_changes)
+ active_pipes = state->active_pipes;
+ else
+ active_pipes = dev_priv->active_pipes;
+
+ /* Skip if pipe is inactive */
+ if (!(BIT(pipe) & active_pipes))
+ continue;
+
+ /*
+ * Pipe can be active in this state or in dev_priv
+ * as we haven't committed thise changes yet(and we shouldn't)
+ * - we need to check both.
+ */
+ if (state->active_pipe_changes & BIT(pipe)) {
+ bool state_sagv_masked = \
+ (BIT(pipe) & state->crtc_sagv_mask) == 0;
+ if (state_sagv_masked)
+ return false;
+ } else {
+ bool sagv_masked = \
+ (BIT(pipe) & dev_priv->crtc_sagv_mask) == 0;
+ if (sagv_masked)
+ return false;
+ }
+ }
return true;
}
@@ -3925,6 +4045,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
int color_plane);
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
+ u32 latency,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */);
@@ -3947,7 +4068,10 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
WARN_ON(ret);
for (level = 0; level <= max_level; level++) {
- skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
+ u32 latency = dev_priv->wm.skl_latency[level];
+
+ skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
+
if (wm.min_ddb_alloc == U16_MAX)
break;
@@ -4212,6 +4336,68 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
return total_data_rate;
}
+static int
+tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
+ struct skl_ddb_allocation *ddb /* out */)
+{
+ struct drm_crtc *crtc = crtc_state->base.crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
+ u16 alloc_size;
+ u16 total[I915_MAX_PLANES] = {};
+ u64 total_data_rate;
+ enum plane_id plane_id;
+ int num_active;
+ u64 plane_data_rate[I915_MAX_PLANES] = {};
+ u32 blocks;
+
+ /*
+ * No need to check gen here, we call this only for gen12
+ */
+ total_data_rate =
+ icl_get_total_relative_data_rate(crtc_state,
+ plane_data_rate);
+
+ skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
+ total_data_rate,
+ ddb, alloc, &num_active);
+ alloc_size = skl_ddb_entry_size(alloc);
+ if (alloc_size == 0)
+ return -ENOSPC;
+
+ /* Allocate fixed number of blocks for cursor. */
+ total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
+ alloc_size -= total[PLANE_CURSOR];
+ crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
+ alloc->end - total[PLANE_CURSOR];
+ crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
+
+ /*
+ * Do check if we can fit L0 + sagv_block_time and
+ * disable SAGV if we can't.
+ */
+ blocks = 0;
+ for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+
+ if (plane_id == PLANE_CURSOR) {
+ if (WARN_ON(wm->sagv_wm0.min_ddb_alloc >
+ total[PLANE_CURSOR])) {
+ blocks = U32_MAX;
+ break;
+ }
+ continue;
+ }
+
+ blocks += wm->sagv_wm0.min_ddb_alloc;
+ if (blocks > alloc_size)
+ return -ENOSPC;
+ }
+ return 0;
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
struct skl_ddb_allocation *ddb /* out */)
@@ -4641,6 +4827,7 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
+ u32 latency,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
@@ -4767,20 +4954,45 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
static void
skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wm_params,
- struct skl_wm_level *levels)
+ struct skl_plane_wm *plane_wm,
+ bool yuv)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int level, max_level = ilk_wm_max_level(dev_priv);
+ /*
+ * Check which kind of plane is it and based on that calculate
+ * correspondent WM levels.
+ */
+ struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm;
struct skl_wm_level *result_prev = &levels[0];
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = &levels[level];
+ u32 latency = dev_priv->wm.skl_latency[level];
- skl_compute_plane_wm(crtc_state, level, wm_params,
- result_prev, result);
+ skl_compute_plane_wm(crtc_state, level, latency,
+ wm_params, result_prev, result);
result_prev = result;
}
+ /*
+ * For Gen12 if it is an L0 we need to also
+ * consider sagv_block_time when calculating
+ * L0 watermark - we will need that when making
+ * a decision whether enable SAGV or not.
+ * For older gens we agreed to copy L0 value for
+ * compatibility.
+ */
+ if ((INTEL_GEN(dev_priv) >= 12)) {
+ u32 latency = dev_priv->wm.skl_latency[0];
+
+ latency += dev_priv->sagv_block_time_us;
+ skl_compute_plane_wm(crtc_state, 0, latency,
+ wm_params, &levels[0],
+ &plane_wm->sagv_wm0);
+ } else
+ memcpy(&plane_wm->sagv_wm0, &levels[0],
+ sizeof(struct skl_wm_level));
}
static u32
@@ -4873,7 +5085,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
skl_compute_transition_wm(crtc_state, &wm_params, wm);
return 0;
@@ -4895,7 +5107,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
return 0;
}
@@ -5167,6 +5379,8 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
return 0;
}
+static void tgl_set_sagv_wm0(struct intel_atomic_state *state);
+
static int
skl_compute_ddb(struct intel_atomic_state *state)
{
@@ -5177,6 +5391,11 @@ skl_compute_ddb(struct intel_atomic_state *state)
struct intel_crtc *crtc;
int ret, i;
+ /* For Gen12+ for SAGV we have a special L0 wm values */
+ if (INTEL_GEN(dev_priv) >= 12)
+ if (intel_can_enable_sagv(state))
+ tgl_set_sagv_wm0(state);
+
memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
@@ -5443,6 +5662,56 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
return 0;
}
+void tgl_set_sagv_wm0(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc_state *old_crtc_state;
+ struct drm_device *dev = state->base.dev;
+ const struct drm_i915_private *dev_priv = to_i915(dev);
+ int i;
+
+ /*
+ * If we determined that we can actually enable SAGV, then
+ * actually use those levels tgl_check_pipe_fits_sagv_wm
+ * has already taken care of checking if L0 + sagv block time
+ * fits into ddb.
+ */
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ struct intel_plane *plane;
+
+ for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+ enum plane_id plane_id = plane->id;
+
+ struct skl_plane_wm *plane_wm = \
+ &new_crtc_state->wm.skl.optimal.planes[plane_id];
+ struct skl_wm_level *sagv_wm0 = &plane_wm->sagv_wm0;
+ struct skl_wm_level *l0_wm0 = &plane_wm->wm[0];
+
+ memcpy(l0_wm0, sagv_wm0, sizeof(struct skl_wm_level));
+ }
+ }
+}
+
+static void tgl_set_sagv_mask(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc_state *old_crtc_state;
+ struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
+ int ret, i;
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
+ if (!ret) {
+ int pipe_bit = BIT(crtc->pipe);
+ state->crtc_sagv_mask |= pipe_bit;
+ }
+ }
+}
+
static int
skl_compute_wm(struct intel_atomic_state *state)
{
@@ -5455,6 +5724,9 @@ skl_compute_wm(struct intel_atomic_state *state)
/* Clear all dirty flags */
results->dirty_pipes = 0;
+ /* If we exit before check is done */
+ state->crtc_sagv_mask = 0;
+
ret = skl_ddb_add_affected_pipes(state);
if (ret)
return ret;
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v10 1/2] drm/i915: Refactor intel_can_enable_sagv
@ 2019-11-07 15:30 ` Stanislav Lisovskiy
0 siblings, 0 replies; 25+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-07 15:30 UTC (permalink / raw)
To: intel-gfx
Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.
v2:
- Rework watermark calculation algorithm to
attempt to calculate Level 0 watermark
with added sagv block time latency and
check if it fits in DBuf in order to
determine if SAGV can be enabled already
at this stage, just as BSpec 49325 states.
if that fails rollback to usual Level 0
latency and disable SAGV.
- Remove unneeded tabs(James Ausmus)
v3: Rebased the patch
v4: - Added back interlaced check for Gen12 and
added separate function for TGL SAGV check
(thanks to James Ausmus for spotting)
- Removed unneeded gen check
- Extracted Gen12 SAGV decision making code
to a separate function from skl_compute_wm
v5: - Added SAGV global state to dev_priv, because
we need to track all pipes, not only those
in atomic state. Each pipe has now correspondent
bit mask reflecting, whether it can tolerate
SAGV or not(thanks to Ville Syrjala for suggestions).
- Now using active flag instead of enable in crc
usage check.
v6: - Fixed rebase conflicts
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +
.../drm/i915/display/intel_display_types.h | 9 +
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/intel_pm.c | 296 +++++++++++++++++-
4 files changed, 303 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 876fc25968bf..7ea1e7518ab6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14855,6 +14855,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (dev_priv->display.optimize_watermarks)
dev_priv->display.optimize_watermarks(state,
new_crtc_state);
+ if (state->crtc_sagv_mask & BIT(crtc->pipe))
+ dev_priv->crtc_sagv_mask |= BIT(crtc->pipe);
+ else
+ dev_priv->crtc_sagv_mask &= ~BIT(crtc->pipe);
}
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index fadd9853f966..fb274538af23 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -490,6 +490,14 @@ struct intel_atomic_state {
*/
u8 active_pipe_changes;
+ /*
+ * Contains a mask which reflects whether correspondent pipe
+ * can tolerate SAGV or not, so that we can make a decision
+ * at atomic_commit_tail stage, whether we enable it or not
+ * based on global state in dev_priv.
+ */
+ u32 crtc_sagv_mask;
+
u8 active_pipes;
/* minimum acceptable cdclk for each pipe */
int min_cdclk[I915_MAX_PIPES];
@@ -670,6 +678,7 @@ struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
+ struct skl_wm_level sagv_wm0;
bool is_planar;
};
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7e0f67babe20..4f4e2e839513 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1176,6 +1176,12 @@ struct drm_i915_private {
u32 sagv_block_time_us;
+ /*
+ * Contains a bit mask, whether correspondent
+ * pipe allows SAGV or not.
+ */
+ u32 crtc_sagv_mask;
+
struct {
/*
* Raw watermark latency values:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2d389e437e87..c792dd168742 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3740,7 +3740,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+static void skl_set_sagv_mask(struct intel_atomic_state *state)
{
struct drm_device *dev = state->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -3750,21 +3750,23 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
enum pipe pipe;
int level, latency;
+ state->crtc_sagv_mask = 0;
+
if (!intel_has_sagv(dev_priv))
- return false;
+ return;
/*
* If there are no active CRTCs, no additional checks need be performed
*/
if (hweight8(state->active_pipes) == 0)
- return true;
+ return;
/*
* SKL+ workaround: bspec recommends we disable SAGV when we have
* more then one pipe enabled
*/
if (hweight8(state->active_pipes) > 1)
- return false;
+ return;
/* Since we're now guaranteed to only have one active CRTC... */
pipe = ffs(state->active_pipes) - 1;
@@ -3772,7 +3774,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
crtc_state = to_intel_crtc_state(crtc->base.state);
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
- return false;
+ return;
for_each_intel_plane_on_crtc(dev, crtc, plane) {
struct skl_plane_wm *wm =
@@ -3800,9 +3802,127 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
* can't enable SAGV.
*/
if (latency < dev_priv->sagv_block_time_us)
- return false;
+ return;
}
+ state->crtc_sagv_mask |= BIT(crtc->pipe);
+}
+
+static void tgl_set_sagv_mask(struct intel_atomic_state *state);
+
+static void icl_set_sagv_mask(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ int level, latency;
+ int i;
+ int plane_id;
+
+ state->crtc_sagv_mask = 0;
+
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ /*
+ * If there are no active CRTCs, no additional checks need be performed
+ */
+ if (hweight8(state->active_pipes) == 0)
+ return;
+
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ unsigned int flags = crtc->base.state->adjusted_mode.flags;
+ bool can_sagv;
+
+ if (flags & DRM_MODE_FLAG_INTERLACE)
+ continue;
+
+ if (!new_crtc_state->base.active)
+ continue;
+
+ can_sagv = true;
+ for_each_plane_id_on_crtc(crtc, plane_id) {
+ struct skl_plane_wm *wm =
+ &new_crtc_state->wm.skl.optimal.planes[plane_id];
+
+ /* Skip this plane if it's not enabled */
+ if (!wm->wm[0].plane_en)
+ continue;
+
+ /* Find the highest enabled wm level for this plane */
+ for (level = ilk_wm_max_level(dev_priv);
+ !wm->wm[level].plane_en; --level) {
+ }
+
+ latency = dev_priv->wm.skl_latency[level];
+
+ /*
+ * If any of the planes on this pipe don't enable
+ * wm levels that incur memory latencies higher than
+ * sagv_block_time_us we can't enable SAGV.
+ */
+ if (latency < dev_priv->sagv_block_time_us) {
+ can_sagv = false;
+ break;
+ }
+ }
+ if (can_sagv)
+ state->crtc_sagv_mask |= BIT(crtc->pipe);
+ }
+}
+
+bool intel_can_enable_sagv(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum pipe pipe;
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ tgl_set_sagv_mask(state);
+ else if (INTEL_GEN(dev_priv) == 11)
+ icl_set_sagv_mask(state);
+ else
+ skl_set_sagv_mask(state);
+
+ /*
+ * For SAGV we need to account all the pipes,
+ * not only the ones which are in state currently.
+ */
+ for_each_pipe(dev_priv, pipe) {
+ unsigned int active_pipes;
+ /*
+ * Figure out if we are changing active pipes here
+ * then after commit dev_priv->active_pipes will
+ * anyway be assigned to state->active_pipes.
+ */
+ if (state->active_pipe_changes)
+ active_pipes = state->active_pipes;
+ else
+ active_pipes = dev_priv->active_pipes;
+
+ /* Skip if pipe is inactive */
+ if (!(BIT(pipe) & active_pipes))
+ continue;
+
+ /*
+ * Pipe can be active in this state or in dev_priv
+ * as we haven't committed thise changes yet(and we shouldn't)
+ * - we need to check both.
+ */
+ if (state->active_pipe_changes & BIT(pipe)) {
+ bool state_sagv_masked = \
+ (BIT(pipe) & state->crtc_sagv_mask) == 0;
+ if (state_sagv_masked)
+ return false;
+ } else {
+ bool sagv_masked = \
+ (BIT(pipe) & dev_priv->crtc_sagv_mask) == 0;
+ if (sagv_masked)
+ return false;
+ }
+ }
return true;
}
@@ -3925,6 +4045,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
int color_plane);
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
+ u32 latency,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */);
@@ -3947,7 +4068,10 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
WARN_ON(ret);
for (level = 0; level <= max_level; level++) {
- skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
+ u32 latency = dev_priv->wm.skl_latency[level];
+
+ skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
+
if (wm.min_ddb_alloc == U16_MAX)
break;
@@ -4212,6 +4336,68 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
return total_data_rate;
}
+static int
+tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
+ struct skl_ddb_allocation *ddb /* out */)
+{
+ struct drm_crtc *crtc = crtc_state->base.crtc;
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
+ u16 alloc_size;
+ u16 total[I915_MAX_PLANES] = {};
+ u64 total_data_rate;
+ enum plane_id plane_id;
+ int num_active;
+ u64 plane_data_rate[I915_MAX_PLANES] = {};
+ u32 blocks;
+
+ /*
+ * No need to check gen here, we call this only for gen12
+ */
+ total_data_rate =
+ icl_get_total_relative_data_rate(crtc_state,
+ plane_data_rate);
+
+ skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
+ total_data_rate,
+ ddb, alloc, &num_active);
+ alloc_size = skl_ddb_entry_size(alloc);
+ if (alloc_size == 0)
+ return -ENOSPC;
+
+ /* Allocate fixed number of blocks for cursor. */
+ total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
+ alloc_size -= total[PLANE_CURSOR];
+ crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
+ alloc->end - total[PLANE_CURSOR];
+ crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
+
+ /*
+ * Do check if we can fit L0 + sagv_block_time and
+ * disable SAGV if we can't.
+ */
+ blocks = 0;
+ for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+
+ if (plane_id == PLANE_CURSOR) {
+ if (WARN_ON(wm->sagv_wm0.min_ddb_alloc >
+ total[PLANE_CURSOR])) {
+ blocks = U32_MAX;
+ break;
+ }
+ continue;
+ }
+
+ blocks += wm->sagv_wm0.min_ddb_alloc;
+ if (blocks > alloc_size)
+ return -ENOSPC;
+ }
+ return 0;
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
struct skl_ddb_allocation *ddb /* out */)
@@ -4641,6 +4827,7 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
+ u32 latency,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
@@ -4767,20 +4954,45 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
static void
skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wm_params,
- struct skl_wm_level *levels)
+ struct skl_plane_wm *plane_wm,
+ bool yuv)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int level, max_level = ilk_wm_max_level(dev_priv);
+ /*
+ * Check which kind of plane is it and based on that calculate
+ * correspondent WM levels.
+ */
+ struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm;
struct skl_wm_level *result_prev = &levels[0];
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = &levels[level];
+ u32 latency = dev_priv->wm.skl_latency[level];
- skl_compute_plane_wm(crtc_state, level, wm_params,
- result_prev, result);
+ skl_compute_plane_wm(crtc_state, level, latency,
+ wm_params, result_prev, result);
result_prev = result;
}
+ /*
+ * For Gen12 if it is an L0 we need to also
+ * consider sagv_block_time when calculating
+ * L0 watermark - we will need that when making
+ * a decision whether enable SAGV or not.
+ * For older gens we agreed to copy L0 value for
+ * compatibility.
+ */
+ if ((INTEL_GEN(dev_priv) >= 12)) {
+ u32 latency = dev_priv->wm.skl_latency[0];
+
+ latency += dev_priv->sagv_block_time_us;
+ skl_compute_plane_wm(crtc_state, 0, latency,
+ wm_params, &levels[0],
+ &plane_wm->sagv_wm0);
+ } else
+ memcpy(&plane_wm->sagv_wm0, &levels[0],
+ sizeof(struct skl_wm_level));
}
static u32
@@ -4873,7 +5085,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
skl_compute_transition_wm(crtc_state, &wm_params, wm);
return 0;
@@ -4895,7 +5107,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
return 0;
}
@@ -5167,6 +5379,8 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
return 0;
}
+static void tgl_set_sagv_wm0(struct intel_atomic_state *state);
+
static int
skl_compute_ddb(struct intel_atomic_state *state)
{
@@ -5177,6 +5391,11 @@ skl_compute_ddb(struct intel_atomic_state *state)
struct intel_crtc *crtc;
int ret, i;
+ /* For Gen12+ for SAGV we have a special L0 wm values */
+ if (INTEL_GEN(dev_priv) >= 12)
+ if (intel_can_enable_sagv(state))
+ tgl_set_sagv_wm0(state);
+
memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
@@ -5443,6 +5662,56 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
return 0;
}
+void tgl_set_sagv_wm0(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc_state *old_crtc_state;
+ struct drm_device *dev = state->base.dev;
+ const struct drm_i915_private *dev_priv = to_i915(dev);
+ int i;
+
+ /*
+ * If we determined that we can actually enable SAGV, then
+ * actually use those levels tgl_check_pipe_fits_sagv_wm
+ * has already taken care of checking if L0 + sagv block time
+ * fits into ddb.
+ */
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ struct intel_plane *plane;
+
+ for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+ enum plane_id plane_id = plane->id;
+
+ struct skl_plane_wm *plane_wm = \
+ &new_crtc_state->wm.skl.optimal.planes[plane_id];
+ struct skl_wm_level *sagv_wm0 = &plane_wm->sagv_wm0;
+ struct skl_wm_level *l0_wm0 = &plane_wm->wm[0];
+
+ memcpy(l0_wm0, sagv_wm0, sizeof(struct skl_wm_level));
+ }
+ }
+}
+
+static void tgl_set_sagv_mask(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc_state *old_crtc_state;
+ struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
+ int ret, i;
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
+ if (!ret) {
+ int pipe_bit = BIT(crtc->pipe);
+ state->crtc_sagv_mask |= pipe_bit;
+ }
+ }
+}
+
static int
skl_compute_wm(struct intel_atomic_state *state)
{
@@ -5455,6 +5724,9 @@ skl_compute_wm(struct intel_atomic_state *state)
/* Clear all dirty flags */
results->dirty_pipes = 0;
+ /* If we exit before check is done */
+ state->crtc_sagv_mask = 0;
+
ret = skl_ddb_add_affected_pipes(state);
if (ret)
return ret;
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v10 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.
@ 2019-11-07 15:30 ` Stanislav Lisovskiy
0 siblings, 0 replies; 25+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-07 15:30 UTC (permalink / raw)
To: intel-gfx
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid simultaneous legacy SAGV PCode requests and
restricting qgv points. Put the actual restriction
to commit function, added serialization(thanks to Ville)
to prevent commit being applied out of order in case of
nonblocking and/or nomodeset commits.
v4:
- Minor code refactoring, fixed few typos(thanks to James Ausmus)
- Change the naming of qgv point
masking/unmasking functions(James Ausmus).
- Simplify the masking/unmasking operation itself,
as we don't need to mask only single point per request(James Ausmus)
- Reject and stick to highest bandwidth point if SAGV
can't be enabled(BSpec)
v5:
- Add new mailbox reply codes, which seems to happen during boot
time for TGL and indicate that QGV setting is not yet available.
v6:
- Increase number of supported QGV points to be in sync with BSpec.
v7: - Rebased and resolved conflict to fix build failure.
- Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)
v8: - Don't report an error if we can't restrict qgv points, as SAGV
can be disabled by BIOS, which is completely legal. So don't
make CI panic. Instead if we detect that there is only 1 QGV
point accessible just analyze if we can fit the required bandwidth
requirements, but no need in restricting.
v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
simultaneously.
v10: - Fix CDCLK corruption, because of global state getting serialized
without modeset, which caused copying of non-calculated cdclk
to be copied to dev_priv(thanks to Ville for the hint).
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.h | 3 +
drivers/gpu/drm/i915/display/intel_bw.c | 137 +++++++++++++++---
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 104 ++++++++++++-
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 8 +
drivers/gpu/drm/i915/intel_pm.c | 15 +-
drivers/gpu/drm/i915/intel_pm.h | 1 +
drivers/gpu/drm/i915/intel_sideband.c | 27 +++-
drivers/gpu/drm/i915/intel_sideband.h | 1 -
11 files changed, 264 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
index 7b49623419ba..3ab6d7ec75ae 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -7,6 +7,7 @@
#define __INTEL_ATOMIC_H__
#include <linux/types.h>
+#include "intel_display_types.h"
struct drm_atomic_state;
struct drm_connector;
@@ -41,6 +42,8 @@ void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
void intel_atomic_state_clear(struct drm_atomic_state *state);
+int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
+
struct intel_crtc_state *
intel_atomic_get_crtc_state(struct drm_atomic_state *state,
struct intel_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 3f6e29f61323..1dde4e1574fb 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -8,6 +8,9 @@
#include "intel_bw.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
+#include "intel_atomic.h"
+#include "intel_pm.h"
+
/* Parameters for Qclk Geyserville (QGV) */
struct intel_qgv_point {
@@ -15,7 +18,7 @@ struct intel_qgv_point {
};
struct intel_qgv_info {
- struct intel_qgv_point points[3];
+ struct intel_qgv_point points[NUM_SAGV_POINTS];
u8 num_points;
u8 num_channels;
u8 t_bl;
@@ -113,6 +116,27 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
return 0;
}
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask)
+{
+ int ret;
+
+ /* bspec says to keep retrying for at least 1 ms */
+ ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+ points_mask,
+ GEN11_PCODE_POINTS_RESTRICTED_MASK,
+ GEN11_PCODE_POINTS_RESTRICTED,
+ 1);
+
+ if (ret < 0) {
+ DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+
static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
struct intel_qgv_info *qi)
{
@@ -176,7 +200,7 @@ static const struct intel_sa_info tgl_sa_info = {
static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
{
- struct intel_qgv_info qi = {};
+ struct intel_qgv_info qi;
bool is_y_tile = true; /* assume y tile may be used */
int num_channels;
int deinterleave;
@@ -270,22 +294,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
icl_get_bw_info(dev_priv, &icl_sa_info);
}
-static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
- int num_planes)
-{
- if (INTEL_GEN(dev_priv) >= 11)
- /*
- * FIXME with SAGV disabled maybe we can assume
- * point 1 will always be used? Seems to match
- * the behaviour observed in the wild.
- */
- return min3(icl_max_bw(dev_priv, num_planes, 0),
- icl_max_bw(dev_priv, num_planes, 1),
- icl_max_bw(dev_priv, num_planes, 2));
- else
- return UINT_MAX;
-}
-
static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
{
/*
@@ -377,7 +385,12 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
unsigned int data_rate, max_data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
- int i;
+ int i, ret;
+ struct intel_qgv_info qi = {};
+ u32 allowed_points = 0;
+ unsigned int max_bw_point = 0, max_bw = 0;
+ unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+ u32 mask = (1 << num_qgv_points) - 1;
/* FIXME earlier gens need some checks too */
if (INTEL_GEN(dev_priv) < 11)
@@ -421,16 +434,92 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
data_rate = intel_bw_data_rate(dev_priv, bw_state);
num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
- max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
-
data_rate = DIV_ROUND_UP(data_rate, 1000);
- if (data_rate > max_data_rate) {
- DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
- data_rate, max_data_rate, num_active_planes);
+ for (i = 0; i < num_qgv_points; i++) {
+ max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
+ /*
+ * We need to know which qgv point gives us
+ * maximum bandwidth in order to disable SAGV
+ * if we find that we exceed SAGV block time
+ * with watermarks. By that moment we already
+ * have those, as it is calculated earlier in
+ * intel_atomic_check,
+ */
+ if (max_data_rate > max_bw) {
+ max_bw_point = i;
+ max_bw = max_data_rate;
+ }
+ if (max_data_rate >= data_rate)
+ allowed_points |= 1 << i;
+ DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
+ i, max_data_rate, data_rate);
+ }
+
+ /*
+ * BSpec states that we always should have at least one allowed point
+ * left, so if we couldn't - simply reject the configuration for obvious
+ * reasons.
+ */
+ if (allowed_points == 0) {
+ DRM_DEBUG_KMS("Could not find any suitable QGV points\n");
return -EINVAL;
}
+ /*
+ * In case if SAGV is disabled in BIOS, we always get 1
+ * SAGV point, but we can't send PCode commands to restrict it
+ * as it will fail and pointless anyway.
+ */
+ if (qi.num_points == 1)
+ dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+ else
+ dev_priv->sagv_status = I915_SAGV_ENABLED;
+
+ /*
+ * Leave only single point with highest bandwidth, if
+ * we can't enable SAGV according to BSpec.
+ */
+ if (!intel_can_enable_sagv(state)) {
+
+ /*
+ * This is a border line condition when we have 0 planes
+ * and SAGV not enabled means that we should keep QGV with
+ * highest bandwidth, however algorithm returns wrong result
+ * for 0 planes and 0 data rate, so just stick to last config
+ * then. Otherwise use the QGV point with highest BW according
+ * to BSpec.
+ */
+ if (!data_rate && !num_active_planes) {
+ DRM_DEBUG_KMS("No SAGV, using old QGV mask\n");
+ allowed_points = (~dev_priv->qgv_points_mask) & mask;
+ } else {
+ allowed_points = 1 << max_bw_point;
+ DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n",
+ max_bw_point);
+ }
+ }
+ /*
+ * We store the ones which need to be masked as that is what PCode
+ * actually accepts as a parameter.
+ */
+ state->qgv_points_mask = (~allowed_points) & mask;
+
+ DRM_DEBUG_KMS("New state %p qgv mask %x\n",
+ state, state->qgv_points_mask);
+
+ /*
+ * If the actual mask had changed we need to make sure that
+ * the commits are serialized(in case this is a nomodeset, nonblocking)
+ */
+ if (state->qgv_points_mask != dev_priv->qgv_points_mask) {
+ ret = intel_atomic_serialize_global_state(state);
+ if (ret) {
+ DRM_DEBUG_KMS("Could not serialize global state\n");
+ return ret;
+ }
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 9db10af012f4..66bf9bc10b73 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -28,5 +28,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state);
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask);
#endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7ea1e7518ab6..71f6aaa1f6b9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14744,6 +14744,80 @@ static void intel_atomic_cleanup_work(struct work_struct *work)
intel_atomic_helper_free_state(i915);
}
+static void intel_qgv_points_mask(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ int ret;
+ u32 new_mask = dev_priv->qgv_points_mask | state->qgv_points_mask;
+ unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+ unsigned int mask = (1 << num_qgv_points) - 1;
+
+ /*
+ * As we don't know initial hardware state during initial commit
+ * we should not do anything, until we actually figure out,
+ * what are the qgv points to mask.
+ */
+ if (!new_mask)
+ return;
+
+ WARN_ON(new_mask == mask);
+
+ /*
+ * Just return if we can't control SAGV or don't have it.
+ */
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ /*
+ * Restrict required qgv points before updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n",
+ ret);
+ else
+ dev_priv->qgv_points_mask = new_mask;
+}
+
+static void intel_qgv_points_unmask(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ int ret;
+ u32 new_mask = dev_priv->qgv_points_mask & state->qgv_points_mask;
+
+ /*
+ * As we don't know initial hardware state during initial commit
+ * we should not do anything, until we actually figure out,
+ * what are the qgv points to mask.
+ */
+ if (!new_mask)
+ return;
+
+ /*
+ * Just return if we can't control SAGV or don't have it.
+ */
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ /*
+ * Allow required qgv points after updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n",
+ ret);
+ else
+ dev_priv->qgv_points_mask = new_mask;
+}
+
static void intel_atomic_commit_tail(struct intel_atomic_state *state)
{
struct drm_device *dev = state->base.dev;
@@ -14771,6 +14845,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
}
}
+ if ((INTEL_GEN(dev_priv) >= 11))
+ intel_qgv_points_mask(state);
+
intel_commit_modeset_disables(state);
/* FIXME: Eventually get rid of our crtc->config pointer */
@@ -14789,8 +14866,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
* SKL workaround: bspec recommends we disable the SAGV when we
* have more then one pipe enabled
*/
- if (!intel_can_enable_sagv(state))
- intel_disable_sagv(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11)
+ if (!intel_can_enable_sagv(state))
+ intel_disable_sagv(dev_priv);
intel_modeset_verify_disabled(dev_priv, state);
}
@@ -14873,8 +14951,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
intel_verify_planes(state);
- if (state->modeset && intel_can_enable_sagv(state))
- intel_enable_sagv(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11) {
+ if (state->modeset && intel_can_enable_sagv(state))
+ intel_enable_sagv(dev_priv);
+ } else
+ intel_qgv_points_unmask(state);
drm_atomic_helper_commit_hw_done(&state->base);
@@ -14962,7 +15043,18 @@ static int intel_atomic_commit(struct drm_device *dev,
{
struct intel_atomic_state *state = to_intel_atomic_state(_state);
struct drm_i915_private *dev_priv = to_i915(dev);
- int ret = 0;
+ struct intel_crtc_state *new_crtc_state, *old_crtc_state;
+ int ret = 0, i;
+ bool any_ms = false;
+ struct intel_crtc *crtc;
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ if (needs_modeset(new_crtc_state)) {
+ any_ms = true;
+ break;
+ }
+ }
state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
@@ -15021,7 +15113,7 @@ static int intel_atomic_commit(struct drm_device *dev,
intel_shared_dpll_swap_state(state);
intel_atomic_track_fbs(state);
- if (state->global_state_changed) {
+ if (state->global_state_changed && any_ms) {
assert_global_state_locked(dev_priv);
memcpy(dev_priv->min_cdclk, state->min_cdclk,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index fb274538af23..896b13bc4494 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -528,6 +528,9 @@ struct intel_atomic_state {
struct i915_sw_fence commit_ready;
struct llist_node freed;
+
+ /* Gen11+ only */
+ u32 qgv_points_mask;
};
struct intel_plane_state {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4f4e2e839513..9924390cb94b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1243,11 +1243,13 @@ struct drm_i915_private {
} dram_info;
struct intel_bw_info {
- unsigned int deratedbw[3]; /* for each QGV point */
+ unsigned int deratedbw[NUM_SAGV_POINTS]; /* for each QGV point */
u8 num_qgv_points;
u8 num_planes;
} max_bw[6];
+ u32 qgv_points_mask;
+
struct drm_private_obj bw_obj;
struct intel_runtime_pm runtime_pm;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a607ea520829..6d6ecf1d9f6b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8951,6 +8951,9 @@ enum {
#define VLV_RENDER_C0_COUNT _MMIO(0x138118)
#define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
+/* BSpec precisely defines this */
+#define NUM_SAGV_POINTS 8
+
#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
#define GEN6_PCODE_READY (1 << 31)
#define GEN6_PCODE_ERROR_MASK 0xFF
@@ -8961,6 +8964,8 @@ enum {
#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
#define GEN7_PCODE_TIMEOUT 0x2
#define GEN7_PCODE_ILLEGAL_DATA 0x3
+#define GEN11_PCODE_MAIL_BOX_LOCKED 0x6
+#define GEN11_PCODE_REJECTED 0x11
#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
#define GEN6_PCODE_WRITE_RC6VIDS 0x4
#define GEN6_PCODE_READ_RC6VIDS 0x5
@@ -8982,6 +8987,7 @@ enum {
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
+#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
@@ -8994,6 +9000,8 @@ enum {
#define GEN9_SAGV_IS_DISABLED 0x1
#define GEN9_SAGV_ENABLE 0x3
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
+#define GEN11_PCODE_POINTS_RESTRICTED 0x0
+#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
#define GEN6_PCODE_DATA _MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c792dd168742..10816f3e29f0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3617,13 +3617,9 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
}
-static bool
+bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
- /* HACK! */
- if (IS_GEN(dev_priv, 12))
- return false;
-
return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
}
@@ -3839,7 +3835,7 @@ static void icl_set_sagv_mask(struct intel_atomic_state *state)
if (flags & DRM_MODE_FLAG_INTERLACE)
continue;
- if (!new_crtc_state->base.active)
+ if (!new_crtc_state->hw.enable)
continue;
can_sagv = true;
@@ -3886,6 +3882,9 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
else
skl_set_sagv_mask(state);
+ DRM_DEBUG_KMS("Crtc sagv masks, state %x global state %x\n",
+ state->crtc_sagv_mask,
+ dev_priv->crtc_sagv_mask);
/*
* For SAGV we need to account all the pipes,
* not only the ones which are in state currently.
@@ -4340,7 +4339,7 @@ static int
tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
struct skl_ddb_allocation *ddb /* out */)
{
- struct drm_crtc *crtc = crtc_state->base.crtc;
+ struct drm_crtc *crtc = crtc_state->uapi.crtc;
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
@@ -4833,7 +4832,6 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
struct skl_wm_level *result /* out */)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- u32 latency = dev_priv->wm.skl_latency[level];
uint_fixed_16_16_t method1, method2;
uint_fixed_16_16_t selected_result;
u32 res_blocks, res_lines, min_ddb_alloc = 0;
@@ -5707,6 +5705,7 @@ static void tgl_set_sagv_mask(struct intel_atomic_state *state)
ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
if (!ret) {
int pipe_bit = BIT(crtc->pipe);
+
state->crtc_sagv_mask |= pipe_bit;
}
}
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index b579c724b915..53275860731a 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -43,6 +43,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
bool intel_can_enable_sagv(struct intel_atomic_state *state);
+bool intel_has_sagv(struct drm_i915_private *dev_priv);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
bool skl_wm_level_equals(const struct skl_wm_level *l1,
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index e06b35b844a0..ff9dbed094d8 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -371,6 +371,29 @@ static inline int gen7_check_mailbox_status(u32 mbox)
}
}
+static inline int gen11_check_mailbox_status(u32 mbox)
+{
+ switch (mbox & GEN6_PCODE_ERROR_MASK) {
+ case GEN6_PCODE_SUCCESS:
+ return 0;
+ case GEN6_PCODE_ILLEGAL_CMD:
+ return -ENXIO;
+ case GEN7_PCODE_TIMEOUT:
+ return -ETIMEDOUT;
+ case GEN7_PCODE_ILLEGAL_DATA:
+ return -EINVAL;
+ case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
+ return -EOVERFLOW;
+ case GEN11_PCODE_MAIL_BOX_LOCKED:
+ return -EAGAIN;
+ case GEN11_PCODE_REJECTED:
+ return -EACCES;
+ default:
+ MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
+ return 0;
+ }
+}
+
static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
u32 mbox, u32 *val, u32 *val1,
int fast_timeout_us,
@@ -408,7 +431,9 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
if (is_read && val1)
*val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
- if (INTEL_GEN(i915) > 6)
+ if (INTEL_GEN(i915) >= 11)
+ return gen11_check_mailbox_status(mbox);
+ else if (INTEL_GEN(i915) > 6)
return gen7_check_mailbox_status(mbox);
else
return gen6_check_mailbox_status(mbox);
diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h
index 7fb95745a444..14627ace99ae 100644
--- a/drivers/gpu/drm/i915/intel_sideband.h
+++ b/drivers/gpu/drm/i915/intel_sideband.h
@@ -137,5 +137,4 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
-
#endif /* _INTEL_SIDEBAND_H */
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v10 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.
@ 2019-11-07 15:30 ` Stanislav Lisovskiy
0 siblings, 0 replies; 25+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-07 15:30 UTC (permalink / raw)
To: intel-gfx
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid simultaneous legacy SAGV PCode requests and
restricting qgv points. Put the actual restriction
to commit function, added serialization(thanks to Ville)
to prevent commit being applied out of order in case of
nonblocking and/or nomodeset commits.
v4:
- Minor code refactoring, fixed few typos(thanks to James Ausmus)
- Change the naming of qgv point
masking/unmasking functions(James Ausmus).
- Simplify the masking/unmasking operation itself,
as we don't need to mask only single point per request(James Ausmus)
- Reject and stick to highest bandwidth point if SAGV
can't be enabled(BSpec)
v5:
- Add new mailbox reply codes, which seems to happen during boot
time for TGL and indicate that QGV setting is not yet available.
v6:
- Increase number of supported QGV points to be in sync with BSpec.
v7: - Rebased and resolved conflict to fix build failure.
- Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)
v8: - Don't report an error if we can't restrict qgv points, as SAGV
can be disabled by BIOS, which is completely legal. So don't
make CI panic. Instead if we detect that there is only 1 QGV
point accessible just analyze if we can fit the required bandwidth
requirements, but no need in restricting.
v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
simultaneously.
v10: - Fix CDCLK corruption, because of global state getting serialized
without modeset, which caused copying of non-calculated cdclk
to be copied to dev_priv(thanks to Ville for the hint).
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.h | 3 +
drivers/gpu/drm/i915/display/intel_bw.c | 137 +++++++++++++++---
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 104 ++++++++++++-
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 8 +
drivers/gpu/drm/i915/intel_pm.c | 15 +-
drivers/gpu/drm/i915/intel_pm.h | 1 +
drivers/gpu/drm/i915/intel_sideband.c | 27 +++-
drivers/gpu/drm/i915/intel_sideband.h | 1 -
11 files changed, 264 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
index 7b49623419ba..3ab6d7ec75ae 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -7,6 +7,7 @@
#define __INTEL_ATOMIC_H__
#include <linux/types.h>
+#include "intel_display_types.h"
struct drm_atomic_state;
struct drm_connector;
@@ -41,6 +42,8 @@ void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
void intel_atomic_state_clear(struct drm_atomic_state *state);
+int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
+
struct intel_crtc_state *
intel_atomic_get_crtc_state(struct drm_atomic_state *state,
struct intel_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 3f6e29f61323..1dde4e1574fb 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -8,6 +8,9 @@
#include "intel_bw.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
+#include "intel_atomic.h"
+#include "intel_pm.h"
+
/* Parameters for Qclk Geyserville (QGV) */
struct intel_qgv_point {
@@ -15,7 +18,7 @@ struct intel_qgv_point {
};
struct intel_qgv_info {
- struct intel_qgv_point points[3];
+ struct intel_qgv_point points[NUM_SAGV_POINTS];
u8 num_points;
u8 num_channels;
u8 t_bl;
@@ -113,6 +116,27 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
return 0;
}
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask)
+{
+ int ret;
+
+ /* bspec says to keep retrying for at least 1 ms */
+ ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+ points_mask,
+ GEN11_PCODE_POINTS_RESTRICTED_MASK,
+ GEN11_PCODE_POINTS_RESTRICTED,
+ 1);
+
+ if (ret < 0) {
+ DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+
static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
struct intel_qgv_info *qi)
{
@@ -176,7 +200,7 @@ static const struct intel_sa_info tgl_sa_info = {
static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
{
- struct intel_qgv_info qi = {};
+ struct intel_qgv_info qi;
bool is_y_tile = true; /* assume y tile may be used */
int num_channels;
int deinterleave;
@@ -270,22 +294,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
icl_get_bw_info(dev_priv, &icl_sa_info);
}
-static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
- int num_planes)
-{
- if (INTEL_GEN(dev_priv) >= 11)
- /*
- * FIXME with SAGV disabled maybe we can assume
- * point 1 will always be used? Seems to match
- * the behaviour observed in the wild.
- */
- return min3(icl_max_bw(dev_priv, num_planes, 0),
- icl_max_bw(dev_priv, num_planes, 1),
- icl_max_bw(dev_priv, num_planes, 2));
- else
- return UINT_MAX;
-}
-
static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
{
/*
@@ -377,7 +385,12 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
unsigned int data_rate, max_data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
- int i;
+ int i, ret;
+ struct intel_qgv_info qi = {};
+ u32 allowed_points = 0;
+ unsigned int max_bw_point = 0, max_bw = 0;
+ unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+ u32 mask = (1 << num_qgv_points) - 1;
/* FIXME earlier gens need some checks too */
if (INTEL_GEN(dev_priv) < 11)
@@ -421,16 +434,92 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
data_rate = intel_bw_data_rate(dev_priv, bw_state);
num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
- max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
-
data_rate = DIV_ROUND_UP(data_rate, 1000);
- if (data_rate > max_data_rate) {
- DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
- data_rate, max_data_rate, num_active_planes);
+ for (i = 0; i < num_qgv_points; i++) {
+ max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
+ /*
+ * We need to know which qgv point gives us
+ * maximum bandwidth in order to disable SAGV
+ * if we find that we exceed SAGV block time
+ * with watermarks. By that moment we already
+ * have those, as it is calculated earlier in
+ * intel_atomic_check,
+ */
+ if (max_data_rate > max_bw) {
+ max_bw_point = i;
+ max_bw = max_data_rate;
+ }
+ if (max_data_rate >= data_rate)
+ allowed_points |= 1 << i;
+ DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
+ i, max_data_rate, data_rate);
+ }
+
+ /*
+ * BSpec states that we always should have at least one allowed point
+ * left, so if we couldn't - simply reject the configuration for obvious
+ * reasons.
+ */
+ if (allowed_points == 0) {
+ DRM_DEBUG_KMS("Could not find any suitable QGV points\n");
return -EINVAL;
}
+ /*
+ * In case if SAGV is disabled in BIOS, we always get 1
+ * SAGV point, but we can't send PCode commands to restrict it
+ * as it will fail and pointless anyway.
+ */
+ if (qi.num_points == 1)
+ dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+ else
+ dev_priv->sagv_status = I915_SAGV_ENABLED;
+
+ /*
+ * Leave only single point with highest bandwidth, if
+ * we can't enable SAGV according to BSpec.
+ */
+ if (!intel_can_enable_sagv(state)) {
+
+ /*
+ * This is a border line condition when we have 0 planes
+ * and SAGV not enabled means that we should keep QGV with
+ * highest bandwidth, however algorithm returns wrong result
+ * for 0 planes and 0 data rate, so just stick to last config
+ * then. Otherwise use the QGV point with highest BW according
+ * to BSpec.
+ */
+ if (!data_rate && !num_active_planes) {
+ DRM_DEBUG_KMS("No SAGV, using old QGV mask\n");
+ allowed_points = (~dev_priv->qgv_points_mask) & mask;
+ } else {
+ allowed_points = 1 << max_bw_point;
+ DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n",
+ max_bw_point);
+ }
+ }
+ /*
+ * We store the ones which need to be masked as that is what PCode
+ * actually accepts as a parameter.
+ */
+ state->qgv_points_mask = (~allowed_points) & mask;
+
+ DRM_DEBUG_KMS("New state %p qgv mask %x\n",
+ state, state->qgv_points_mask);
+
+ /*
+ * If the actual mask had changed we need to make sure that
+ * the commits are serialized(in case this is a nomodeset, nonblocking)
+ */
+ if (state->qgv_points_mask != dev_priv->qgv_points_mask) {
+ ret = intel_atomic_serialize_global_state(state);
+ if (ret) {
+ DRM_DEBUG_KMS("Could not serialize global state\n");
+ return ret;
+ }
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 9db10af012f4..66bf9bc10b73 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -28,5 +28,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state);
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask);
#endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7ea1e7518ab6..71f6aaa1f6b9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14744,6 +14744,80 @@ static void intel_atomic_cleanup_work(struct work_struct *work)
intel_atomic_helper_free_state(i915);
}
+static void intel_qgv_points_mask(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ int ret;
+ u32 new_mask = dev_priv->qgv_points_mask | state->qgv_points_mask;
+ unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+ unsigned int mask = (1 << num_qgv_points) - 1;
+
+ /*
+ * As we don't know initial hardware state during initial commit
+ * we should not do anything, until we actually figure out,
+ * what are the qgv points to mask.
+ */
+ if (!new_mask)
+ return;
+
+ WARN_ON(new_mask == mask);
+
+ /*
+ * Just return if we can't control SAGV or don't have it.
+ */
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ /*
+ * Restrict required qgv points before updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n",
+ ret);
+ else
+ dev_priv->qgv_points_mask = new_mask;
+}
+
+static void intel_qgv_points_unmask(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ int ret;
+ u32 new_mask = dev_priv->qgv_points_mask & state->qgv_points_mask;
+
+ /*
+ * As we don't know initial hardware state during initial commit
+ * we should not do anything, until we actually figure out,
+ * what are the qgv points to mask.
+ */
+ if (!new_mask)
+ return;
+
+ /*
+ * Just return if we can't control SAGV or don't have it.
+ */
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ /*
+ * Allow required qgv points after updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n",
+ ret);
+ else
+ dev_priv->qgv_points_mask = new_mask;
+}
+
static void intel_atomic_commit_tail(struct intel_atomic_state *state)
{
struct drm_device *dev = state->base.dev;
@@ -14771,6 +14845,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
}
}
+ if ((INTEL_GEN(dev_priv) >= 11))
+ intel_qgv_points_mask(state);
+
intel_commit_modeset_disables(state);
/* FIXME: Eventually get rid of our crtc->config pointer */
@@ -14789,8 +14866,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
* SKL workaround: bspec recommends we disable the SAGV when we
* have more then one pipe enabled
*/
- if (!intel_can_enable_sagv(state))
- intel_disable_sagv(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11)
+ if (!intel_can_enable_sagv(state))
+ intel_disable_sagv(dev_priv);
intel_modeset_verify_disabled(dev_priv, state);
}
@@ -14873,8 +14951,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
intel_verify_planes(state);
- if (state->modeset && intel_can_enable_sagv(state))
- intel_enable_sagv(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11) {
+ if (state->modeset && intel_can_enable_sagv(state))
+ intel_enable_sagv(dev_priv);
+ } else
+ intel_qgv_points_unmask(state);
drm_atomic_helper_commit_hw_done(&state->base);
@@ -14962,7 +15043,18 @@ static int intel_atomic_commit(struct drm_device *dev,
{
struct intel_atomic_state *state = to_intel_atomic_state(_state);
struct drm_i915_private *dev_priv = to_i915(dev);
- int ret = 0;
+ struct intel_crtc_state *new_crtc_state, *old_crtc_state;
+ int ret = 0, i;
+ bool any_ms = false;
+ struct intel_crtc *crtc;
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ if (needs_modeset(new_crtc_state)) {
+ any_ms = true;
+ break;
+ }
+ }
state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
@@ -15021,7 +15113,7 @@ static int intel_atomic_commit(struct drm_device *dev,
intel_shared_dpll_swap_state(state);
intel_atomic_track_fbs(state);
- if (state->global_state_changed) {
+ if (state->global_state_changed && any_ms) {
assert_global_state_locked(dev_priv);
memcpy(dev_priv->min_cdclk, state->min_cdclk,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index fb274538af23..896b13bc4494 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -528,6 +528,9 @@ struct intel_atomic_state {
struct i915_sw_fence commit_ready;
struct llist_node freed;
+
+ /* Gen11+ only */
+ u32 qgv_points_mask;
};
struct intel_plane_state {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4f4e2e839513..9924390cb94b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1243,11 +1243,13 @@ struct drm_i915_private {
} dram_info;
struct intel_bw_info {
- unsigned int deratedbw[3]; /* for each QGV point */
+ unsigned int deratedbw[NUM_SAGV_POINTS]; /* for each QGV point */
u8 num_qgv_points;
u8 num_planes;
} max_bw[6];
+ u32 qgv_points_mask;
+
struct drm_private_obj bw_obj;
struct intel_runtime_pm runtime_pm;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a607ea520829..6d6ecf1d9f6b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8951,6 +8951,9 @@ enum {
#define VLV_RENDER_C0_COUNT _MMIO(0x138118)
#define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
+/* BSpec precisely defines this */
+#define NUM_SAGV_POINTS 8
+
#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
#define GEN6_PCODE_READY (1 << 31)
#define GEN6_PCODE_ERROR_MASK 0xFF
@@ -8961,6 +8964,8 @@ enum {
#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
#define GEN7_PCODE_TIMEOUT 0x2
#define GEN7_PCODE_ILLEGAL_DATA 0x3
+#define GEN11_PCODE_MAIL_BOX_LOCKED 0x6
+#define GEN11_PCODE_REJECTED 0x11
#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
#define GEN6_PCODE_WRITE_RC6VIDS 0x4
#define GEN6_PCODE_READ_RC6VIDS 0x5
@@ -8982,6 +8987,7 @@ enum {
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
+#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
@@ -8994,6 +9000,8 @@ enum {
#define GEN9_SAGV_IS_DISABLED 0x1
#define GEN9_SAGV_ENABLE 0x3
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
+#define GEN11_PCODE_POINTS_RESTRICTED 0x0
+#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
#define GEN6_PCODE_DATA _MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c792dd168742..10816f3e29f0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3617,13 +3617,9 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
}
-static bool
+bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
- /* HACK! */
- if (IS_GEN(dev_priv, 12))
- return false;
-
return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
}
@@ -3839,7 +3835,7 @@ static void icl_set_sagv_mask(struct intel_atomic_state *state)
if (flags & DRM_MODE_FLAG_INTERLACE)
continue;
- if (!new_crtc_state->base.active)
+ if (!new_crtc_state->hw.enable)
continue;
can_sagv = true;
@@ -3886,6 +3882,9 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
else
skl_set_sagv_mask(state);
+ DRM_DEBUG_KMS("Crtc sagv masks, state %x global state %x\n",
+ state->crtc_sagv_mask,
+ dev_priv->crtc_sagv_mask);
/*
* For SAGV we need to account all the pipes,
* not only the ones which are in state currently.
@@ -4340,7 +4339,7 @@ static int
tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
struct skl_ddb_allocation *ddb /* out */)
{
- struct drm_crtc *crtc = crtc_state->base.crtc;
+ struct drm_crtc *crtc = crtc_state->uapi.crtc;
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
@@ -4833,7 +4832,6 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
struct skl_wm_level *result /* out */)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- u32 latency = dev_priv->wm.skl_latency[level];
uint_fixed_16_16_t method1, method2;
uint_fixed_16_16_t selected_result;
u32 res_blocks, res_lines, min_ddb_alloc = 0;
@@ -5707,6 +5705,7 @@ static void tgl_set_sagv_mask(struct intel_atomic_state *state)
ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
if (!ret) {
int pipe_bit = BIT(crtc->pipe);
+
state->crtc_sagv_mask |= pipe_bit;
}
}
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index b579c724b915..53275860731a 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -43,6 +43,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
bool intel_can_enable_sagv(struct intel_atomic_state *state);
+bool intel_has_sagv(struct drm_i915_private *dev_priv);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
bool skl_wm_level_equals(const struct skl_wm_level *l1,
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index e06b35b844a0..ff9dbed094d8 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -371,6 +371,29 @@ static inline int gen7_check_mailbox_status(u32 mbox)
}
}
+static inline int gen11_check_mailbox_status(u32 mbox)
+{
+ switch (mbox & GEN6_PCODE_ERROR_MASK) {
+ case GEN6_PCODE_SUCCESS:
+ return 0;
+ case GEN6_PCODE_ILLEGAL_CMD:
+ return -ENXIO;
+ case GEN7_PCODE_TIMEOUT:
+ return -ETIMEDOUT;
+ case GEN7_PCODE_ILLEGAL_DATA:
+ return -EINVAL;
+ case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
+ return -EOVERFLOW;
+ case GEN11_PCODE_MAIL_BOX_LOCKED:
+ return -EAGAIN;
+ case GEN11_PCODE_REJECTED:
+ return -EACCES;
+ default:
+ MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
+ return 0;
+ }
+}
+
static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
u32 mbox, u32 *val, u32 *val1,
int fast_timeout_us,
@@ -408,7 +431,9 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
if (is_read && val1)
*val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
- if (INTEL_GEN(i915) > 6)
+ if (INTEL_GEN(i915) >= 11)
+ return gen11_check_mailbox_status(mbox);
+ else if (INTEL_GEN(i915) > 6)
return gen7_check_mailbox_status(mbox);
else
return gen6_check_mailbox_status(mbox);
diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h
index 7fb95745a444..14627ace99ae 100644
--- a/drivers/gpu/drm/i915/intel_sideband.h
+++ b/drivers/gpu/drm/i915/intel_sideband.h
@@ -137,5 +137,4 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
-
#endif /* _INTEL_SIDEBAND_H */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev10)
@ 2019-11-07 19:43 ` Patchwork
0 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-11-07 19:43 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev10)
URL : https://patchwork.freedesktop.org/series/68028/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a731ea6228dd drm/i915: Refactor intel_can_enable_sagv
-:191: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#191: FILE: drivers/gpu/drm/i915/intel_pm.c:3835:
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
-:271: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#271: FILE: drivers/gpu/drm/i915/intel_pm.c:3915:
+ bool state_sagv_masked = \
-:276: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#276: FILE: drivers/gpu/drm/i915/intel_pm.c:3920:
+ bool sagv_masked = \
-:311: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#311: FILE: drivers/gpu/drm/i915/intel_pm.c:4341:
+tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
+ struct skl_ddb_allocation *ddb /* out */)
-:423: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#423: FILE: drivers/gpu/drm/i915/intel_pm.c:4991:
+ skl_compute_plane_wm(crtc_state, 0, latency,
+ wm_params, &levels[0],
-:425: CHECK:BRACES: Unbalanced braces around else statement
#425: FILE: drivers/gpu/drm/i915/intel_pm.c:4993:
+ } else
-:427: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#427: FILE: drivers/gpu/drm/i915/intel_pm.c:4995:
+ memcpy(&plane_wm->sagv_wm0, &levels[0],
+ sizeof(struct skl_wm_level));
-:490: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#490: FILE: drivers/gpu/drm/i915/intel_pm.c:5681:
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
-:496: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#496: FILE: drivers/gpu/drm/i915/intel_pm.c:5687:
+ struct skl_plane_wm *plane_wm = \
-:519: WARNING:LINE_SPACING: Missing a blank line after declarations
#519: FILE: drivers/gpu/drm/i915/intel_pm.c:5710:
+ int pipe_bit = BIT(crtc->pipe);
+ state->crtc_sagv_mask |= pipe_bit;
total: 0 errors, 4 warnings, 6 checks, 454 lines checked
1fca0e7b861d drm/i915: Restrict qgv points which don't have enough bandwidth.
-:131: CHECK:LINE_SPACING: Please don't use multiple blank lines
#131: FILE: drivers/gpu/drm/i915/display/intel_bw.c:139:
+
+
-:237: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#237: FILE: drivers/gpu/drm/i915/display/intel_bw.c:484:
+ if (!intel_can_enable_sagv(state)) {
+
-:404: CHECK:BRACES: braces {} should be used on all arms of this statement
#404: FILE: drivers/gpu/drm/i915/display/intel_display.c:14963:
+ if (INTEL_GEN(dev_priv) < 11) {
[...]
+ } else
[...]
-:407: CHECK:BRACES: Unbalanced braces around else statement
#407: FILE: drivers/gpu/drm/i915/display/intel_display.c:14966:
+ } else
total: 0 errors, 0 warnings, 4 checks, 505 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev10)
@ 2019-11-07 19:43 ` Patchwork
0 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-11-07 19:43 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev10)
URL : https://patchwork.freedesktop.org/series/68028/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a731ea6228dd drm/i915: Refactor intel_can_enable_sagv
-:191: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#191: FILE: drivers/gpu/drm/i915/intel_pm.c:3835:
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
-:271: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#271: FILE: drivers/gpu/drm/i915/intel_pm.c:3915:
+ bool state_sagv_masked = \
-:276: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#276: FILE: drivers/gpu/drm/i915/intel_pm.c:3920:
+ bool sagv_masked = \
-:311: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#311: FILE: drivers/gpu/drm/i915/intel_pm.c:4341:
+tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
+ struct skl_ddb_allocation *ddb /* out */)
-:423: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#423: FILE: drivers/gpu/drm/i915/intel_pm.c:4991:
+ skl_compute_plane_wm(crtc_state, 0, latency,
+ wm_params, &levels[0],
-:425: CHECK:BRACES: Unbalanced braces around else statement
#425: FILE: drivers/gpu/drm/i915/intel_pm.c:4993:
+ } else
-:427: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#427: FILE: drivers/gpu/drm/i915/intel_pm.c:4995:
+ memcpy(&plane_wm->sagv_wm0, &levels[0],
+ sizeof(struct skl_wm_level));
-:490: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#490: FILE: drivers/gpu/drm/i915/intel_pm.c:5681:
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
-:496: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#496: FILE: drivers/gpu/drm/i915/intel_pm.c:5687:
+ struct skl_plane_wm *plane_wm = \
-:519: WARNING:LINE_SPACING: Missing a blank line after declarations
#519: FILE: drivers/gpu/drm/i915/intel_pm.c:5710:
+ int pipe_bit = BIT(crtc->pipe);
+ state->crtc_sagv_mask |= pipe_bit;
total: 0 errors, 4 warnings, 6 checks, 454 lines checked
1fca0e7b861d drm/i915: Restrict qgv points which don't have enough bandwidth.
-:131: CHECK:LINE_SPACING: Please don't use multiple blank lines
#131: FILE: drivers/gpu/drm/i915/display/intel_bw.c:139:
+
+
-:237: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#237: FILE: drivers/gpu/drm/i915/display/intel_bw.c:484:
+ if (!intel_can_enable_sagv(state)) {
+
-:404: CHECK:BRACES: braces {} should be used on all arms of this statement
#404: FILE: drivers/gpu/drm/i915/display/intel_display.c:14963:
+ if (INTEL_GEN(dev_priv) < 11) {
[...]
+ } else
[...]
-:407: CHECK:BRACES: Unbalanced braces around else statement
#407: FILE: drivers/gpu/drm/i915/display/intel_display.c:14966:
+ } else
total: 0 errors, 0 warnings, 4 checks, 505 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✗ Fi.CI.SPARSE: warning for Refactor Gen11+ SAGV support (rev10)
@ 2019-11-07 19:44 ` Patchwork
0 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-11-07 19:44 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev10)
URL : https://patchwork.freedesktop.org/series/68028/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor Gen11+ SAGV support (rev10)
@ 2019-11-07 19:44 ` Patchwork
0 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-11-07 19:44 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev10)
URL : https://patchwork.freedesktop.org/series/68028/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✓ Fi.CI.BAT: success for Refactor Gen11+ SAGV support (rev10)
@ 2019-11-07 20:04 ` Patchwork
0 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-11-07 20:04 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev10)
URL : https://patchwork.freedesktop.org/series/68028/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7288 -> Patchwork_15178
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/index.html
Known issues
------------
Here are the changes found in Patchwork_15178 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_gem_contexts:
- fi-bsw-nick: [PASS][1] -> [INCOMPLETE][2] ([fdo# 111542])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-y: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] / [fdo#108569])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-icl-y/igt@i915_selftest@live_hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/fi-icl-y/igt@i915_selftest@live_hangcheck.html
#### Possible fixes ####
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-skl-6700k2: [INCOMPLETE][5] ([fdo#104108]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-skl-6700k2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/fi-skl-6700k2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
#### Warnings ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][7] ([fdo#111407]) -> [FAIL][8] ([fdo#111045] / [fdo#111096])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (51 -> 45)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7288 -> Patchwork_15178
CI-20190529: 20190529
CI_DRM_7288: 41eb27f39e60d822edc75e6aaeb416b72bc1dcf2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15178: 1fca0e7b861dfd3f3fe14940f5b29e9922c9d87d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1fca0e7b861d drm/i915: Restrict qgv points which don't have enough bandwidth.
a731ea6228dd drm/i915: Refactor intel_can_enable_sagv
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Refactor Gen11+ SAGV support (rev10)
@ 2019-11-07 20:04 ` Patchwork
0 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-11-07 20:04 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev10)
URL : https://patchwork.freedesktop.org/series/68028/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7288 -> Patchwork_15178
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/index.html
Known issues
------------
Here are the changes found in Patchwork_15178 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_gem_contexts:
- fi-bsw-nick: [PASS][1] -> [INCOMPLETE][2] ([fdo# 111542])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-y: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] / [fdo#108569])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-icl-y/igt@i915_selftest@live_hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/fi-icl-y/igt@i915_selftest@live_hangcheck.html
#### Possible fixes ####
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-skl-6700k2: [INCOMPLETE][5] ([fdo#104108]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-skl-6700k2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/fi-skl-6700k2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
#### Warnings ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][7] ([fdo#111407]) -> [FAIL][8] ([fdo#111045] / [fdo#111096])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (51 -> 45)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7288 -> Patchwork_15178
CI-20190529: 20190529
CI_DRM_7288: 41eb27f39e60d822edc75e6aaeb416b72bc1dcf2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5266: 60a67653613c87a69ebecf12cf00aa362ac87597 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15178: 1fca0e7b861dfd3f3fe14940f5b29e9922c9d87d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1fca0e7b861d drm/i915: Restrict qgv points which don't have enough bandwidth.
a731ea6228dd drm/i915: Refactor intel_can_enable_sagv
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✗ Fi.CI.IGT: failure for Refactor Gen11+ SAGV support (rev10)
@ 2019-11-09 1:49 ` Patchwork
0 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-11-09 1:49 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev10)
URL : https://patchwork.freedesktop.org/series/68028/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7288_full -> Patchwork_15178_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15178_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15178_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15178_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- shard-tglb: [PASS][1] -> [FAIL][2] +4 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb1/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb5/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-tglb: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb3/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
- shard-tglb: [PASS][4] -> [DMESG-FAIL][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb4/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb3/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
Known issues
------------
Here are the changes found in Patchwork_15178_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@bcs0-s3:
- shard-tglb: [PASS][6] -> [INCOMPLETE][7] ([fdo#111832]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb9/igt@gem_ctx_isolation@bcs0-s3.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb8/igt@gem_ctx_isolation@bcs0-s3.html
* igt@gem_ctx_persistence@vcs1-queued:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#109276] / [fdo#112080]) +4 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb4/igt@gem_ctx_persistence@vcs1-queued.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb6/igt@gem_ctx_persistence@vcs1-queued.html
* igt@gem_ctx_shared@q-smoketest-bsd1:
- shard-tglb: [PASS][10] -> [INCOMPLETE][11] ([fdo#111735])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb2/igt@gem_ctx_shared@q-smoketest-bsd1.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb6/igt@gem_ctx_shared@q-smoketest-bsd1.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-hsw: [PASS][12] -> [INCOMPLETE][13] ([fdo#103540])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-hsw6/igt@gem_eio@in-flight-contexts-10ms.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-hsw5/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_exec_parallel@vcs1-fds:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#112080]) +13 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb4/igt@gem_exec_parallel@vcs1-fds.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb6/igt@gem_exec_parallel@vcs1-fds.html
* igt@gem_exec_schedule@preempt-queue-chain-render:
- shard-tglb: [PASS][16] -> [INCOMPLETE][17] ([fdo#111606] / [fdo#111677])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb7/igt@gem_exec_schedule@preempt-queue-chain-render.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb6/igt@gem_exec_schedule@preempt-queue-chain-render.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [PASS][18] -> [SKIP][19] ([fdo#112146]) +5 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb3/igt@gem_exec_schedule@wide-bsd.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb1/igt@gem_exec_schedule@wide-bsd.html
* igt@gem_mmap_gtt@hang:
- shard-tglb: [PASS][20] -> [INCOMPLETE][21] ([fdo#111998])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb9/igt@gem_mmap_gtt@hang.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb6/igt@gem_mmap_gtt@hang.html
* igt@gem_persistent_relocs@forked-thrashing:
- shard-snb: [PASS][22] -> [FAIL][23] ([fdo#112037])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-snb2/igt@gem_persistent_relocs@forked-thrashing.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-snb7/igt@gem_persistent_relocs@forked-thrashing.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-snb: [PASS][24] -> [DMESG-WARN][25] ([fdo#111870])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
* igt@gem_userptr_blits@sync-unmap:
- shard-hsw: [PASS][26] -> [DMESG-WARN][27] ([fdo#111870])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-hsw6/igt@gem_userptr_blits@sync-unmap.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-hsw2/igt@gem_userptr_blits@sync-unmap.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][28] -> [FAIL][29] ([fdo#110548])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb2/igt@i915_pm_dc@dc6-psr.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
* igt@i915_selftest@live_gt_timelines:
- shard-tglb: [PASS][30] -> [INCOMPLETE][31] ([fdo#111831])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb7/igt@i915_selftest@live_gt_timelines.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb6/igt@i915_selftest@live_gt_timelines.html
* igt@kms_big_fb@linear-64bpp-rotate-180:
- shard-glk: [PASS][32] -> [DMESG-FAIL][33] ([fdo#105763] / [fdo#106538]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-glk1/igt@kms_big_fb@linear-64bpp-rotate-180.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-glk8/igt@kms_big_fb@linear-64bpp-rotate-180.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-tglb: [PASS][34] -> [FAIL][35] ([fdo#102670]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb3/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb8/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-tglb: [PASS][36] -> [INCOMPLETE][37] ([fdo#111747] / [fdo#111832] / [fdo#111850])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb9/igt@kms_fbcon_fbt@fbc-suspend.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbc-badstride:
- shard-iclb: [PASS][38] -> [FAIL][39] ([fdo#103167]) +5 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-badstride.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-badstride.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt:
- shard-tglb: [PASS][40] -> [FAIL][41] ([fdo#103167]) +4 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb9/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-skl: [PASS][42] -> [FAIL][43] ([fdo#103166])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl10/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-skl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][44] -> [FAIL][45] ([fdo#108145])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][46] -> [FAIL][47] ([fdo#108145] / [fdo#110403])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][48] -> [SKIP][49] ([fdo#109441]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
* igt@kms_psr@psr2_suspend:
- shard-tglb: [PASS][50] -> [INCOMPLETE][51] ([fdo#111832] / [fdo#111850]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb4/igt@kms_psr@psr2_suspend.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb2/igt@kms_psr@psr2_suspend.html
* igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend:
- shard-tglb: [PASS][52] -> [INCOMPLETE][53] ([fdo#111850])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb3/igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb8/igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [PASS][54] -> [SKIP][55] ([fdo#109276]) +13 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb4/igt@prime_busy@hang-bsd2.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb6/igt@prime_busy@hang-bsd2.html
* igt@prime_vgem@sync-render:
- shard-iclb: [PASS][56] -> [INCOMPLETE][57] ([fdo#107713])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb7/igt@prime_vgem@sync-render.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb5/igt@prime_vgem@sync-render.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [SKIP][58] ([fdo#109276] / [fdo#112080]) -> [PASS][59] +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb6/igt@gem_ctx_isolation@vcs1-dirty-create.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb1/igt@gem_ctx_isolation@vcs1-dirty-create.html
* igt@gem_ctx_persistence@bcs0-mixed-process:
- shard-skl: [FAIL][60] ([fdo#112194]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl8/igt@gem_ctx_persistence@bcs0-mixed-process.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-skl6/igt@gem_ctx_persistence@bcs0-mixed-process.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [SKIP][62] ([fdo#110841]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb7/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_ctx_switch@vcs1-heavy:
- shard-iclb: [SKIP][64] ([fdo#112080]) -> [PASS][65] +9 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb3/igt@gem_ctx_switch@vcs1-heavy.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb4/igt@gem_ctx_switch@vcs1-heavy.html
* igt@gem_exec_create@basic:
- shard-tglb: [INCOMPLETE][66] ([fdo#111736]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb6/igt@gem_exec_create@basic.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb3/igt@gem_exec_create@basic.html
* igt@gem_exec_schedule@preempt-queue-contexts-blt:
- shard-tglb: [INCOMPLETE][68] ([fdo#111606] / [fdo#111677]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-blt.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb4/igt@gem_exec_schedule@preempt-queue-contexts-blt.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [SKIP][70] ([fdo#112146]) -> [PASS][71] +4 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb1/igt@gem_exec_schedule@reorder-wide-bsd.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb7/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-hsw: [DMESG-WARN][72] ([fdo#111870]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-hsw8/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-hsw8/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
* igt@gem_workarounds@suspend-resume:
- shard-kbl: [DMESG-WARN][74] ([fdo#103313]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-kbl4/igt@gem_workarounds@suspend-resume.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-kbl3/igt@gem_workarounds@suspend-resume.html
* igt@i915_pm_rpm@system-suspend:
- shard-tglb: [INCOMPLETE][76] ([fdo#111747] / [fdo#111850]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb3/igt@i915_pm_rpm@system-suspend.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb8/igt@i915_pm_rpm@system-suspend.html
* igt@i915_selftest@live_hangcheck:
- shard-snb: [INCOMPLETE][78] ([fdo#105411]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-snb4/igt@i915_selftest@live_hangcheck.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-snb1/igt@i915_selftest@live_hangcheck.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][80] ([fdo#108566]) -> [PASS][81] +2 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-apl6/igt@i915_suspend@sysfs-reader.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-apl8/igt@i915_suspend@sysfs-reader.html
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-hsw: [DMESG-WARN][82] ([fdo#102614]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-hsw5/igt@kms_atomic_transition@plane-all-modeset-transition.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-hsw4/igt@kms_atomic_transition@plane-all-modeset-transition.html
* igt@kms_color@pipe-a-gamma:
- shard-skl: [FAIL][84] ([fdo#104782]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl4/igt@kms_color@pipe-a-gamma.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-skl4/igt@kms_color@pipe-a-gamma.html
* igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen:
- shard-skl: [FAIL][86] ([fdo#103232]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled:
- shard-skl: [FAIL][88] ([fdo#103184] / [fdo#103232]) -> [PASS][89] +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl4/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-skl4/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt:
- shard-tglb: [FAIL][90] ([fdo#103167]) -> [PASS][91] +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [DMESG-WARN][92] ([fdo#108566]) -> [PASS][93] +9 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: [FAIL][94] ([fdo#103167]) -> [PASS][95] +4 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
- shard-skl: [FAIL][96] ([fdo#103167]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- shard-skl: [FAIL][98] ([fdo#103191]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl4/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-skl4/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][100] ([fdo#108145]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [SKIP][102] ([fdo#109642] / [fdo#111068]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb7/igt@kms_psr2_su@page_flip.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb2/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_primary_page_flip:
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Refactor Gen11+ SAGV support (rev10)
@ 2019-11-09 1:49 ` Patchwork
0 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-11-09 1:49 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev10)
URL : https://patchwork.freedesktop.org/series/68028/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7288_full -> Patchwork_15178_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15178_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15178_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15178_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- shard-tglb: [PASS][1] -> [FAIL][2] +4 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb1/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb5/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-tglb: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb3/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
- shard-tglb: [PASS][4] -> [DMESG-FAIL][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb4/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb3/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
Known issues
------------
Here are the changes found in Patchwork_15178_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@bcs0-s3:
- shard-tglb: [PASS][6] -> [INCOMPLETE][7] ([fdo#111832]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb9/igt@gem_ctx_isolation@bcs0-s3.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb8/igt@gem_ctx_isolation@bcs0-s3.html
* igt@gem_ctx_persistence@vcs1-queued:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#109276] / [fdo#112080]) +4 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb4/igt@gem_ctx_persistence@vcs1-queued.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb6/igt@gem_ctx_persistence@vcs1-queued.html
* igt@gem_ctx_shared@q-smoketest-bsd1:
- shard-tglb: [PASS][10] -> [INCOMPLETE][11] ([fdo#111735])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb2/igt@gem_ctx_shared@q-smoketest-bsd1.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb6/igt@gem_ctx_shared@q-smoketest-bsd1.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-hsw: [PASS][12] -> [INCOMPLETE][13] ([fdo#103540])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-hsw6/igt@gem_eio@in-flight-contexts-10ms.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-hsw5/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_exec_parallel@vcs1-fds:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#112080]) +13 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb4/igt@gem_exec_parallel@vcs1-fds.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb6/igt@gem_exec_parallel@vcs1-fds.html
* igt@gem_exec_schedule@preempt-queue-chain-render:
- shard-tglb: [PASS][16] -> [INCOMPLETE][17] ([fdo#111606] / [fdo#111677])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb7/igt@gem_exec_schedule@preempt-queue-chain-render.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb6/igt@gem_exec_schedule@preempt-queue-chain-render.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [PASS][18] -> [SKIP][19] ([fdo#112146]) +5 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb3/igt@gem_exec_schedule@wide-bsd.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb1/igt@gem_exec_schedule@wide-bsd.html
* igt@gem_mmap_gtt@hang:
- shard-tglb: [PASS][20] -> [INCOMPLETE][21] ([fdo#111998])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb9/igt@gem_mmap_gtt@hang.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb6/igt@gem_mmap_gtt@hang.html
* igt@gem_persistent_relocs@forked-thrashing:
- shard-snb: [PASS][22] -> [FAIL][23] ([fdo#112037])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-snb2/igt@gem_persistent_relocs@forked-thrashing.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-snb7/igt@gem_persistent_relocs@forked-thrashing.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-snb: [PASS][24] -> [DMESG-WARN][25] ([fdo#111870])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
* igt@gem_userptr_blits@sync-unmap:
- shard-hsw: [PASS][26] -> [DMESG-WARN][27] ([fdo#111870])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-hsw6/igt@gem_userptr_blits@sync-unmap.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-hsw2/igt@gem_userptr_blits@sync-unmap.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][28] -> [FAIL][29] ([fdo#110548])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb2/igt@i915_pm_dc@dc6-psr.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
* igt@i915_selftest@live_gt_timelines:
- shard-tglb: [PASS][30] -> [INCOMPLETE][31] ([fdo#111831])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb7/igt@i915_selftest@live_gt_timelines.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb6/igt@i915_selftest@live_gt_timelines.html
* igt@kms_big_fb@linear-64bpp-rotate-180:
- shard-glk: [PASS][32] -> [DMESG-FAIL][33] ([fdo#105763] / [fdo#106538]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-glk1/igt@kms_big_fb@linear-64bpp-rotate-180.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-glk8/igt@kms_big_fb@linear-64bpp-rotate-180.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-tglb: [PASS][34] -> [FAIL][35] ([fdo#102670]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb3/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb8/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-tglb: [PASS][36] -> [INCOMPLETE][37] ([fdo#111747] / [fdo#111832] / [fdo#111850])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb9/igt@kms_fbcon_fbt@fbc-suspend.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbc-badstride:
- shard-iclb: [PASS][38] -> [FAIL][39] ([fdo#103167]) +5 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-badstride.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-badstride.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt:
- shard-tglb: [PASS][40] -> [FAIL][41] ([fdo#103167]) +4 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb9/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-skl: [PASS][42] -> [FAIL][43] ([fdo#103166])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl10/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-skl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][44] -> [FAIL][45] ([fdo#108145])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][46] -> [FAIL][47] ([fdo#108145] / [fdo#110403])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][48] -> [SKIP][49] ([fdo#109441]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
* igt@kms_psr@psr2_suspend:
- shard-tglb: [PASS][50] -> [INCOMPLETE][51] ([fdo#111832] / [fdo#111850]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb4/igt@kms_psr@psr2_suspend.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb2/igt@kms_psr@psr2_suspend.html
* igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend:
- shard-tglb: [PASS][52] -> [INCOMPLETE][53] ([fdo#111850])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb3/igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb8/igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [PASS][54] -> [SKIP][55] ([fdo#109276]) +13 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb4/igt@prime_busy@hang-bsd2.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb6/igt@prime_busy@hang-bsd2.html
* igt@prime_vgem@sync-render:
- shard-iclb: [PASS][56] -> [INCOMPLETE][57] ([fdo#107713])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb7/igt@prime_vgem@sync-render.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb5/igt@prime_vgem@sync-render.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [SKIP][58] ([fdo#109276] / [fdo#112080]) -> [PASS][59] +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb6/igt@gem_ctx_isolation@vcs1-dirty-create.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb1/igt@gem_ctx_isolation@vcs1-dirty-create.html
* igt@gem_ctx_persistence@bcs0-mixed-process:
- shard-skl: [FAIL][60] ([fdo#112194]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl8/igt@gem_ctx_persistence@bcs0-mixed-process.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-skl6/igt@gem_ctx_persistence@bcs0-mixed-process.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [SKIP][62] ([fdo#110841]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb7/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_ctx_switch@vcs1-heavy:
- shard-iclb: [SKIP][64] ([fdo#112080]) -> [PASS][65] +9 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb3/igt@gem_ctx_switch@vcs1-heavy.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb4/igt@gem_ctx_switch@vcs1-heavy.html
* igt@gem_exec_create@basic:
- shard-tglb: [INCOMPLETE][66] ([fdo#111736]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb6/igt@gem_exec_create@basic.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb3/igt@gem_exec_create@basic.html
* igt@gem_exec_schedule@preempt-queue-contexts-blt:
- shard-tglb: [INCOMPLETE][68] ([fdo#111606] / [fdo#111677]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-blt.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb4/igt@gem_exec_schedule@preempt-queue-contexts-blt.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [SKIP][70] ([fdo#112146]) -> [PASS][71] +4 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb1/igt@gem_exec_schedule@reorder-wide-bsd.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb7/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-hsw: [DMESG-WARN][72] ([fdo#111870]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-hsw8/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-hsw8/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
* igt@gem_workarounds@suspend-resume:
- shard-kbl: [DMESG-WARN][74] ([fdo#103313]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-kbl4/igt@gem_workarounds@suspend-resume.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-kbl3/igt@gem_workarounds@suspend-resume.html
* igt@i915_pm_rpm@system-suspend:
- shard-tglb: [INCOMPLETE][76] ([fdo#111747] / [fdo#111850]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb3/igt@i915_pm_rpm@system-suspend.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb8/igt@i915_pm_rpm@system-suspend.html
* igt@i915_selftest@live_hangcheck:
- shard-snb: [INCOMPLETE][78] ([fdo#105411]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-snb4/igt@i915_selftest@live_hangcheck.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-snb1/igt@i915_selftest@live_hangcheck.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][80] ([fdo#108566]) -> [PASS][81] +2 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-apl6/igt@i915_suspend@sysfs-reader.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-apl8/igt@i915_suspend@sysfs-reader.html
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-hsw: [DMESG-WARN][82] ([fdo#102614]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-hsw5/igt@kms_atomic_transition@plane-all-modeset-transition.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-hsw4/igt@kms_atomic_transition@plane-all-modeset-transition.html
* igt@kms_color@pipe-a-gamma:
- shard-skl: [FAIL][84] ([fdo#104782]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl4/igt@kms_color@pipe-a-gamma.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-skl4/igt@kms_color@pipe-a-gamma.html
* igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen:
- shard-skl: [FAIL][86] ([fdo#103232]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled:
- shard-skl: [FAIL][88] ([fdo#103184] / [fdo#103232]) -> [PASS][89] +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl4/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-skl4/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt:
- shard-tglb: [FAIL][90] ([fdo#103167]) -> [PASS][91] +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [DMESG-WARN][92] ([fdo#108566]) -> [PASS][93] +9 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: [FAIL][94] ([fdo#103167]) -> [PASS][95] +4 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
- shard-skl: [FAIL][96] ([fdo#103167]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- shard-skl: [FAIL][98] ([fdo#103191]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl4/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-skl4/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][100] ([fdo#108145]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [SKIP][102] ([fdo#109642] / [fdo#111068]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7288/shard-iclb7/igt@kms_psr2_su@page_flip.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/shard-iclb2/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_primary_page_flip:
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15178/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v10 1/2] drm/i915: Refactor intel_can_enable_sagv
@ 2019-11-12 0:15 ` Matt Roper
0 siblings, 0 replies; 25+ messages in thread
From: Matt Roper @ 2019-11-12 0:15 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Thu, Nov 07, 2019 at 05:30:36PM +0200, Stanislav Lisovskiy wrote:
> Currently intel_can_enable_sagv function contains
> a mix of workarounds for different platforms
> some of them are not valid for gens >= 11 already,
> so lets split it into separate functions.
>
> v2:
> - Rework watermark calculation algorithm to
> attempt to calculate Level 0 watermark
> with added sagv block time latency and
> check if it fits in DBuf in order to
> determine if SAGV can be enabled already
> at this stage, just as BSpec 49325 states.
> if that fails rollback to usual Level 0
> latency and disable SAGV.
> - Remove unneeded tabs(James Ausmus)
>
> v3: Rebased the patch
>
> v4: - Added back interlaced check for Gen12 and
> added separate function for TGL SAGV check
> (thanks to James Ausmus for spotting)
> - Removed unneeded gen check
> - Extracted Gen12 SAGV decision making code
> to a separate function from skl_compute_wm
>
> v5: - Added SAGV global state to dev_priv, because
> we need to track all pipes, not only those
> in atomic state. Each pipe has now correspondent
> bit mask reflecting, whether it can tolerate
> SAGV or not(thanks to Ville Syrjala for suggestions).
> - Now using active flag instead of enable in crc
> usage check.
>
> v6: - Fixed rebase conflicts
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 +
> .../drm/i915/display/intel_display_types.h | 9 +
> drivers/gpu/drm/i915/i915_drv.h | 6 +
> drivers/gpu/drm/i915/intel_pm.c | 296 +++++++++++++++++-
> 4 files changed, 303 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 876fc25968bf..7ea1e7518ab6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14855,6 +14855,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> if (dev_priv->display.optimize_watermarks)
> dev_priv->display.optimize_watermarks(state,
> new_crtc_state);
> + if (state->crtc_sagv_mask & BIT(crtc->pipe))
> + dev_priv->crtc_sagv_mask |= BIT(crtc->pipe);
> + else
> + dev_priv->crtc_sagv_mask &= ~BIT(crtc->pipe);
> }
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index fadd9853f966..fb274538af23 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -490,6 +490,14 @@ struct intel_atomic_state {
> */
> u8 active_pipe_changes;
>
> + /*
> + * Contains a mask which reflects whether correspondent pipe
> + * can tolerate SAGV or not, so that we can make a decision
> + * at atomic_commit_tail stage, whether we enable it or not
> + * based on global state in dev_priv.
> + */
> + u32 crtc_sagv_mask;
> +
> u8 active_pipes;
> /* minimum acceptable cdclk for each pipe */
> int min_cdclk[I915_MAX_PIPES];
> @@ -670,6 +678,7 @@ struct skl_plane_wm {
> struct skl_wm_level wm[8];
> struct skl_wm_level uv_wm[8];
> struct skl_wm_level trans_wm;
> + struct skl_wm_level sagv_wm0;
> bool is_planar;
> };
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7e0f67babe20..4f4e2e839513 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1176,6 +1176,12 @@ struct drm_i915_private {
>
> u32 sagv_block_time_us;
>
> + /*
> + * Contains a bit mask, whether correspondent
> + * pipe allows SAGV or not.
> + */
> + u32 crtc_sagv_mask;
> +
> struct {
> /*
> * Raw watermark latency values:
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2d389e437e87..c792dd168742 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3740,7 +3740,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> return 0;
> }
>
> -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +static void skl_set_sagv_mask(struct intel_atomic_state *state)
> {
> struct drm_device *dev = state->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -3750,21 +3750,23 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> enum pipe pipe;
> int level, latency;
>
> + state->crtc_sagv_mask = 0;
> +
> if (!intel_has_sagv(dev_priv))
> - return false;
> + return;
>
> /*
> * If there are no active CRTCs, no additional checks need be performed
> */
> if (hweight8(state->active_pipes) == 0)
> - return true;
> + return;
>
> /*
> * SKL+ workaround: bspec recommends we disable SAGV when we have
> * more then one pipe enabled
> */
> if (hweight8(state->active_pipes) > 1)
> - return false;
> + return;
>
> /* Since we're now guaranteed to only have one active CRTC... */
> pipe = ffs(state->active_pipes) - 1;
> @@ -3772,7 +3774,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> crtc_state = to_intel_crtc_state(crtc->base.state);
>
> if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> - return false;
> + return;
>
> for_each_intel_plane_on_crtc(dev, crtc, plane) {
> struct skl_plane_wm *wm =
> @@ -3800,9 +3802,127 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> * can't enable SAGV.
> */
> if (latency < dev_priv->sagv_block_time_us)
> - return false;
> + return;
> }
>
> + state->crtc_sagv_mask |= BIT(crtc->pipe);
> +}
> +
> +static void tgl_set_sagv_mask(struct intel_atomic_state *state);
> +
> +static void icl_set_sagv_mask(struct intel_atomic_state *state)
> +{
> + struct drm_device *dev = state->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *new_crtc_state;
> + int level, latency;
> + int i;
> + int plane_id;
> +
> + state->crtc_sagv_mask = 0;
> +
> + if (!intel_has_sagv(dev_priv))
> + return;
> +
> + /*
> + * If there are no active CRTCs, no additional checks need be performed
> + */
> + if (hweight8(state->active_pipes) == 0)
> + return;
> +
> + for_each_new_intel_crtc_in_state(state, crtc,
> + new_crtc_state, i) {
> + unsigned int flags = crtc->base.state->adjusted_mode.flags;
> + bool can_sagv;
> +
> + if (flags & DRM_MODE_FLAG_INTERLACE)
> + continue;
> +
> + if (!new_crtc_state->base.active)
> + continue;
> +
> + can_sagv = true;
> + for_each_plane_id_on_crtc(crtc, plane_id) {
> + struct skl_plane_wm *wm =
> + &new_crtc_state->wm.skl.optimal.planes[plane_id];
> +
> + /* Skip this plane if it's not enabled */
> + if (!wm->wm[0].plane_en)
> + continue;
> +
> + /* Find the highest enabled wm level for this plane */
> + for (level = ilk_wm_max_level(dev_priv);
> + !wm->wm[level].plane_en; --level) {
> + }
> +
> + latency = dev_priv->wm.skl_latency[level];
> +
> + /*
> + * If any of the planes on this pipe don't enable
> + * wm levels that incur memory latencies higher than
> + * sagv_block_time_us we can't enable SAGV.
> + */
> + if (latency < dev_priv->sagv_block_time_us) {
> + can_sagv = false;
> + break;
> + }
I find the wording of the bspec ("if any enabled plane will not be able
to enable watermarks for memory latency >= SAGV block time") in this
area somewhat ambiguous. To me that wording sounds like they want us to
calculate the watermarks one more time, but using the SAGV blocking time
rather than any of the 8 latency values we received from the pcode ---
if the calculated watermark value for that "sagv level" fits within the
DDB allocation then we can enable SAGV, otherwise we can't.
Your approach here somewhat approximates that. If the highest watermark
level we enabled had a latency higher than the SAGV blocking time, then
we automatically know we also would have had a valid watermark value for
a lower sagv latency. But if the highest latency we enabled has a lower
latency, we can't say for certain whether the SAGV's blocking time would
have led to valid or invalid watermarks. If the first watermark level
we failed on also had a lower latency than the SAGV time then we can
conclude that the SAGV can't be enabled. But if the next level up had a
latency higher than the blocking time (i.e., good < SAGV < bad), we
can't really tell whether SAGV was possible without actually doing the
extra watermark calculation.
But even given the above, the bspec suggestion seems somewhat surprising
to me. Intuitively it seems like SAGV would be introducing an
additional delay on top of the existing memory fetch latency, not
replacing the latency entirely. Intuitively the algorithm suggested for
TGL makes sense to me (i.e., add the SAGV's extra delay to the WM0
latency to ensure that regular latency plus an extra SAGV delay doesn't
lead us to run dry), but that's not what the bspec calls for on ICL.
I'm not really sure whether that's truly an intentional behavior change
between platforms or whether the TGL bspec section does just a better
job of explaining what was supposed to be done and clarifying the
language.
Anyway, we should probably trust the bspec for now, so it seems to me
like we should add a "fake" watermark level associated with the SAGV
block time and explicitly calculate that as enabled/disabled anytime we
have a good < SAGV < bad situation.
> + }
> + if (can_sagv)
> + state->crtc_sagv_mask |= BIT(crtc->pipe);
> + }
> +}
> +
> +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +{
> + struct drm_device *dev = state->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + enum pipe pipe;
> +
> + if (INTEL_GEN(dev_priv) >= 12)
> + tgl_set_sagv_mask(state);
> + else if (INTEL_GEN(dev_priv) == 11)
> + icl_set_sagv_mask(state);
> + else
> + skl_set_sagv_mask(state);
> +
> + /*
> + * For SAGV we need to account all the pipes,
> + * not only the ones which are in state currently.
> + */
> + for_each_pipe(dev_priv, pipe) {
> + unsigned int active_pipes;
> + /*
> + * Figure out if we are changing active pipes here
> + * then after commit dev_priv->active_pipes will
> + * anyway be assigned to state->active_pipes.
> + */
> + if (state->active_pipe_changes)
> + active_pipes = state->active_pipes;
> + else
> + active_pipes = dev_priv->active_pipes;
> +
> + /* Skip if pipe is inactive */
> + if (!(BIT(pipe) & active_pipes))
> + continue;
> +
> + /*
> + * Pipe can be active in this state or in dev_priv
> + * as we haven't committed thise changes yet(and we shouldn't)
> + * - we need to check both.
> + */
> + if (state->active_pipe_changes & BIT(pipe)) {
> + bool state_sagv_masked = \
> + (BIT(pipe) & state->crtc_sagv_mask) == 0;
> + if (state_sagv_masked)
> + return false;
> + } else {
> + bool sagv_masked = \
> + (BIT(pipe) & dev_priv->crtc_sagv_mask) == 0;
If we're not changing which pipes are active, then we didn't globally
lock everything at the beginning of this atomic transaction; we can have
racing commits against different CRTC's. So when you look at
dev_priv->crtc_sagv_mask here, the value might change immediately
afterward if a commit on a different CRTC completed in the meantime.
I don't think we want to look at other CRTC's outside our current
transaction here. We should just figure out whether our own CRTC's are
okay with SAGV or not. Then in the commit phase we'd need to grab some
kind of SAGV lock, combine our local "SAGV okay" with the global "SAGV
okay" and enable/disable as necessary.
Some kind of reference-counting mechanism might make this simpler...is
there any way we could tie this in with power domains (e.g., adding a
"SAGV off" power domain and power well that we grab during commit when
we've calculated that our own crtcs can't cope with SAGV latency)?
> + if (sagv_masked)
> + return false;
> + }
> + }
> return true;
> }
>
> @@ -3925,6 +4045,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> int color_plane);
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> int level,
> + u32 latency,
> const struct skl_wm_params *wp,
> const struct skl_wm_level *result_prev,
> struct skl_wm_level *result /* out */);
> @@ -3947,7 +4068,10 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
> WARN_ON(ret);
>
> for (level = 0; level <= max_level; level++) {
> - skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
> + u32 latency = dev_priv->wm.skl_latency[level];
> +
> + skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
> +
> if (wm.min_ddb_alloc == U16_MAX)
> break;
>
> @@ -4212,6 +4336,68 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
> return total_data_rate;
> }
>
> +static int
> +tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
> + struct skl_ddb_allocation *ddb /* out */)
> +{
> + struct drm_crtc *crtc = crtc_state->base.crtc;
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
> + u16 alloc_size;
> + u16 total[I915_MAX_PLANES] = {};
> + u64 total_data_rate;
> + enum plane_id plane_id;
> + int num_active;
> + u64 plane_data_rate[I915_MAX_PLANES] = {};
> + u32 blocks;
> +
> + /*
> + * No need to check gen here, we call this only for gen12
> + */
> + total_data_rate =
> + icl_get_total_relative_data_rate(crtc_state,
> + plane_data_rate);
> +
> + skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
> + total_data_rate,
> + ddb, alloc, &num_active);
> + alloc_size = skl_ddb_entry_size(alloc);
> + if (alloc_size == 0)
> + return -ENOSPC;
> +
> + /* Allocate fixed number of blocks for cursor. */
> + total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
> + alloc_size -= total[PLANE_CURSOR];
> + crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
> + alloc->end - total[PLANE_CURSOR];
> + crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
> +
> + /*
> + * Do check if we can fit L0 + sagv_block_time and
> + * disable SAGV if we can't.
> + */
> + blocks = 0;
> + for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> + const struct skl_plane_wm *wm =
> + &crtc_state->wm.skl.optimal.planes[plane_id];
> +
> + if (plane_id == PLANE_CURSOR) {
> + if (WARN_ON(wm->sagv_wm0.min_ddb_alloc >
> + total[PLANE_CURSOR])) {
> + blocks = U32_MAX;
> + break;
> + }
> + continue;
> + }
> +
> + blocks += wm->sagv_wm0.min_ddb_alloc;
> + if (blocks > alloc_size)
> + return -ENOSPC;
> + }
> + return 0;
> +}
> +
> static int
> skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
> struct skl_ddb_allocation *ddb /* out */)
> @@ -4641,6 +4827,7 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
>
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> int level,
> + u32 latency,
> const struct skl_wm_params *wp,
> const struct skl_wm_level *result_prev,
> struct skl_wm_level *result /* out */)
It doesn't look like this latency parameter gets used (it gets masked by
a local latency variable still.
> @@ -4767,20 +4954,45 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> static void
> skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> const struct skl_wm_params *wm_params,
> - struct skl_wm_level *levels)
> + struct skl_plane_wm *plane_wm,
> + bool yuv)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> int level, max_level = ilk_wm_max_level(dev_priv);
> + /*
> + * Check which kind of plane is it and based on that calculate
> + * correspondent WM levels.
> + */
> + struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm;
> struct skl_wm_level *result_prev = &levels[0];
>
> for (level = 0; level <= max_level; level++) {
> struct skl_wm_level *result = &levels[level];
> + u32 latency = dev_priv->wm.skl_latency[level];
>
> - skl_compute_plane_wm(crtc_state, level, wm_params,
> - result_prev, result);
> + skl_compute_plane_wm(crtc_state, level, latency,
> + wm_params, result_prev, result);
>
> result_prev = result;
> }
> + /*
> + * For Gen12 if it is an L0 we need to also
> + * consider sagv_block_time when calculating
> + * L0 watermark - we will need that when making
> + * a decision whether enable SAGV or not.
> + * For older gens we agreed to copy L0 value for
> + * compatibility.
> + */
> + if ((INTEL_GEN(dev_priv) >= 12)) {
> + u32 latency = dev_priv->wm.skl_latency[0];
> +
> + latency += dev_priv->sagv_block_time_us;
> + skl_compute_plane_wm(crtc_state, 0, latency,
> + wm_params, &levels[0],
> + &plane_wm->sagv_wm0);
> + } else
> + memcpy(&plane_wm->sagv_wm0, &levels[0],
> + sizeof(struct skl_wm_level));
> }
>
> static u32
> @@ -4873,7 +5085,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> - skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> + skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
> skl_compute_transition_wm(crtc_state, &wm_params, wm);
>
> return 0;
> @@ -4895,7 +5107,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> - skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
> + skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
>
> return 0;
> }
> @@ -5167,6 +5379,8 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
> return 0;
> }
>
> +static void tgl_set_sagv_wm0(struct intel_atomic_state *state);
> +
> static int
> skl_compute_ddb(struct intel_atomic_state *state)
> {
> @@ -5177,6 +5391,11 @@ skl_compute_ddb(struct intel_atomic_state *state)
> struct intel_crtc *crtc;
> int ret, i;
>
> + /* For Gen12+ for SAGV we have a special L0 wm values */
> + if (INTEL_GEN(dev_priv) >= 12)
> + if (intel_can_enable_sagv(state))
> + tgl_set_sagv_wm0(state);
> +
> memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> @@ -5443,6 +5662,56 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
> return 0;
> }
>
> +void tgl_set_sagv_wm0(struct intel_atomic_state *state)
> +{
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *new_crtc_state;
> + struct intel_crtc_state *old_crtc_state;
> + struct drm_device *dev = state->base.dev;
> + const struct drm_i915_private *dev_priv = to_i915(dev);
> + int i;
> +
> + /*
> + * If we determined that we can actually enable SAGV, then
> + * actually use those levels tgl_check_pipe_fits_sagv_wm
> + * has already taken care of checking if L0 + sagv block time
> + * fits into ddb.
> + */
> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> + new_crtc_state, i) {
> + struct intel_plane *plane;
> +
> + for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> + enum plane_id plane_id = plane->id;
> +
> + struct skl_plane_wm *plane_wm = \
> + &new_crtc_state->wm.skl.optimal.planes[plane_id];
> + struct skl_wm_level *sagv_wm0 = &plane_wm->sagv_wm0;
> + struct skl_wm_level *l0_wm0 = &plane_wm->wm[0];
> +
> + memcpy(l0_wm0, sagv_wm0, sizeof(struct skl_wm_level));
> + }
> + }
> +}
> +
> +static void tgl_set_sagv_mask(struct intel_atomic_state *state)
> +{
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *new_crtc_state;
> + struct intel_crtc_state *old_crtc_state;
> + struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
> + int ret, i;
> +
> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> + new_crtc_state, i) {
> + ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
> + if (!ret) {
> + int pipe_bit = BIT(crtc->pipe);
> + state->crtc_sagv_mask |= pipe_bit;
> + }
> + }
> +}
> +
> static int
> skl_compute_wm(struct intel_atomic_state *state)
> {
> @@ -5455,6 +5724,9 @@ skl_compute_wm(struct intel_atomic_state *state)
> /* Clear all dirty flags */
> results->dirty_pipes = 0;
>
> + /* If we exit before check is done */
> + state->crtc_sagv_mask = 0;
> +
> ret = skl_ddb_add_affected_pipes(state);
> if (ret)
> return ret;
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH v10 1/2] drm/i915: Refactor intel_can_enable_sagv
@ 2019-11-12 0:15 ` Matt Roper
0 siblings, 0 replies; 25+ messages in thread
From: Matt Roper @ 2019-11-12 0:15 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Thu, Nov 07, 2019 at 05:30:36PM +0200, Stanislav Lisovskiy wrote:
> Currently intel_can_enable_sagv function contains
> a mix of workarounds for different platforms
> some of them are not valid for gens >= 11 already,
> so lets split it into separate functions.
>
> v2:
> - Rework watermark calculation algorithm to
> attempt to calculate Level 0 watermark
> with added sagv block time latency and
> check if it fits in DBuf in order to
> determine if SAGV can be enabled already
> at this stage, just as BSpec 49325 states.
> if that fails rollback to usual Level 0
> latency and disable SAGV.
> - Remove unneeded tabs(James Ausmus)
>
> v3: Rebased the patch
>
> v4: - Added back interlaced check for Gen12 and
> added separate function for TGL SAGV check
> (thanks to James Ausmus for spotting)
> - Removed unneeded gen check
> - Extracted Gen12 SAGV decision making code
> to a separate function from skl_compute_wm
>
> v5: - Added SAGV global state to dev_priv, because
> we need to track all pipes, not only those
> in atomic state. Each pipe has now correspondent
> bit mask reflecting, whether it can tolerate
> SAGV or not(thanks to Ville Syrjala for suggestions).
> - Now using active flag instead of enable in crc
> usage check.
>
> v6: - Fixed rebase conflicts
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 +
> .../drm/i915/display/intel_display_types.h | 9 +
> drivers/gpu/drm/i915/i915_drv.h | 6 +
> drivers/gpu/drm/i915/intel_pm.c | 296 +++++++++++++++++-
> 4 files changed, 303 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 876fc25968bf..7ea1e7518ab6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14855,6 +14855,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> if (dev_priv->display.optimize_watermarks)
> dev_priv->display.optimize_watermarks(state,
> new_crtc_state);
> + if (state->crtc_sagv_mask & BIT(crtc->pipe))
> + dev_priv->crtc_sagv_mask |= BIT(crtc->pipe);
> + else
> + dev_priv->crtc_sagv_mask &= ~BIT(crtc->pipe);
> }
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index fadd9853f966..fb274538af23 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -490,6 +490,14 @@ struct intel_atomic_state {
> */
> u8 active_pipe_changes;
>
> + /*
> + * Contains a mask which reflects whether correspondent pipe
> + * can tolerate SAGV or not, so that we can make a decision
> + * at atomic_commit_tail stage, whether we enable it or not
> + * based on global state in dev_priv.
> + */
> + u32 crtc_sagv_mask;
> +
> u8 active_pipes;
> /* minimum acceptable cdclk for each pipe */
> int min_cdclk[I915_MAX_PIPES];
> @@ -670,6 +678,7 @@ struct skl_plane_wm {
> struct skl_wm_level wm[8];
> struct skl_wm_level uv_wm[8];
> struct skl_wm_level trans_wm;
> + struct skl_wm_level sagv_wm0;
> bool is_planar;
> };
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7e0f67babe20..4f4e2e839513 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1176,6 +1176,12 @@ struct drm_i915_private {
>
> u32 sagv_block_time_us;
>
> + /*
> + * Contains a bit mask, whether correspondent
> + * pipe allows SAGV or not.
> + */
> + u32 crtc_sagv_mask;
> +
> struct {
> /*
> * Raw watermark latency values:
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2d389e437e87..c792dd168742 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3740,7 +3740,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> return 0;
> }
>
> -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +static void skl_set_sagv_mask(struct intel_atomic_state *state)
> {
> struct drm_device *dev = state->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -3750,21 +3750,23 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> enum pipe pipe;
> int level, latency;
>
> + state->crtc_sagv_mask = 0;
> +
> if (!intel_has_sagv(dev_priv))
> - return false;
> + return;
>
> /*
> * If there are no active CRTCs, no additional checks need be performed
> */
> if (hweight8(state->active_pipes) == 0)
> - return true;
> + return;
>
> /*
> * SKL+ workaround: bspec recommends we disable SAGV when we have
> * more then one pipe enabled
> */
> if (hweight8(state->active_pipes) > 1)
> - return false;
> + return;
>
> /* Since we're now guaranteed to only have one active CRTC... */
> pipe = ffs(state->active_pipes) - 1;
> @@ -3772,7 +3774,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> crtc_state = to_intel_crtc_state(crtc->base.state);
>
> if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> - return false;
> + return;
>
> for_each_intel_plane_on_crtc(dev, crtc, plane) {
> struct skl_plane_wm *wm =
> @@ -3800,9 +3802,127 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> * can't enable SAGV.
> */
> if (latency < dev_priv->sagv_block_time_us)
> - return false;
> + return;
> }
>
> + state->crtc_sagv_mask |= BIT(crtc->pipe);
> +}
> +
> +static void tgl_set_sagv_mask(struct intel_atomic_state *state);
> +
> +static void icl_set_sagv_mask(struct intel_atomic_state *state)
> +{
> + struct drm_device *dev = state->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *new_crtc_state;
> + int level, latency;
> + int i;
> + int plane_id;
> +
> + state->crtc_sagv_mask = 0;
> +
> + if (!intel_has_sagv(dev_priv))
> + return;
> +
> + /*
> + * If there are no active CRTCs, no additional checks need be performed
> + */
> + if (hweight8(state->active_pipes) == 0)
> + return;
> +
> + for_each_new_intel_crtc_in_state(state, crtc,
> + new_crtc_state, i) {
> + unsigned int flags = crtc->base.state->adjusted_mode.flags;
> + bool can_sagv;
> +
> + if (flags & DRM_MODE_FLAG_INTERLACE)
> + continue;
> +
> + if (!new_crtc_state->base.active)
> + continue;
> +
> + can_sagv = true;
> + for_each_plane_id_on_crtc(crtc, plane_id) {
> + struct skl_plane_wm *wm =
> + &new_crtc_state->wm.skl.optimal.planes[plane_id];
> +
> + /* Skip this plane if it's not enabled */
> + if (!wm->wm[0].plane_en)
> + continue;
> +
> + /* Find the highest enabled wm level for this plane */
> + for (level = ilk_wm_max_level(dev_priv);
> + !wm->wm[level].plane_en; --level) {
> + }
> +
> + latency = dev_priv->wm.skl_latency[level];
> +
> + /*
> + * If any of the planes on this pipe don't enable
> + * wm levels that incur memory latencies higher than
> + * sagv_block_time_us we can't enable SAGV.
> + */
> + if (latency < dev_priv->sagv_block_time_us) {
> + can_sagv = false;
> + break;
> + }
I find the wording of the bspec ("if any enabled plane will not be able
to enable watermarks for memory latency >= SAGV block time") in this
area somewhat ambiguous. To me that wording sounds like they want us to
calculate the watermarks one more time, but using the SAGV blocking time
rather than any of the 8 latency values we received from the pcode ---
if the calculated watermark value for that "sagv level" fits within the
DDB allocation then we can enable SAGV, otherwise we can't.
Your approach here somewhat approximates that. If the highest watermark
level we enabled had a latency higher than the SAGV blocking time, then
we automatically know we also would have had a valid watermark value for
a lower sagv latency. But if the highest latency we enabled has a lower
latency, we can't say for certain whether the SAGV's blocking time would
have led to valid or invalid watermarks. If the first watermark level
we failed on also had a lower latency than the SAGV time then we can
conclude that the SAGV can't be enabled. But if the next level up had a
latency higher than the blocking time (i.e., good < SAGV < bad), we
can't really tell whether SAGV was possible without actually doing the
extra watermark calculation.
But even given the above, the bspec suggestion seems somewhat surprising
to me. Intuitively it seems like SAGV would be introducing an
additional delay on top of the existing memory fetch latency, not
replacing the latency entirely. Intuitively the algorithm suggested for
TGL makes sense to me (i.e., add the SAGV's extra delay to the WM0
latency to ensure that regular latency plus an extra SAGV delay doesn't
lead us to run dry), but that's not what the bspec calls for on ICL.
I'm not really sure whether that's truly an intentional behavior change
between platforms or whether the TGL bspec section does just a better
job of explaining what was supposed to be done and clarifying the
language.
Anyway, we should probably trust the bspec for now, so it seems to me
like we should add a "fake" watermark level associated with the SAGV
block time and explicitly calculate that as enabled/disabled anytime we
have a good < SAGV < bad situation.
> + }
> + if (can_sagv)
> + state->crtc_sagv_mask |= BIT(crtc->pipe);
> + }
> +}
> +
> +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +{
> + struct drm_device *dev = state->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + enum pipe pipe;
> +
> + if (INTEL_GEN(dev_priv) >= 12)
> + tgl_set_sagv_mask(state);
> + else if (INTEL_GEN(dev_priv) == 11)
> + icl_set_sagv_mask(state);
> + else
> + skl_set_sagv_mask(state);
> +
> + /*
> + * For SAGV we need to account all the pipes,
> + * not only the ones which are in state currently.
> + */
> + for_each_pipe(dev_priv, pipe) {
> + unsigned int active_pipes;
> + /*
> + * Figure out if we are changing active pipes here
> + * then after commit dev_priv->active_pipes will
> + * anyway be assigned to state->active_pipes.
> + */
> + if (state->active_pipe_changes)
> + active_pipes = state->active_pipes;
> + else
> + active_pipes = dev_priv->active_pipes;
> +
> + /* Skip if pipe is inactive */
> + if (!(BIT(pipe) & active_pipes))
> + continue;
> +
> + /*
> + * Pipe can be active in this state or in dev_priv
> + * as we haven't committed thise changes yet(and we shouldn't)
> + * - we need to check both.
> + */
> + if (state->active_pipe_changes & BIT(pipe)) {
> + bool state_sagv_masked = \
> + (BIT(pipe) & state->crtc_sagv_mask) == 0;
> + if (state_sagv_masked)
> + return false;
> + } else {
> + bool sagv_masked = \
> + (BIT(pipe) & dev_priv->crtc_sagv_mask) == 0;
If we're not changing which pipes are active, then we didn't globally
lock everything at the beginning of this atomic transaction; we can have
racing commits against different CRTC's. So when you look at
dev_priv->crtc_sagv_mask here, the value might change immediately
afterward if a commit on a different CRTC completed in the meantime.
I don't think we want to look at other CRTC's outside our current
transaction here. We should just figure out whether our own CRTC's are
okay with SAGV or not. Then in the commit phase we'd need to grab some
kind of SAGV lock, combine our local "SAGV okay" with the global "SAGV
okay" and enable/disable as necessary.
Some kind of reference-counting mechanism might make this simpler...is
there any way we could tie this in with power domains (e.g., adding a
"SAGV off" power domain and power well that we grab during commit when
we've calculated that our own crtcs can't cope with SAGV latency)?
> + if (sagv_masked)
> + return false;
> + }
> + }
> return true;
> }
>
> @@ -3925,6 +4045,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> int color_plane);
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> int level,
> + u32 latency,
> const struct skl_wm_params *wp,
> const struct skl_wm_level *result_prev,
> struct skl_wm_level *result /* out */);
> @@ -3947,7 +4068,10 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
> WARN_ON(ret);
>
> for (level = 0; level <= max_level; level++) {
> - skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
> + u32 latency = dev_priv->wm.skl_latency[level];
> +
> + skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
> +
> if (wm.min_ddb_alloc == U16_MAX)
> break;
>
> @@ -4212,6 +4336,68 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
> return total_data_rate;
> }
>
> +static int
> +tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
> + struct skl_ddb_allocation *ddb /* out */)
> +{
> + struct drm_crtc *crtc = crtc_state->base.crtc;
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
> + u16 alloc_size;
> + u16 total[I915_MAX_PLANES] = {};
> + u64 total_data_rate;
> + enum plane_id plane_id;
> + int num_active;
> + u64 plane_data_rate[I915_MAX_PLANES] = {};
> + u32 blocks;
> +
> + /*
> + * No need to check gen here, we call this only for gen12
> + */
> + total_data_rate =
> + icl_get_total_relative_data_rate(crtc_state,
> + plane_data_rate);
> +
> + skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
> + total_data_rate,
> + ddb, alloc, &num_active);
> + alloc_size = skl_ddb_entry_size(alloc);
> + if (alloc_size == 0)
> + return -ENOSPC;
> +
> + /* Allocate fixed number of blocks for cursor. */
> + total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
> + alloc_size -= total[PLANE_CURSOR];
> + crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
> + alloc->end - total[PLANE_CURSOR];
> + crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
> +
> + /*
> + * Do check if we can fit L0 + sagv_block_time and
> + * disable SAGV if we can't.
> + */
> + blocks = 0;
> + for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> + const struct skl_plane_wm *wm =
> + &crtc_state->wm.skl.optimal.planes[plane_id];
> +
> + if (plane_id == PLANE_CURSOR) {
> + if (WARN_ON(wm->sagv_wm0.min_ddb_alloc >
> + total[PLANE_CURSOR])) {
> + blocks = U32_MAX;
> + break;
> + }
> + continue;
> + }
> +
> + blocks += wm->sagv_wm0.min_ddb_alloc;
> + if (blocks > alloc_size)
> + return -ENOSPC;
> + }
> + return 0;
> +}
> +
> static int
> skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
> struct skl_ddb_allocation *ddb /* out */)
> @@ -4641,6 +4827,7 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
>
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> int level,
> + u32 latency,
> const struct skl_wm_params *wp,
> const struct skl_wm_level *result_prev,
> struct skl_wm_level *result /* out */)
It doesn't look like this latency parameter gets used (it gets masked by
a local latency variable still.
> @@ -4767,20 +4954,45 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> static void
> skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> const struct skl_wm_params *wm_params,
> - struct skl_wm_level *levels)
> + struct skl_plane_wm *plane_wm,
> + bool yuv)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> int level, max_level = ilk_wm_max_level(dev_priv);
> + /*
> + * Check which kind of plane is it and based on that calculate
> + * correspondent WM levels.
> + */
> + struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm;
> struct skl_wm_level *result_prev = &levels[0];
>
> for (level = 0; level <= max_level; level++) {
> struct skl_wm_level *result = &levels[level];
> + u32 latency = dev_priv->wm.skl_latency[level];
>
> - skl_compute_plane_wm(crtc_state, level, wm_params,
> - result_prev, result);
> + skl_compute_plane_wm(crtc_state, level, latency,
> + wm_params, result_prev, result);
>
> result_prev = result;
> }
> + /*
> + * For Gen12 if it is an L0 we need to also
> + * consider sagv_block_time when calculating
> + * L0 watermark - we will need that when making
> + * a decision whether enable SAGV or not.
> + * For older gens we agreed to copy L0 value for
> + * compatibility.
> + */
> + if ((INTEL_GEN(dev_priv) >= 12)) {
> + u32 latency = dev_priv->wm.skl_latency[0];
> +
> + latency += dev_priv->sagv_block_time_us;
> + skl_compute_plane_wm(crtc_state, 0, latency,
> + wm_params, &levels[0],
> + &plane_wm->sagv_wm0);
> + } else
> + memcpy(&plane_wm->sagv_wm0, &levels[0],
> + sizeof(struct skl_wm_level));
> }
>
> static u32
> @@ -4873,7 +5085,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> - skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> + skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
> skl_compute_transition_wm(crtc_state, &wm_params, wm);
>
> return 0;
> @@ -4895,7 +5107,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> - skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
> + skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
>
> return 0;
> }
> @@ -5167,6 +5379,8 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
> return 0;
> }
>
> +static void tgl_set_sagv_wm0(struct intel_atomic_state *state);
> +
> static int
> skl_compute_ddb(struct intel_atomic_state *state)
> {
> @@ -5177,6 +5391,11 @@ skl_compute_ddb(struct intel_atomic_state *state)
> struct intel_crtc *crtc;
> int ret, i;
>
> + /* For Gen12+ for SAGV we have a special L0 wm values */
> + if (INTEL_GEN(dev_priv) >= 12)
> + if (intel_can_enable_sagv(state))
> + tgl_set_sagv_wm0(state);
> +
> memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> @@ -5443,6 +5662,56 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
> return 0;
> }
>
> +void tgl_set_sagv_wm0(struct intel_atomic_state *state)
> +{
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *new_crtc_state;
> + struct intel_crtc_state *old_crtc_state;
> + struct drm_device *dev = state->base.dev;
> + const struct drm_i915_private *dev_priv = to_i915(dev);
> + int i;
> +
> + /*
> + * If we determined that we can actually enable SAGV, then
> + * actually use those levels tgl_check_pipe_fits_sagv_wm
> + * has already taken care of checking if L0 + sagv block time
> + * fits into ddb.
> + */
> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> + new_crtc_state, i) {
> + struct intel_plane *plane;
> +
> + for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> + enum plane_id plane_id = plane->id;
> +
> + struct skl_plane_wm *plane_wm = \
> + &new_crtc_state->wm.skl.optimal.planes[plane_id];
> + struct skl_wm_level *sagv_wm0 = &plane_wm->sagv_wm0;
> + struct skl_wm_level *l0_wm0 = &plane_wm->wm[0];
> +
> + memcpy(l0_wm0, sagv_wm0, sizeof(struct skl_wm_level));
> + }
> + }
> +}
> +
> +static void tgl_set_sagv_mask(struct intel_atomic_state *state)
> +{
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *new_crtc_state;
> + struct intel_crtc_state *old_crtc_state;
> + struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
> + int ret, i;
> +
> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> + new_crtc_state, i) {
> + ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
> + if (!ret) {
> + int pipe_bit = BIT(crtc->pipe);
> + state->crtc_sagv_mask |= pipe_bit;
> + }
> + }
> +}
> +
> static int
> skl_compute_wm(struct intel_atomic_state *state)
> {
> @@ -5455,6 +5724,9 @@ skl_compute_wm(struct intel_atomic_state *state)
> /* Clear all dirty flags */
> results->dirty_pipes = 0;
>
> + /* If we exit before check is done */
> + state->crtc_sagv_mask = 0;
> +
> ret = skl_ddb_add_affected_pipes(state);
> if (ret)
> return ret;
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v10 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.
@ 2019-11-12 1:22 ` Matt Roper
0 siblings, 0 replies; 25+ messages in thread
From: Matt Roper @ 2019-11-12 1:22 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Thu, Nov 07, 2019 at 05:30:37PM +0200, Stanislav Lisovskiy wrote:
> According to BSpec 53998, we should try to
> restrict qgv points, which can't provide
> enough bandwidth for desired display configuration.
>
> Currently we are just comparing against all of
> those and take minimum(worst case).
>
> v2: Fixed wrong PCode reply mask, removed hardcoded
> values.
>
> v3: Forbid simultaneous legacy SAGV PCode requests and
> restricting qgv points. Put the actual restriction
> to commit function, added serialization(thanks to Ville)
> to prevent commit being applied out of order in case of
> nonblocking and/or nomodeset commits.
>
> v4:
> - Minor code refactoring, fixed few typos(thanks to James Ausmus)
> - Change the naming of qgv point
> masking/unmasking functions(James Ausmus).
> - Simplify the masking/unmasking operation itself,
> as we don't need to mask only single point per request(James Ausmus)
> - Reject and stick to highest bandwidth point if SAGV
> can't be enabled(BSpec)
>
> v5:
> - Add new mailbox reply codes, which seems to happen during boot
> time for TGL and indicate that QGV setting is not yet available.
>
> v6:
> - Increase number of supported QGV points to be in sync with BSpec.
>
> v7: - Rebased and resolved conflict to fix build failure.
> - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)
>
> v8: - Don't report an error if we can't restrict qgv points, as SAGV
> can be disabled by BIOS, which is completely legal. So don't
> make CI panic. Instead if we detect that there is only 1 QGV
> point accessible just analyze if we can fit the required bandwidth
> requirements, but no need in restricting.
>
> v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
> simultaneously.
>
> v10: - Fix CDCLK corruption, because of global state getting serialized
> without modeset, which caused copying of non-calculated cdclk
> to be copied to dev_priv(thanks to Ville for the hint).
>
> Reviewed-by: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_atomic.h | 3 +
> drivers/gpu/drm/i915/display/intel_bw.c | 137 +++++++++++++++---
> drivers/gpu/drm/i915/display/intel_bw.h | 2 +
> drivers/gpu/drm/i915/display/intel_display.c | 104 ++++++++++++-
> .../drm/i915/display/intel_display_types.h | 3 +
> drivers/gpu/drm/i915/i915_drv.h | 4 +-
> drivers/gpu/drm/i915/i915_reg.h | 8 +
> drivers/gpu/drm/i915/intel_pm.c | 15 +-
> drivers/gpu/drm/i915/intel_pm.h | 1 +
> drivers/gpu/drm/i915/intel_sideband.c | 27 +++-
> drivers/gpu/drm/i915/intel_sideband.h | 1 -
> 11 files changed, 264 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 7b49623419ba..3ab6d7ec75ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -7,6 +7,7 @@
> #define __INTEL_ATOMIC_H__
>
> #include <linux/types.h>
> +#include "intel_display_types.h"
Is this change needed? We already have a forward declaration of
intel_atomic_state so it doesn't seem like this should be necessary for
the function prototype below.
>
> struct drm_atomic_state;
> struct drm_connector;
> @@ -41,6 +42,8 @@ void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
> struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
> void intel_atomic_state_clear(struct drm_atomic_state *state);
>
> +int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
> +
> struct intel_crtc_state *
> intel_atomic_get_crtc_state(struct drm_atomic_state *state,
> struct intel_crtc *crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 3f6e29f61323..1dde4e1574fb 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -8,6 +8,9 @@
> #include "intel_bw.h"
> #include "intel_display_types.h"
> #include "intel_sideband.h"
> +#include "intel_atomic.h"
> +#include "intel_pm.h"
> +
>
> /* Parameters for Qclk Geyserville (QGV) */
> struct intel_qgv_point {
> @@ -15,7 +18,7 @@ struct intel_qgv_point {
> };
>
> struct intel_qgv_info {
> - struct intel_qgv_point points[3];
> + struct intel_qgv_point points[NUM_SAGV_POINTS];
> u8 num_points;
> u8 num_channels;
> u8 t_bl;
> @@ -113,6 +116,27 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
> return 0;
> }
>
> +int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> + u32 points_mask)
> +{
> + int ret;
> +
> + /* bspec says to keep retrying for at least 1 ms */
> + ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
> + points_mask,
> + GEN11_PCODE_POINTS_RESTRICTED_MASK,
> + GEN11_PCODE_POINTS_RESTRICTED,
> + 1);
> +
> + if (ret < 0) {
> + DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +
Minor nitpick: one too many blank lines here.
> static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
> struct intel_qgv_info *qi)
> {
> @@ -176,7 +200,7 @@ static const struct intel_sa_info tgl_sa_info = {
>
> static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
> {
> - struct intel_qgv_info qi = {};
> + struct intel_qgv_info qi;
Is there a reason we don't want to zero out the structure here? I don't
think it should hurt anything, plus it helps prevent us from making
mistakes in the future and trying to interpret garbage data associated
with the non-existent QGV points.
> bool is_y_tile = true; /* assume y tile may be used */
> int num_channels;
> int deinterleave;
> @@ -270,22 +294,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
> icl_get_bw_info(dev_priv, &icl_sa_info);
> }
>
> -static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
> - int num_planes)
> -{
> - if (INTEL_GEN(dev_priv) >= 11)
> - /*
> - * FIXME with SAGV disabled maybe we can assume
> - * point 1 will always be used? Seems to match
> - * the behaviour observed in the wild.
> - */
> - return min3(icl_max_bw(dev_priv, num_planes, 0),
> - icl_max_bw(dev_priv, num_planes, 1),
> - icl_max_bw(dev_priv, num_planes, 2));
> - else
> - return UINT_MAX;
> -}
> -
> static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
> {
> /*
> @@ -377,7 +385,12 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> unsigned int data_rate, max_data_rate;
> unsigned int num_active_planes;
> struct intel_crtc *crtc;
> - int i;
> + int i, ret;
> + struct intel_qgv_info qi = {};
> + u32 allowed_points = 0;
> + unsigned int max_bw_point = 0, max_bw = 0;
> + unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
> + u32 mask = (1 << num_qgv_points) - 1;
>
> /* FIXME earlier gens need some checks too */
> if (INTEL_GEN(dev_priv) < 11)
> @@ -421,16 +434,92 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> data_rate = intel_bw_data_rate(dev_priv, bw_state);
> num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
>
> - max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
> -
> data_rate = DIV_ROUND_UP(data_rate, 1000);
>
> - if (data_rate > max_data_rate) {
> - DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
> - data_rate, max_data_rate, num_active_planes);
> + for (i = 0; i < num_qgv_points; i++) {
> + max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
> + /*
> + * We need to know which qgv point gives us
> + * maximum bandwidth in order to disable SAGV
> + * if we find that we exceed SAGV block time
> + * with watermarks. By that moment we already
> + * have those, as it is calculated earlier in
> + * intel_atomic_check,
> + */
> + if (max_data_rate > max_bw) {
> + max_bw_point = i;
> + max_bw = max_data_rate;
> + }
> + if (max_data_rate >= data_rate)
> + allowed_points |= 1 << i;
Minor nitpick; cleaner to use BIT(i) for this.
> + DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
> + i, max_data_rate, data_rate);
> + }
> +
> + /*
> + * BSpec states that we always should have at least one allowed point
> + * left, so if we couldn't - simply reject the configuration for obvious
> + * reasons.
> + */
> + if (allowed_points == 0) {
> + DRM_DEBUG_KMS("Could not find any suitable QGV points\n");
We might want to make some mention of memory bandwidth in this message
for people who don't know what a QGV point is. E.g., "No QGV points
provide sufficient memory bandwidth for display configuration."
> return -EINVAL;
> }
>
> + /*
> + * In case if SAGV is disabled in BIOS, we always get 1
> + * SAGV point, but we can't send PCode commands to restrict it
> + * as it will fail and pointless anyway.
> + */
> + if (qi.num_points == 1)
> + dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
> + else
> + dev_priv->sagv_status = I915_SAGV_ENABLED;
> +
> + /*
> + * Leave only single point with highest bandwidth, if
> + * we can't enable SAGV according to BSpec.
> + */
> + if (!intel_can_enable_sagv(state)) {
> +
> + /*
> + * This is a border line condition when we have 0 planes
> + * and SAGV not enabled means that we should keep QGV with
> + * highest bandwidth, however algorithm returns wrong result
> + * for 0 planes and 0 data rate, so just stick to last config
> + * then. Otherwise use the QGV point with highest BW according
> + * to BSpec.
> + */
Isn't the QGV with the highest bandwidth constant? Can we just figure
it out once at startup and then set it directly here instead of
re-finding it each commit?
> + if (!data_rate && !num_active_planes) {
> + DRM_DEBUG_KMS("No SAGV, using old QGV mask\n");
> + allowed_points = (~dev_priv->qgv_points_mask) & mask;
> + } else {
> + allowed_points = 1 << max_bw_point;
> + DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n",
> + max_bw_point);
> + }
> + }
> + /*
> + * We store the ones which need to be masked as that is what PCode
> + * actually accepts as a parameter.
> + */
> + state->qgv_points_mask = (~allowed_points) & mask;
> +
> + DRM_DEBUG_KMS("New state %p qgv mask %x\n",
> + state, state->qgv_points_mask);
> +
> + /*
> + * If the actual mask had changed we need to make sure that
> + * the commits are serialized(in case this is a nomodeset, nonblocking)
> + */
> + if (state->qgv_points_mask != dev_priv->qgv_points_mask) {
> + ret = intel_atomic_serialize_global_state(state);
> + if (ret) {
> + DRM_DEBUG_KMS("Could not serialize global state\n");
> + return ret;
> + }
> + }
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> index 9db10af012f4..66bf9bc10b73 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -28,5 +28,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
> int intel_bw_atomic_check(struct intel_atomic_state *state);
> void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> const struct intel_crtc_state *crtc_state);
> +int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> + u32 points_mask);
>
> #endif /* __INTEL_BW_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7ea1e7518ab6..71f6aaa1f6b9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14744,6 +14744,80 @@ static void intel_atomic_cleanup_work(struct work_struct *work)
> intel_atomic_helper_free_state(i915);
> }
>
> +static void intel_qgv_points_mask(struct intel_atomic_state *state)
> +{
> + struct drm_device *dev = state->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + int ret;
> + u32 new_mask = dev_priv->qgv_points_mask | state->qgv_points_mask;
> + unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
> + unsigned int mask = (1 << num_qgv_points) - 1;
> +
> + /*
> + * As we don't know initial hardware state during initial commit
> + * we should not do anything, until we actually figure out,
> + * what are the qgv points to mask.
> + */
> + if (!new_mask)
> + return;
> +
> + WARN_ON(new_mask == mask);
> +
> + /*
> + * Just return if we can't control SAGV or don't have it.
> + */
> + if (!intel_has_sagv(dev_priv))
> + return;
> +
> + /*
> + * Restrict required qgv points before updating the configuration.
> + * According to BSpec we can't mask and unmask qgv points at the same
> + * time. Also masking should be done before updating the configuration
> + * and unmasking afterwards.
> + */
> + ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> + if (ret < 0)
> + DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n",
> + ret);
> + else
> + dev_priv->qgv_points_mask = new_mask;
> +}
> +
> +static void intel_qgv_points_unmask(struct intel_atomic_state *state)
> +{
> + struct drm_device *dev = state->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + int ret;
> + u32 new_mask = dev_priv->qgv_points_mask & state->qgv_points_mask;
> +
> + /*
> + * As we don't know initial hardware state during initial commit
> + * we should not do anything, until we actually figure out,
> + * what are the qgv points to mask.
> + */
> + if (!new_mask)
> + return;
> +
> + /*
> + * Just return if we can't control SAGV or don't have it.
> + */
> + if (!intel_has_sagv(dev_priv))
> + return;
> +
> + /*
> + * Allow required qgv points after updating the configuration.
> + * According to BSpec we can't mask and unmask qgv points at the same
> + * time. Also masking should be done before updating the configuration
> + * and unmasking afterwards.
> + */
> + ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> + if (ret < 0)
> + DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n",
> + ret);
> + else
> + dev_priv->qgv_points_mask = new_mask;
> +}
> +
> static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> {
> struct drm_device *dev = state->base.dev;
> @@ -14771,6 +14845,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> }
> }
>
> + if ((INTEL_GEN(dev_priv) >= 11))
> + intel_qgv_points_mask(state);
> +
> intel_commit_modeset_disables(state);
>
> /* FIXME: Eventually get rid of our crtc->config pointer */
> @@ -14789,8 +14866,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> * SKL workaround: bspec recommends we disable the SAGV when we
> * have more then one pipe enabled
> */
> - if (!intel_can_enable_sagv(state))
> - intel_disable_sagv(dev_priv);
> + if (INTEL_GEN(dev_priv) < 11)
> + if (!intel_can_enable_sagv(state))
> + intel_disable_sagv(dev_priv);
>
> intel_modeset_verify_disabled(dev_priv, state);
> }
> @@ -14873,8 +14951,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> if (state->modeset)
> intel_verify_planes(state);
>
> - if (state->modeset && intel_can_enable_sagv(state))
> - intel_enable_sagv(dev_priv);
> + if (INTEL_GEN(dev_priv) < 11) {
> + if (state->modeset && intel_can_enable_sagv(state))
> + intel_enable_sagv(dev_priv);
> + } else
> + intel_qgv_points_unmask(state);
>
> drm_atomic_helper_commit_hw_done(&state->base);
>
> @@ -14962,7 +15043,18 @@ static int intel_atomic_commit(struct drm_device *dev,
> {
> struct intel_atomic_state *state = to_intel_atomic_state(_state);
> struct drm_i915_private *dev_priv = to_i915(dev);
> - int ret = 0;
> + struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> + int ret = 0, i;
> + bool any_ms = false;
> + struct intel_crtc *crtc;
> +
> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> + new_crtc_state, i) {
> + if (needs_modeset(new_crtc_state)) {
> + any_ms = true;
> + break;
> + }
> + }
I think we already have this in state->modeset.
>
> state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
>
> @@ -15021,7 +15113,7 @@ static int intel_atomic_commit(struct drm_device *dev,
> intel_shared_dpll_swap_state(state);
> intel_atomic_track_fbs(state);
>
> - if (state->global_state_changed) {
> + if (state->global_state_changed && any_ms) {
> assert_global_state_locked(dev_priv);
>
> memcpy(dev_priv->min_cdclk, state->min_cdclk,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index fb274538af23..896b13bc4494 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -528,6 +528,9 @@ struct intel_atomic_state {
> struct i915_sw_fence commit_ready;
>
> struct llist_node freed;
> +
> + /* Gen11+ only */
> + u32 qgv_points_mask;
> };
>
> struct intel_plane_state {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4f4e2e839513..9924390cb94b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1243,11 +1243,13 @@ struct drm_i915_private {
> } dram_info;
>
> struct intel_bw_info {
> - unsigned int deratedbw[3]; /* for each QGV point */
> + unsigned int deratedbw[NUM_SAGV_POINTS]; /* for each QGV point */
> u8 num_qgv_points;
> u8 num_planes;
> } max_bw[6];
>
> + u32 qgv_points_mask;
> +
> struct drm_private_obj bw_obj;
>
> struct intel_runtime_pm runtime_pm;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a607ea520829..6d6ecf1d9f6b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8951,6 +8951,9 @@ enum {
> #define VLV_RENDER_C0_COUNT _MMIO(0x138118)
> #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
>
> +/* BSpec precisely defines this */
> +#define NUM_SAGV_POINTS 8
> +
Any specific reason this is in the reg file rather than either
i915_drv.h where it's used or something like intel_bw.h?
> #define GEN6_PCODE_MAILBOX _MMIO(0x138124)
> #define GEN6_PCODE_READY (1 << 31)
> #define GEN6_PCODE_ERROR_MASK 0xFF
> @@ -8961,6 +8964,8 @@ enum {
> #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
> #define GEN7_PCODE_TIMEOUT 0x2
> #define GEN7_PCODE_ILLEGAL_DATA 0x3
> +#define GEN11_PCODE_MAIL_BOX_LOCKED 0x6
> +#define GEN11_PCODE_REJECTED 0x11
> #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
> #define GEN6_PCODE_WRITE_RC6VIDS 0x4
> #define GEN6_PCODE_READ_RC6VIDS 0x5
> @@ -8982,6 +8987,7 @@ enum {
> #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
> #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
> #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
> +#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
> #define GEN6_PCODE_READ_D_COMP 0x10
> #define GEN6_PCODE_WRITE_D_COMP 0x11
> #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
> @@ -8994,6 +9000,8 @@ enum {
> #define GEN9_SAGV_IS_DISABLED 0x1
> #define GEN9_SAGV_ENABLE 0x3
> #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
> +#define GEN11_PCODE_POINTS_RESTRICTED 0x0
> +#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
> #define GEN6_PCODE_DATA _MMIO(0x138128)
> #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
> #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c792dd168742..10816f3e29f0 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3617,13 +3617,9 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
> return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
> }
>
> -static bool
> +bool
> intel_has_sagv(struct drm_i915_private *dev_priv)
> {
> - /* HACK! */
> - if (IS_GEN(dev_priv, 12))
> - return false;
> -
> return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
> dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
> }
> @@ -3839,7 +3835,7 @@ static void icl_set_sagv_mask(struct intel_atomic_state *state)
> if (flags & DRM_MODE_FLAG_INTERLACE)
> continue;
>
> - if (!new_crtc_state->base.active)
> + if (!new_crtc_state->hw.enable)
> continue;
Looks like this was a bug in the previous patch. Any specific reason
we're switching from active to enable?
>
> can_sagv = true;
> @@ -3886,6 +3882,9 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> else
> skl_set_sagv_mask(state);
>
> + DRM_DEBUG_KMS("Crtc sagv masks, state %x global state %x\n",
> + state->crtc_sagv_mask,
> + dev_priv->crtc_sagv_mask);
> /*
> * For SAGV we need to account all the pipes,
> * not only the ones which are in state currently.
> @@ -4340,7 +4339,7 @@ static int
> tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
> struct skl_ddb_allocation *ddb /* out */)
> {
> - struct drm_crtc *crtc = crtc_state->base.crtc;
> + struct drm_crtc *crtc = crtc_state->uapi.crtc;
Also a bug in the previous patch.
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
> @@ -4833,7 +4832,6 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> struct skl_wm_level *result /* out */)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> - u32 latency = dev_priv->wm.skl_latency[level];
Mentioned on previous patch.
> uint_fixed_16_16_t method1, method2;
> uint_fixed_16_16_t selected_result;
> u32 res_blocks, res_lines, min_ddb_alloc = 0;
> @@ -5707,6 +5705,7 @@ static void tgl_set_sagv_mask(struct intel_atomic_state *state)
> ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
> if (!ret) {
> int pipe_bit = BIT(crtc->pipe);
> +
> state->crtc_sagv_mask |= pipe_bit;
Unrelated change.
> }
> }
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index b579c724b915..53275860731a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -43,6 +43,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> bool intel_can_enable_sagv(struct intel_atomic_state *state);
> +bool intel_has_sagv(struct drm_i915_private *dev_priv);
> int intel_enable_sagv(struct drm_i915_private *dev_priv);
> int intel_disable_sagv(struct drm_i915_private *dev_priv);
> bool skl_wm_level_equals(const struct skl_wm_level *l1,
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index e06b35b844a0..ff9dbed094d8 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -371,6 +371,29 @@ static inline int gen7_check_mailbox_status(u32 mbox)
> }
> }
>
> +static inline int gen11_check_mailbox_status(u32 mbox)
> +{
> + switch (mbox & GEN6_PCODE_ERROR_MASK) {
> + case GEN6_PCODE_SUCCESS:
> + return 0;
> + case GEN6_PCODE_ILLEGAL_CMD:
> + return -ENXIO;
> + case GEN7_PCODE_TIMEOUT:
> + return -ETIMEDOUT;
> + case GEN7_PCODE_ILLEGAL_DATA:
> + return -EINVAL;
> + case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
> + return -EOVERFLOW;
> + case GEN11_PCODE_MAIL_BOX_LOCKED:
> + return -EAGAIN;
> + case GEN11_PCODE_REJECTED:
> + return -EACCES;
> + default:
> + MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
> + return 0;
> + }
> +}
> +
> static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
> u32 mbox, u32 *val, u32 *val1,
> int fast_timeout_us,
> @@ -408,7 +431,9 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
> if (is_read && val1)
> *val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
>
> - if (INTEL_GEN(i915) > 6)
> + if (INTEL_GEN(i915) >= 11)
> + return gen11_check_mailbox_status(mbox);
> + else if (INTEL_GEN(i915) > 6)
> return gen7_check_mailbox_status(mbox);
> else
> return gen6_check_mailbox_status(mbox);
> diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h
> index 7fb95745a444..14627ace99ae 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.h
> +++ b/drivers/gpu/drm/i915/intel_sideband.h
> @@ -137,5 +137,4 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
>
> int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
> u32 reply_mask, u32 reply, int timeout_base_ms);
> -
> #endif /* _INTEL_SIDEBAND_H */
Unrelated change.
In general, I wonder if we could break this patch up a bit more. It
seems like there are a lot of moving pieces here which makes it a bit
harder to review.
Matt
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH v10 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.
@ 2019-11-12 1:22 ` Matt Roper
0 siblings, 0 replies; 25+ messages in thread
From: Matt Roper @ 2019-11-12 1:22 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Thu, Nov 07, 2019 at 05:30:37PM +0200, Stanislav Lisovskiy wrote:
> According to BSpec 53998, we should try to
> restrict qgv points, which can't provide
> enough bandwidth for desired display configuration.
>
> Currently we are just comparing against all of
> those and take minimum(worst case).
>
> v2: Fixed wrong PCode reply mask, removed hardcoded
> values.
>
> v3: Forbid simultaneous legacy SAGV PCode requests and
> restricting qgv points. Put the actual restriction
> to commit function, added serialization(thanks to Ville)
> to prevent commit being applied out of order in case of
> nonblocking and/or nomodeset commits.
>
> v4:
> - Minor code refactoring, fixed few typos(thanks to James Ausmus)
> - Change the naming of qgv point
> masking/unmasking functions(James Ausmus).
> - Simplify the masking/unmasking operation itself,
> as we don't need to mask only single point per request(James Ausmus)
> - Reject and stick to highest bandwidth point if SAGV
> can't be enabled(BSpec)
>
> v5:
> - Add new mailbox reply codes, which seems to happen during boot
> time for TGL and indicate that QGV setting is not yet available.
>
> v6:
> - Increase number of supported QGV points to be in sync with BSpec.
>
> v7: - Rebased and resolved conflict to fix build failure.
> - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)
>
> v8: - Don't report an error if we can't restrict qgv points, as SAGV
> can be disabled by BIOS, which is completely legal. So don't
> make CI panic. Instead if we detect that there is only 1 QGV
> point accessible just analyze if we can fit the required bandwidth
> requirements, but no need in restricting.
>
> v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
> simultaneously.
>
> v10: - Fix CDCLK corruption, because of global state getting serialized
> without modeset, which caused copying of non-calculated cdclk
> to be copied to dev_priv(thanks to Ville for the hint).
>
> Reviewed-by: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_atomic.h | 3 +
> drivers/gpu/drm/i915/display/intel_bw.c | 137 +++++++++++++++---
> drivers/gpu/drm/i915/display/intel_bw.h | 2 +
> drivers/gpu/drm/i915/display/intel_display.c | 104 ++++++++++++-
> .../drm/i915/display/intel_display_types.h | 3 +
> drivers/gpu/drm/i915/i915_drv.h | 4 +-
> drivers/gpu/drm/i915/i915_reg.h | 8 +
> drivers/gpu/drm/i915/intel_pm.c | 15 +-
> drivers/gpu/drm/i915/intel_pm.h | 1 +
> drivers/gpu/drm/i915/intel_sideband.c | 27 +++-
> drivers/gpu/drm/i915/intel_sideband.h | 1 -
> 11 files changed, 264 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 7b49623419ba..3ab6d7ec75ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -7,6 +7,7 @@
> #define __INTEL_ATOMIC_H__
>
> #include <linux/types.h>
> +#include "intel_display_types.h"
Is this change needed? We already have a forward declaration of
intel_atomic_state so it doesn't seem like this should be necessary for
the function prototype below.
>
> struct drm_atomic_state;
> struct drm_connector;
> @@ -41,6 +42,8 @@ void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
> struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
> void intel_atomic_state_clear(struct drm_atomic_state *state);
>
> +int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
> +
> struct intel_crtc_state *
> intel_atomic_get_crtc_state(struct drm_atomic_state *state,
> struct intel_crtc *crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 3f6e29f61323..1dde4e1574fb 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -8,6 +8,9 @@
> #include "intel_bw.h"
> #include "intel_display_types.h"
> #include "intel_sideband.h"
> +#include "intel_atomic.h"
> +#include "intel_pm.h"
> +
>
> /* Parameters for Qclk Geyserville (QGV) */
> struct intel_qgv_point {
> @@ -15,7 +18,7 @@ struct intel_qgv_point {
> };
>
> struct intel_qgv_info {
> - struct intel_qgv_point points[3];
> + struct intel_qgv_point points[NUM_SAGV_POINTS];
> u8 num_points;
> u8 num_channels;
> u8 t_bl;
> @@ -113,6 +116,27 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
> return 0;
> }
>
> +int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> + u32 points_mask)
> +{
> + int ret;
> +
> + /* bspec says to keep retrying for at least 1 ms */
> + ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
> + points_mask,
> + GEN11_PCODE_POINTS_RESTRICTED_MASK,
> + GEN11_PCODE_POINTS_RESTRICTED,
> + 1);
> +
> + if (ret < 0) {
> + DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +
Minor nitpick: one too many blank lines here.
> static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
> struct intel_qgv_info *qi)
> {
> @@ -176,7 +200,7 @@ static const struct intel_sa_info tgl_sa_info = {
>
> static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
> {
> - struct intel_qgv_info qi = {};
> + struct intel_qgv_info qi;
Is there a reason we don't want to zero out the structure here? I don't
think it should hurt anything, plus it helps prevent us from making
mistakes in the future and trying to interpret garbage data associated
with the non-existent QGV points.
> bool is_y_tile = true; /* assume y tile may be used */
> int num_channels;
> int deinterleave;
> @@ -270,22 +294,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
> icl_get_bw_info(dev_priv, &icl_sa_info);
> }
>
> -static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
> - int num_planes)
> -{
> - if (INTEL_GEN(dev_priv) >= 11)
> - /*
> - * FIXME with SAGV disabled maybe we can assume
> - * point 1 will always be used? Seems to match
> - * the behaviour observed in the wild.
> - */
> - return min3(icl_max_bw(dev_priv, num_planes, 0),
> - icl_max_bw(dev_priv, num_planes, 1),
> - icl_max_bw(dev_priv, num_planes, 2));
> - else
> - return UINT_MAX;
> -}
> -
> static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
> {
> /*
> @@ -377,7 +385,12 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> unsigned int data_rate, max_data_rate;
> unsigned int num_active_planes;
> struct intel_crtc *crtc;
> - int i;
> + int i, ret;
> + struct intel_qgv_info qi = {};
> + u32 allowed_points = 0;
> + unsigned int max_bw_point = 0, max_bw = 0;
> + unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
> + u32 mask = (1 << num_qgv_points) - 1;
>
> /* FIXME earlier gens need some checks too */
> if (INTEL_GEN(dev_priv) < 11)
> @@ -421,16 +434,92 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> data_rate = intel_bw_data_rate(dev_priv, bw_state);
> num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
>
> - max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
> -
> data_rate = DIV_ROUND_UP(data_rate, 1000);
>
> - if (data_rate > max_data_rate) {
> - DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
> - data_rate, max_data_rate, num_active_planes);
> + for (i = 0; i < num_qgv_points; i++) {
> + max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
> + /*
> + * We need to know which qgv point gives us
> + * maximum bandwidth in order to disable SAGV
> + * if we find that we exceed SAGV block time
> + * with watermarks. By that moment we already
> + * have those, as it is calculated earlier in
> + * intel_atomic_check,
> + */
> + if (max_data_rate > max_bw) {
> + max_bw_point = i;
> + max_bw = max_data_rate;
> + }
> + if (max_data_rate >= data_rate)
> + allowed_points |= 1 << i;
Minor nitpick; cleaner to use BIT(i) for this.
> + DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
> + i, max_data_rate, data_rate);
> + }
> +
> + /*
> + * BSpec states that we always should have at least one allowed point
> + * left, so if we couldn't - simply reject the configuration for obvious
> + * reasons.
> + */
> + if (allowed_points == 0) {
> + DRM_DEBUG_KMS("Could not find any suitable QGV points\n");
We might want to make some mention of memory bandwidth in this message
for people who don't know what a QGV point is. E.g., "No QGV points
provide sufficient memory bandwidth for display configuration."
> return -EINVAL;
> }
>
> + /*
> + * In case if SAGV is disabled in BIOS, we always get 1
> + * SAGV point, but we can't send PCode commands to restrict it
> + * as it will fail and pointless anyway.
> + */
> + if (qi.num_points == 1)
> + dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
> + else
> + dev_priv->sagv_status = I915_SAGV_ENABLED;
> +
> + /*
> + * Leave only single point with highest bandwidth, if
> + * we can't enable SAGV according to BSpec.
> + */
> + if (!intel_can_enable_sagv(state)) {
> +
> + /*
> + * This is a border line condition when we have 0 planes
> + * and SAGV not enabled means that we should keep QGV with
> + * highest bandwidth, however algorithm returns wrong result
> + * for 0 planes and 0 data rate, so just stick to last config
> + * then. Otherwise use the QGV point with highest BW according
> + * to BSpec.
> + */
Isn't the QGV with the highest bandwidth constant? Can we just figure
it out once at startup and then set it directly here instead of
re-finding it each commit?
> + if (!data_rate && !num_active_planes) {
> + DRM_DEBUG_KMS("No SAGV, using old QGV mask\n");
> + allowed_points = (~dev_priv->qgv_points_mask) & mask;
> + } else {
> + allowed_points = 1 << max_bw_point;
> + DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n",
> + max_bw_point);
> + }
> + }
> + /*
> + * We store the ones which need to be masked as that is what PCode
> + * actually accepts as a parameter.
> + */
> + state->qgv_points_mask = (~allowed_points) & mask;
> +
> + DRM_DEBUG_KMS("New state %p qgv mask %x\n",
> + state, state->qgv_points_mask);
> +
> + /*
> + * If the actual mask had changed we need to make sure that
> + * the commits are serialized(in case this is a nomodeset, nonblocking)
> + */
> + if (state->qgv_points_mask != dev_priv->qgv_points_mask) {
> + ret = intel_atomic_serialize_global_state(state);
> + if (ret) {
> + DRM_DEBUG_KMS("Could not serialize global state\n");
> + return ret;
> + }
> + }
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> index 9db10af012f4..66bf9bc10b73 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -28,5 +28,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
> int intel_bw_atomic_check(struct intel_atomic_state *state);
> void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> const struct intel_crtc_state *crtc_state);
> +int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> + u32 points_mask);
>
> #endif /* __INTEL_BW_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7ea1e7518ab6..71f6aaa1f6b9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14744,6 +14744,80 @@ static void intel_atomic_cleanup_work(struct work_struct *work)
> intel_atomic_helper_free_state(i915);
> }
>
> +static void intel_qgv_points_mask(struct intel_atomic_state *state)
> +{
> + struct drm_device *dev = state->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + int ret;
> + u32 new_mask = dev_priv->qgv_points_mask | state->qgv_points_mask;
> + unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
> + unsigned int mask = (1 << num_qgv_points) - 1;
> +
> + /*
> + * As we don't know initial hardware state during initial commit
> + * we should not do anything, until we actually figure out,
> + * what are the qgv points to mask.
> + */
> + if (!new_mask)
> + return;
> +
> + WARN_ON(new_mask == mask);
> +
> + /*
> + * Just return if we can't control SAGV or don't have it.
> + */
> + if (!intel_has_sagv(dev_priv))
> + return;
> +
> + /*
> + * Restrict required qgv points before updating the configuration.
> + * According to BSpec we can't mask and unmask qgv points at the same
> + * time. Also masking should be done before updating the configuration
> + * and unmasking afterwards.
> + */
> + ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> + if (ret < 0)
> + DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n",
> + ret);
> + else
> + dev_priv->qgv_points_mask = new_mask;
> +}
> +
> +static void intel_qgv_points_unmask(struct intel_atomic_state *state)
> +{
> + struct drm_device *dev = state->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + int ret;
> + u32 new_mask = dev_priv->qgv_points_mask & state->qgv_points_mask;
> +
> + /*
> + * As we don't know initial hardware state during initial commit
> + * we should not do anything, until we actually figure out,
> + * what are the qgv points to mask.
> + */
> + if (!new_mask)
> + return;
> +
> + /*
> + * Just return if we can't control SAGV or don't have it.
> + */
> + if (!intel_has_sagv(dev_priv))
> + return;
> +
> + /*
> + * Allow required qgv points after updating the configuration.
> + * According to BSpec we can't mask and unmask qgv points at the same
> + * time. Also masking should be done before updating the configuration
> + * and unmasking afterwards.
> + */
> + ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> + if (ret < 0)
> + DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n",
> + ret);
> + else
> + dev_priv->qgv_points_mask = new_mask;
> +}
> +
> static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> {
> struct drm_device *dev = state->base.dev;
> @@ -14771,6 +14845,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> }
> }
>
> + if ((INTEL_GEN(dev_priv) >= 11))
> + intel_qgv_points_mask(state);
> +
> intel_commit_modeset_disables(state);
>
> /* FIXME: Eventually get rid of our crtc->config pointer */
> @@ -14789,8 +14866,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> * SKL workaround: bspec recommends we disable the SAGV when we
> * have more then one pipe enabled
> */
> - if (!intel_can_enable_sagv(state))
> - intel_disable_sagv(dev_priv);
> + if (INTEL_GEN(dev_priv) < 11)
> + if (!intel_can_enable_sagv(state))
> + intel_disable_sagv(dev_priv);
>
> intel_modeset_verify_disabled(dev_priv, state);
> }
> @@ -14873,8 +14951,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> if (state->modeset)
> intel_verify_planes(state);
>
> - if (state->modeset && intel_can_enable_sagv(state))
> - intel_enable_sagv(dev_priv);
> + if (INTEL_GEN(dev_priv) < 11) {
> + if (state->modeset && intel_can_enable_sagv(state))
> + intel_enable_sagv(dev_priv);
> + } else
> + intel_qgv_points_unmask(state);
>
> drm_atomic_helper_commit_hw_done(&state->base);
>
> @@ -14962,7 +15043,18 @@ static int intel_atomic_commit(struct drm_device *dev,
> {
> struct intel_atomic_state *state = to_intel_atomic_state(_state);
> struct drm_i915_private *dev_priv = to_i915(dev);
> - int ret = 0;
> + struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> + int ret = 0, i;
> + bool any_ms = false;
> + struct intel_crtc *crtc;
> +
> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> + new_crtc_state, i) {
> + if (needs_modeset(new_crtc_state)) {
> + any_ms = true;
> + break;
> + }
> + }
I think we already have this in state->modeset.
>
> state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
>
> @@ -15021,7 +15113,7 @@ static int intel_atomic_commit(struct drm_device *dev,
> intel_shared_dpll_swap_state(state);
> intel_atomic_track_fbs(state);
>
> - if (state->global_state_changed) {
> + if (state->global_state_changed && any_ms) {
> assert_global_state_locked(dev_priv);
>
> memcpy(dev_priv->min_cdclk, state->min_cdclk,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index fb274538af23..896b13bc4494 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -528,6 +528,9 @@ struct intel_atomic_state {
> struct i915_sw_fence commit_ready;
>
> struct llist_node freed;
> +
> + /* Gen11+ only */
> + u32 qgv_points_mask;
> };
>
> struct intel_plane_state {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4f4e2e839513..9924390cb94b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1243,11 +1243,13 @@ struct drm_i915_private {
> } dram_info;
>
> struct intel_bw_info {
> - unsigned int deratedbw[3]; /* for each QGV point */
> + unsigned int deratedbw[NUM_SAGV_POINTS]; /* for each QGV point */
> u8 num_qgv_points;
> u8 num_planes;
> } max_bw[6];
>
> + u32 qgv_points_mask;
> +
> struct drm_private_obj bw_obj;
>
> struct intel_runtime_pm runtime_pm;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a607ea520829..6d6ecf1d9f6b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8951,6 +8951,9 @@ enum {
> #define VLV_RENDER_C0_COUNT _MMIO(0x138118)
> #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
>
> +/* BSpec precisely defines this */
> +#define NUM_SAGV_POINTS 8
> +
Any specific reason this is in the reg file rather than either
i915_drv.h where it's used or something like intel_bw.h?
> #define GEN6_PCODE_MAILBOX _MMIO(0x138124)
> #define GEN6_PCODE_READY (1 << 31)
> #define GEN6_PCODE_ERROR_MASK 0xFF
> @@ -8961,6 +8964,8 @@ enum {
> #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
> #define GEN7_PCODE_TIMEOUT 0x2
> #define GEN7_PCODE_ILLEGAL_DATA 0x3
> +#define GEN11_PCODE_MAIL_BOX_LOCKED 0x6
> +#define GEN11_PCODE_REJECTED 0x11
> #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
> #define GEN6_PCODE_WRITE_RC6VIDS 0x4
> #define GEN6_PCODE_READ_RC6VIDS 0x5
> @@ -8982,6 +8987,7 @@ enum {
> #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
> #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
> #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
> +#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
> #define GEN6_PCODE_READ_D_COMP 0x10
> #define GEN6_PCODE_WRITE_D_COMP 0x11
> #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
> @@ -8994,6 +9000,8 @@ enum {
> #define GEN9_SAGV_IS_DISABLED 0x1
> #define GEN9_SAGV_ENABLE 0x3
> #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
> +#define GEN11_PCODE_POINTS_RESTRICTED 0x0
> +#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
> #define GEN6_PCODE_DATA _MMIO(0x138128)
> #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
> #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c792dd168742..10816f3e29f0 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3617,13 +3617,9 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
> return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
> }
>
> -static bool
> +bool
> intel_has_sagv(struct drm_i915_private *dev_priv)
> {
> - /* HACK! */
> - if (IS_GEN(dev_priv, 12))
> - return false;
> -
> return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
> dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
> }
> @@ -3839,7 +3835,7 @@ static void icl_set_sagv_mask(struct intel_atomic_state *state)
> if (flags & DRM_MODE_FLAG_INTERLACE)
> continue;
>
> - if (!new_crtc_state->base.active)
> + if (!new_crtc_state->hw.enable)
> continue;
Looks like this was a bug in the previous patch. Any specific reason
we're switching from active to enable?
>
> can_sagv = true;
> @@ -3886,6 +3882,9 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> else
> skl_set_sagv_mask(state);
>
> + DRM_DEBUG_KMS("Crtc sagv masks, state %x global state %x\n",
> + state->crtc_sagv_mask,
> + dev_priv->crtc_sagv_mask);
> /*
> * For SAGV we need to account all the pipes,
> * not only the ones which are in state currently.
> @@ -4340,7 +4339,7 @@ static int
> tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
> struct skl_ddb_allocation *ddb /* out */)
> {
> - struct drm_crtc *crtc = crtc_state->base.crtc;
> + struct drm_crtc *crtc = crtc_state->uapi.crtc;
Also a bug in the previous patch.
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
> @@ -4833,7 +4832,6 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> struct skl_wm_level *result /* out */)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> - u32 latency = dev_priv->wm.skl_latency[level];
Mentioned on previous patch.
> uint_fixed_16_16_t method1, method2;
> uint_fixed_16_16_t selected_result;
> u32 res_blocks, res_lines, min_ddb_alloc = 0;
> @@ -5707,6 +5705,7 @@ static void tgl_set_sagv_mask(struct intel_atomic_state *state)
> ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
> if (!ret) {
> int pipe_bit = BIT(crtc->pipe);
> +
> state->crtc_sagv_mask |= pipe_bit;
Unrelated change.
> }
> }
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index b579c724b915..53275860731a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -43,6 +43,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> bool intel_can_enable_sagv(struct intel_atomic_state *state);
> +bool intel_has_sagv(struct drm_i915_private *dev_priv);
> int intel_enable_sagv(struct drm_i915_private *dev_priv);
> int intel_disable_sagv(struct drm_i915_private *dev_priv);
> bool skl_wm_level_equals(const struct skl_wm_level *l1,
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index e06b35b844a0..ff9dbed094d8 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -371,6 +371,29 @@ static inline int gen7_check_mailbox_status(u32 mbox)
> }
> }
>
> +static inline int gen11_check_mailbox_status(u32 mbox)
> +{
> + switch (mbox & GEN6_PCODE_ERROR_MASK) {
> + case GEN6_PCODE_SUCCESS:
> + return 0;
> + case GEN6_PCODE_ILLEGAL_CMD:
> + return -ENXIO;
> + case GEN7_PCODE_TIMEOUT:
> + return -ETIMEDOUT;
> + case GEN7_PCODE_ILLEGAL_DATA:
> + return -EINVAL;
> + case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
> + return -EOVERFLOW;
> + case GEN11_PCODE_MAIL_BOX_LOCKED:
> + return -EAGAIN;
> + case GEN11_PCODE_REJECTED:
> + return -EACCES;
> + default:
> + MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
> + return 0;
> + }
> +}
> +
> static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
> u32 mbox, u32 *val, u32 *val1,
> int fast_timeout_us,
> @@ -408,7 +431,9 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
> if (is_read && val1)
> *val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
>
> - if (INTEL_GEN(i915) > 6)
> + if (INTEL_GEN(i915) >= 11)
> + return gen11_check_mailbox_status(mbox);
> + else if (INTEL_GEN(i915) > 6)
> return gen7_check_mailbox_status(mbox);
> else
> return gen6_check_mailbox_status(mbox);
> diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h
> index 7fb95745a444..14627ace99ae 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.h
> +++ b/drivers/gpu/drm/i915/intel_sideband.h
> @@ -137,5 +137,4 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
>
> int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
> u32 reply_mask, u32 reply, int timeout_base_ms);
> -
> #endif /* _INTEL_SIDEBAND_H */
Unrelated change.
In general, I wonder if we could break this patch up a bit more. It
seems like there are a lot of moving pieces here which makes it a bit
harder to review.
Matt
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v10 1/2] drm/i915: Refactor intel_can_enable_sagv
@ 2019-11-12 16:04 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 25+ messages in thread
From: Lisovskiy, Stanislav @ 2019-11-12 16:04 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: intel-gfx
On Mon, 2019-11-11 at 16:15 -0800, Matt Roper wrote:
> On Thu, Nov 07, 2019 at 05:30:36PM +0200, Stanislav Lisovskiy wrote:
> > Currently intel_can_enable_sagv function contains
> > a mix of workarounds for different platforms
> > some of them are not valid for gens >= 11 already,
> > so lets split it into separate functions.
> >
> > v2:
> > - Rework watermark calculation algorithm to
> > attempt to calculate Level 0 watermark
> > with added sagv block time latency and
> > check if it fits in DBuf in order to
> > determine if SAGV can be enabled already
> > at this stage, just as BSpec 49325 states.
> > if that fails rollback to usual Level 0
> > latency and disable SAGV.
> > - Remove unneeded tabs(James Ausmus)
> >
> > v3: Rebased the patch
> >
> > v4: - Added back interlaced check for Gen12 and
> > added separate function for TGL SAGV check
> > (thanks to James Ausmus for spotting)
> > - Removed unneeded gen check
> > - Extracted Gen12 SAGV decision making code
> > to a separate function from skl_compute_wm
> >
> > v5: - Added SAGV global state to dev_priv, because
> > we need to track all pipes, not only those
> > in atomic state. Each pipe has now correspondent
> > bit mask reflecting, whether it can tolerate
> > SAGV or not(thanks to Ville Syrjala for suggestions).
> > - Now using active flag instead of enable in crc
> > usage check.
> >
> > v6: - Fixed rebase conflicts
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 4 +
> > .../drm/i915/display/intel_display_types.h | 9 +
> > drivers/gpu/drm/i915/i915_drv.h | 6 +
> > drivers/gpu/drm/i915/intel_pm.c | 296
> > +++++++++++++++++-
> > 4 files changed, 303 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 876fc25968bf..7ea1e7518ab6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -14855,6 +14855,10 @@ static void
> > intel_atomic_commit_tail(struct intel_atomic_state *state)
> > if (dev_priv->display.optimize_watermarks)
> > dev_priv->display.optimize_watermarks(state,
> > new_crtc_
> > state);
> > + if (state->crtc_sagv_mask & BIT(crtc->pipe))
> > + dev_priv->crtc_sagv_mask |= BIT(crtc->pipe);
> > + else
> > + dev_priv->crtc_sagv_mask &= ~BIT(crtc->pipe);
> > }
> >
> > for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state, new_crtc_state, i) {
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index fadd9853f966..fb274538af23 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -490,6 +490,14 @@ struct intel_atomic_state {
> > */
> > u8 active_pipe_changes;
> >
> > + /*
> > + * Contains a mask which reflects whether correspondent pipe
> > + * can tolerate SAGV or not, so that we can make a decision
> > + * at atomic_commit_tail stage, whether we enable it or not
> > + * based on global state in dev_priv.
> > + */
> > + u32 crtc_sagv_mask;
> > +
> > u8 active_pipes;
> > /* minimum acceptable cdclk for each pipe */
> > int min_cdclk[I915_MAX_PIPES];
> > @@ -670,6 +678,7 @@ struct skl_plane_wm {
> > struct skl_wm_level wm[8];
> > struct skl_wm_level uv_wm[8];
> > struct skl_wm_level trans_wm;
> > + struct skl_wm_level sagv_wm0;
> > bool is_planar;
> > };
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 7e0f67babe20..4f4e2e839513 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1176,6 +1176,12 @@ struct drm_i915_private {
> >
> > u32 sagv_block_time_us;
> >
> > + /*
> > + * Contains a bit mask, whether correspondent
> > + * pipe allows SAGV or not.
> > + */
> > + u32 crtc_sagv_mask;
> > +
> > struct {
> > /*
> > * Raw watermark latency values:
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 2d389e437e87..c792dd168742 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3740,7 +3740,7 @@ intel_disable_sagv(struct drm_i915_private
> > *dev_priv)
> > return 0;
> > }
> >
> > -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > +static void skl_set_sagv_mask(struct intel_atomic_state *state)
> > {
> > struct drm_device *dev = state->base.dev;
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > @@ -3750,21 +3750,23 @@ bool intel_can_enable_sagv(struct
> > intel_atomic_state *state)
> > enum pipe pipe;
> > int level, latency;
> >
> > + state->crtc_sagv_mask = 0;
> > +
> > if (!intel_has_sagv(dev_priv))
> > - return false;
> > + return;
> >
> > /*
> > * If there are no active CRTCs, no additional checks need be
> > performed
> > */
> > if (hweight8(state->active_pipes) == 0)
> > - return true;
> > + return;
> >
> > /*
> > * SKL+ workaround: bspec recommends we disable SAGV when we
> > have
> > * more then one pipe enabled
> > */
> > if (hweight8(state->active_pipes) > 1)
> > - return false;
> > + return;
> >
> > /* Since we're now guaranteed to only have one active CRTC...
> > */
> > pipe = ffs(state->active_pipes) - 1;
> > @@ -3772,7 +3774,7 @@ bool intel_can_enable_sagv(struct
> > intel_atomic_state *state)
> > crtc_state = to_intel_crtc_state(crtc->base.state);
> >
> > if (crtc_state->hw.adjusted_mode.flags &
> > DRM_MODE_FLAG_INTERLACE)
> > - return false;
> > + return;
> >
> > for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > struct skl_plane_wm *wm =
> > @@ -3800,9 +3802,127 @@ bool intel_can_enable_sagv(struct
> > intel_atomic_state *state)
> > * can't enable SAGV.
> > */
> > if (latency < dev_priv->sagv_block_time_us)
> > - return false;
> > + return;
> > }
> >
> > + state->crtc_sagv_mask |= BIT(crtc->pipe);
> > +}
> > +
> > +static void tgl_set_sagv_mask(struct intel_atomic_state *state);
> > +
> > +static void icl_set_sagv_mask(struct intel_atomic_state *state)
> > +{
> > + struct drm_device *dev = state->base.dev;
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + struct intel_crtc *crtc;
> > + struct intel_crtc_state *new_crtc_state;
> > + int level, latency;
> > + int i;
> > + int plane_id;
> > +
> > + state->crtc_sagv_mask = 0;
> > +
> > + if (!intel_has_sagv(dev_priv))
> > + return;
> > +
> > + /*
> > + * If there are no active CRTCs, no additional checks need be
> > performed
> > + */
> > + if (hweight8(state->active_pipes) == 0)
> > + return;
> > +
> > + for_each_new_intel_crtc_in_state(state, crtc,
> > + new_crtc_state, i) {
> > + unsigned int flags = crtc->base.state-
> > >adjusted_mode.flags;
> > + bool can_sagv;
> > +
> > + if (flags & DRM_MODE_FLAG_INTERLACE)
> > + continue;
> > +
> > + if (!new_crtc_state->base.active)
> > + continue;
> > +
> > + can_sagv = true;
> > + for_each_plane_id_on_crtc(crtc, plane_id) {
> > + struct skl_plane_wm *wm =
> > + &new_crtc_state-
> > >wm.skl.optimal.planes[plane_id];
> > +
> > + /* Skip this plane if it's not enabled */
> > + if (!wm->wm[0].plane_en)
> > + continue;
> > +
> > + /* Find the highest enabled wm level for this
> > plane */
> > + for (level = ilk_wm_max_level(dev_priv);
> > + !wm->wm[level].plane_en; --level) {
> > + }
> > +
> > + latency = dev_priv->wm.skl_latency[level];
> > +
> > + /*
> > + * If any of the planes on this pipe don't
> > enable
> > + * wm levels that incur memory latencies higher
> > than
> > + * sagv_block_time_us we can't enable SAGV.
> > + */
> > + if (latency < dev_priv->sagv_block_time_us) {
> > + can_sagv = false;
> > + break;
> > + }
>
> I find the wording of the bspec ("if any enabled plane will not be
> able
> to enable watermarks for memory latency >= SAGV block time") in this
> area somewhat ambiguous. To me that wording sounds like they want us
> to
> calculate the watermarks one more time, but using the SAGV blocking
> time
> rather than any of the 8 latency values we received from the pcode --
> -
> if the calculated watermark value for that "sagv level" fits within
> the
> DDB allocation then we can enable SAGV, otherwise we can't.
>
> Your approach here somewhat approximates that. If the highest
> watermark
> level we enabled had a latency higher than the SAGV blocking time,
> then
> we automatically know we also would have had a valid watermark value
> for
> a lower sagv latency. But if the highest latency we enabled has a
> lower
> latency, we can't say for certain whether the SAGV's blocking time
> would
> have led to valid or invalid watermarks. If the first watermark
> level
> we failed on also had a lower latency than the SAGV time then we can
> conclude that the SAGV can't be enabled. But if the next level up
> had a
> latency higher than the blocking time (i.e., good < SAGV < bad), we
> can't really tell whether SAGV was possible without actually doing
> the
> extra watermark calculation.
>
> But even given the above, the bspec suggestion seems somewhat
> surprising
> to me. Intuitively it seems like SAGV would be introducing an
> additional delay on top of the existing memory fetch latency, not
> replacing the latency entirely. Intuitively the algorithm suggested
> for
> TGL makes sense to me (i.e., add the SAGV's extra delay to the WM0
> latency to ensure that regular latency plus an extra SAGV delay
> doesn't
> lead us to run dry), but that's not what the bspec calls for on ICL.
> I'm not really sure whether that's truly an intentional behavior
> change
> between platforms or whether the TGL bspec section does just a better
> job of explaining what was supposed to be done and clarifying the
> language.
>
> Anyway, we should probably trust the bspec for now, so it seems to me
> like we should add a "fake" watermark level associated with the SAGV
> block time and explicitly calculate that as enabled/disabled anytime
> we
> have a good < SAGV < bad situation.
I totally agree, had same questions during implementation, however
still I simply stick to what has been defined in a spec and also done
for previous platforms, as this is basically the same how it's done
now. What I did is mostly just splitting the code to get rid of some
skl specific ugly workaround there.
Regarding "fake" watermark level, as you might noticed now I would be
storing both sagv_wm and "normal" wm level to let intel_can_enable_sagv
to make decision later based on that(mostly decision now is simply
dictated by whether we could fit this into dbuf or not).
Regarding intel_can_enable_sagv implementation I will reply inline
also below.
>
> > + }
> > + if (can_sagv)
> > + state->crtc_sagv_mask |= BIT(crtc->pipe);
> > + }
> > +}
> > +
> > +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > +{
> > + struct drm_device *dev = state->base.dev;
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + enum pipe pipe;
> > +
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + tgl_set_sagv_mask(state);
> > + else if (INTEL_GEN(dev_priv) == 11)
> > + icl_set_sagv_mask(state);
> > + else
> > + skl_set_sagv_mask(state);
> > +
> > + /*
> > + * For SAGV we need to account all the pipes,
> > + * not only the ones which are in state currently.
> > + */
> > + for_each_pipe(dev_priv, pipe) {
> > + unsigned int active_pipes;
> > + /*
> > + * Figure out if we are changing active pipes here
> > + * then after commit dev_priv->active_pipes will
> > + * anyway be assigned to state->active_pipes.
> > + */
> > + if (state->active_pipe_changes)
> > + active_pipes = state->active_pipes;
> > + else
> > + active_pipes = dev_priv->active_pipes;
> > +
> > + /* Skip if pipe is inactive */
> > + if (!(BIT(pipe) & active_pipes))
> > + continue;
> > +
> > + /*
> > + * Pipe can be active in this state or in dev_priv
> > + * as we haven't committed thise changes yet(and we
> > shouldn't)
> > + * - we need to check both.
> > + */
> > + if (state->active_pipe_changes & BIT(pipe)) {
> > + bool state_sagv_masked = \
> > + (BIT(pipe) & state->crtc_sagv_mask) ==
> > 0;
> > + if (state_sagv_masked)
> > + return false;
> > + } else {
> > + bool sagv_masked = \
> > + (BIT(pipe) & dev_priv->crtc_sagv_mask)
> > == 0;
>
> If we're not changing which pipes are active, then we didn't globally
> lock everything at the beginning of this atomic transaction; we can
> have
> racing commits against different CRTC's. So when you look at
> dev_priv->crtc_sagv_mask here, the value might change immediately
> afterward if a commit on a different CRTC completed in the meantime.
>
> I don't think we want to look at other CRTC's outside our current
> transaction here. We should just figure out whether our own CRTC's
> are
> okay with SAGV or not. Then in the commit phase we'd need to grab
> some
> kind of SAGV lock, combine our local "SAGV okay" with the global
> "SAGV
> okay" and enable/disable as necessary.
>
> Some kind of reference-counting mechanism might make this
> simpler...is
> there any way we could tie this in with power domains (e.g., adding a
> "SAGV off" power domain and power well that we grab during commit
> when
> we've calculated that our own crtcs can't cope with SAGV latency)?
>
Yes, however the problem is that we need to know whether we can enable
SAGV or not already on calculation stage(i.e during
intel_atomic_check). Bandwidth checking code calls this as according to
BSpec if SAGV can't be enabled - it should stick to the highest
bandwidth point only. Also during ddb/wm calculation we call this check
to understand which wm level we should fit into dbuf.
And we can't make this decision based on this state only as it might
not contain all the crtcs - however if any of the pipes, even those
which are not in this state can't tolerate SAGV - then we can't enable
it anyway, even if those crtc in this state can.
That is why I have to iterate through all of the crtcs. However it is
good that you pointed out that those might change on the fly, I guess
we need to protect those from being changed by other commits.
We already do something similar by using serializing global state from
Ville, i.e once we add detect that we are changing some dev_priv global
state variables we mark that this commit should be serialized by adding
all the crtcs to the state.
>
> > + if (sagv_masked)
> > + return false;
> > + }
> > + }
> > return true;
> > }
> >
> > @@ -3925,6 +4045,7 @@ static int skl_compute_wm_params(const struct
> > intel_crtc_state *crtc_state,
> > int color_plane);
> > static void skl_compute_plane_wm(const struct intel_crtc_state
> > *crtc_state,
> > int level,
> > + u32 latency,
> > const struct skl_wm_params *wp,
> > const struct skl_wm_level
> > *result_prev,
> > struct skl_wm_level *result /* out
> > */);
> > @@ -3947,7 +4068,10 @@ skl_cursor_allocation(const struct
> > intel_crtc_state *crtc_state,
> > WARN_ON(ret);
> >
> > for (level = 0; level <= max_level; level++) {
> > - skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
> > + u32 latency = dev_priv->wm.skl_latency[level];
> > +
> > + skl_compute_plane_wm(crtc_state, level, latency, &wp,
> > &wm, &wm);
> > +
> > if (wm.min_ddb_alloc == U16_MAX)
> > break;
> >
> > @@ -4212,6 +4336,68 @@ icl_get_total_relative_data_rate(struct
> > intel_crtc_state *crtc_state,
> > return total_data_rate;
> > }
> >
> > +static int
> > +tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
> > + struct skl_ddb_allocation *ddb /* out */)
> > +{
> > + struct drm_crtc *crtc = crtc_state->base.crtc;
> > + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > + struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
> > + u16 alloc_size;
> > + u16 total[I915_MAX_PLANES] = {};
> > + u64 total_data_rate;
> > + enum plane_id plane_id;
> > + int num_active;
> > + u64 plane_data_rate[I915_MAX_PLANES] = {};
> > + u32 blocks;
> > +
> > + /*
> > + * No need to check gen here, we call this only for gen12
> > + */
> > + total_data_rate =
> > + icl_get_total_relative_data_rate(crtc_state,
> > + plane_data_rate);
> > +
> > + skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
> > + total_data_rate,
> > + ddb, alloc, &num_active);
> > + alloc_size = skl_ddb_entry_size(alloc);
> > + if (alloc_size == 0)
> > + return -ENOSPC;
> > +
> > + /* Allocate fixed number of blocks for cursor. */
> > + total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state,
> > num_active);
> > + alloc_size -= total[PLANE_CURSOR];
> > + crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
> > + alloc->end - total[PLANE_CURSOR];
> > + crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
> > +
> > + /*
> > + * Do check if we can fit L0 + sagv_block_time and
> > + * disable SAGV if we can't.
> > + */
> > + blocks = 0;
> > + for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > + const struct skl_plane_wm *wm =
> > + &crtc_state->wm.skl.optimal.planes[plane_id];
> > +
> > + if (plane_id == PLANE_CURSOR) {
> > + if (WARN_ON(wm->sagv_wm0.min_ddb_alloc >
> > + total[PLANE_CURSOR])) {
> > + blocks = U32_MAX;
> > + break;
> > + }
> > + continue;
> > + }
> > +
> > + blocks += wm->sagv_wm0.min_ddb_alloc;
> > + if (blocks > alloc_size)
> > + return -ENOSPC;
> > + }
> > + return 0;
> > +}
> > +
> > static int
> > skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
> > struct skl_ddb_allocation *ddb /* out */)
> > @@ -4641,6 +4827,7 @@ static bool skl_wm_has_lines(struct
> > drm_i915_private *dev_priv, int level)
> >
> > static void skl_compute_plane_wm(const struct intel_crtc_state
> > *crtc_state,
> > int level,
> > + u32 latency,
> > const struct skl_wm_params *wp,
> > const struct skl_wm_level
> > *result_prev,
> > struct skl_wm_level *result /* out */)
>
> It doesn't look like this latency parameter gets used (it gets masked
> by
> a local latency variable still.
Actually no, there are no other latency variables declared in
skl_compute_plane_wm(did I accidentally fix this some how?) as I see.
Anyway thank you for a really precise review.
>
>
> > @@ -4767,20 +4954,45 @@ static void skl_compute_plane_wm(const
> > struct intel_crtc_state *crtc_state,
> > static void
> > skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> > const struct skl_wm_params *wm_params,
> > - struct skl_wm_level *levels)
> > + struct skl_plane_wm *plane_wm,
> > + bool yuv)
> > {
> > struct drm_i915_private *dev_priv = to_i915(crtc_state-
> > >uapi.crtc->dev);
> > int level, max_level = ilk_wm_max_level(dev_priv);
> > + /*
> > + * Check which kind of plane is it and based on that calculate
> > + * correspondent WM levels.
> > + */
> > + struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm-
> > >wm;
> > struct skl_wm_level *result_prev = &levels[0];
> >
> > for (level = 0; level <= max_level; level++) {
> > struct skl_wm_level *result = &levels[level];
> > + u32 latency = dev_priv->wm.skl_latency[level];
> >
> > - skl_compute_plane_wm(crtc_state, level, wm_params,
> > - result_prev, result);
> > + skl_compute_plane_wm(crtc_state, level, latency,
> > + wm_params, result_prev, result);
> >
> > result_prev = result;
> > }
> > + /*
> > + * For Gen12 if it is an L0 we need to also
> > + * consider sagv_block_time when calculating
> > + * L0 watermark - we will need that when making
> > + * a decision whether enable SAGV or not.
> > + * For older gens we agreed to copy L0 value for
> > + * compatibility.
> > + */
> > + if ((INTEL_GEN(dev_priv) >= 12)) {
> > + u32 latency = dev_priv->wm.skl_latency[0];
> > +
> > + latency += dev_priv->sagv_block_time_us;
> > + skl_compute_plane_wm(crtc_state, 0, latency,
> > + wm_params, &levels[0],
> > + &plane_wm->sagv_wm0);
> > + } else
> > + memcpy(&plane_wm->sagv_wm0, &levels[0],
> > + sizeof(struct skl_wm_level));
> > }
> >
> > static u32
> > @@ -4873,7 +5085,7 @@ static int skl_build_plane_wm_single(struct
> > intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > - skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> > + skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
> > skl_compute_transition_wm(crtc_state, &wm_params, wm);
> >
> > return 0;
> > @@ -4895,7 +5107,7 @@ static int skl_build_plane_wm_uv(struct
> > intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > - skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
> > + skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
> >
> > return 0;
> > }
> > @@ -5167,6 +5379,8 @@ skl_ddb_add_affected_planes(const struct
> > intel_crtc_state *old_crtc_state,
> > return 0;
> > }
> >
> > +static void tgl_set_sagv_wm0(struct intel_atomic_state *state);
> > +
> > static int
> > skl_compute_ddb(struct intel_atomic_state *state)
> > {
> > @@ -5177,6 +5391,11 @@ skl_compute_ddb(struct intel_atomic_state
> > *state)
> > struct intel_crtc *crtc;
> > int ret, i;
> >
> > + /* For Gen12+ for SAGV we have a special L0 wm values */
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + if (intel_can_enable_sagv(state))
> > + tgl_set_sagv_wm0(state);
> > +
> > memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
> >
> > for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state,
> > @@ -5443,6 +5662,56 @@ static int skl_wm_add_affected_planes(struct
> > intel_atomic_state *state,
> > return 0;
> > }
> >
> > +void tgl_set_sagv_wm0(struct intel_atomic_state *state)
> > +{
> > + struct intel_crtc *crtc;
> > + struct intel_crtc_state *new_crtc_state;
> > + struct intel_crtc_state *old_crtc_state;
> > + struct drm_device *dev = state->base.dev;
> > + const struct drm_i915_private *dev_priv = to_i915(dev);
> > + int i;
> > +
> > + /*
> > + * If we determined that we can actually enable SAGV, then
> > + * actually use those levels tgl_check_pipe_fits_sagv_wm
> > + * has already taken care of checking if L0 + sagv block time
> > + * fits into ddb.
> > + */
> > + for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state,
> > + new_crtc_state, i) {
> > + struct intel_plane *plane;
> > +
> > + for_each_intel_plane_on_crtc(&dev_priv->drm, crtc,
> > plane) {
> > + enum plane_id plane_id = plane->id;
> > +
> > + struct skl_plane_wm *plane_wm = \
> > + &new_crtc_state-
> > >wm.skl.optimal.planes[plane_id];
> > + struct skl_wm_level *sagv_wm0 = &plane_wm-
> > >sagv_wm0;
> > + struct skl_wm_level *l0_wm0 = &plane_wm->wm[0];
> > +
> > + memcpy(l0_wm0, sagv_wm0, sizeof(struct
> > skl_wm_level));
> > + }
> > + }
> > +}
> > +
> > +static void tgl_set_sagv_mask(struct intel_atomic_state *state)
> > +{
> > + struct intel_crtc *crtc;
> > + struct intel_crtc_state *new_crtc_state;
> > + struct intel_crtc_state *old_crtc_state;
> > + struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
> > + int ret, i;
> > +
> > + for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state,
> > + new_crtc_state, i) {
> > + ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
> > + if (!ret) {
> > + int pipe_bit = BIT(crtc->pipe);
> > + state->crtc_sagv_mask |= pipe_bit;
> > + }
> > + }
> > +}
> > +
> > static int
> > skl_compute_wm(struct intel_atomic_state *state)
> > {
> > @@ -5455,6 +5724,9 @@ skl_compute_wm(struct intel_atomic_state
> > *state)
> > /* Clear all dirty flags */
> > results->dirty_pipes = 0;
> >
> > + /* If we exit before check is done */
> > + state->crtc_sagv_mask = 0;
> > +
> > ret = skl_ddb_add_affected_pipes(state);
> > if (ret)
> > return ret;
> > --
> > 2.17.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH v10 1/2] drm/i915: Refactor intel_can_enable_sagv
@ 2019-11-12 16:04 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 25+ messages in thread
From: Lisovskiy, Stanislav @ 2019-11-12 16:04 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: intel-gfx
On Mon, 2019-11-11 at 16:15 -0800, Matt Roper wrote:
> On Thu, Nov 07, 2019 at 05:30:36PM +0200, Stanislav Lisovskiy wrote:
> > Currently intel_can_enable_sagv function contains
> > a mix of workarounds for different platforms
> > some of them are not valid for gens >= 11 already,
> > so lets split it into separate functions.
> >
> > v2:
> > - Rework watermark calculation algorithm to
> > attempt to calculate Level 0 watermark
> > with added sagv block time latency and
> > check if it fits in DBuf in order to
> > determine if SAGV can be enabled already
> > at this stage, just as BSpec 49325 states.
> > if that fails rollback to usual Level 0
> > latency and disable SAGV.
> > - Remove unneeded tabs(James Ausmus)
> >
> > v3: Rebased the patch
> >
> > v4: - Added back interlaced check for Gen12 and
> > added separate function for TGL SAGV check
> > (thanks to James Ausmus for spotting)
> > - Removed unneeded gen check
> > - Extracted Gen12 SAGV decision making code
> > to a separate function from skl_compute_wm
> >
> > v5: - Added SAGV global state to dev_priv, because
> > we need to track all pipes, not only those
> > in atomic state. Each pipe has now correspondent
> > bit mask reflecting, whether it can tolerate
> > SAGV or not(thanks to Ville Syrjala for suggestions).
> > - Now using active flag instead of enable in crc
> > usage check.
> >
> > v6: - Fixed rebase conflicts
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 4 +
> > .../drm/i915/display/intel_display_types.h | 9 +
> > drivers/gpu/drm/i915/i915_drv.h | 6 +
> > drivers/gpu/drm/i915/intel_pm.c | 296
> > +++++++++++++++++-
> > 4 files changed, 303 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 876fc25968bf..7ea1e7518ab6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -14855,6 +14855,10 @@ static void
> > intel_atomic_commit_tail(struct intel_atomic_state *state)
> > if (dev_priv->display.optimize_watermarks)
> > dev_priv->display.optimize_watermarks(state,
> > new_crtc_
> > state);
> > + if (state->crtc_sagv_mask & BIT(crtc->pipe))
> > + dev_priv->crtc_sagv_mask |= BIT(crtc->pipe);
> > + else
> > + dev_priv->crtc_sagv_mask &= ~BIT(crtc->pipe);
> > }
> >
> > for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state, new_crtc_state, i) {
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index fadd9853f966..fb274538af23 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -490,6 +490,14 @@ struct intel_atomic_state {
> > */
> > u8 active_pipe_changes;
> >
> > + /*
> > + * Contains a mask which reflects whether correspondent pipe
> > + * can tolerate SAGV or not, so that we can make a decision
> > + * at atomic_commit_tail stage, whether we enable it or not
> > + * based on global state in dev_priv.
> > + */
> > + u32 crtc_sagv_mask;
> > +
> > u8 active_pipes;
> > /* minimum acceptable cdclk for each pipe */
> > int min_cdclk[I915_MAX_PIPES];
> > @@ -670,6 +678,7 @@ struct skl_plane_wm {
> > struct skl_wm_level wm[8];
> > struct skl_wm_level uv_wm[8];
> > struct skl_wm_level trans_wm;
> > + struct skl_wm_level sagv_wm0;
> > bool is_planar;
> > };
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 7e0f67babe20..4f4e2e839513 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1176,6 +1176,12 @@ struct drm_i915_private {
> >
> > u32 sagv_block_time_us;
> >
> > + /*
> > + * Contains a bit mask, whether correspondent
> > + * pipe allows SAGV or not.
> > + */
> > + u32 crtc_sagv_mask;
> > +
> > struct {
> > /*
> > * Raw watermark latency values:
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 2d389e437e87..c792dd168742 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3740,7 +3740,7 @@ intel_disable_sagv(struct drm_i915_private
> > *dev_priv)
> > return 0;
> > }
> >
> > -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > +static void skl_set_sagv_mask(struct intel_atomic_state *state)
> > {
> > struct drm_device *dev = state->base.dev;
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > @@ -3750,21 +3750,23 @@ bool intel_can_enable_sagv(struct
> > intel_atomic_state *state)
> > enum pipe pipe;
> > int level, latency;
> >
> > + state->crtc_sagv_mask = 0;
> > +
> > if (!intel_has_sagv(dev_priv))
> > - return false;
> > + return;
> >
> > /*
> > * If there are no active CRTCs, no additional checks need be
> > performed
> > */
> > if (hweight8(state->active_pipes) == 0)
> > - return true;
> > + return;
> >
> > /*
> > * SKL+ workaround: bspec recommends we disable SAGV when we
> > have
> > * more then one pipe enabled
> > */
> > if (hweight8(state->active_pipes) > 1)
> > - return false;
> > + return;
> >
> > /* Since we're now guaranteed to only have one active CRTC...
> > */
> > pipe = ffs(state->active_pipes) - 1;
> > @@ -3772,7 +3774,7 @@ bool intel_can_enable_sagv(struct
> > intel_atomic_state *state)
> > crtc_state = to_intel_crtc_state(crtc->base.state);
> >
> > if (crtc_state->hw.adjusted_mode.flags &
> > DRM_MODE_FLAG_INTERLACE)
> > - return false;
> > + return;
> >
> > for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > struct skl_plane_wm *wm =
> > @@ -3800,9 +3802,127 @@ bool intel_can_enable_sagv(struct
> > intel_atomic_state *state)
> > * can't enable SAGV.
> > */
> > if (latency < dev_priv->sagv_block_time_us)
> > - return false;
> > + return;
> > }
> >
> > + state->crtc_sagv_mask |= BIT(crtc->pipe);
> > +}
> > +
> > +static void tgl_set_sagv_mask(struct intel_atomic_state *state);
> > +
> > +static void icl_set_sagv_mask(struct intel_atomic_state *state)
> > +{
> > + struct drm_device *dev = state->base.dev;
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + struct intel_crtc *crtc;
> > + struct intel_crtc_state *new_crtc_state;
> > + int level, latency;
> > + int i;
> > + int plane_id;
> > +
> > + state->crtc_sagv_mask = 0;
> > +
> > + if (!intel_has_sagv(dev_priv))
> > + return;
> > +
> > + /*
> > + * If there are no active CRTCs, no additional checks need be
> > performed
> > + */
> > + if (hweight8(state->active_pipes) == 0)
> > + return;
> > +
> > + for_each_new_intel_crtc_in_state(state, crtc,
> > + new_crtc_state, i) {
> > + unsigned int flags = crtc->base.state-
> > >adjusted_mode.flags;
> > + bool can_sagv;
> > +
> > + if (flags & DRM_MODE_FLAG_INTERLACE)
> > + continue;
> > +
> > + if (!new_crtc_state->base.active)
> > + continue;
> > +
> > + can_sagv = true;
> > + for_each_plane_id_on_crtc(crtc, plane_id) {
> > + struct skl_plane_wm *wm =
> > + &new_crtc_state-
> > >wm.skl.optimal.planes[plane_id];
> > +
> > + /* Skip this plane if it's not enabled */
> > + if (!wm->wm[0].plane_en)
> > + continue;
> > +
> > + /* Find the highest enabled wm level for this
> > plane */
> > + for (level = ilk_wm_max_level(dev_priv);
> > + !wm->wm[level].plane_en; --level) {
> > + }
> > +
> > + latency = dev_priv->wm.skl_latency[level];
> > +
> > + /*
> > + * If any of the planes on this pipe don't
> > enable
> > + * wm levels that incur memory latencies higher
> > than
> > + * sagv_block_time_us we can't enable SAGV.
> > + */
> > + if (latency < dev_priv->sagv_block_time_us) {
> > + can_sagv = false;
> > + break;
> > + }
>
> I find the wording of the bspec ("if any enabled plane will not be
> able
> to enable watermarks for memory latency >= SAGV block time") in this
> area somewhat ambiguous. To me that wording sounds like they want us
> to
> calculate the watermarks one more time, but using the SAGV blocking
> time
> rather than any of the 8 latency values we received from the pcode --
> -
> if the calculated watermark value for that "sagv level" fits within
> the
> DDB allocation then we can enable SAGV, otherwise we can't.
>
> Your approach here somewhat approximates that. If the highest
> watermark
> level we enabled had a latency higher than the SAGV blocking time,
> then
> we automatically know we also would have had a valid watermark value
> for
> a lower sagv latency. But if the highest latency we enabled has a
> lower
> latency, we can't say for certain whether the SAGV's blocking time
> would
> have led to valid or invalid watermarks. If the first watermark
> level
> we failed on also had a lower latency than the SAGV time then we can
> conclude that the SAGV can't be enabled. But if the next level up
> had a
> latency higher than the blocking time (i.e., good < SAGV < bad), we
> can't really tell whether SAGV was possible without actually doing
> the
> extra watermark calculation.
>
> But even given the above, the bspec suggestion seems somewhat
> surprising
> to me. Intuitively it seems like SAGV would be introducing an
> additional delay on top of the existing memory fetch latency, not
> replacing the latency entirely. Intuitively the algorithm suggested
> for
> TGL makes sense to me (i.e., add the SAGV's extra delay to the WM0
> latency to ensure that regular latency plus an extra SAGV delay
> doesn't
> lead us to run dry), but that's not what the bspec calls for on ICL.
> I'm not really sure whether that's truly an intentional behavior
> change
> between platforms or whether the TGL bspec section does just a better
> job of explaining what was supposed to be done and clarifying the
> language.
>
> Anyway, we should probably trust the bspec for now, so it seems to me
> like we should add a "fake" watermark level associated with the SAGV
> block time and explicitly calculate that as enabled/disabled anytime
> we
> have a good < SAGV < bad situation.
I totally agree, had same questions during implementation, however
still I simply stick to what has been defined in a spec and also done
for previous platforms, as this is basically the same how it's done
now. What I did is mostly just splitting the code to get rid of some
skl specific ugly workaround there.
Regarding "fake" watermark level, as you might noticed now I would be
storing both sagv_wm and "normal" wm level to let intel_can_enable_sagv
to make decision later based on that(mostly decision now is simply
dictated by whether we could fit this into dbuf or not).
Regarding intel_can_enable_sagv implementation I will reply inline
also below.
>
> > + }
> > + if (can_sagv)
> > + state->crtc_sagv_mask |= BIT(crtc->pipe);
> > + }
> > +}
> > +
> > +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > +{
> > + struct drm_device *dev = state->base.dev;
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + enum pipe pipe;
> > +
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + tgl_set_sagv_mask(state);
> > + else if (INTEL_GEN(dev_priv) == 11)
> > + icl_set_sagv_mask(state);
> > + else
> > + skl_set_sagv_mask(state);
> > +
> > + /*
> > + * For SAGV we need to account all the pipes,
> > + * not only the ones which are in state currently.
> > + */
> > + for_each_pipe(dev_priv, pipe) {
> > + unsigned int active_pipes;
> > + /*
> > + * Figure out if we are changing active pipes here
> > + * then after commit dev_priv->active_pipes will
> > + * anyway be assigned to state->active_pipes.
> > + */
> > + if (state->active_pipe_changes)
> > + active_pipes = state->active_pipes;
> > + else
> > + active_pipes = dev_priv->active_pipes;
> > +
> > + /* Skip if pipe is inactive */
> > + if (!(BIT(pipe) & active_pipes))
> > + continue;
> > +
> > + /*
> > + * Pipe can be active in this state or in dev_priv
> > + * as we haven't committed thise changes yet(and we
> > shouldn't)
> > + * - we need to check both.
> > + */
> > + if (state->active_pipe_changes & BIT(pipe)) {
> > + bool state_sagv_masked = \
> > + (BIT(pipe) & state->crtc_sagv_mask) ==
> > 0;
> > + if (state_sagv_masked)
> > + return false;
> > + } else {
> > + bool sagv_masked = \
> > + (BIT(pipe) & dev_priv->crtc_sagv_mask)
> > == 0;
>
> If we're not changing which pipes are active, then we didn't globally
> lock everything at the beginning of this atomic transaction; we can
> have
> racing commits against different CRTC's. So when you look at
> dev_priv->crtc_sagv_mask here, the value might change immediately
> afterward if a commit on a different CRTC completed in the meantime.
>
> I don't think we want to look at other CRTC's outside our current
> transaction here. We should just figure out whether our own CRTC's
> are
> okay with SAGV or not. Then in the commit phase we'd need to grab
> some
> kind of SAGV lock, combine our local "SAGV okay" with the global
> "SAGV
> okay" and enable/disable as necessary.
>
> Some kind of reference-counting mechanism might make this
> simpler...is
> there any way we could tie this in with power domains (e.g., adding a
> "SAGV off" power domain and power well that we grab during commit
> when
> we've calculated that our own crtcs can't cope with SAGV latency)?
>
Yes, however the problem is that we need to know whether we can enable
SAGV or not already on calculation stage(i.e during
intel_atomic_check). Bandwidth checking code calls this as according to
BSpec if SAGV can't be enabled - it should stick to the highest
bandwidth point only. Also during ddb/wm calculation we call this check
to understand which wm level we should fit into dbuf.
And we can't make this decision based on this state only as it might
not contain all the crtcs - however if any of the pipes, even those
which are not in this state can't tolerate SAGV - then we can't enable
it anyway, even if those crtc in this state can.
That is why I have to iterate through all of the crtcs. However it is
good that you pointed out that those might change on the fly, I guess
we need to protect those from being changed by other commits.
We already do something similar by using serializing global state from
Ville, i.e once we add detect that we are changing some dev_priv global
state variables we mark that this commit should be serialized by adding
all the crtcs to the state.
>
> > + if (sagv_masked)
> > + return false;
> > + }
> > + }
> > return true;
> > }
> >
> > @@ -3925,6 +4045,7 @@ static int skl_compute_wm_params(const struct
> > intel_crtc_state *crtc_state,
> > int color_plane);
> > static void skl_compute_plane_wm(const struct intel_crtc_state
> > *crtc_state,
> > int level,
> > + u32 latency,
> > const struct skl_wm_params *wp,
> > const struct skl_wm_level
> > *result_prev,
> > struct skl_wm_level *result /* out
> > */);
> > @@ -3947,7 +4068,10 @@ skl_cursor_allocation(const struct
> > intel_crtc_state *crtc_state,
> > WARN_ON(ret);
> >
> > for (level = 0; level <= max_level; level++) {
> > - skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
> > + u32 latency = dev_priv->wm.skl_latency[level];
> > +
> > + skl_compute_plane_wm(crtc_state, level, latency, &wp,
> > &wm, &wm);
> > +
> > if (wm.min_ddb_alloc == U16_MAX)
> > break;
> >
> > @@ -4212,6 +4336,68 @@ icl_get_total_relative_data_rate(struct
> > intel_crtc_state *crtc_state,
> > return total_data_rate;
> > }
> >
> > +static int
> > +tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
> > + struct skl_ddb_allocation *ddb /* out */)
> > +{
> > + struct drm_crtc *crtc = crtc_state->base.crtc;
> > + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > + struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
> > + u16 alloc_size;
> > + u16 total[I915_MAX_PLANES] = {};
> > + u64 total_data_rate;
> > + enum plane_id plane_id;
> > + int num_active;
> > + u64 plane_data_rate[I915_MAX_PLANES] = {};
> > + u32 blocks;
> > +
> > + /*
> > + * No need to check gen here, we call this only for gen12
> > + */
> > + total_data_rate =
> > + icl_get_total_relative_data_rate(crtc_state,
> > + plane_data_rate);
> > +
> > + skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
> > + total_data_rate,
> > + ddb, alloc, &num_active);
> > + alloc_size = skl_ddb_entry_size(alloc);
> > + if (alloc_size == 0)
> > + return -ENOSPC;
> > +
> > + /* Allocate fixed number of blocks for cursor. */
> > + total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state,
> > num_active);
> > + alloc_size -= total[PLANE_CURSOR];
> > + crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
> > + alloc->end - total[PLANE_CURSOR];
> > + crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
> > +
> > + /*
> > + * Do check if we can fit L0 + sagv_block_time and
> > + * disable SAGV if we can't.
> > + */
> > + blocks = 0;
> > + for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > + const struct skl_plane_wm *wm =
> > + &crtc_state->wm.skl.optimal.planes[plane_id];
> > +
> > + if (plane_id == PLANE_CURSOR) {
> > + if (WARN_ON(wm->sagv_wm0.min_ddb_alloc >
> > + total[PLANE_CURSOR])) {
> > + blocks = U32_MAX;
> > + break;
> > + }
> > + continue;
> > + }
> > +
> > + blocks += wm->sagv_wm0.min_ddb_alloc;
> > + if (blocks > alloc_size)
> > + return -ENOSPC;
> > + }
> > + return 0;
> > +}
> > +
> > static int
> > skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
> > struct skl_ddb_allocation *ddb /* out */)
> > @@ -4641,6 +4827,7 @@ static bool skl_wm_has_lines(struct
> > drm_i915_private *dev_priv, int level)
> >
> > static void skl_compute_plane_wm(const struct intel_crtc_state
> > *crtc_state,
> > int level,
> > + u32 latency,
> > const struct skl_wm_params *wp,
> > const struct skl_wm_level
> > *result_prev,
> > struct skl_wm_level *result /* out */)
>
> It doesn't look like this latency parameter gets used (it gets masked
> by
> a local latency variable still.
Actually no, there are no other latency variables declared in
skl_compute_plane_wm(did I accidentally fix this some how?) as I see.
Anyway thank you for a really precise review.
>
>
> > @@ -4767,20 +4954,45 @@ static void skl_compute_plane_wm(const
> > struct intel_crtc_state *crtc_state,
> > static void
> > skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> > const struct skl_wm_params *wm_params,
> > - struct skl_wm_level *levels)
> > + struct skl_plane_wm *plane_wm,
> > + bool yuv)
> > {
> > struct drm_i915_private *dev_priv = to_i915(crtc_state-
> > >uapi.crtc->dev);
> > int level, max_level = ilk_wm_max_level(dev_priv);
> > + /*
> > + * Check which kind of plane is it and based on that calculate
> > + * correspondent WM levels.
> > + */
> > + struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm-
> > >wm;
> > struct skl_wm_level *result_prev = &levels[0];
> >
> > for (level = 0; level <= max_level; level++) {
> > struct skl_wm_level *result = &levels[level];
> > + u32 latency = dev_priv->wm.skl_latency[level];
> >
> > - skl_compute_plane_wm(crtc_state, level, wm_params,
> > - result_prev, result);
> > + skl_compute_plane_wm(crtc_state, level, latency,
> > + wm_params, result_prev, result);
> >
> > result_prev = result;
> > }
> > + /*
> > + * For Gen12 if it is an L0 we need to also
> > + * consider sagv_block_time when calculating
> > + * L0 watermark - we will need that when making
> > + * a decision whether enable SAGV or not.
> > + * For older gens we agreed to copy L0 value for
> > + * compatibility.
> > + */
> > + if ((INTEL_GEN(dev_priv) >= 12)) {
> > + u32 latency = dev_priv->wm.skl_latency[0];
> > +
> > + latency += dev_priv->sagv_block_time_us;
> > + skl_compute_plane_wm(crtc_state, 0, latency,
> > + wm_params, &levels[0],
> > + &plane_wm->sagv_wm0);
> > + } else
> > + memcpy(&plane_wm->sagv_wm0, &levels[0],
> > + sizeof(struct skl_wm_level));
> > }
> >
> > static u32
> > @@ -4873,7 +5085,7 @@ static int skl_build_plane_wm_single(struct
> > intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > - skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> > + skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
> > skl_compute_transition_wm(crtc_state, &wm_params, wm);
> >
> > return 0;
> > @@ -4895,7 +5107,7 @@ static int skl_build_plane_wm_uv(struct
> > intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > - skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
> > + skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
> >
> > return 0;
> > }
> > @@ -5167,6 +5379,8 @@ skl_ddb_add_affected_planes(const struct
> > intel_crtc_state *old_crtc_state,
> > return 0;
> > }
> >
> > +static void tgl_set_sagv_wm0(struct intel_atomic_state *state);
> > +
> > static int
> > skl_compute_ddb(struct intel_atomic_state *state)
> > {
> > @@ -5177,6 +5391,11 @@ skl_compute_ddb(struct intel_atomic_state
> > *state)
> > struct intel_crtc *crtc;
> > int ret, i;
> >
> > + /* For Gen12+ for SAGV we have a special L0 wm values */
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + if (intel_can_enable_sagv(state))
> > + tgl_set_sagv_wm0(state);
> > +
> > memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
> >
> > for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state,
> > @@ -5443,6 +5662,56 @@ static int skl_wm_add_affected_planes(struct
> > intel_atomic_state *state,
> > return 0;
> > }
> >
> > +void tgl_set_sagv_wm0(struct intel_atomic_state *state)
> > +{
> > + struct intel_crtc *crtc;
> > + struct intel_crtc_state *new_crtc_state;
> > + struct intel_crtc_state *old_crtc_state;
> > + struct drm_device *dev = state->base.dev;
> > + const struct drm_i915_private *dev_priv = to_i915(dev);
> > + int i;
> > +
> > + /*
> > + * If we determined that we can actually enable SAGV, then
> > + * actually use those levels tgl_check_pipe_fits_sagv_wm
> > + * has already taken care of checking if L0 + sagv block time
> > + * fits into ddb.
> > + */
> > + for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state,
> > + new_crtc_state, i) {
> > + struct intel_plane *plane;
> > +
> > + for_each_intel_plane_on_crtc(&dev_priv->drm, crtc,
> > plane) {
> > + enum plane_id plane_id = plane->id;
> > +
> > + struct skl_plane_wm *plane_wm = \
> > + &new_crtc_state-
> > >wm.skl.optimal.planes[plane_id];
> > + struct skl_wm_level *sagv_wm0 = &plane_wm-
> > >sagv_wm0;
> > + struct skl_wm_level *l0_wm0 = &plane_wm->wm[0];
> > +
> > + memcpy(l0_wm0, sagv_wm0, sizeof(struct
> > skl_wm_level));
> > + }
> > + }
> > +}
> > +
> > +static void tgl_set_sagv_mask(struct intel_atomic_state *state)
> > +{
> > + struct intel_crtc *crtc;
> > + struct intel_crtc_state *new_crtc_state;
> > + struct intel_crtc_state *old_crtc_state;
> > + struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
> > + int ret, i;
> > +
> > + for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state,
> > + new_crtc_state, i) {
> > + ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
> > + if (!ret) {
> > + int pipe_bit = BIT(crtc->pipe);
> > + state->crtc_sagv_mask |= pipe_bit;
> > + }
> > + }
> > +}
> > +
> > static int
> > skl_compute_wm(struct intel_atomic_state *state)
> > {
> > @@ -5455,6 +5724,9 @@ skl_compute_wm(struct intel_atomic_state
> > *state)
> > /* Clear all dirty flags */
> > results->dirty_pipes = 0;
> >
> > + /* If we exit before check is done */
> > + state->crtc_sagv_mask = 0;
> > +
> > ret = skl_ddb_add_affected_pipes(state);
> > if (ret)
> > return ret;
> > --
> > 2.17.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v10 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.
@ 2019-11-12 16:18 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 25+ messages in thread
From: Lisovskiy, Stanislav @ 2019-11-12 16:18 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: intel-gfx
On Mon, 2019-11-11 at 17:22 -0800, Matt Roper wrote:
> On Thu, Nov 07, 2019 at 05:30:37PM +0200, Stanislav Lisovskiy wrote:
> > According to BSpec 53998, we should try to
> > restrict qgv points, which can't provide
> > enough bandwidth for desired display configuration.
> >
> > Currently we are just comparing against all of
> > those and take minimum(worst case).
> >
> > v2: Fixed wrong PCode reply mask, removed hardcoded
> > values.
> >
> > v3: Forbid simultaneous legacy SAGV PCode requests and
> > restricting qgv points. Put the actual restriction
> > to commit function, added serialization(thanks to Ville)
> > to prevent commit being applied out of order in case of
> > nonblocking and/or nomodeset commits.
> >
> > v4:
> > - Minor code refactoring, fixed few typos(thanks to James
> > Ausmus)
> > - Change the naming of qgv point
> > masking/unmasking functions(James Ausmus).
> > - Simplify the masking/unmasking operation itself,
> > as we don't need to mask only single point per request(James
> > Ausmus)
> > - Reject and stick to highest bandwidth point if SAGV
> > can't be enabled(BSpec)
> >
> > v5:
> > - Add new mailbox reply codes, which seems to happen during
> > boot
> > time for TGL and indicate that QGV setting is not yet
> > available.
> >
> > v6:
> > - Increase number of supported QGV points to be in sync with
> > BSpec.
> >
> > v7: - Rebased and resolved conflict to fix build failure.
> > - Fix NUM_QGV_POINTS to 8 and moved that to header file(James
> > Ausmus)
> >
> > v8: - Don't report an error if we can't restrict qgv points, as
> > SAGV
> > can be disabled by BIOS, which is completely legal. So don't
> > make CI panic. Instead if we detect that there is only 1 QGV
> > point accessible just analyze if we can fit the required
> > bandwidth
> > requirements, but no need in restricting.
> >
> > v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
> > simultaneously.
> >
> > v10: - Fix CDCLK corruption, because of global state getting
> > serialized
> > without modeset, which caused copying of non-calculated
> > cdclk
> > to be copied to dev_priv(thanks to Ville for the hint).
> >
> > Reviewed-by: James Ausmus <james.ausmus@intel.com>
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_atomic.h | 3 +
> > drivers/gpu/drm/i915/display/intel_bw.c | 137
> > +++++++++++++++---
> > drivers/gpu/drm/i915/display/intel_bw.h | 2 +
> > drivers/gpu/drm/i915/display/intel_display.c | 104 ++++++++++++-
> > .../drm/i915/display/intel_display_types.h | 3 +
> > drivers/gpu/drm/i915/i915_drv.h | 4 +-
> > drivers/gpu/drm/i915/i915_reg.h | 8 +
> > drivers/gpu/drm/i915/intel_pm.c | 15 +-
> > drivers/gpu/drm/i915/intel_pm.h | 1 +
> > drivers/gpu/drm/i915/intel_sideband.c | 27 +++-
> > drivers/gpu/drm/i915/intel_sideband.h | 1 -
> > 11 files changed, 264 insertions(+), 41 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
> > b/drivers/gpu/drm/i915/display/intel_atomic.h
> > index 7b49623419ba..3ab6d7ec75ae 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> > @@ -7,6 +7,7 @@
> > #define __INTEL_ATOMIC_H__
> >
> > #include <linux/types.h>
> > +#include "intel_display_types.h"
>
> Is this change needed? We already have a forward declaration of
> intel_atomic_state so it doesn't seem like this should be necessary
> for
> the function prototype below.
Good point I will check if it will build without this.
>
> > const struct intel_sa_info *sa)
> > {
> > - struct intel_qgv_info qi = {};
> > + struct intel_qgv_info qi;
>
> Is there a reason we don't want to zero out the structure here? I
> don't
> think it should hurt anything, plus it helps prevent us from making
> mistakes in the future and trying to interpret garbage data
> associated
> with the non-existent QGV points.
I was actually planning to store it in dev_priv but then found another
way to access number of qgv points, through another structure already
stored there, then put it back, so thanks for spotting.
>
> > bool is_y_tile = true; /* assume y tile may be used */
> > int num_channels;
> > int deinterleave;
> > @@ -270,22 +294,6 @@ void intel_bw_init_hw(struct drm_i915_private
> > *dev_priv)
> > icl_get_bw_info(dev_priv, &icl_sa_info);
> > }
> >
> > -static unsigned int intel_max_data_rate(struct drm_i915_private
> > *dev_priv,
> > - int num_planes)
> > -{
> > - if (INTEL_GEN(dev_priv) >= 11)
> > - /*
> > - * FIXME with SAGV disabled maybe we can assume
> > - * point 1 will always be used? Seems to match
> > - * the behaviour observed in the wild.
> > - */
> > - return min3(icl_max_bw(dev_priv, num_planes, 0),
> > - icl_max_bw(dev_priv, num_planes, 1),
> > - icl_max_bw(dev_priv, num_planes, 2));
> > - else
> > - return UINT_MAX;
> > -}
> > -
> > static unsigned int intel_bw_crtc_num_active_planes(const struct
> > intel_crtc_state *crtc_state)
> > {
> > /*
> > @@ -377,7 +385,12 @@ int intel_bw_atomic_check(struct
> > intel_atomic_state *state)
> > unsigned int data_rate, max_data_rate;
> > unsigned int num_active_planes;
> > struct intel_crtc *crtc;
> > - int i;
> > + int i, ret;
> > + struct intel_qgv_info qi = {};
> > + u32 allowed_points = 0;
> > + unsigned int max_bw_point = 0, max_bw = 0;
> > + unsigned int num_qgv_points = dev_priv-
> > >max_bw[0].num_qgv_points;
> > + u32 mask = (1 << num_qgv_points) - 1;
> >
> > /* FIXME earlier gens need some checks too */
> > if (INTEL_GEN(dev_priv) < 11)
> > @@ -421,16 +434,92 @@ int intel_bw_atomic_check(struct
> > intel_atomic_state *state)
> > data_rate = intel_bw_data_rate(dev_priv, bw_state);
> > num_active_planes = intel_bw_num_active_planes(dev_priv,
> > bw_state);
> >
> > - max_data_rate = intel_max_data_rate(dev_priv,
> > num_active_planes);
> > -
> > data_rate = DIV_ROUND_UP(data_rate, 1000);
> >
> > - if (data_rate > max_data_rate) {
> > - DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available
> > %d MB/s (%d active planes)\n",
> > - data_rate, max_data_rate,
> > num_active_planes);
> > + for (i = 0; i < num_qgv_points; i++) {
> > + max_data_rate = icl_max_bw(dev_priv, num_active_planes,
> > i);
> > + /*
> > + * We need to know which qgv point gives us
> > + * maximum bandwidth in order to disable SAGV
> > + * if we find that we exceed SAGV block time
> > + * with watermarks. By that moment we already
> > + * have those, as it is calculated earlier in
> > + * intel_atomic_check,
> > + */
> > + if (max_data_rate > max_bw) {
> > + max_bw_point = i;
> > + max_bw = max_data_rate;
> > + }
> > + if (max_data_rate >= data_rate)
> > + allowed_points |= 1 << i;
>
> Minor nitpick; cleaner to use BIT(i) for this.
>
> > + DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
> > + i, max_data_rate, data_rate);
> > + }
> > +
> > + /*
> > + * BSpec states that we always should have at least one allowed
> > point
> > + * left, so if we couldn't - simply reject the configuration
> > for obvious
> > + * reasons.
> > + */
> > + if (allowed_points == 0) {
> > + DRM_DEBUG_KMS("Could not find any suitable QGV
> > points\n");
>
> We might want to make some mention of memory bandwidth in this
> message
> for people who don't know what a QGV point is. E.g., "No QGV points
> provide sufficient memory bandwidth for display configuration."
>
> > return -EINVAL;
> > }
> >
> > + /*
> > + * In case if SAGV is disabled in BIOS, we always get 1
> > + * SAGV point, but we can't send PCode commands to restrict it
> > + * as it will fail and pointless anyway.
> > + */
> > + if (qi.num_points == 1)
> > + dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
> > + else
> > + dev_priv->sagv_status = I915_SAGV_ENABLED;
> > +
> > + /*
> > + * Leave only single point with highest bandwidth, if
> > + * we can't enable SAGV according to BSpec.
> > + */
> > + if (!intel_can_enable_sagv(state)) {
> > +
> > + /*
> > + * This is a border line condition when we have 0
> > planes
> > + * and SAGV not enabled means that we should keep QGV
> > with
> > + * highest bandwidth, however algorithm returns wrong
> > result
> > + * for 0 planes and 0 data rate, so just stick to last
> > config
> > + * then. Otherwise use the QGV point with highest BW
> > according
> > + * to BSpec.
> > + */
>
> Isn't the QGV with the highest bandwidth constant? Can we just
> figure
> it out once at startup and then set it directly here instead of
> re-finding it each commit?
It seems to be constant however there is a mentioning in BSpec
something like
"there are cases when higher point allows less bandwidth than lower",
as I understand depending on contraints, the algorithm itself might
change, so I preferred not to rely on that we know which point provides
highest bandwidth but just calculate it. We could of course figure it
out only once, however not sure if something else won't ever change and
affect that. Iterating through few points doesn't seem to be too hard
anyway.
>
> > + if (!data_rate && !num_active_planes) {
> > + DRM_DEBUG_KMS("No SAGV, using old QGV mask\n");
> > + allowed_points = (~dev_priv->qgv_points_mask) &
> > mask;
> > + } else {
> > + allowed_points = 1 << max_bw_point;
> > + DRM_DEBUG_KMS("No SAGV, using single QGV point
> > %d\n",
> > + max_bw_point);
> > + }
> > + }
> > + /*
> > + * We store the ones which need to be masked as that is what
> > PCode
> > + * actually accepts as a parameter.
> > + */
> > + state->qgv_points_mask = (~allowed_points) & mask;
> > +
> > + DRM_DEBUG_KMS("New state %p qgv mask %x\n",
> > + state, state->qgv_points_mask);
> > +
> > + /*
> > + * If the actual mask had changed we need to make sure that
> > + * the commits are serialized(in case this is a nomodeset,
> > nonblocking)
> > + */
> > + if (state->qgv_points_mask != dev_priv->qgv_points_mask) {
> > + ret = intel_atomic_serialize_global_state(state);
> > + if (ret) {
> > + DRM_DEBUG_KMS("Could not serialize global
> > state\n");
> > + return ret;
> > + }
> > + }
> > +
> > return 0;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
> > b/drivers/gpu/drm/i915/display/intel_bw.h
> > index 9db10af012f4..66bf9bc10b73 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > @@ -28,5 +28,7 @@ int intel_bw_init(struct drm_i915_private
> > *dev_priv);
> > int intel_bw_atomic_check(struct intel_atomic_state *state);
> > void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> > const struct intel_crtc_state *crtc_state);
> > +int icl_pcode_restrict_qgv_points(struct drm_i915_private
> > *dev_priv,
> > + u32 points_mask);
> >
> > #endif /* __INTEL_BW_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 7ea1e7518ab6..71f6aaa1f6b9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -14744,6 +14744,80 @@ static void
> > intel_atomic_cleanup_work(struct work_struct *work)
> > intel_atomic_helper_free_state(i915);
> > }
> >
> > +static void intel_qgv_points_mask(struct intel_atomic_state
> > *state)
> > +{
> > + struct drm_device *dev = state->base.dev;
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + int ret;
> > + u32 new_mask = dev_priv->qgv_points_mask | state-
> > >qgv_points_mask;
> > + unsigned int num_qgv_points = dev_priv-
> > >max_bw[0].num_qgv_points;
> > + unsigned int mask = (1 << num_qgv_points) - 1;
> > +
> > + /*
> > + * As we don't know initial hardware state during initial
> > commit
> > + * we should not do anything, until we actually figure out,
> > + * what are the qgv points to mask.
> > + */
> > + if (!new_mask)
> > + return;
> > +
> > + WARN_ON(new_mask == mask);
> > +
> > + /*
> > + * Just return if we can't control SAGV or don't have it.
> > + */
> > + if (!intel_has_sagv(dev_priv))
> > + return;
> > +
> > + /*
> > + * Restrict required qgv points before updating the
> > configuration.
> > + * According to BSpec we can't mask and unmask qgv points at
> > the same
> > + * time. Also masking should be done before updating the
> > configuration
> > + * and unmasking afterwards.
> > + */
> > + ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> > + if (ret < 0)
> > + DRM_DEBUG_KMS("Could not restrict required qgv
> > points(%d)\n",
> > + ret);
> > + else
> > + dev_priv->qgv_points_mask = new_mask;
> > +}
> > +
> > +static void intel_qgv_points_unmask(struct intel_atomic_state
> > *state)
> > +{
> > + struct drm_device *dev = state->base.dev;
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + int ret;
> > + u32 new_mask = dev_priv->qgv_points_mask & state-
> > >qgv_points_mask;
> > +
> > + /*
> > + * As we don't know initial hardware state during initial
> > commit
> > + * we should not do anything, until we actually figure out,
> > + * what are the qgv points to mask.
> > + */
> > + if (!new_mask)
> > + return;
> > +
> > + /*
> > + * Just return if we can't control SAGV or don't have it.
> > + */
> > + if (!intel_has_sagv(dev_priv))
> > + return;
> > +
> > + /*
> > + * Allow required qgv points after updating the configuration.
> > + * According to BSpec we can't mask and unmask qgv points at
> > the same
> > + * time. Also masking should be done before updating the
> > configuration
> > + * and unmasking afterwards.
> > + */
> > + ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> > + if (ret < 0)
> > + DRM_DEBUG_KMS("Could not restrict required qgv
> > points(%d)\n",
> > + ret);
> > + else
> > + dev_priv->qgv_points_mask = new_mask;
> > +}
> > +
> > static void intel_atomic_commit_tail(struct intel_atomic_state
> > *state)
> > {
> > struct drm_device *dev = state->base.dev;
> > @@ -14771,6 +14845,9 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> > }
> > }
> >
> > + if ((INTEL_GEN(dev_priv) >= 11))
> > + intel_qgv_points_mask(state);
> > +
> > intel_commit_modeset_disables(state);
> >
> > /* FIXME: Eventually get rid of our crtc->config pointer */
> > @@ -14789,8 +14866,9 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> > * SKL workaround: bspec recommends we disable the SAGV
> > when we
> > * have more then one pipe enabled
> > */
> > - if (!intel_can_enable_sagv(state))
> > - intel_disable_sagv(dev_priv);
> > + if (INTEL_GEN(dev_priv) < 11)
> > + if (!intel_can_enable_sagv(state))
> > + intel_disable_sagv(dev_priv);
> >
> > intel_modeset_verify_disabled(dev_priv, state);
> > }
> > @@ -14873,8 +14951,11 @@ static void
> > intel_atomic_commit_tail(struct intel_atomic_state *state)
> > if (state->modeset)
> > intel_verify_planes(state);
> >
> > - if (state->modeset && intel_can_enable_sagv(state))
> > - intel_enable_sagv(dev_priv);
> > + if (INTEL_GEN(dev_priv) < 11) {
> > + if (state->modeset && intel_can_enable_sagv(state))
> > + intel_enable_sagv(dev_priv);
> > + } else
> > + intel_qgv_points_unmask(state);
> >
> > drm_atomic_helper_commit_hw_done(&state->base);
> >
> > @@ -14962,7 +15043,18 @@ static int intel_atomic_commit(struct
> > drm_device *dev,
> > {
> > struct intel_atomic_state *state =
> > to_intel_atomic_state(_state);
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > - int ret = 0;
> > + struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> > + int ret = 0, i;
> > + bool any_ms = false;
> > + struct intel_crtc *crtc;
> > +
> > + for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state,
> > + new_crtc_state, i) {
> > + if (needs_modeset(new_crtc_state)) {
> > + any_ms = true;
> > + break;
> > + }
> > + }
>
> I think we already have this in state->modeset.
>
> >
> > state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> >
> > @@ -15021,7 +15113,7 @@ static int intel_atomic_commit(struct
> > drm_device *dev,
> > intel_shared_dpll_swap_state(state);
> > intel_atomic_track_fbs(state);
> >
> > - if (state->global_state_changed) {
> > + if (state->global_state_changed && any_ms) {
> > assert_global_state_locked(dev_priv);
> >
> > memcpy(dev_priv->min_cdclk, state->min_cdclk,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index fb274538af23..896b13bc4494 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -528,6 +528,9 @@ struct intel_atomic_state {
> > struct i915_sw_fence commit_ready;
> >
> > struct llist_node freed;
> > +
> > + /* Gen11+ only */
> > + u32 qgv_points_mask;
> > };
> >
> > struct intel_plane_state {
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 4f4e2e839513..9924390cb94b 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1243,11 +1243,13 @@ struct drm_i915_private {
> > } dram_info;
> >
> > struct intel_bw_info {
> > - unsigned int deratedbw[3]; /* for each QGV point */
> > + unsigned int deratedbw[NUM_SAGV_POINTS]; /* for each
> > QGV point */
> > u8 num_qgv_points;
> > u8 num_planes;
> > } max_bw[6];
> >
> > + u32 qgv_points_mask;
> > +
> > struct drm_private_obj bw_obj;
> >
> > struct intel_runtime_pm runtime_pm;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index a607ea520829..6d6ecf1d9f6b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8951,6 +8951,9 @@ enum {
> > #define VLV_RENDER_C0_COUNT _MMIO(0x138118)
> > #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
> >
> > +/* BSpec precisely defines this */
> > +#define NUM_SAGV_POINTS 8
> > +
>
> Any specific reason this is in the reg file rather than either
> i915_drv.h where it's used or something like intel_bw.h?
Probably none. I can look for a better place for this.
>
> > #define GEN6_PCODE_MAILBOX _MMIO(0x138124)
> > #define GEN6_PCODE_READY (1 << 31)
> > #define GEN6_PCODE_ERROR_MASK 0xFF
> > @@ -8961,6 +8964,8 @@ enum {
> > #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
> > #define GEN7_PCODE_TIMEOUT 0x2
> > #define GEN7_PCODE_ILLEGAL_DATA 0x3
> > +#define GEN11_PCODE_MAIL_BOX_LOCKED 0x6
> > +#define GEN11_PCODE_REJECTED 0x11
> > #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
> > #define GEN6_PCODE_WRITE_RC6VIDS 0x4
> > #define GEN6_PCODE_READ_RC6VIDS 0x5
> > @@ -8982,6 +8987,7 @@ enum {
> > #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
> > #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
> > #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((poin
> > t) << 16) | (0x1 << 8))
> > +#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
> > #define GEN6_PCODE_READ_D_COMP 0x10
> > #define GEN6_PCODE_WRITE_D_COMP 0x11
> > #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
> > @@ -8994,6 +9000,8 @@ enum {
> > #define GEN9_SAGV_IS_DISABLED 0x1
> > #define GEN9_SAGV_ENABLE 0x3
> > #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
> > +#define GEN11_PCODE_POINTS_RESTRICTED 0x0
> > +#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
> > #define GEN6_PCODE_DATA _MMIO(0x138128)
> > #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
> > #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index c792dd168742..10816f3e29f0 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3617,13 +3617,9 @@ static bool skl_needs_memory_bw_wa(struct
> > drm_i915_private *dev_priv)
> > return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
> > }
> >
> > -static bool
> > +bool
> > intel_has_sagv(struct drm_i915_private *dev_priv)
> > {
> > - /* HACK! */
> > - if (IS_GEN(dev_priv, 12))
> > - return false;
> > -
> > return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
> > dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
> > }
> > @@ -3839,7 +3835,7 @@ static void icl_set_sagv_mask(struct
> > intel_atomic_state *state)
> > if (flags & DRM_MODE_FLAG_INTERLACE)
> > continue;
> >
> > - if (!new_crtc_state->base.active)
> > + if (!new_crtc_state->hw.enable)
> > continue;
>
> Looks like this was a bug in the previous patch. Any specific reason
> we're switching from active to enable?
Yees, we discussed that with Ville, there are seems to be some
confusion about when to use active or enable. In intel_pm many
functions were using enable so I simply followed same approach, as
I understood in theory we should use "active" here, however there were
recent changes, separating hw state and uapi which probably confused me
into using this again.
>
> >
> > can_sagv = true;
> > @@ -3886,6 +3882,9 @@ bool intel_can_enable_sagv(struct
> > intel_atomic_state *state)
> > else
> > skl_set_sagv_mask(state);
> >
> > + DRM_DEBUG_KMS("Crtc sagv masks, state %x global state %x\n",
> > + state->crtc_sagv_mask,
> > + dev_priv->crtc_sagv_mask);
> > /*
> > * For SAGV we need to account all the pipes,
> > * not only the ones which are in state currently.
> > @@ -4340,7 +4339,7 @@ static int
> > tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
> > struct skl_ddb_allocation *ddb /* out */)
> > {
> > - struct drm_crtc *crtc = crtc_state->base.crtc;
> > + struct drm_crtc *crtc = crtc_state->uapi.crtc;
>
> Also a bug in the previous patch.
>
>
> > struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> > struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
> > @@ -4833,7 +4832,6 @@ static void skl_compute_plane_wm(const struct
> > intel_crtc_state *crtc_state,
> > struct skl_wm_level *result /* out */)
> > {
> > struct drm_i915_private *dev_priv = to_i915(crtc_state-
> > >uapi.crtc->dev);
> > - u32 latency = dev_priv->wm.skl_latency[level];
>
> Mentioned on previous patch.
>
>
> > uint_fixed_16_16_t method1, method2;
> > uint_fixed_16_16_t selected_result;
> > u32 res_blocks, res_lines, min_ddb_alloc = 0;
> > @@ -5707,6 +5705,7 @@ static void tgl_set_sagv_mask(struct
> > intel_atomic_state *state)
> > ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
> > if (!ret) {
> > int pipe_bit = BIT(crtc->pipe);
> > +
> > state->crtc_sagv_mask |= pipe_bit;
>
> Unrelated change.
>
> > }
> > }
> > diff --git a/drivers/gpu/drm/i915/intel_pm.h
> > b/drivers/gpu/drm/i915/intel_pm.h
> > index b579c724b915..53275860731a 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.h
> > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > @@ -43,6 +43,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc
> > *crtc,
> > void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> > void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> > bool intel_can_enable_sagv(struct intel_atomic_state *state);
> > +bool intel_has_sagv(struct drm_i915_private *dev_priv);
> > int intel_enable_sagv(struct drm_i915_private *dev_priv);
> > int intel_disable_sagv(struct drm_i915_private *dev_priv);
> > bool skl_wm_level_equals(const struct skl_wm_level *l1,
> > diff --git a/drivers/gpu/drm/i915/intel_sideband.c
> > b/drivers/gpu/drm/i915/intel_sideband.c
> > index e06b35b844a0..ff9dbed094d8 100644
> > --- a/drivers/gpu/drm/i915/intel_sideband.c
> > +++ b/drivers/gpu/drm/i915/intel_sideband.c
> > @@ -371,6 +371,29 @@ static inline int
> > gen7_check_mailbox_status(u32 mbox)
> > }
> > }
> >
> > +static inline int gen11_check_mailbox_status(u32 mbox)
> > +{
> > + switch (mbox & GEN6_PCODE_ERROR_MASK) {
> > + case GEN6_PCODE_SUCCESS:
> > + return 0;
> > + case GEN6_PCODE_ILLEGAL_CMD:
> > + return -ENXIO;
> > + case GEN7_PCODE_TIMEOUT:
> > + return -ETIMEDOUT;
> > + case GEN7_PCODE_ILLEGAL_DATA:
> > + return -EINVAL;
> > + case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
> > + return -EOVERFLOW;
> > + case GEN11_PCODE_MAIL_BOX_LOCKED:
> > + return -EAGAIN;
> > + case GEN11_PCODE_REJECTED:
> > + return -EACCES;
> > + default:
> > + MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
> > + return 0;
> > + }
> > +}
> > +
> > static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
> > u32 mbox, u32 *val, u32 *val1,
> > int fast_timeout_us,
> > @@ -408,7 +431,9 @@ static int __sandybridge_pcode_rw(struct
> > drm_i915_private *i915,
> > if (is_read && val1)
> > *val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
> >
> > - if (INTEL_GEN(i915) > 6)
> > + if (INTEL_GEN(i915) >= 11)
> > + return gen11_check_mailbox_status(mbox);
> > + else if (INTEL_GEN(i915) > 6)
> > return gen7_check_mailbox_status(mbox);
> > else
> > return gen6_check_mailbox_status(mbox);
> > diff --git a/drivers/gpu/drm/i915/intel_sideband.h
> > b/drivers/gpu/drm/i915/intel_sideband.h
> > index 7fb95745a444..14627ace99ae 100644
> > --- a/drivers/gpu/drm/i915/intel_sideband.h
> > +++ b/drivers/gpu/drm/i915/intel_sideband.h
> > @@ -137,5 +137,4 @@ int sandybridge_pcode_write_timeout(struct
> > drm_i915_private *i915, u32 mbox,
> >
> > int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32
> > request,
> > u32 reply_mask, u32 reply, int timeout_base_ms);
> > -
> > #endif /* _INTEL_SIDEBAND_H */
>
> Unrelated change.
>
>
> In general, I wonder if we could break this patch up a bit more. It
> seems like there are a lot of moving pieces here which makes it a bit
> harder to review.
Sounds like good idea, we seem to need a fix for static QGV array
warning which we get for tgl, so I will probably try to split out
that part with some preparation stuff to make this at least look
less complex.
- Stan
>
>
> Matt
>
>
> > --
> > 2.17.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH v10 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.
@ 2019-11-12 16:18 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 25+ messages in thread
From: Lisovskiy, Stanislav @ 2019-11-12 16:18 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: intel-gfx
On Mon, 2019-11-11 at 17:22 -0800, Matt Roper wrote:
> On Thu, Nov 07, 2019 at 05:30:37PM +0200, Stanislav Lisovskiy wrote:
> > According to BSpec 53998, we should try to
> > restrict qgv points, which can't provide
> > enough bandwidth for desired display configuration.
> >
> > Currently we are just comparing against all of
> > those and take minimum(worst case).
> >
> > v2: Fixed wrong PCode reply mask, removed hardcoded
> > values.
> >
> > v3: Forbid simultaneous legacy SAGV PCode requests and
> > restricting qgv points. Put the actual restriction
> > to commit function, added serialization(thanks to Ville)
> > to prevent commit being applied out of order in case of
> > nonblocking and/or nomodeset commits.
> >
> > v4:
> > - Minor code refactoring, fixed few typos(thanks to James
> > Ausmus)
> > - Change the naming of qgv point
> > masking/unmasking functions(James Ausmus).
> > - Simplify the masking/unmasking operation itself,
> > as we don't need to mask only single point per request(James
> > Ausmus)
> > - Reject and stick to highest bandwidth point if SAGV
> > can't be enabled(BSpec)
> >
> > v5:
> > - Add new mailbox reply codes, which seems to happen during
> > boot
> > time for TGL and indicate that QGV setting is not yet
> > available.
> >
> > v6:
> > - Increase number of supported QGV points to be in sync with
> > BSpec.
> >
> > v7: - Rebased and resolved conflict to fix build failure.
> > - Fix NUM_QGV_POINTS to 8 and moved that to header file(James
> > Ausmus)
> >
> > v8: - Don't report an error if we can't restrict qgv points, as
> > SAGV
> > can be disabled by BIOS, which is completely legal. So don't
> > make CI panic. Instead if we detect that there is only 1 QGV
> > point accessible just analyze if we can fit the required
> > bandwidth
> > requirements, but no need in restricting.
> >
> > v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
> > simultaneously.
> >
> > v10: - Fix CDCLK corruption, because of global state getting
> > serialized
> > without modeset, which caused copying of non-calculated
> > cdclk
> > to be copied to dev_priv(thanks to Ville for the hint).
> >
> > Reviewed-by: James Ausmus <james.ausmus@intel.com>
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_atomic.h | 3 +
> > drivers/gpu/drm/i915/display/intel_bw.c | 137
> > +++++++++++++++---
> > drivers/gpu/drm/i915/display/intel_bw.h | 2 +
> > drivers/gpu/drm/i915/display/intel_display.c | 104 ++++++++++++-
> > .../drm/i915/display/intel_display_types.h | 3 +
> > drivers/gpu/drm/i915/i915_drv.h | 4 +-
> > drivers/gpu/drm/i915/i915_reg.h | 8 +
> > drivers/gpu/drm/i915/intel_pm.c | 15 +-
> > drivers/gpu/drm/i915/intel_pm.h | 1 +
> > drivers/gpu/drm/i915/intel_sideband.c | 27 +++-
> > drivers/gpu/drm/i915/intel_sideband.h | 1 -
> > 11 files changed, 264 insertions(+), 41 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
> > b/drivers/gpu/drm/i915/display/intel_atomic.h
> > index 7b49623419ba..3ab6d7ec75ae 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> > @@ -7,6 +7,7 @@
> > #define __INTEL_ATOMIC_H__
> >
> > #include <linux/types.h>
> > +#include "intel_display_types.h"
>
> Is this change needed? We already have a forward declaration of
> intel_atomic_state so it doesn't seem like this should be necessary
> for
> the function prototype below.
Good point I will check if it will build without this.
>
> > const struct intel_sa_info *sa)
> > {
> > - struct intel_qgv_info qi = {};
> > + struct intel_qgv_info qi;
>
> Is there a reason we don't want to zero out the structure here? I
> don't
> think it should hurt anything, plus it helps prevent us from making
> mistakes in the future and trying to interpret garbage data
> associated
> with the non-existent QGV points.
I was actually planning to store it in dev_priv but then found another
way to access number of qgv points, through another structure already
stored there, then put it back, so thanks for spotting.
>
> > bool is_y_tile = true; /* assume y tile may be used */
> > int num_channels;
> > int deinterleave;
> > @@ -270,22 +294,6 @@ void intel_bw_init_hw(struct drm_i915_private
> > *dev_priv)
> > icl_get_bw_info(dev_priv, &icl_sa_info);
> > }
> >
> > -static unsigned int intel_max_data_rate(struct drm_i915_private
> > *dev_priv,
> > - int num_planes)
> > -{
> > - if (INTEL_GEN(dev_priv) >= 11)
> > - /*
> > - * FIXME with SAGV disabled maybe we can assume
> > - * point 1 will always be used? Seems to match
> > - * the behaviour observed in the wild.
> > - */
> > - return min3(icl_max_bw(dev_priv, num_planes, 0),
> > - icl_max_bw(dev_priv, num_planes, 1),
> > - icl_max_bw(dev_priv, num_planes, 2));
> > - else
> > - return UINT_MAX;
> > -}
> > -
> > static unsigned int intel_bw_crtc_num_active_planes(const struct
> > intel_crtc_state *crtc_state)
> > {
> > /*
> > @@ -377,7 +385,12 @@ int intel_bw_atomic_check(struct
> > intel_atomic_state *state)
> > unsigned int data_rate, max_data_rate;
> > unsigned int num_active_planes;
> > struct intel_crtc *crtc;
> > - int i;
> > + int i, ret;
> > + struct intel_qgv_info qi = {};
> > + u32 allowed_points = 0;
> > + unsigned int max_bw_point = 0, max_bw = 0;
> > + unsigned int num_qgv_points = dev_priv-
> > >max_bw[0].num_qgv_points;
> > + u32 mask = (1 << num_qgv_points) - 1;
> >
> > /* FIXME earlier gens need some checks too */
> > if (INTEL_GEN(dev_priv) < 11)
> > @@ -421,16 +434,92 @@ int intel_bw_atomic_check(struct
> > intel_atomic_state *state)
> > data_rate = intel_bw_data_rate(dev_priv, bw_state);
> > num_active_planes = intel_bw_num_active_planes(dev_priv,
> > bw_state);
> >
> > - max_data_rate = intel_max_data_rate(dev_priv,
> > num_active_planes);
> > -
> > data_rate = DIV_ROUND_UP(data_rate, 1000);
> >
> > - if (data_rate > max_data_rate) {
> > - DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available
> > %d MB/s (%d active planes)\n",
> > - data_rate, max_data_rate,
> > num_active_planes);
> > + for (i = 0; i < num_qgv_points; i++) {
> > + max_data_rate = icl_max_bw(dev_priv, num_active_planes,
> > i);
> > + /*
> > + * We need to know which qgv point gives us
> > + * maximum bandwidth in order to disable SAGV
> > + * if we find that we exceed SAGV block time
> > + * with watermarks. By that moment we already
> > + * have those, as it is calculated earlier in
> > + * intel_atomic_check,
> > + */
> > + if (max_data_rate > max_bw) {
> > + max_bw_point = i;
> > + max_bw = max_data_rate;
> > + }
> > + if (max_data_rate >= data_rate)
> > + allowed_points |= 1 << i;
>
> Minor nitpick; cleaner to use BIT(i) for this.
>
> > + DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
> > + i, max_data_rate, data_rate);
> > + }
> > +
> > + /*
> > + * BSpec states that we always should have at least one allowed
> > point
> > + * left, so if we couldn't - simply reject the configuration
> > for obvious
> > + * reasons.
> > + */
> > + if (allowed_points == 0) {
> > + DRM_DEBUG_KMS("Could not find any suitable QGV
> > points\n");
>
> We might want to make some mention of memory bandwidth in this
> message
> for people who don't know what a QGV point is. E.g., "No QGV points
> provide sufficient memory bandwidth for display configuration."
>
> > return -EINVAL;
> > }
> >
> > + /*
> > + * In case if SAGV is disabled in BIOS, we always get 1
> > + * SAGV point, but we can't send PCode commands to restrict it
> > + * as it will fail and pointless anyway.
> > + */
> > + if (qi.num_points == 1)
> > + dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
> > + else
> > + dev_priv->sagv_status = I915_SAGV_ENABLED;
> > +
> > + /*
> > + * Leave only single point with highest bandwidth, if
> > + * we can't enable SAGV according to BSpec.
> > + */
> > + if (!intel_can_enable_sagv(state)) {
> > +
> > + /*
> > + * This is a border line condition when we have 0
> > planes
> > + * and SAGV not enabled means that we should keep QGV
> > with
> > + * highest bandwidth, however algorithm returns wrong
> > result
> > + * for 0 planes and 0 data rate, so just stick to last
> > config
> > + * then. Otherwise use the QGV point with highest BW
> > according
> > + * to BSpec.
> > + */
>
> Isn't the QGV with the highest bandwidth constant? Can we just
> figure
> it out once at startup and then set it directly here instead of
> re-finding it each commit?
It seems to be constant however there is a mentioning in BSpec
something like
"there are cases when higher point allows less bandwidth than lower",
as I understand depending on contraints, the algorithm itself might
change, so I preferred not to rely on that we know which point provides
highest bandwidth but just calculate it. We could of course figure it
out only once, however not sure if something else won't ever change and
affect that. Iterating through few points doesn't seem to be too hard
anyway.
>
> > + if (!data_rate && !num_active_planes) {
> > + DRM_DEBUG_KMS("No SAGV, using old QGV mask\n");
> > + allowed_points = (~dev_priv->qgv_points_mask) &
> > mask;
> > + } else {
> > + allowed_points = 1 << max_bw_point;
> > + DRM_DEBUG_KMS("No SAGV, using single QGV point
> > %d\n",
> > + max_bw_point);
> > + }
> > + }
> > + /*
> > + * We store the ones which need to be masked as that is what
> > PCode
> > + * actually accepts as a parameter.
> > + */
> > + state->qgv_points_mask = (~allowed_points) & mask;
> > +
> > + DRM_DEBUG_KMS("New state %p qgv mask %x\n",
> > + state, state->qgv_points_mask);
> > +
> > + /*
> > + * If the actual mask had changed we need to make sure that
> > + * the commits are serialized(in case this is a nomodeset,
> > nonblocking)
> > + */
> > + if (state->qgv_points_mask != dev_priv->qgv_points_mask) {
> > + ret = intel_atomic_serialize_global_state(state);
> > + if (ret) {
> > + DRM_DEBUG_KMS("Could not serialize global
> > state\n");
> > + return ret;
> > + }
> > + }
> > +
> > return 0;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
> > b/drivers/gpu/drm/i915/display/intel_bw.h
> > index 9db10af012f4..66bf9bc10b73 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > @@ -28,5 +28,7 @@ int intel_bw_init(struct drm_i915_private
> > *dev_priv);
> > int intel_bw_atomic_check(struct intel_atomic_state *state);
> > void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> > const struct intel_crtc_state *crtc_state);
> > +int icl_pcode_restrict_qgv_points(struct drm_i915_private
> > *dev_priv,
> > + u32 points_mask);
> >
> > #endif /* __INTEL_BW_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 7ea1e7518ab6..71f6aaa1f6b9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -14744,6 +14744,80 @@ static void
> > intel_atomic_cleanup_work(struct work_struct *work)
> > intel_atomic_helper_free_state(i915);
> > }
> >
> > +static void intel_qgv_points_mask(struct intel_atomic_state
> > *state)
> > +{
> > + struct drm_device *dev = state->base.dev;
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + int ret;
> > + u32 new_mask = dev_priv->qgv_points_mask | state-
> > >qgv_points_mask;
> > + unsigned int num_qgv_points = dev_priv-
> > >max_bw[0].num_qgv_points;
> > + unsigned int mask = (1 << num_qgv_points) - 1;
> > +
> > + /*
> > + * As we don't know initial hardware state during initial
> > commit
> > + * we should not do anything, until we actually figure out,
> > + * what are the qgv points to mask.
> > + */
> > + if (!new_mask)
> > + return;
> > +
> > + WARN_ON(new_mask == mask);
> > +
> > + /*
> > + * Just return if we can't control SAGV or don't have it.
> > + */
> > + if (!intel_has_sagv(dev_priv))
> > + return;
> > +
> > + /*
> > + * Restrict required qgv points before updating the
> > configuration.
> > + * According to BSpec we can't mask and unmask qgv points at
> > the same
> > + * time. Also masking should be done before updating the
> > configuration
> > + * and unmasking afterwards.
> > + */
> > + ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> > + if (ret < 0)
> > + DRM_DEBUG_KMS("Could not restrict required qgv
> > points(%d)\n",
> > + ret);
> > + else
> > + dev_priv->qgv_points_mask = new_mask;
> > +}
> > +
> > +static void intel_qgv_points_unmask(struct intel_atomic_state
> > *state)
> > +{
> > + struct drm_device *dev = state->base.dev;
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + int ret;
> > + u32 new_mask = dev_priv->qgv_points_mask & state-
> > >qgv_points_mask;
> > +
> > + /*
> > + * As we don't know initial hardware state during initial
> > commit
> > + * we should not do anything, until we actually figure out,
> > + * what are the qgv points to mask.
> > + */
> > + if (!new_mask)
> > + return;
> > +
> > + /*
> > + * Just return if we can't control SAGV or don't have it.
> > + */
> > + if (!intel_has_sagv(dev_priv))
> > + return;
> > +
> > + /*
> > + * Allow required qgv points after updating the configuration.
> > + * According to BSpec we can't mask and unmask qgv points at
> > the same
> > + * time. Also masking should be done before updating the
> > configuration
> > + * and unmasking afterwards.
> > + */
> > + ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> > + if (ret < 0)
> > + DRM_DEBUG_KMS("Could not restrict required qgv
> > points(%d)\n",
> > + ret);
> > + else
> > + dev_priv->qgv_points_mask = new_mask;
> > +}
> > +
> > static void intel_atomic_commit_tail(struct intel_atomic_state
> > *state)
> > {
> > struct drm_device *dev = state->base.dev;
> > @@ -14771,6 +14845,9 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> > }
> > }
> >
> > + if ((INTEL_GEN(dev_priv) >= 11))
> > + intel_qgv_points_mask(state);
> > +
> > intel_commit_modeset_disables(state);
> >
> > /* FIXME: Eventually get rid of our crtc->config pointer */
> > @@ -14789,8 +14866,9 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> > * SKL workaround: bspec recommends we disable the SAGV
> > when we
> > * have more then one pipe enabled
> > */
> > - if (!intel_can_enable_sagv(state))
> > - intel_disable_sagv(dev_priv);
> > + if (INTEL_GEN(dev_priv) < 11)
> > + if (!intel_can_enable_sagv(state))
> > + intel_disable_sagv(dev_priv);
> >
> > intel_modeset_verify_disabled(dev_priv, state);
> > }
> > @@ -14873,8 +14951,11 @@ static void
> > intel_atomic_commit_tail(struct intel_atomic_state *state)
> > if (state->modeset)
> > intel_verify_planes(state);
> >
> > - if (state->modeset && intel_can_enable_sagv(state))
> > - intel_enable_sagv(dev_priv);
> > + if (INTEL_GEN(dev_priv) < 11) {
> > + if (state->modeset && intel_can_enable_sagv(state))
> > + intel_enable_sagv(dev_priv);
> > + } else
> > + intel_qgv_points_unmask(state);
> >
> > drm_atomic_helper_commit_hw_done(&state->base);
> >
> > @@ -14962,7 +15043,18 @@ static int intel_atomic_commit(struct
> > drm_device *dev,
> > {
> > struct intel_atomic_state *state =
> > to_intel_atomic_state(_state);
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > - int ret = 0;
> > + struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> > + int ret = 0, i;
> > + bool any_ms = false;
> > + struct intel_crtc *crtc;
> > +
> > + for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state,
> > + new_crtc_state, i) {
> > + if (needs_modeset(new_crtc_state)) {
> > + any_ms = true;
> > + break;
> > + }
> > + }
>
> I think we already have this in state->modeset.
>
> >
> > state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> >
> > @@ -15021,7 +15113,7 @@ static int intel_atomic_commit(struct
> > drm_device *dev,
> > intel_shared_dpll_swap_state(state);
> > intel_atomic_track_fbs(state);
> >
> > - if (state->global_state_changed) {
> > + if (state->global_state_changed && any_ms) {
> > assert_global_state_locked(dev_priv);
> >
> > memcpy(dev_priv->min_cdclk, state->min_cdclk,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index fb274538af23..896b13bc4494 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -528,6 +528,9 @@ struct intel_atomic_state {
> > struct i915_sw_fence commit_ready;
> >
> > struct llist_node freed;
> > +
> > + /* Gen11+ only */
> > + u32 qgv_points_mask;
> > };
> >
> > struct intel_plane_state {
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 4f4e2e839513..9924390cb94b 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1243,11 +1243,13 @@ struct drm_i915_private {
> > } dram_info;
> >
> > struct intel_bw_info {
> > - unsigned int deratedbw[3]; /* for each QGV point */
> > + unsigned int deratedbw[NUM_SAGV_POINTS]; /* for each
> > QGV point */
> > u8 num_qgv_points;
> > u8 num_planes;
> > } max_bw[6];
> >
> > + u32 qgv_points_mask;
> > +
> > struct drm_private_obj bw_obj;
> >
> > struct intel_runtime_pm runtime_pm;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index a607ea520829..6d6ecf1d9f6b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8951,6 +8951,9 @@ enum {
> > #define VLV_RENDER_C0_COUNT _MMIO(0x138118)
> > #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
> >
> > +/* BSpec precisely defines this */
> > +#define NUM_SAGV_POINTS 8
> > +
>
> Any specific reason this is in the reg file rather than either
> i915_drv.h where it's used or something like intel_bw.h?
Probably none. I can look for a better place for this.
>
> > #define GEN6_PCODE_MAILBOX _MMIO(0x138124)
> > #define GEN6_PCODE_READY (1 << 31)
> > #define GEN6_PCODE_ERROR_MASK 0xFF
> > @@ -8961,6 +8964,8 @@ enum {
> > #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
> > #define GEN7_PCODE_TIMEOUT 0x2
> > #define GEN7_PCODE_ILLEGAL_DATA 0x3
> > +#define GEN11_PCODE_MAIL_BOX_LOCKED 0x6
> > +#define GEN11_PCODE_REJECTED 0x11
> > #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
> > #define GEN6_PCODE_WRITE_RC6VIDS 0x4
> > #define GEN6_PCODE_READ_RC6VIDS 0x5
> > @@ -8982,6 +8987,7 @@ enum {
> > #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
> > #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
> > #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((poin
> > t) << 16) | (0x1 << 8))
> > +#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
> > #define GEN6_PCODE_READ_D_COMP 0x10
> > #define GEN6_PCODE_WRITE_D_COMP 0x11
> > #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
> > @@ -8994,6 +9000,8 @@ enum {
> > #define GEN9_SAGV_IS_DISABLED 0x1
> > #define GEN9_SAGV_ENABLE 0x3
> > #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
> > +#define GEN11_PCODE_POINTS_RESTRICTED 0x0
> > +#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
> > #define GEN6_PCODE_DATA _MMIO(0x138128)
> > #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
> > #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index c792dd168742..10816f3e29f0 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3617,13 +3617,9 @@ static bool skl_needs_memory_bw_wa(struct
> > drm_i915_private *dev_priv)
> > return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
> > }
> >
> > -static bool
> > +bool
> > intel_has_sagv(struct drm_i915_private *dev_priv)
> > {
> > - /* HACK! */
> > - if (IS_GEN(dev_priv, 12))
> > - return false;
> > -
> > return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
> > dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
> > }
> > @@ -3839,7 +3835,7 @@ static void icl_set_sagv_mask(struct
> > intel_atomic_state *state)
> > if (flags & DRM_MODE_FLAG_INTERLACE)
> > continue;
> >
> > - if (!new_crtc_state->base.active)
> > + if (!new_crtc_state->hw.enable)
> > continue;
>
> Looks like this was a bug in the previous patch. Any specific reason
> we're switching from active to enable?
Yees, we discussed that with Ville, there are seems to be some
confusion about when to use active or enable. In intel_pm many
functions were using enable so I simply followed same approach, as
I understood in theory we should use "active" here, however there were
recent changes, separating hw state and uapi which probably confused me
into using this again.
>
> >
> > can_sagv = true;
> > @@ -3886,6 +3882,9 @@ bool intel_can_enable_sagv(struct
> > intel_atomic_state *state)
> > else
> > skl_set_sagv_mask(state);
> >
> > + DRM_DEBUG_KMS("Crtc sagv masks, state %x global state %x\n",
> > + state->crtc_sagv_mask,
> > + dev_priv->crtc_sagv_mask);
> > /*
> > * For SAGV we need to account all the pipes,
> > * not only the ones which are in state currently.
> > @@ -4340,7 +4339,7 @@ static int
> > tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
> > struct skl_ddb_allocation *ddb /* out */)
> > {
> > - struct drm_crtc *crtc = crtc_state->base.crtc;
> > + struct drm_crtc *crtc = crtc_state->uapi.crtc;
>
> Also a bug in the previous patch.
>
>
> > struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> > struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
> > @@ -4833,7 +4832,6 @@ static void skl_compute_plane_wm(const struct
> > intel_crtc_state *crtc_state,
> > struct skl_wm_level *result /* out */)
> > {
> > struct drm_i915_private *dev_priv = to_i915(crtc_state-
> > >uapi.crtc->dev);
> > - u32 latency = dev_priv->wm.skl_latency[level];
>
> Mentioned on previous patch.
>
>
> > uint_fixed_16_16_t method1, method2;
> > uint_fixed_16_16_t selected_result;
> > u32 res_blocks, res_lines, min_ddb_alloc = 0;
> > @@ -5707,6 +5705,7 @@ static void tgl_set_sagv_mask(struct
> > intel_atomic_state *state)
> > ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
> > if (!ret) {
> > int pipe_bit = BIT(crtc->pipe);
> > +
> > state->crtc_sagv_mask |= pipe_bit;
>
> Unrelated change.
>
> > }
> > }
> > diff --git a/drivers/gpu/drm/i915/intel_pm.h
> > b/drivers/gpu/drm/i915/intel_pm.h
> > index b579c724b915..53275860731a 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.h
> > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > @@ -43,6 +43,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc
> > *crtc,
> > void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> > void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> > bool intel_can_enable_sagv(struct intel_atomic_state *state);
> > +bool intel_has_sagv(struct drm_i915_private *dev_priv);
> > int intel_enable_sagv(struct drm_i915_private *dev_priv);
> > int intel_disable_sagv(struct drm_i915_private *dev_priv);
> > bool skl_wm_level_equals(const struct skl_wm_level *l1,
> > diff --git a/drivers/gpu/drm/i915/intel_sideband.c
> > b/drivers/gpu/drm/i915/intel_sideband.c
> > index e06b35b844a0..ff9dbed094d8 100644
> > --- a/drivers/gpu/drm/i915/intel_sideband.c
> > +++ b/drivers/gpu/drm/i915/intel_sideband.c
> > @@ -371,6 +371,29 @@ static inline int
> > gen7_check_mailbox_status(u32 mbox)
> > }
> > }
> >
> > +static inline int gen11_check_mailbox_status(u32 mbox)
> > +{
> > + switch (mbox & GEN6_PCODE_ERROR_MASK) {
> > + case GEN6_PCODE_SUCCESS:
> > + return 0;
> > + case GEN6_PCODE_ILLEGAL_CMD:
> > + return -ENXIO;
> > + case GEN7_PCODE_TIMEOUT:
> > + return -ETIMEDOUT;
> > + case GEN7_PCODE_ILLEGAL_DATA:
> > + return -EINVAL;
> > + case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
> > + return -EOVERFLOW;
> > + case GEN11_PCODE_MAIL_BOX_LOCKED:
> > + return -EAGAIN;
> > + case GEN11_PCODE_REJECTED:
> > + return -EACCES;
> > + default:
> > + MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
> > + return 0;
> > + }
> > +}
> > +
> > static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
> > u32 mbox, u32 *val, u32 *val1,
> > int fast_timeout_us,
> > @@ -408,7 +431,9 @@ static int __sandybridge_pcode_rw(struct
> > drm_i915_private *i915,
> > if (is_read && val1)
> > *val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
> >
> > - if (INTEL_GEN(i915) > 6)
> > + if (INTEL_GEN(i915) >= 11)
> > + return gen11_check_mailbox_status(mbox);
> > + else if (INTEL_GEN(i915) > 6)
> > return gen7_check_mailbox_status(mbox);
> > else
> > return gen6_check_mailbox_status(mbox);
> > diff --git a/drivers/gpu/drm/i915/intel_sideband.h
> > b/drivers/gpu/drm/i915/intel_sideband.h
> > index 7fb95745a444..14627ace99ae 100644
> > --- a/drivers/gpu/drm/i915/intel_sideband.h
> > +++ b/drivers/gpu/drm/i915/intel_sideband.h
> > @@ -137,5 +137,4 @@ int sandybridge_pcode_write_timeout(struct
> > drm_i915_private *i915, u32 mbox,
> >
> > int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32
> > request,
> > u32 reply_mask, u32 reply, int timeout_base_ms);
> > -
> > #endif /* _INTEL_SIDEBAND_H */
>
> Unrelated change.
>
>
> In general, I wonder if we could break this patch up a bit more. It
> seems like there are a lot of moving pieces here which makes it a bit
> harder to review.
Sounds like good idea, we seem to need a fix for static QGV array
warning which we get for tgl, so I will probably try to split out
that part with some preparation stuff to make this at least look
less complex.
- Stan
>
>
> Matt
>
>
> > --
> > 2.17.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v10 0/2] Refactor Gen11+ SAGV support
@ 2019-11-07 10:22 Stanislav Lisovskiy
0 siblings, 0 replies; 25+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-07 10:22 UTC (permalink / raw)
To: intel-gfx
For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.
Stanislav Lisovskiy (2):
drm/i915: Refactor intel_can_enable_sagv
drm/i915: Restrict qgv points which don't have enough bandwidth.
drivers/gpu/drm/i915/display/intel_atomic.h | 3 +
drivers/gpu/drm/i915/display/intel_bw.c | 137 ++++++--
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 101 +++++-
.../drm/i915/display/intel_display_types.h | 12 +
drivers/gpu/drm/i915/i915_drv.h | 10 +-
drivers/gpu/drm/i915/i915_reg.h | 8 +
drivers/gpu/drm/i915/intel_pm.c | 307 +++++++++++++++++-
drivers/gpu/drm/i915/intel_pm.h | 1 +
drivers/gpu/drm/i915/intel_sideband.c | 27 +-
drivers/gpu/drm/i915/intel_sideband.h | 1 -
11 files changed, 560 insertions(+), 49 deletions(-)
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v10 0/2] Refactor Gen11+ SAGV support
@ 2019-11-05 15:57 Stanislav Lisovskiy
0 siblings, 0 replies; 25+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-05 15:57 UTC (permalink / raw)
To: intel-gfx
For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.
Stanislav Lisovskiy (2):
drm/i915: Refactor intel_can_enable_sagv
drm/i915: Restrict qgv points which don't have enough bandwidth.
drivers/gpu/drm/i915/display/intel_atomic.h | 3 +
drivers/gpu/drm/i915/display/intel_bw.c | 118 +++++--
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 73 ++++-
.../drm/i915/display/intel_display_types.h | 12 +
drivers/gpu/drm/i915/i915_drv.h | 10 +-
drivers/gpu/drm/i915/i915_reg.h | 8 +
drivers/gpu/drm/i915/intel_pm.c | 303 ++++++++++++++++--
drivers/gpu/drm/i915/intel_pm.h | 1 +
drivers/gpu/drm/i915/intel_sideband.c | 27 +-
10 files changed, 510 insertions(+), 47 deletions(-)
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v10 0/2] Refactor Gen11+ SAGV support
@ 2019-11-01 12:35 Stanislav Lisovskiy
0 siblings, 0 replies; 25+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-01 12:35 UTC (permalink / raw)
To: intel-gfx
For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.
Stanislav Lisovskiy (2):
drm/i915: Refactor intel_can_enable_sagv
drm/i915: Restrict qgv points which don't have enough bandwidth.
drivers/gpu/drm/i915/display/intel_atomic.h | 3 +
drivers/gpu/drm/i915/display/intel_bw.c | 108 +++++--
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 61 +++-
.../drm/i915/display/intel_display_types.h | 12 +
drivers/gpu/drm/i915/i915_drv.h | 10 +-
drivers/gpu/drm/i915/i915_reg.h | 8 +
drivers/gpu/drm/i915/intel_pm.c | 299 +++++++++++++++++-
drivers/gpu/drm/i915/intel_sideband.c | 27 +-
9 files changed, 487 insertions(+), 43 deletions(-)
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2019-11-12 16:18 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-07 15:30 [PATCH v10 0/2] Refactor Gen11+ SAGV support Stanislav Lisovskiy
2019-11-07 15:30 ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-07 15:30 ` [PATCH v10 1/2] drm/i915: Refactor intel_can_enable_sagv Stanislav Lisovskiy
2019-11-07 15:30 ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-12 0:15 ` Matt Roper
2019-11-12 0:15 ` [Intel-gfx] " Matt Roper
2019-11-12 16:04 ` Lisovskiy, Stanislav
2019-11-12 16:04 ` [Intel-gfx] " Lisovskiy, Stanislav
2019-11-07 15:30 ` [PATCH v10 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
2019-11-07 15:30 ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-12 1:22 ` Matt Roper
2019-11-12 1:22 ` [Intel-gfx] " Matt Roper
2019-11-12 16:18 ` Lisovskiy, Stanislav
2019-11-12 16:18 ` [Intel-gfx] " Lisovskiy, Stanislav
2019-11-07 19:43 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev10) Patchwork
2019-11-07 19:43 ` [Intel-gfx] " Patchwork
2019-11-07 19:44 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-11-07 19:44 ` [Intel-gfx] " Patchwork
2019-11-07 20:04 ` ✓ Fi.CI.BAT: success " Patchwork
2019-11-07 20:04 ` [Intel-gfx] " Patchwork
2019-11-09 1:49 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-11-09 1:49 ` [Intel-gfx] " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2019-11-07 10:22 [PATCH v10 0/2] Refactor Gen11+ SAGV support Stanislav Lisovskiy
2019-11-05 15:57 Stanislav Lisovskiy
2019-11-01 12:35 Stanislav Lisovskiy
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