[igt-dev] [PATCH i-g-t 1/3] test/perf: Add support for TGL in perf tests

[igt-dev] [PATCH i-g-t 1/3] test/perf: Add support for TGL in perf tests

[Umesh Nerlige Ramappa]

Add following changes to enable perf tests on TGL
- Support only a single OA format
- Add TGL metrics
- Update whitelist test case
- Cleanup mi-rpc test if it fails
- Skip unsupported test - gen8-unprivileged-single-ctx-counters

v2: Remove error cleanup in mi-rpc
v3: Use the right address for NOA WRITE (Lionel)

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 tests/perf.c | 61 +++++++++++++++++++++++++++++++++++++++-------------
 1 file changed, 46 insertions(+), 15 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index 5ad8b2db..2b6be134 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -159,6 +159,15 @@ static struct oa_format gen8_oa_formats[I915_OA_FORMAT_MAX] = {
 		.b_off = 32, .n_b = 8, },
 };
 
+static struct oa_format gen12_oa_formats[I915_OA_FORMAT_MAX] = {
+	[I915_OA_FORMAT_A32u40_A4u32_B8_C8] = {
+		"A32u40_A4u32_B8_C8", .size = 256,
+		.a40_high_off = 160, .a40_low_off = 16, .n_a40 = 32,
+		.a_off = 144, .n_a = 4, .first_a = 32,
+		.b_off = 192, .n_b = 8,
+		.c_off = 224, .n_c = 8, },
+};
+
 static bool hsw_undefined_a_counters[45] = {
 	[4] = true,
 	[6] = true,
@@ -206,7 +215,10 @@ get_oa_format(enum drm_i915_oa_format format)
 {
 	if (IS_HASWELL(devid))
 		return hsw_oa_formats[format];
-	return gen8_oa_formats[format];
+	else if (IS_GEN12(devid))
+		return gen12_oa_formats[format];
+	else
+		return gen8_oa_formats[format];
 }
 
 static void
@@ -945,6 +957,8 @@ init_sys_info(void)
 			test_set_uuid = "db41edd4-d8e7-4730-ad11-b9a2d6833503";
 		} else if (IS_ICELAKE(devid)) {
 			test_set_uuid = "a291665e-244b-4b76-9b9a-01de9d3c8068";
+		} else if (IS_TIGERLAKE(devid)) {
+			test_set_uuid = "80a833f0-2504-4321-8894-e9277844ce7b";
 		} else {
 			igt_debug("unsupported GT\n");
 			return false;
@@ -3846,6 +3860,8 @@ test_whitelisted_registers_userspace_config(void)
 	uint32_t b_counters_regs[200];
 	uint32_t flex_regs[200];
 	uint32_t i;
+	uint32_t oa_start_trig1, oa_start_trig8;
+	uint32_t oa_report_trig1, oa_report_trig8;
 	uint64_t config_id;
 	char path[512];
 	int ret;
@@ -3869,14 +3885,26 @@ test_whitelisted_registers_userspace_config(void)
 	memset(&config, 0, sizeof(config));
 	memcpy(config.uuid, uuid, sizeof(config.uuid));
 
+	if (intel_gen(devid) >= 12) {
+		oa_start_trig1 = 0xd900;
+		oa_start_trig8 = 0xd91c;
+		oa_report_trig1 = 0xd920;
+		oa_report_trig8 = 0xd93c;
+	} else {
+		oa_start_trig1 = 0x2710;
+		oa_start_trig8 = 0x272c;
+		oa_report_trig1 = 0x2740;
+		oa_report_trig8 = 0x275c;
+	}
+
 	/* OASTARTTRIG[1-8] */
-	for (i = 0x2710; i <= 0x272c; i += 4) {
+	for (i = oa_start_trig1; i <= oa_start_trig8; i += 4) {
 		b_counters_regs[config.n_boolean_regs * 2] = i;
 		b_counters_regs[config.n_boolean_regs * 2 + 1] = 0;
 		config.n_boolean_regs++;
 	}
 	/* OAREPORTTRIG[1-8] */
-	for (i = 0x2740; i <= 0x275c; i += 4) {
+	for (i = oa_report_trig1; i <= oa_report_trig8; i += 4) {
 		b_counters_regs[config.n_boolean_regs * 2] = i;
 		b_counters_regs[config.n_boolean_regs * 2 + 1] = 0;
 		config.n_boolean_regs++;
@@ -3897,7 +3925,7 @@ test_whitelisted_registers_userspace_config(void)
 	i = 0;
 
 	/* NOA_WRITE */
-	mux_regs[i++] = 0x9800;
+	mux_regs[i++] = 0x9888;
 	mux_regs[i++] = 0;
 
 	if (IS_HASWELL(devid)) {
@@ -3922,10 +3950,6 @@ test_whitelisted_registers_userspace_config(void)
 		mux_regs[i++] = 0;
 	}
 
-	/* HALF_SLICE_CHICKEN2 (shared with kernel workaround) */
-	mux_regs[i++] = 0xE180;
-	mux_regs[i++] = 0;
-
 	if (IS_CHERRYVIEW(devid)) {
 		/* Cherryview specific. undocumented... */
 		mux_regs[i++] = 0x182300;
@@ -3934,12 +3958,17 @@ test_whitelisted_registers_userspace_config(void)
 		mux_regs[i++] = 0;
 	}
 
-	/* PERFCNT[12] */
-	mux_regs[i++] = 0x91B8;
-	mux_regs[i++] = 0;
-	/* PERFMATRIX */
-	mux_regs[i++] = 0x91C8;
-	mux_regs[i++] = 0;
+	if (intel_gen(devid) <= 11) {
+		/* HALF_SLICE_CHICKEN2 (shared with kernel workaround) */
+		mux_regs[i++] = 0xE180;
+		mux_regs[i++] = 0;
+		/* PERFCNT[12] */
+		mux_regs[i++] = 0x91B8;
+		mux_regs[i++] = 0;
+		/* PERFMATRIX */
+		mux_regs[i++] = 0x91C8;
+		mux_regs[i++] = 0;
+	}
 
 	config.mux_regs_ptr = (uintptr_t) mux_regs;
 	config.n_mux_regs = i / 2;
@@ -4170,8 +4199,10 @@ igt_main
 		 * functionality to HW filter timer reports for a specific
 		 * context (SKL+) can't stop multiple applications viewing
 		 * system-wide data via MI_REPORT_PERF_COUNT commands.
+		 *
+		 * For gen12 implement a separate test that uses only OAR
 		 */
-		igt_require(intel_gen(devid) >= 8);
+		igt_require(intel_gen(devid) >= 8 && intel_gen(devid) < 12);
 		gen8_test_single_ctx_render_target_writes_a_counter();
 	}
 
-- 
2.23.0

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[igt-dev] [PATCH i-g-t 2/3] test/perf: Add test for TGL OAR unit

[Umesh Nerlige Ramappa]

Add a test that measures work using MI-RPC for the specific context
without using reports from the OA buffer.

Tigerlake introduces an OA unit that measures work specific to render
workloads. This means we do not have to rely on reports from the OA
buffer to normalize the reports obtained from MI REPORT PERF COUNT
anymore.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/perf.c | 353 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 353 insertions(+)

diff --git a/tests/perf.c b/tests/perf.c
index 2b6be134..b439e5bd 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -210,6 +210,19 @@ static uint32_t (*read_report_ticks)(uint32_t *report,
 static void (*sanity_check_reports)(uint32_t *oa_report0, uint32_t *oa_report1,
 				    enum drm_i915_oa_format format);
 
+static void
+dump_report(const uint32_t *report, uint32_t size, const char *message) {
+	uint32_t i;
+	igt_debug("%s\n", message);
+	for (i = 0; i < size; i += 4) {
+		igt_debug("%08x %08x %08x %08x\n",
+				report[i],
+				report[i + 1],
+				report[i + 2],
+				report[i + 3]);
+	}
+}
+
 static struct oa_format
 get_oa_format(enum drm_i915_oa_format format)
 {
@@ -874,6 +887,7 @@ init_sys_info(void)
 	igt_assert_neq(devid, 0);
 
 	timestamp_frequency = get_cs_timestamp_frequency();
+	igt_debug("timestamp_frequency = %lu\n", timestamp_frequency);
 	igt_assert_neq(timestamp_frequency, 0);
 
 	if (IS_HASWELL(devid)) {
@@ -1289,6 +1303,7 @@ read_2_oa_reports(int format_id,
 			igt_assert_eq(header->size, sample_size);
 
 			report = (const void *)(header + 1);
+			dump_report(report, 64, "oa-formats");
 
 			igt_debug("read report: reason = %x, timestamp = %x, exponent mask=%x\n",
 				  report[0], report[1], exponent_mask);
@@ -2856,6 +2871,7 @@ test_mi_rpc(void)
 	igt_assert_eq(ret, 0);
 
 	report32 = bo->virtual;
+	dump_report(report32, 64, "mi-rpc");
 	igt_assert_eq(report32[0], 0xdeadbeef); /* report ID */
 	igt_assert_neq(report32[1], 0); /* timestamp */
 
@@ -3335,11 +3351,13 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
 			prev = report0_32;
 			ctx_id = prev[2];
 			igt_debug("MI_RPC(start) CTX ID: %u\n", ctx_id);
+			dump_report(report0_32, 64, "report0_32");
 
 			report1_32 = report0_32 + 64; /* 64 uint32_t = 256bytes offset */
 			igt_assert_eq(report1_32[0], 0xbeefbeef); /* report ID */
 			igt_assert_neq(report1_32[1], 0); /* timestamp */
 			ctx1_id = report1_32[2];
+			dump_report(report1_32, 64, "report1_32");
 
 			memset(accumulator.deltas, 0, sizeof(accumulator.deltas));
 			accumulate_reports(&accumulator, report0_32, report1_32);
@@ -3434,6 +3452,7 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
 				igt_assert_eq(header->size, sample_size);
 
 				report = (void *)(header + 1);
+				dump_report(report, 64, "OA report");
 
 				/* Don't expect zero for timestamps */
 				igt_assert_neq(report[1], 0);
@@ -3581,6 +3600,335 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
 	} while (WEXITSTATUS(child_ret) == EAGAIN);
 }
 
+static void gen12_single_ctx_helper(struct drm_i915_perf_open_param *param)
+{
+	uint64_t *ctx_id_ptr;
+	drm_intel_bufmgr *bufmgr;
+	drm_intel_context *context0, *context1;
+	struct intel_batchbuffer *batch;
+	struct igt_buf src[3], dst[3];
+	drm_intel_bo *bo;
+	uint32_t *report0_32, *report1_32, *report2_32, *report3_32;
+	uint64_t timestamp0_64, timestamp1_64;
+	uint32_t delta_ts64, delta_oa32;
+	uint64_t delta_ts64_ns, delta_oa32_ns;
+	uint32_t delta_delta;
+	int width = 800;
+	int height = 600;
+#define INVALID_CTX_ID 0xffffffff
+	uint32_t ctx0_id = INVALID_CTX_ID;
+	uint32_t ctx1_id = INVALID_CTX_ID;
+	int ret;
+	struct accumulator accumulator = {
+		.format = test_oa_format
+	};
+
+	bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
+	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
+
+	for (int i = 0; i < ARRAY_SIZE(src); i++) {
+		scratch_buf_init(bufmgr, &src[i], width, height, 0xff0000ff);
+		scratch_buf_init(bufmgr, &dst[i], width, height, 0x00ff00ff);
+	}
+
+	batch = intel_batchbuffer_alloc(bufmgr, devid);
+
+	context0 = drm_intel_gem_context_create(bufmgr);
+	igt_assert(context0);
+
+	context1 = drm_intel_gem_context_create(bufmgr);
+	igt_assert(context1);
+
+	igt_debug("submitting warm up render_copy\n");
+
+	/* Submit some early, unmeasured, work to the context we want
+	 * to measure to try and catch issues with i915-perf
+	 * initializing the HW context ID for filtering.
+	 *
+	 * We do this because i915-perf single context filtering had
+	 * previously only relied on a hook into context pinning to
+	 * initialize the HW context ID, instead of also trying to
+	 * determine the HW ID while opening the stream, in case it
+	 * has already been pinned.
+	 *
+	 * This wasn't noticed by the previous unit test because we
+	 * were opening the stream while the context hadn't been
+	 * touched or pinned yet and so it worked out correctly to wait
+	 * for the pinning hook.
+	 *
+	 * Now a buggy version of i915-perf will fail to measure
+	 * anything for context0 once this initial render_copy() ends
+	 * up pinning the context since there won't ever be a pinning
+	 * hook callback.
+	 */
+	render_copy(batch, context0,
+		    &src[0], 0, 0, width, height,
+		    &dst[0], 0, 0);
+
+	/* Initialize the context parameter to the perf open ioctl here */
+	ret = drm_intel_gem_context_get_id(context0, &ctx0_id);
+	igt_assert_eq(ret, 0);
+	igt_assert_neq(ctx0_id, 0xffffffff);
+	ctx_id_ptr = (uint64_t *) from_user_pointer(param->properties_ptr);
+	ctx_id_ptr[1] = ctx0_id;
+
+	igt_debug("opening i915-perf stream\n");
+	stream_fd = __perf_open(drm_fd, param, false);
+
+	bo = drm_intel_bo_alloc(bufmgr, "mi_rpc dest bo", 4096, 64);
+
+	/* Set write domain to cpu briefly to fill the buffer with 80s */
+	ret = drm_intel_bo_map(bo, true);
+	igt_assert_eq(ret, 0);
+	memset(bo->virtual, 0x80, 2048);
+	memset(bo->virtual + 2048, 0, 2048);
+	drm_intel_bo_unmap(bo);
+
+	/* Submit an mi-rpc to context0 before measurable work */
+#define BO_TIMESTAMP_OFFSET0 1024
+#define BO_REPORT_OFFSET0 0
+#define BO_REPORT_ID0 0xdeadbeef
+	emit_stall_timestamp_and_rpc(batch,
+				     bo,
+				     BO_TIMESTAMP_OFFSET0,
+				     BO_REPORT_OFFSET0,
+				     BO_REPORT_ID0);
+	intel_batchbuffer_flush_with_context(batch, context0);
+
+	/* This is the work/context that is measured for counter increments */
+	render_copy(batch, context0,
+		    &src[0], 0, 0, width, height,
+		    &dst[0], 0, 0);
+	intel_batchbuffer_flush_with_context(batch, context0);
+
+	/* Submit an mi-rpc to context1 before work
+	 *
+	 * On gen12, this measurement should just yield counters that are
+	 * all zeroes, since the counters will only increment for the
+	 * context passed to perf open ioctl
+	 */
+#define BO_TIMESTAMP_OFFSET2 1040
+#define BO_REPORT_OFFSET2 512
+#define BO_REPORT_ID2 0x00c0ffee
+	emit_stall_timestamp_and_rpc(batch,
+				     bo,
+				     BO_TIMESTAMP_OFFSET2,
+				     BO_REPORT_OFFSET2,
+				     BO_REPORT_ID2);
+	intel_batchbuffer_flush_with_context(batch, context1);
+
+	/* Submit two copies on the other context to avoid a false
+	 * positive in case the driver somehow ended up filtering for
+	 * context1
+	 */
+	render_copy(batch, context1,
+		    &src[1], 0, 0, width, height,
+		    &dst[1], 0, 0);
+	ret = drm_intel_gem_context_get_id(context1, &ctx1_id);
+	igt_assert_eq(ret, 0);
+	igt_assert_neq(ctx1_id, 0xffffffff);
+
+	render_copy(batch, context1,
+		    &src[2], 0, 0, width, height,
+		    &dst[2], 0, 0);
+	intel_batchbuffer_flush_with_context(batch, context1);
+
+	/* Submit an mi-rpc to context1 after all work */
+#define BO_TIMESTAMP_OFFSET3 1048
+#define BO_REPORT_OFFSET3 768
+#define BO_REPORT_ID3 0x01c0ffee
+	emit_stall_timestamp_and_rpc(batch,
+				     bo,
+				     BO_TIMESTAMP_OFFSET3,
+				     BO_REPORT_OFFSET3,
+				     BO_REPORT_ID3);
+	intel_batchbuffer_flush_with_context(batch, context1);
+
+	/* Submit an mi-rpc to context0 after all measurable work */
+#define BO_TIMESTAMP_OFFSET1 1032
+#define BO_REPORT_OFFSET1 256
+#define BO_REPORT_ID1 0xbeefbeef
+	emit_stall_timestamp_and_rpc(batch,
+				     bo,
+				     BO_TIMESTAMP_OFFSET1,
+				     BO_REPORT_OFFSET1,
+				     BO_REPORT_ID1);
+	intel_batchbuffer_flush_with_context(batch, context0);
+
+	/* Set write domain to none */
+	ret = drm_intel_bo_map(bo, false);
+	igt_assert_eq(ret, 0);
+
+	/* Sanity check reports
+	 * reportX_32[0]: report id passed with mi-rpc
+	 * reportX_32[1]: timestamp
+	 * reportX_32[2]: context id
+	 *
+	 * report0_32: start of measurable work
+	 * report1_32: end of measurable work
+	 * report2_32: start of other work
+	 * report3_32: end of other work
+	 */
+	report0_32 = bo->virtual;
+	igt_assert_eq(report0_32[0], 0xdeadbeef);
+	igt_assert_neq(report0_32[1], 0);
+	ctx0_id = report0_32[2];
+	igt_debug("MI_RPC(start) CTX ID: %u\n", ctx0_id);
+	dump_report(report0_32, 64, "report0_32");
+
+	report1_32 = report0_32 + 64;
+	igt_assert_eq(report1_32[0], 0xbeefbeef);
+	igt_assert_neq(report1_32[1], 0);
+	ctx1_id = report1_32[2];
+	dump_report(report1_32, 64, "report1_32");
+
+	/* Verify that counters in context1 are all zeroes */
+	report2_32 = report0_32 + 128;
+	igt_assert_eq(report2_32[0], 0x00c0ffee);
+	igt_assert_neq(report2_32[1], 0);
+	dump_report(report2_32, 64, "report2_32");
+	igt_assert_eq(0, memcmp(&report2_32[4],
+				bo->virtual + 2048,
+				240));
+
+	report3_32 = report0_32 + 192;
+	igt_assert_eq(report3_32[0], 0x01c0ffee);
+	igt_assert_neq(report3_32[1], 0);
+	dump_report(report3_32, 64, "report3_32");
+	igt_assert_eq(0, memcmp(&report3_32[4],
+				bo->virtual + 2048,
+				240));
+
+	/* Accumulate deltas for counters - A0, A21 and A26 */
+	memset(accumulator.deltas, 0, sizeof(accumulator.deltas));
+	accumulate_reports(&accumulator, report0_32, report1_32);
+	igt_debug("total: A0 = %"PRIu64", A21 = %"PRIu64", A26 = %"PRIu64"\n",
+			accumulator.deltas[2 + 0],
+			accumulator.deltas[2 + 21],
+			accumulator.deltas[2 + 26]);
+
+	igt_debug("oa_timestamp32 0 = %u\n", report0_32[1]);
+	igt_debug("oa_timestamp32 1 = %u\n", report1_32[1]);
+	igt_debug("ctx_id 0 = %u\n", report0_32[2]);
+	igt_debug("ctx_id 1 = %u\n", report1_32[2]);
+
+	/* The delta as calculated via the PIPE_CONTROL timestamp or
+	 * the OA report timestamps should be almost identical but
+	 * allow a 500 nanoseconds margin.
+	 */
+	timestamp0_64 = *(uint64_t *)(((uint8_t *)bo->virtual) + BO_TIMESTAMP_OFFSET0);
+	timestamp1_64 = *(uint64_t *)(((uint8_t *)bo->virtual) + BO_TIMESTAMP_OFFSET1);
+
+	igt_debug("ts_timestamp64 0 = %"PRIu64"\n", timestamp0_64);
+	igt_debug("ts_timestamp64 1 = %"PRIu64"\n", timestamp1_64);
+
+	delta_ts64 = timestamp1_64 - timestamp0_64;
+	delta_oa32 = report1_32[1] - report0_32[1];
+
+	/* Sanity check that we can pass the delta to timebase_scale */
+	igt_assert(delta_ts64 < UINT32_MAX);
+	delta_oa32_ns = timebase_scale(delta_oa32);
+	delta_ts64_ns = timebase_scale(delta_ts64);
+
+	igt_debug("oa32 delta = %u, = %uns\n",
+			delta_oa32, (unsigned)delta_oa32_ns);
+	igt_debug("ts64 delta = %u, = %uns\n",
+			delta_ts64, (unsigned)delta_ts64_ns);
+
+	delta_delta = delta_ts64_ns > delta_oa32_ns ?
+		      (delta_ts64_ns - delta_oa32_ns) :
+		      (delta_oa32_ns - delta_ts64_ns);
+	if (delta_delta > 500) {
+		igt_debug("delta_delta exceeds margin, skipping..\n");
+		exit(EAGAIN);
+	}
+
+	igt_debug("n samples written = %"PRIu64"/%"PRIu64" (%ix%i)\n",
+		  accumulator.deltas[2 + 21],
+		  accumulator.deltas[2 + 26],
+		  width, height);
+	accumulator_print(&accumulator, "filtered");
+
+	/* Verify that the work actually happened by comparing the src
+	 * and dst buffers
+	 */
+	ret = drm_intel_bo_map(src[0].bo, false);
+	igt_assert_eq(ret, 0);
+	ret = drm_intel_bo_map(dst[0].bo, false);
+	igt_assert_eq(ret, 0);
+
+	ret = memcmp(src[0].bo->virtual, dst[0].bo->virtual, 4 * width * height);
+	if (ret != 0) {
+		accumulator_print(&accumulator, "total");
+		exit(EAGAIN);
+	}
+
+	drm_intel_bo_unmap(src[0].bo);
+	drm_intel_bo_unmap(dst[0].bo);
+
+	/* Check that this test passed. The test measures the number of 2x2
+	 * samples written to the render target using the counter A26. For
+	 * OAR, this counter will only have increments relevant to this specific
+	 * context. The value equals the width * height of the rendered work.
+	 */
+	igt_assert_eq(accumulator.deltas[2 + 26], width * height);
+
+	/* Clean up */
+	for (int i = 0; i < ARRAY_SIZE(src); i++) {
+		drm_intel_bo_unreference(src[i].bo);
+		drm_intel_bo_unreference(dst[i].bo);
+	}
+
+	drm_intel_bo_unmap(bo);
+	drm_intel_bo_unreference(bo);
+	intel_batchbuffer_free(batch);
+	drm_intel_gem_context_destroy(context0);
+	drm_intel_gem_context_destroy(context1);
+	drm_intel_bufmgr_destroy(bufmgr);
+	__perf_close(stream_fd);
+}
+
+static void
+gen12_test_single_ctx_render_target_writes_a_counter(void)
+{
+	uint64_t properties[] = {
+		/* Have a random value here for the context id, but initialize
+		 * it once you figure out the context ID for the work to be
+		 * measured
+		 */
+		DRM_I915_PERF_PROP_CTX_HANDLE, UINT64_MAX,
+
+		/* OA unit configuration:
+		 * DRM_I915_PERF_PROP_SAMPLE_OA is no longer required for Gen12
+		 * because the OAR unit increments counters only for the
+		 * relevant context. No other parameters are needed since we do
+		 * not rely on the OA buffer anymore to normalize the counter
+		 * values.
+		 */
+		DRM_I915_PERF_PROP_OA_METRICS_SET, test_metric_set_id,
+		DRM_I915_PERF_PROP_OA_FORMAT, test_oa_format,
+	};
+	struct drm_i915_perf_open_param param = {
+		.flags = I915_PERF_FLAG_FD_CLOEXEC,
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	int child_ret;
+	struct igt_helper_process child = {};
+
+	/* Ensure perf_stream_paranoid is set to 1 by default */
+	write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
+
+	do {
+		igt_fork_helper(&child) {
+			gen12_single_ctx_helper(&param);
+		}
+		child_ret = igt_wait_helper(&child);
+		igt_assert(WEXITSTATUS(child_ret) == EAGAIN ||
+			   WEXITSTATUS(child_ret) == 0);
+	} while (WEXITSTATUS(child_ret) == EAGAIN);
+}
+
 static unsigned long rc6_residency_ms(void)
 {
 	return sysfs_read("power/rc6_residency_ms");
@@ -4206,6 +4554,11 @@ igt_main
 		gen8_test_single_ctx_render_target_writes_a_counter();
 	}
 
+	igt_subtest("gen12-unprivileged-single-ctx-counters") {
+		igt_require(intel_gen(devid) >= 12);
+		gen12_test_single_ctx_render_target_writes_a_counter();
+	}
+
 	igt_subtest("rc6-disable")
 		test_rc6_disable();
 
-- 
2.23.0

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[igt-dev] [PATCH i-g-t 3/3] test/perf: Pass context id for gen12 mi rpc test

[Umesh Nerlige Ramappa]

On Gen12, MI RPC uses OAR. OAR is configured only for the render context
that wants to measure the performance. Hence a context must be passed to
perf in the gen12 MI RPC when compared to previous gens.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/perf.c | 109 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 108 insertions(+), 1 deletion(-)

diff --git a/tests/perf.c b/tests/perf.c
index b439e5bd..b6bc1428 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -2816,6 +2816,106 @@ test_disabled_read_error(void)
 	__perf_close(stream_fd);
 }
 
+static void
+gen12_test_mi_rpc(void)
+{
+	uint64_t properties[] = {
+		/* On Gen12, MI RPC uses OAR. OAR is configured only for the
+		 * render context that wants to measure the performance. Hence a
+		 * context must be specified in the gen12 MI RPC when compared
+		 * to previous gens.
+		 *
+		 * Have a random value here for the context id, but initialize
+		 * it once you figure out the context ID for the work to be
+		 * measured
+		 */
+		DRM_I915_PERF_PROP_CTX_HANDLE, UINT64_MAX,
+
+		/* OA unit configuration:
+		 * DRM_I915_PERF_PROP_SAMPLE_OA is no longer required for Gen12
+		 * because the OAR unit increments counters only for the
+		 * relevant context. No other parameters are needed since we do
+		 * not rely on the OA buffer anymore to normalize the counter
+		 * values.
+		 */
+		DRM_I915_PERF_PROP_OA_METRICS_SET, test_metric_set_id,
+		DRM_I915_PERF_PROP_OA_FORMAT, test_oa_format,
+	};
+	struct drm_i915_perf_open_param param = {
+		.flags = I915_PERF_FLAG_FD_CLOEXEC,
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	drm_intel_bo *bo;
+	drm_intel_bufmgr *bufmgr;
+	drm_intel_context *context;
+	struct intel_batchbuffer *batch;
+#define INVALID_CTX_ID 0xffffffff
+	uint32_t ctx_id = INVALID_CTX_ID;
+	uint32_t *report32;
+	int ret;
+	size_t format_size_32;
+
+	/* Ensure perf_stream_paranoid is set to 1 by default */
+	write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
+
+	bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
+	igt_assert(bufmgr);
+
+	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
+
+	context = drm_intel_gem_context_create(bufmgr);
+	igt_assert(context);
+
+	ret = drm_intel_gem_context_get_id(context, &ctx_id);
+	igt_assert_eq(ret, 0);
+	igt_assert_neq(ctx_id, INVALID_CTX_ID);
+	properties[1] = ctx_id;
+
+	batch = intel_batchbuffer_alloc(bufmgr, devid);
+	bo = drm_intel_bo_alloc(bufmgr, "mi_rpc dest bo", 4096, 64);
+
+	ret = drm_intel_bo_map(bo, true);
+	igt_assert_eq(ret, 0);
+	memset(bo->virtual, 0x80, 4096);
+	drm_intel_bo_unmap(bo);
+
+	stream_fd = __perf_open(drm_fd, &param, false);
+
+#define REPORT_ID 0xdeadbeef
+#define REPORT_OFFSET 0
+	emit_report_perf_count(batch,
+			       bo,
+			       REPORT_OFFSET,
+			       REPORT_ID);
+	intel_batchbuffer_flush_with_context(batch, context);
+
+	ret = drm_intel_bo_map(bo, false);
+	igt_assert_eq(ret, 0);
+
+	report32 = bo->virtual;
+	format_size_32 = get_oa_format(test_oa_format).size >> 2;
+	dump_report(report32, format_size_32, "mi-rpc");
+
+	/* Sanity check reports
+	 * reportX_32[0]: report id passed with mi-rpc
+	 * reportX_32[1]: timestamp
+	 * reportX_32[format_size_32 - 1]: end of report
+	 * reportX_32[format_size_32]: outside report
+	 */
+	igt_assert_eq(report32[0], REPORT_ID);
+	igt_assert_neq(report32[1], 0);
+	igt_assert_neq(report32[format_size_32 - 1], 0x80808080);
+	igt_assert_eq(report32[format_size_32], 0x80808080);
+
+	drm_intel_bo_unmap(bo);
+	drm_intel_bo_unreference(bo);
+	intel_batchbuffer_free(batch);
+	drm_intel_gem_context_destroy(context);
+	drm_intel_bufmgr_destroy(bufmgr);
+	__perf_close(stream_fd);
+}
+
 static void
 test_mi_rpc(void)
 {
@@ -4533,8 +4633,15 @@ igt_main
 	igt_subtest("short-reads")
 		test_short_reads();
 
-	igt_subtest("mi-rpc")
+	igt_subtest("mi-rpc") {
+		igt_require(intel_gen(devid) < 12);
 		test_mi_rpc();
+	}
+
+	igt_subtest("gen12-mi-rpc") {
+		igt_require(intel_gen(devid) >= 12);
+		gen12_test_mi_rpc();
+	}
 
 	igt_subtest("unprivileged-single-ctx-counters") {
 		igt_require(IS_HASWELL(devid));
-- 
2.23.0

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[igt-dev] ✗ GitLab.Pipeline: failure for series starting with [i-g-t,1/3] test/perf: Add support for TGL in perf tests

[Patchwork]

== Series Details ==

Series: series starting with [i-g-t,1/3] test/perf: Add support for TGL in perf tests
URL   : https://patchwork.freedesktop.org/series/69322/
State : failure

== Summary ==

ERROR! This series introduces new undocumented tests:

perf@gen12-mi-rpc
perf@gen12-unprivileged-single-ctx-counters

Can you document them as per the requirement in the [CONTRIBUTING.md]?

[Documentation] has more details on how to do this.

Here are few examples:
https://gitlab.freedesktop.org/drm/igt-gpu-tools/commit/0316695d03aa46108296b27f3982ec93200c7a6e
https://gitlab.freedesktop.org/drm/igt-gpu-tools/commit/443cc658e1e6b492ee17bf4f4d891029eb7a205d

Thanks in advance!

[CONTRIBUTING.md]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/blob/master/CONTRIBUTING.md#L19
[Documentation]: https://drm.pages.freedesktop.org/igt-gpu-tools/igt-gpu-tools-Core.html#igt-describe

Other than that, pipeline status: SUCCESS.

see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/78100 for the overview.

== Logs ==

For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/78100
_______________________________________________
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[igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/3] test/perf: Add support for TGL in perf tests

[Patchwork]

== Series Details ==

Series: series starting with [i-g-t,1/3] test/perf: Add support for TGL in perf tests
URL   : https://patchwork.freedesktop.org/series/69322/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7311 -> IGTPW_3684
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/index.html

Known issues
------------

  Here are the changes found in IGTPW_3684 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [PASS][1] -> [FAIL][2] ([fdo#111407])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [FAIL][3] ([fdo#108511]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@kms_busy@basic-flip-pipe-b:
    - fi-skl-6770hq:      [DMESG-WARN][5] ([fdo#105541]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/fi-skl-6770hq/igt@kms_busy@basic-flip-pipe-b.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/fi-skl-6770hq/igt@kms_busy@basic-flip-pipe-b.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - fi-skl-6770hq:      [WARN][7] -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/fi-skl-6770hq/igt@kms_setmode@basic-clone-single-crtc.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/fi-skl-6770hq/igt@kms_setmode@basic-clone-single-crtc.html

  
  [fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407


Participating hosts (52 -> 45)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5271 -> IGTPW_3684

  CI-20190529: 20190529
  CI_DRM_7311: 36d31f70111ea87432ee8a8981943c5b20e36213 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3684: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/index.html
  IGT_5271: 05f0400c50af843df301efb5475e9f5e2d16a098 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@perf@gen12-mi-rpc
+igt@perf@gen12-unprivileged-single-ctx-counters

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/index.html
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[igt-dev] ✓ Fi.CI.IGT: success for series starting with [i-g-t,1/3] test/perf: Add support for TGL in perf tests

[Patchwork]

== Series Details ==

Series: series starting with [i-g-t,1/3] test/perf: Add support for TGL in perf tests
URL   : https://patchwork.freedesktop.org/series/69322/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7311_full -> IGTPW_3684_full
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with IGTPW_3684_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_3684_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_3684_full:

### IGT changes ###

#### Possible regressions ####

  * {igt@perf@gen12-mi-rpc} (NEW):
    - shard-iclb:         NOTRUN -> [SKIP][1] +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb3/igt@perf@gen12-mi-rpc.html

  * {igt@perf@gen12-unprivileged-single-ctx-counters} (NEW):
    - shard-tglb:         NOTRUN -> [FAIL][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-tglb3/igt@perf@gen12-unprivileged-single-ctx-counters.html

  
#### Warnings ####

  * igt@perf@mi-rpc:
    - shard-tglb:         [SKIP][3] ([fdo#112172]) -> [SKIP][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-tglb5/igt@perf@mi-rpc.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-tglb1/igt@perf@mi-rpc.html

  
New tests
---------

  New tests have been introduced between CI_DRM_7311_full and IGTPW_3684_full:

### New IGT tests (2) ###

  * igt@perf@gen12-mi-rpc:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@perf@gen12-unprivileged-single-ctx-counters:
    - Statuses : 1 fail(s) 6 skip(s)
    - Exec time: [0.0, 0.03] s

  

Known issues
------------

  Here are the changes found in IGTPW_3684_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@vcs0-s3:
    - shard-apl:          [PASS][5] -> [DMESG-WARN][6] ([fdo#108566])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-apl3/igt@gem_ctx_isolation@vcs0-s3.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-apl4/igt@gem_ctx_isolation@vcs0-s3.html

  * igt@gem_ctx_isolation@vcs1-s3:
    - shard-tglb:         [PASS][7] -> [INCOMPLETE][8] ([fdo#111832])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-tglb2/igt@gem_ctx_isolation@vcs1-s3.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-tglb3/igt@gem_ctx_isolation@vcs1-s3.html

  * igt@gem_ctx_persistence@vcs1-queued:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#109276] / [fdo#112080]) +2 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-iclb1/igt@gem_ctx_persistence@vcs1-queued.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb8/igt@gem_ctx_persistence@vcs1-queued.html

  * igt@gem_ctx_switch@queue-light:
    - shard-tglb:         [PASS][11] -> [INCOMPLETE][12] ([fdo#111672])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-tglb8/igt@gem_ctx_switch@queue-light.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-tglb6/igt@gem_ctx_switch@queue-light.html

  * igt@gem_ctx_switch@vcs1:
    - shard-iclb:         [PASS][13] -> [SKIP][14] ([fdo#112080]) +9 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-iclb1/igt@gem_ctx_switch@vcs1.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb5/igt@gem_ctx_switch@vcs1.html

  * igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd1:
    - shard-tglb:         [PASS][15] -> [INCOMPLETE][16] ([fdo#111677])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-tglb9/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd1.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd1.html

  * igt@gem_exec_schedule@preemptive-hang-bsd:
    - shard-iclb:         [PASS][17] -> [SKIP][18] ([fdo#112146]) +4 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-iclb3/igt@gem_exec_schedule@preemptive-hang-bsd.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html

  * igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
    - shard-iclb:         [PASS][19] -> [TIMEOUT][20] ([fdo#112068 ])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-iclb1/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb4/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html

  * igt@gem_userptr_blits@sync-unmap-after-close:
    - shard-hsw:          [PASS][21] -> [DMESG-WARN][22] ([fdo#111870]) +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-hsw2/igt@gem_userptr_blits@sync-unmap-after-close.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-hsw8/igt@gem_userptr_blits@sync-unmap-after-close.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-snb:          [PASS][23] -> [DMESG-WARN][24] ([fdo#111870]) +2 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-snb2/igt@gem_userptr_blits@sync-unmap-cycles.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-snb5/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [PASS][25] -> [FAIL][26] ([fdo#111830 ])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-iclb7/igt@i915_pm_dc@dc6-dpms.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html

  * igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge:
    - shard-hsw:          [PASS][27] -> [INCOMPLETE][28] ([fdo#103540])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-hsw5/igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-hsw1/igt@kms_cursor_edge_walk@pipe-a-64x64-top-edge.html

  * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
    - shard-tglb:         [PASS][29] -> [FAIL][30] ([fdo#103167]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-iclb:         [PASS][31] -> [FAIL][32] ([fdo#103167]) +6 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_lease@cursor_implicit_plane:
    - shard-kbl:          [PASS][33] -> [DMESG-WARN][34] ([fdo#103558] / [fdo#105602]) +6 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-kbl4/igt@kms_lease@cursor_implicit_plane.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-kbl6/igt@kms_lease@cursor_implicit_plane.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [PASS][35] -> [DMESG-WARN][36] ([fdo#108566]) +5 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][37] -> [SKIP][38] ([fdo#109441]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb8/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][39] -> [FAIL][40] ([fdo#99912])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-apl7/igt@kms_setmode@basic.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-apl1/igt@kms_setmode@basic.html
    - shard-hsw:          [PASS][41] -> [FAIL][42] ([fdo#99912])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-hsw7/igt@kms_setmode@basic.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-hsw8/igt@kms_setmode@basic.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [PASS][43] -> [SKIP][44] ([fdo#109276]) +19 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-iclb4/igt@prime_busy@hang-bsd2.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb7/igt@prime_busy@hang-bsd2.html

  
#### Possible fixes ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [SKIP][45] ([fdo#112080]) -> [PASS][46] +14 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-iclb8/igt@gem_busy@busy-vcs1.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb1/igt@gem_busy@busy-vcs1.html

  * igt@gem_ctx_isolation@bcs0-s3:
    - shard-iclb:         [DMESG-WARN][47] ([fdo#111764]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-iclb5/igt@gem_ctx_isolation@bcs0-s3.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb7/igt@gem_ctx_isolation@bcs0-s3.html
    - shard-tglb:         [INCOMPLETE][49] ([fdo#111832]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-tglb8/igt@gem_ctx_isolation@bcs0-s3.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-tglb7/igt@gem_ctx_isolation@bcs0-s3.html

  * igt@gem_ctx_isolation@vcs1-dirty-create:
    - shard-iclb:         [SKIP][51] ([fdo#109276] / [fdo#112080]) -> [PASS][52] +2 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-iclb7/igt@gem_ctx_isolation@vcs1-dirty-create.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb4/igt@gem_ctx_isolation@vcs1-dirty-create.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [SKIP][53] ([fdo#110841]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_eio@in-flight-10ms:
    - shard-snb:          [FAIL][55] ([fdo#111946]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-snb4/igt@gem_eio@in-flight-10ms.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-snb7/igt@gem_eio@in-flight-10ms.html

  * igt@gem_eio@in-flight-suspend:
    - shard-tglb:         [INCOMPLETE][57] ([fdo#111832] / [fdo#111850] / [fdo#112081]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-tglb4/igt@gem_eio@in-flight-suspend.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-tglb2/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_create@madvise:
    - shard-tglb:         [INCOMPLETE][59] ([fdo#111747]) -> [PASS][60] +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-tglb6/igt@gem_exec_create@madvise.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-tglb5/igt@gem_exec_create@madvise.html

  * igt@gem_exec_schedule@preempt-contexts-bsd2:
    - shard-iclb:         [SKIP][61] ([fdo#109276]) -> [PASS][62] +14 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-iclb7/igt@gem_exec_schedule@preempt-contexts-bsd2.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb4/igt@gem_exec_schedule@preempt-contexts-bsd2.html

  * igt@gem_exec_schedule@wide-bsd:
    - shard-iclb:         [SKIP][63] ([fdo#112146]) -> [PASS][64] +3 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-iclb2/igt@gem_exec_schedule@wide-bsd.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb5/igt@gem_exec_schedule@wide-bsd.html

  * igt@gem_exec_suspend@basic-s3-devices:
    - shard-tglb:         [INCOMPLETE][65] ([fdo#111832] / [fdo#111850]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-tglb3/igt@gem_exec_suspend@basic-s3-devices.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-tglb9/igt@gem_exec_suspend@basic-s3-devices.html

  * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing:
    - shard-iclb:         [TIMEOUT][67] ([fdo#112068 ]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-iclb8/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb1/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html

  * igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
    - shard-hsw:          [FAIL][69] ([fdo#112037]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-hsw5/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-hsw8/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html

  * igt@gem_softpin@softpin:
    - shard-hsw:          [INCOMPLETE][71] ([fdo#103540]) -> [PASS][72] +1 similar issue
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-hsw7/igt@gem_softpin@softpin.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-hsw1/igt@gem_softpin@softpin.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy:
    - shard-snb:          [DMESG-WARN][73] ([fdo#111870]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-snb7/igt@gem_userptr_blits@map-fixed-invalidate-busy.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-hsw:          [DMESG-WARN][75] ([fdo#111870]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][77] ([fdo#108566]) -> [PASS][78] +4 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [DMESG-WARN][79] ([fdo#108566]) -> [PASS][80] +1 similar issue
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
    - shard-iclb:         [FAIL][81] ([fdo#103167]) -> [PASS][82] +2 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt:
    - shard-tglb:         [FAIL][83] ([fdo#103167]) -> [PASS][84] +1 similar issue
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
    - shard-tglb:         [INCOMPLETE][85] ([fdo#111832] / [fdo#111850] / [fdo#111884]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-tglb9/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html

  * igt@kms_plane_lowres@pipe-a-tiling-y:
    - shard-iclb:         [FAIL][87] ([fdo#103166]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-y.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-y.html

  * igt@kms_psr@no_drrs:
    - shard-iclb:         [FAIL][89] ([fdo#108341]) -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-iclb1/igt@kms_psr@no_drrs.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb7/igt@kms_psr@no_drrs.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [SKIP][91] ([fdo#109441]) -> [PASS][92] +1 similar issue
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-iclb1/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@perf@invalid-open-flags:
    - shard-tglb:         [SKIP][93] ([fdo#112172]) -> [PASS][94] +11 similar issues
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-tglb6/igt@perf@invalid-open-flags.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-tglb4/igt@perf@invalid-open-flags.html

  * igt@perf@rc6-disable:
    - shard-tglb:         [SKIP][95] ([fdo#111719] / [fdo#112172]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-tglb7/igt@perf@rc6-disable.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-tglb1/igt@perf@rc6-disable.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv-switch:
    - shard-iclb:         [FAIL][97] ([fdo#111329]) -> [SKIP][98] ([fdo#109276] / [fdo#112080])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-iclb7/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html

  * igt@gem_ctx_isolation@vcs2-nonpriv:
    - shard-tglb:         [SKIP][99] ([fdo#112080]) -> [SKIP][100] ([fdo#111912] / [fdo#112080])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-tglb9/igt@gem_ctx_isolation@vcs2-nonpriv.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-tglb1/igt@gem_ctx_isolation@vcs2-nonpriv.html

  * igt@gem_eio@kms:
    - shard-snb:          [DMESG-WARN][101] ([fdo# 112000 ] / [fdo#111781]) -> [INCOMPLETE][102] ([fdo#105411])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-snb6/igt@gem_eio@kms.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-snb1/igt@gem_eio@kms.html

  * igt@gem_exec_schedule@deep-bsd1:
    - shard-tglb:         [FAIL][103] ([fdo#111646]) -> [INCOMPLETE][104] ([fdo#111671])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7311/shard-tglb6/igt@gem_exec_schedule@deep-bsd1.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/shard-tglb2/igt@gem_exec_schedule@deep-bsd1.html

  * igt@gem_mocs_settings@mocs-isolation-bsd2:
    - shard-iclb:         [FAIL][105] ([fdo#111330])

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3684/index.html
_______________________________________________
igt-dev mailing list
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Re: [igt-dev] [PATCH i-g-t 2/3] test/perf: Add test for TGL OAR unit

[Lionel Landwerlin]

Hey Umesh,

Just a few changes but otherwise it looks good.

Thanks,


-Lionel

On 12/11/2019 00:16, Umesh Nerlige Ramappa wrote:
> Add a test that measures work using MI-RPC for the specific context
> without using reports from the OA buffer.
>
> Tigerlake introduces an OA unit that measures work specific to render
> workloads. This means we do not have to rely on reports from the OA
> buffer to normalize the reports obtained from MI REPORT PERF COUNT
> anymore.
>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>   tests/perf.c | 353 +++++++++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 353 insertions(+)
>
> diff --git a/tests/perf.c b/tests/perf.c
> index 2b6be134..b439e5bd 100644
> --- a/tests/perf.c
> +++ b/tests/perf.c
> @@ -210,6 +210,19 @@ static uint32_t (*read_report_ticks)(uint32_t *report,
>   static void (*sanity_check_reports)(uint32_t *oa_report0, uint32_t *oa_report1,
>   				    enum drm_i915_oa_format format);
>   
> +static void
> +dump_report(const uint32_t *report, uint32_t size, const char *message) {
> +	uint32_t i;
> +	igt_debug("%s\n", message);
> +	for (i = 0; i < size; i += 4) {
> +		igt_debug("%08x %08x %08x %08x\n",
> +				report[i],
> +				report[i + 1],
> +				report[i + 2],
> +				report[i + 3]);
> +	}
> +}
> +


I would put all the debug traces in a separate patch preceding this one.


>   static struct oa_format
>   get_oa_format(enum drm_i915_oa_format format)
>   {
> @@ -874,6 +887,7 @@ init_sys_info(void)
>   	igt_assert_neq(devid, 0);
>   
>   	timestamp_frequency = get_cs_timestamp_frequency();
> +	igt_debug("timestamp_frequency = %lu\n", timestamp_frequency);
>   	igt_assert_neq(timestamp_frequency, 0);
>   
>   	if (IS_HASWELL(devid)) {
> @@ -1289,6 +1303,7 @@ read_2_oa_reports(int format_id,
>   			igt_assert_eq(header->size, sample_size);
>   
>   			report = (const void *)(header + 1);
> +			dump_report(report, 64, "oa-formats");
>   
>   			igt_debug("read report: reason = %x, timestamp = %x, exponent mask=%x\n",
>   				  report[0], report[1], exponent_mask);
> @@ -2856,6 +2871,7 @@ test_mi_rpc(void)
>   	igt_assert_eq(ret, 0);
>   
>   	report32 = bo->virtual;
> +	dump_report(report32, 64, "mi-rpc");
>   	igt_assert_eq(report32[0], 0xdeadbeef); /* report ID */
>   	igt_assert_neq(report32[1], 0); /* timestamp */
>   
> @@ -3335,11 +3351,13 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
>   			prev = report0_32;
>   			ctx_id = prev[2];
>   			igt_debug("MI_RPC(start) CTX ID: %u\n", ctx_id);
> +			dump_report(report0_32, 64, "report0_32");
>   
>   			report1_32 = report0_32 + 64; /* 64 uint32_t = 256bytes offset */
>   			igt_assert_eq(report1_32[0], 0xbeefbeef); /* report ID */
>   			igt_assert_neq(report1_32[1], 0); /* timestamp */
>   			ctx1_id = report1_32[2];
> +			dump_report(report1_32, 64, "report1_32");
>   
>   			memset(accumulator.deltas, 0, sizeof(accumulator.deltas));
>   			accumulate_reports(&accumulator, report0_32, report1_32);
> @@ -3434,6 +3452,7 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
>   				igt_assert_eq(header->size, sample_size);
>   
>   				report = (void *)(header + 1);
> +				dump_report(report, 64, "OA report");
>   
>   				/* Don't expect zero for timestamps */
>   				igt_assert_neq(report[1], 0);
> @@ -3581,6 +3600,335 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
>   	} while (WEXITSTATUS(child_ret) == EAGAIN);
>   }
>   
> +static void gen12_single_ctx_helper(struct drm_i915_perf_open_param *param)
> +{
> +	uint64_t *ctx_id_ptr;
> +	drm_intel_bufmgr *bufmgr;
> +	drm_intel_context *context0, *context1;
> +	struct intel_batchbuffer *batch;
> +	struct igt_buf src[3], dst[3];
> +	drm_intel_bo *bo;
> +	uint32_t *report0_32, *report1_32, *report2_32, *report3_32;
> +	uint64_t timestamp0_64, timestamp1_64;
> +	uint32_t delta_ts64, delta_oa32;
> +	uint64_t delta_ts64_ns, delta_oa32_ns;
> +	uint32_t delta_delta;
> +	int width = 800;
> +	int height = 600;
> +#define INVALID_CTX_ID 0xffffffff
> +	uint32_t ctx0_id = INVALID_CTX_ID;
> +	uint32_t ctx1_id = INVALID_CTX_ID;
> +	int ret;
> +	struct accumulator accumulator = {
> +		.format = test_oa_format
> +	};
> +
> +	bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
> +	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
> +
> +	for (int i = 0; i < ARRAY_SIZE(src); i++) {
> +		scratch_buf_init(bufmgr, &src[i], width, height, 0xff0000ff);
> +		scratch_buf_init(bufmgr, &dst[i], width, height, 0x00ff00ff);
> +	}
> +
> +	batch = intel_batchbuffer_alloc(bufmgr, devid);
> +
> +	context0 = drm_intel_gem_context_create(bufmgr);
> +	igt_assert(context0);
> +
> +	context1 = drm_intel_gem_context_create(bufmgr);
> +	igt_assert(context1);
> +
> +	igt_debug("submitting warm up render_copy\n");
> +
> +	/* Submit some early, unmeasured, work to the context we want
> +	 * to measure to try and catch issues with i915-perf
> +	 * initializing the HW context ID for filtering.
> +	 *
> +	 * We do this because i915-perf single context filtering had
> +	 * previously only relied on a hook into context pinning to
> +	 * initialize the HW context ID, instead of also trying to
> +	 * determine the HW ID while opening the stream, in case it
> +	 * has already been pinned.
> +	 *
> +	 * This wasn't noticed by the previous unit test because we
> +	 * were opening the stream while the context hadn't been
> +	 * touched or pinned yet and so it worked out correctly to wait
> +	 * for the pinning hook.
> +	 *
> +	 * Now a buggy version of i915-perf will fail to measure
> +	 * anything for context0 once this initial render_copy() ends
> +	 * up pinning the context since there won't ever be a pinning
> +	 * hook callback.
> +	 */
> +	render_copy(batch, context0,
> +		    &src[0], 0, 0, width, height,
> +		    &dst[0], 0, 0);
> +
> +	/* Initialize the context parameter to the perf open ioctl here */
> +	ret = drm_intel_gem_context_get_id(context0, &ctx0_id);
> +	igt_assert_eq(ret, 0);
> +	igt_assert_neq(ctx0_id, 0xffffffff);
> +	ctx_id_ptr = (uint64_t *) from_user_pointer(param->properties_ptr);
> +	ctx_id_ptr[1] = ctx0_id;


This is a bit complicated, just move the struct drm_i915_perf_open_param 
param etc.. in this function.


> +
> +	igt_debug("opening i915-perf stream\n");
> +	stream_fd = __perf_open(drm_fd, param, false);
> +
> +	bo = drm_intel_bo_alloc(bufmgr, "mi_rpc dest bo", 4096, 64);
> +
> +	/* Set write domain to cpu briefly to fill the buffer with 80s */
> +	ret = drm_intel_bo_map(bo, true);
> +	igt_assert_eq(ret, 0);
> +	memset(bo->virtual, 0x80, 2048);
> +	memset(bo->virtual + 2048, 0, 2048);
> +	drm_intel_bo_unmap(bo);
> +
> +	/* Submit an mi-rpc to context0 before measurable work */
> +#define BO_TIMESTAMP_OFFSET0 1024
> +#define BO_REPORT_OFFSET0 0
> +#define BO_REPORT_ID0 0xdeadbeef
> +	emit_stall_timestamp_and_rpc(batch,
> +				     bo,
> +				     BO_TIMESTAMP_OFFSET0,
> +				     BO_REPORT_OFFSET0,
> +				     BO_REPORT_ID0);
> +	intel_batchbuffer_flush_with_context(batch, context0);
> +
> +	/* This is the work/context that is measured for counter increments */
> +	render_copy(batch, context0,
> +		    &src[0], 0, 0, width, height,
> +		    &dst[0], 0, 0);
> +	intel_batchbuffer_flush_with_context(batch, context0);
> +
> +	/* Submit an mi-rpc to context1 before work
> +	 *
> +	 * On gen12, this measurement should just yield counters that are
> +	 * all zeroes, since the counters will only increment for the
> +	 * context passed to perf open ioctl
> +	 */
> +#define BO_TIMESTAMP_OFFSET2 1040
> +#define BO_REPORT_OFFSET2 512
> +#define BO_REPORT_ID2 0x00c0ffee
> +	emit_stall_timestamp_and_rpc(batch,
> +				     bo,
> +				     BO_TIMESTAMP_OFFSET2,
> +				     BO_REPORT_OFFSET2,
> +				     BO_REPORT_ID2);
> +	intel_batchbuffer_flush_with_context(batch, context1);
> +
> +	/* Submit two copies on the other context to avoid a false
> +	 * positive in case the driver somehow ended up filtering for
> +	 * context1
> +	 */
> +	render_copy(batch, context1,
> +		    &src[1], 0, 0, width, height,
> +		    &dst[1], 0, 0);
> +	ret = drm_intel_gem_context_get_id(context1, &ctx1_id);
> +	igt_assert_eq(ret, 0);
> +	igt_assert_neq(ctx1_id, 0xffffffff);
> +
> +	render_copy(batch, context1,
> +		    &src[2], 0, 0, width, height,
> +		    &dst[2], 0, 0);
> +	intel_batchbuffer_flush_with_context(batch, context1);
> +
> +	/* Submit an mi-rpc to context1 after all work */
> +#define BO_TIMESTAMP_OFFSET3 1048
> +#define BO_REPORT_OFFSET3 768
> +#define BO_REPORT_ID3 0x01c0ffee
> +	emit_stall_timestamp_and_rpc(batch,
> +				     bo,
> +				     BO_TIMESTAMP_OFFSET3,
> +				     BO_REPORT_OFFSET3,
> +				     BO_REPORT_ID3);
> +	intel_batchbuffer_flush_with_context(batch, context1);
> +
> +	/* Submit an mi-rpc to context0 after all measurable work */
> +#define BO_TIMESTAMP_OFFSET1 1032
> +#define BO_REPORT_OFFSET1 256
> +#define BO_REPORT_ID1 0xbeefbeef
> +	emit_stall_timestamp_and_rpc(batch,
> +				     bo,
> +				     BO_TIMESTAMP_OFFSET1,
> +				     BO_REPORT_OFFSET1,
> +				     BO_REPORT_ID1);
> +	intel_batchbuffer_flush_with_context(batch, context0);
> +
> +	/* Set write domain to none */
> +	ret = drm_intel_bo_map(bo, false);
> +	igt_assert_eq(ret, 0);
> +
> +	/* Sanity check reports
> +	 * reportX_32[0]: report id passed with mi-rpc
> +	 * reportX_32[1]: timestamp
> +	 * reportX_32[2]: context id
> +	 *
> +	 * report0_32: start of measurable work
> +	 * report1_32: end of measurable work
> +	 * report2_32: start of other work
> +	 * report3_32: end of other work
> +	 */
> +	report0_32 = bo->virtual;
> +	igt_assert_eq(report0_32[0], 0xdeadbeef);
> +	igt_assert_neq(report0_32[1], 0);
> +	ctx0_id = report0_32[2];
> +	igt_debug("MI_RPC(start) CTX ID: %u\n", ctx0_id);
> +	dump_report(report0_32, 64, "report0_32");
> +
> +	report1_32 = report0_32 + 64;
> +	igt_assert_eq(report1_32[0], 0xbeefbeef);
> +	igt_assert_neq(report1_32[1], 0);
> +	ctx1_id = report1_32[2];
> +	dump_report(report1_32, 64, "report1_32");
> +
> +	/* Verify that counters in context1 are all zeroes */
> +	report2_32 = report0_32 + 128;
> +	igt_assert_eq(report2_32[0], 0x00c0ffee);
> +	igt_assert_neq(report2_32[1], 0);
> +	dump_report(report2_32, 64, "report2_32");
> +	igt_assert_eq(0, memcmp(&report2_32[4],
> +				bo->virtual + 2048,
> +				240));
> +
> +	report3_32 = report0_32 + 192;
> +	igt_assert_eq(report3_32[0], 0x01c0ffee);
> +	igt_assert_neq(report3_32[1], 0);
> +	dump_report(report3_32, 64, "report3_32");
> +	igt_assert_eq(0, memcmp(&report3_32[4],
> +				bo->virtual + 2048,
> +				240));
> +
> +	/* Accumulate deltas for counters - A0, A21 and A26 */
> +	memset(accumulator.deltas, 0, sizeof(accumulator.deltas));
> +	accumulate_reports(&accumulator, report0_32, report1_32);
> +	igt_debug("total: A0 = %"PRIu64", A21 = %"PRIu64", A26 = %"PRIu64"\n",
> +			accumulator.deltas[2 + 0],
> +			accumulator.deltas[2 + 21],
> +			accumulator.deltas[2 + 26]);
> +
> +	igt_debug("oa_timestamp32 0 = %u\n", report0_32[1]);
> +	igt_debug("oa_timestamp32 1 = %u\n", report1_32[1]);
> +	igt_debug("ctx_id 0 = %u\n", report0_32[2]);
> +	igt_debug("ctx_id 1 = %u\n", report1_32[2]);
> +
> +	/* The delta as calculated via the PIPE_CONTROL timestamp or
> +	 * the OA report timestamps should be almost identical but
> +	 * allow a 500 nanoseconds margin.
> +	 */
> +	timestamp0_64 = *(uint64_t *)(((uint8_t *)bo->virtual) + BO_TIMESTAMP_OFFSET0);
> +	timestamp1_64 = *(uint64_t *)(((uint8_t *)bo->virtual) + BO_TIMESTAMP_OFFSET1);
> +
> +	igt_debug("ts_timestamp64 0 = %"PRIu64"\n", timestamp0_64);
> +	igt_debug("ts_timestamp64 1 = %"PRIu64"\n", timestamp1_64);
> +
> +	delta_ts64 = timestamp1_64 - timestamp0_64;
> +	delta_oa32 = report1_32[1] - report0_32[1];
> +
> +	/* Sanity check that we can pass the delta to timebase_scale */
> +	igt_assert(delta_ts64 < UINT32_MAX);
> +	delta_oa32_ns = timebase_scale(delta_oa32);
> +	delta_ts64_ns = timebase_scale(delta_ts64);
> +
> +	igt_debug("oa32 delta = %u, = %uns\n",
> +			delta_oa32, (unsigned)delta_oa32_ns);
> +	igt_debug("ts64 delta = %u, = %uns\n",
> +			delta_ts64, (unsigned)delta_ts64_ns);
> +
> +	delta_delta = delta_ts64_ns > delta_oa32_ns ?
> +		      (delta_ts64_ns - delta_oa32_ns) :
> +		      (delta_oa32_ns - delta_ts64_ns);
> +	if (delta_delta > 500) {
> +		igt_debug("delta_delta exceeds margin, skipping..\n");
> +		exit(EAGAIN);
> +	}
> +
> +	igt_debug("n samples written = %"PRIu64"/%"PRIu64" (%ix%i)\n",
> +		  accumulator.deltas[2 + 21],
> +		  accumulator.deltas[2 + 26],
> +		  width, height);
> +	accumulator_print(&accumulator, "filtered");
> +
> +	/* Verify that the work actually happened by comparing the src
> +	 * and dst buffers
> +	 */
> +	ret = drm_intel_bo_map(src[0].bo, false);
> +	igt_assert_eq(ret, 0);
> +	ret = drm_intel_bo_map(dst[0].bo, false);
> +	igt_assert_eq(ret, 0);
> +
> +	ret = memcmp(src[0].bo->virtual, dst[0].bo->virtual, 4 * width * height);
> +	if (ret != 0) {
> +		accumulator_print(&accumulator, "total");
> +		exit(EAGAIN);
> +	}
> +
> +	drm_intel_bo_unmap(src[0].bo);
> +	drm_intel_bo_unmap(dst[0].bo);
> +
> +	/* Check that this test passed. The test measures the number of 2x2
> +	 * samples written to the render target using the counter A26. For
> +	 * OAR, this counter will only have increments relevant to this specific
> +	 * context. The value equals the width * height of the rendered work.
> +	 */
> +	igt_assert_eq(accumulator.deltas[2 + 26], width * height);
> +
> +	/* Clean up */
> +	for (int i = 0; i < ARRAY_SIZE(src); i++) {
> +		drm_intel_bo_unreference(src[i].bo);
> +		drm_intel_bo_unreference(dst[i].bo);
> +	}
> +
> +	drm_intel_bo_unmap(bo);
> +	drm_intel_bo_unreference(bo);
> +	intel_batchbuffer_free(batch);
> +	drm_intel_gem_context_destroy(context0);
> +	drm_intel_gem_context_destroy(context1);
> +	drm_intel_bufmgr_destroy(bufmgr);
> +	__perf_close(stream_fd);
> +}
> +
> +static void
> +gen12_test_single_ctx_render_target_writes_a_counter(void)
> +{
> +	uint64_t properties[] = {
> +		/* Have a random value here for the context id, but initialize
> +		 * it once you figure out the context ID for the work to be
> +		 * measured
> +		 */
> +		DRM_I915_PERF_PROP_CTX_HANDLE, UINT64_MAX,
> +
> +		/* OA unit configuration:
> +		 * DRM_I915_PERF_PROP_SAMPLE_OA is no longer required for Gen12
> +		 * because the OAR unit increments counters only for the
> +		 * relevant context. No other parameters are needed since we do
> +		 * not rely on the OA buffer anymore to normalize the counter
> +		 * values.
> +		 */
> +		DRM_I915_PERF_PROP_OA_METRICS_SET, test_metric_set_id,
> +		DRM_I915_PERF_PROP_OA_FORMAT, test_oa_format,
> +	};
> +	struct drm_i915_perf_open_param param = {
> +		.flags = I915_PERF_FLAG_FD_CLOEXEC,
> +		.num_properties = ARRAY_SIZE(properties) / 2,
> +		.properties_ptr = to_user_pointer(properties),
> +	};
> +	int child_ret;
> +	struct igt_helper_process child = {};
> +
> +	/* Ensure perf_stream_paranoid is set to 1 by default */
> +	write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
> +
> +	do {
> +		igt_fork_helper(&child) {

You need a call to igt_drop_root() here if you're checking the paranoid 
mode.

Otherwise the child process is still root.


> +			gen12_single_ctx_helper(&param);
> +		}
> +		child_ret = igt_wait_helper(&child);
> +		igt_assert(WEXITSTATUS(child_ret) == EAGAIN ||
> +			   WEXITSTATUS(child_ret) == 0);
> +	} while (WEXITSTATUS(child_ret) == EAGAIN);
> +}
> +
>   static unsigned long rc6_residency_ms(void)
>   {
>   	return sysfs_read("power/rc6_residency_ms");
> @@ -4206,6 +4554,11 @@ igt_main
>   		gen8_test_single_ctx_render_target_writes_a_counter();
>   	}
>   
> +	igt_subtest("gen12-unprivileged-single-ctx-counters") {
> +		igt_require(intel_gen(devid) >= 12);
> +		gen12_test_single_ctx_render_target_writes_a_counter();
> +	}
> +
>   	igt_subtest("rc6-disable")
>   		test_rc6_disable();
>   


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Re: [igt-dev] [PATCH i-g-t 3/3] test/perf: Pass context id for gen12 mi rpc test

[Lionel Landwerlin]

On 12/11/2019 00:16, Umesh Nerlige Ramappa wrote:
> On Gen12, MI RPC uses OAR. OAR is configured only for the render context
> that wants to measure the performance. Hence a context must be passed to
> perf in the gen12 MI RPC when compared to previous gens.
>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>   tests/perf.c | 109 ++++++++++++++++++++++++++++++++++++++++++++++++++-
>   1 file changed, 108 insertions(+), 1 deletion(-)
>
> diff --git a/tests/perf.c b/tests/perf.c
> index b439e5bd..b6bc1428 100644
> --- a/tests/perf.c
> +++ b/tests/perf.c
> @@ -2816,6 +2816,106 @@ test_disabled_read_error(void)
>   	__perf_close(stream_fd);
>   }
>   
> +static void
> +gen12_test_mi_rpc(void)
> +{
> +	uint64_t properties[] = {
> +		/* On Gen12, MI RPC uses OAR. OAR is configured only for the
> +		 * render context that wants to measure the performance. Hence a
> +		 * context must be specified in the gen12 MI RPC when compared
> +		 * to previous gens.
> +		 *
> +		 * Have a random value here for the context id, but initialize
> +		 * it once you figure out the context ID for the work to be
> +		 * measured
> +		 */
> +		DRM_I915_PERF_PROP_CTX_HANDLE, UINT64_MAX,
> +
> +		/* OA unit configuration:
> +		 * DRM_I915_PERF_PROP_SAMPLE_OA is no longer required for Gen12
> +		 * because the OAR unit increments counters only for the
> +		 * relevant context. No other parameters are needed since we do
> +		 * not rely on the OA buffer anymore to normalize the counter
> +		 * values.
> +		 */
> +		DRM_I915_PERF_PROP_OA_METRICS_SET, test_metric_set_id,
> +		DRM_I915_PERF_PROP_OA_FORMAT, test_oa_format,
> +	};
> +	struct drm_i915_perf_open_param param = {
> +		.flags = I915_PERF_FLAG_FD_CLOEXEC,
> +		.num_properties = ARRAY_SIZE(properties) / 2,
> +		.properties_ptr = to_user_pointer(properties),
> +	};
> +	drm_intel_bo *bo;
> +	drm_intel_bufmgr *bufmgr;
> +	drm_intel_context *context;
> +	struct intel_batchbuffer *batch;
> +#define INVALID_CTX_ID 0xffffffff
> +	uint32_t ctx_id = INVALID_CTX_ID;
> +	uint32_t *report32;
> +	int ret;
> +	size_t format_size_32;
> +
> +	/* Ensure perf_stream_paranoid is set to 1 by default */
> +	write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
> +
> +	bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
> +	igt_assert(bufmgr);
> +
> +	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
> +
> +	context = drm_intel_gem_context_create(bufmgr);
> +	igt_assert(context);
> +
> +	ret = drm_intel_gem_context_get_id(context, &ctx_id);
> +	igt_assert_eq(ret, 0);
> +	igt_assert_neq(ctx_id, INVALID_CTX_ID);
> +	properties[1] = ctx_id;
> +
> +	batch = intel_batchbuffer_alloc(bufmgr, devid);
> +	bo = drm_intel_bo_alloc(bufmgr, "mi_rpc dest bo", 4096, 64);
> +
> +	ret = drm_intel_bo_map(bo, true);
> +	igt_assert_eq(ret, 0);
> +	memset(bo->virtual, 0x80, 4096);
> +	drm_intel_bo_unmap(bo);
> +
> +	stream_fd = __perf_open(drm_fd, &param, false);
> +
> +#define REPORT_ID 0xdeadbeef
> +#define REPORT_OFFSET 0
> +	emit_report_perf_count(batch,
> +			       bo,
> +			       REPORT_OFFSET,
> +			       REPORT_ID);
> +	intel_batchbuffer_flush_with_context(batch, context);
> +
> +	ret = drm_intel_bo_map(bo, false);
> +	igt_assert_eq(ret, 0);
> +
> +	report32 = bo->virtual;
> +	format_size_32 = get_oa_format(test_oa_format).size >> 2;
> +	dump_report(report32, format_size_32, "mi-rpc");
> +
> +	/* Sanity check reports
> +	 * reportX_32[0]: report id passed with mi-rpc
> +	 * reportX_32[1]: timestamp
> +	 * reportX_32[format_size_32 - 1]: end of report
> +	 * reportX_32[format_size_32]: outside report
> +	 */
> +	igt_assert_eq(report32[0], REPORT_ID);
> +	igt_assert_neq(report32[1], 0);


In theory you can get very unlucky and get a timestamp value of 0 once 
every ~6minutes.


> +	igt_assert_neq(report32[format_size_32 - 1], 0x80808080);


Again I don't know what the Test config is supposed to generate on the 
last counter.

I would pick Counter B0, it's defined as 0.


> +	igt_assert_eq(report32[format_size_32], 0x80808080);
> +
> +	drm_intel_bo_unmap(bo);
> +	drm_intel_bo_unreference(bo);
> +	intel_batchbuffer_free(batch);
> +	drm_intel_gem_context_destroy(context);
> +	drm_intel_bufmgr_destroy(bufmgr);
> +	__perf_close(stream_fd);
> +}
> +
>   static void
>   test_mi_rpc(void)
>   {
> @@ -4533,8 +4633,15 @@ igt_main
>   	igt_subtest("short-reads")
>   		test_short_reads();
>   
> -	igt_subtest("mi-rpc")
> +	igt_subtest("mi-rpc") {
> +		igt_require(intel_gen(devid) < 12);
>   		test_mi_rpc();
> +	}
> +
> +	igt_subtest("gen12-mi-rpc") {
> +		igt_require(intel_gen(devid) >= 12);
> +		gen12_test_mi_rpc();
> +	}
>   
>   	igt_subtest("unprivileged-single-ctx-counters") {
>   		igt_require(IS_HASWELL(devid));


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Re: [igt-dev] [PATCH i-g-t 3/3] test/perf: Pass context id for gen12 mi rpc test

[Umesh Nerlige Ramappa]

On Mon, Nov 18, 2019 at 03:24:49PM +0200, Lionel Landwerlin wrote:
>On 12/11/2019 00:16, Umesh Nerlige Ramappa wrote:
>>On Gen12, MI RPC uses OAR. OAR is configured only for the render context
>>that wants to measure the performance. Hence a context must be passed to
>>perf in the gen12 MI RPC when compared to previous gens.
>>
>>Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>---
>>  tests/perf.c | 109 ++++++++++++++++++++++++++++++++++++++++++++++++++-
>>  1 file changed, 108 insertions(+), 1 deletion(-)
>>
>>diff --git a/tests/perf.c b/tests/perf.c
>>index b439e5bd..b6bc1428 100644
>>--- a/tests/perf.c
>>+++ b/tests/perf.c
>>@@ -2816,6 +2816,106 @@ test_disabled_read_error(void)
>>  	__perf_close(stream_fd);
>>  }
>>+static void
>>+gen12_test_mi_rpc(void)
>>+{
>>+	uint64_t properties[] = {
>>+		/* On Gen12, MI RPC uses OAR. OAR is configured only for the
>>+		 * render context that wants to measure the performance. Hence a
>>+		 * context must be specified in the gen12 MI RPC when compared
>>+		 * to previous gens.
>>+		 *
>>+		 * Have a random value here for the context id, but initialize
>>+		 * it once you figure out the context ID for the work to be
>>+		 * measured
>>+		 */
>>+		DRM_I915_PERF_PROP_CTX_HANDLE, UINT64_MAX,
>>+
>>+		/* OA unit configuration:
>>+		 * DRM_I915_PERF_PROP_SAMPLE_OA is no longer required for Gen12
>>+		 * because the OAR unit increments counters only for the
>>+		 * relevant context. No other parameters are needed since we do
>>+		 * not rely on the OA buffer anymore to normalize the counter
>>+		 * values.
>>+		 */
>>+		DRM_I915_PERF_PROP_OA_METRICS_SET, test_metric_set_id,
>>+		DRM_I915_PERF_PROP_OA_FORMAT, test_oa_format,
>>+	};
>>+	struct drm_i915_perf_open_param param = {
>>+		.flags = I915_PERF_FLAG_FD_CLOEXEC,
>>+		.num_properties = ARRAY_SIZE(properties) / 2,
>>+		.properties_ptr = to_user_pointer(properties),
>>+	};
>>+	drm_intel_bo *bo;
>>+	drm_intel_bufmgr *bufmgr;
>>+	drm_intel_context *context;
>>+	struct intel_batchbuffer *batch;
>>+#define INVALID_CTX_ID 0xffffffff
>>+	uint32_t ctx_id = INVALID_CTX_ID;
>>+	uint32_t *report32;
>>+	int ret;
>>+	size_t format_size_32;
>>+
>>+	/* Ensure perf_stream_paranoid is set to 1 by default */
>>+	write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
>>+
>>+	bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
>>+	igt_assert(bufmgr);
>>+
>>+	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
>>+
>>+	context = drm_intel_gem_context_create(bufmgr);
>>+	igt_assert(context);
>>+
>>+	ret = drm_intel_gem_context_get_id(context, &ctx_id);
>>+	igt_assert_eq(ret, 0);
>>+	igt_assert_neq(ctx_id, INVALID_CTX_ID);
>>+	properties[1] = ctx_id;
>>+
>>+	batch = intel_batchbuffer_alloc(bufmgr, devid);
>>+	bo = drm_intel_bo_alloc(bufmgr, "mi_rpc dest bo", 4096, 64);
>>+
>>+	ret = drm_intel_bo_map(bo, true);
>>+	igt_assert_eq(ret, 0);
>>+	memset(bo->virtual, 0x80, 4096);
>>+	drm_intel_bo_unmap(bo);
>>+
>>+	stream_fd = __perf_open(drm_fd, &param, false);
>>+
>>+#define REPORT_ID 0xdeadbeef
>>+#define REPORT_OFFSET 0
>>+	emit_report_perf_count(batch,
>>+			       bo,
>>+			       REPORT_OFFSET,
>>+			       REPORT_ID);
>>+	intel_batchbuffer_flush_with_context(batch, context);
>>+
>>+	ret = drm_intel_bo_map(bo, false);
>>+	igt_assert_eq(ret, 0);
>>+
>>+	report32 = bo->virtual;
>>+	format_size_32 = get_oa_format(test_oa_format).size >> 2;
>>+	dump_report(report32, format_size_32, "mi-rpc");
>>+
>>+	/* Sanity check reports
>>+	 * reportX_32[0]: report id passed with mi-rpc
>>+	 * reportX_32[1]: timestamp
>>+	 * reportX_32[format_size_32 - 1]: end of report
>>+	 * reportX_32[format_size_32]: outside report
>>+	 */
>>+	igt_assert_eq(report32[0], REPORT_ID);
>>+	igt_assert_neq(report32[1], 0);
>
>
>In theory you can get very unlucky and get a timestamp value of 0 once 
>every ~6minutes.
>

Good point. For now, slowest perf test runs for around 10 seconds and 
all tests seem to start fresh, so we may never run into this. I think I 
will add a note in the comment so that we don't miss it out if future 
tests run longer or we do not reinitialize the hw on every test. 

Thanks,
Umesh
>
>>+	igt_assert_neq(report32[format_size_32 - 1], 0x80808080);
>
>
>Again I don't know what the Test config is supposed to generate on the 
>last counter.
>
>I would pick Counter B0, it's defined as 0.

>
>
>>+	igt_assert_eq(report32[format_size_32], 0x80808080);
>>+
>>+	drm_intel_bo_unmap(bo);
>>+	drm_intel_bo_unreference(bo);
>>+	intel_batchbuffer_free(batch);
>>+	drm_intel_gem_context_destroy(context);
>>+	drm_intel_bufmgr_destroy(bufmgr);
>>+	__perf_close(stream_fd);
>>+}
>>+
>>  static void
>>  test_mi_rpc(void)
>>  {
>>@@ -4533,8 +4633,15 @@ igt_main
>>  	igt_subtest("short-reads")
>>  		test_short_reads();
>>-	igt_subtest("mi-rpc")
>>+	igt_subtest("mi-rpc") {
>>+		igt_require(intel_gen(devid) < 12);
>>  		test_mi_rpc();
>>+	}
>>+
>>+	igt_subtest("gen12-mi-rpc") {
>>+		igt_require(intel_gen(devid) >= 12);
>>+		gen12_test_mi_rpc();
>>+	}
>>  	igt_subtest("unprivileged-single-ctx-counters") {
>>  		igt_require(IS_HASWELL(devid));
>
>
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