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From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 2/2] drm/i915/tgl: Add Wa_1408615072
Date: Wed, 13 Nov 2019 11:18:40 -0800	[thread overview]
Message-ID: <20191113191840.23620-2-radhakrishna.sripada@intel.com> (raw)
In-Reply-To: <20191113191840.23620-1-radhakrishna.sripada@intel.com>

Disable VS Unit Clockgating.

BSpec: 52857
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2ffcc21670b7..3714eb641124 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4172,6 +4172,7 @@ enum {
 
 #define UNSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9434)
 #define  VFUNIT_CLKGATE_DIS		(1 << 20)
+#define  VSUNIT_CLKGATE_DIS		(1 << 3)
 
 #define INF_UNIT_LEVEL_CLKGATE		_MMIO(0x9560)
 #define   CGPSF_CLKGATE_DIS		(1 << 3)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2d389e437e87..fe32c0433971 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6572,6 +6572,10 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
 
 	I915_WRITE(POWERGATE_ENABLE,
 		   I915_READ(POWERGATE_ENABLE) | vd_pg_enable);
+
+	/* Wa_1408615072:tgl */
+	I915_WRITE(UNSLICE_UNIT_LEVEL_CLKGATE,
+		   I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE) | VFUNIT_CLKGATE_DIS);
 }
 
 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Add Wa_1408615072
Date: Wed, 13 Nov 2019 11:18:40 -0800	[thread overview]
Message-ID: <20191113191840.23620-2-radhakrishna.sripada@intel.com> (raw)
Message-ID: <20191113191840.ZYVUUz4GlRFL3-K3zJpB9lw3YBO4F9FUUpVuIOtSM_0@z> (raw)
In-Reply-To: <20191113191840.23620-1-radhakrishna.sripada@intel.com>

Disable VS Unit Clockgating.

BSpec: 52857
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2ffcc21670b7..3714eb641124 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4172,6 +4172,7 @@ enum {
 
 #define UNSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9434)
 #define  VFUNIT_CLKGATE_DIS		(1 << 20)
+#define  VSUNIT_CLKGATE_DIS		(1 << 3)
 
 #define INF_UNIT_LEVEL_CLKGATE		_MMIO(0x9560)
 #define   CGPSF_CLKGATE_DIS		(1 << 3)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2d389e437e87..fe32c0433971 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6572,6 +6572,10 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
 
 	I915_WRITE(POWERGATE_ENABLE,
 		   I915_READ(POWERGATE_ENABLE) | vd_pg_enable);
+
+	/* Wa_1408615072:tgl */
+	I915_WRITE(UNSLICE_UNIT_LEVEL_CLKGATE,
+		   I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE) | VFUNIT_CLKGATE_DIS);
 }
 
 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2019-11-13 19:16 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-13 19:18 [PATCH 1/2] drm/i915/tgl: Wa_1606679103 Radhakrishna Sripada
2019-11-13 19:18 ` [Intel-gfx] " Radhakrishna Sripada
2019-11-13 19:18 ` Radhakrishna Sripada [this message]
2019-11-13 19:18   ` [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Add Wa_1408615072 Radhakrishna Sripada
2019-11-14 10:28   ` Ville Syrjälä
2019-11-14 10:28     ` [Intel-gfx] " Ville Syrjälä
2019-11-14 21:50   ` [PATCH v2 " Radhakrishna Sripada
2019-11-14 21:50     ` [Intel-gfx] " Radhakrishna Sripada
2019-11-15 21:07     ` Matt Roper
2019-11-15 21:07       ` [Intel-gfx] " Matt Roper
2019-11-13 22:12 ` [PATCH 1/2] drm/i915/tgl: Wa_1606679103 Chris Wilson
2019-11-13 22:12   ` [Intel-gfx] " Chris Wilson
2019-11-13 23:19 ` [PATCH v2 " Radhakrishna Sripada
2019-11-13 23:19   ` [Intel-gfx] " Radhakrishna Sripada
2019-11-13 23:32   ` Chris Wilson
2019-11-13 23:32     ` [Intel-gfx] " Chris Wilson
2019-11-14  3:50 ` ✗ Fi.CI.BAT: failure for series starting with [v2,1/2] drm/i915/tgl: Wa_1606679103 (rev2) Patchwork
2019-11-14  3:50   ` [Intel-gfx] " Patchwork
2019-11-14 22:21 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/tgl: Wa_1606679103 (rev3) Patchwork
2019-11-14 22:21   ` [Intel-gfx] " Patchwork
2019-11-16  3:20 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-11-16  3:20   ` [Intel-gfx] " Patchwork

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