* [PATCH 1/3] drm/i915: Flush idle barriers when waiting
@ 2019-11-15 16:05 ` Chris Wilson
0 siblings, 0 replies; 18+ messages in thread
From: Chris Wilson @ 2019-11-15 16:05 UTC (permalink / raw)
To: intel-gfx
If we do find ourselves with an idle barrier inside our active while
waiting, attempt to flush it by emitting a pulse using the kernel
context.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_active.c | 21 ++++++++-
drivers/gpu/drm/i915/selftests/i915_active.c | 46 ++++++++++++++++++++
2 files changed, 65 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_active.c b/drivers/gpu/drm/i915/i915_active.c
index 5448f37c8102..268ccf7b916d 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -6,6 +6,7 @@
#include <linux/debugobjects.h>
+#include "gt/intel_engine_heartbeat.h"
#include "gt/intel_engine_pm.h"
#include "gt/intel_ring.h"
@@ -434,6 +435,21 @@ static void enable_signaling(struct i915_active_fence *active)
dma_fence_put(fence);
}
+static int flush_barrier(struct active_node *it)
+{
+ struct intel_engine_cs *engine;
+
+ if (!is_barrier(&it->base))
+ return 0;
+
+ engine = __barrier_to_engine(it);
+ smp_rmb(); /* serialise with add_active_barriers */
+ if (!is_barrier(&it->base))
+ return 0;
+
+ return intel_engine_flush_barriers(engine);
+}
+
int i915_active_wait(struct i915_active *ref)
{
struct active_node *it, *n;
@@ -447,8 +463,9 @@ int i915_active_wait(struct i915_active *ref)
/* Flush lazy signals */
enable_signaling(&ref->excl);
rbtree_postorder_for_each_entry_safe(it, n, &ref->tree, node) {
- if (is_barrier(&it->base)) /* unconnected idle barrier */
- continue;
+ err = flush_barrier(it); /* unconnected idle barrier? */
+ if (err)
+ break;
enable_signaling(&it->base);
}
diff --git a/drivers/gpu/drm/i915/selftests/i915_active.c b/drivers/gpu/drm/i915/selftests/i915_active.c
index 60290f78750d..df03bdfd278c 100644
--- a/drivers/gpu/drm/i915/selftests/i915_active.c
+++ b/drivers/gpu/drm/i915/selftests/i915_active.c
@@ -193,11 +193,57 @@ static int live_active_retire(void *arg)
return err;
}
+static int live_active_barrier(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct intel_engine_cs *engine;
+ struct live_active *active;
+ int err = 0;
+
+ /* Check that we get a callback when requests retire upon waiting */
+
+ active = __live_alloc(i915);
+ if (!active)
+ return -ENOMEM;
+
+ err = i915_active_acquire(&active->base);
+ if (err)
+ goto out;
+
+ for_each_uabi_engine(engine, i915) {
+ err = i915_active_acquire_preallocate_barrier(&active->base,
+ engine);
+ if (err)
+ break;
+
+ i915_active_acquire_barrier(&active->base);
+ }
+
+ i915_active_release(&active->base);
+
+ if (err == 0)
+ err = i915_active_wait(&active->base);
+
+ if (err == 0 && !READ_ONCE(active->retired)) {
+ pr_err("i915_active not retired after flushing barriers!\n");
+ err = -EINVAL;
+ }
+
+out:
+ __live_put(active);
+
+ if (igt_flush_test(i915))
+ err = -EIO;
+
+ return err;
+}
+
int i915_active_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_active_wait),
SUBTEST(live_active_retire),
+ SUBTEST(live_active_barrier),
};
if (intel_gt_is_wedged(&i915->gt))
--
2.24.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/i915: Flush idle barriers when waiting
@ 2019-11-15 16:05 ` Chris Wilson
0 siblings, 0 replies; 18+ messages in thread
From: Chris Wilson @ 2019-11-15 16:05 UTC (permalink / raw)
To: intel-gfx
If we do find ourselves with an idle barrier inside our active while
waiting, attempt to flush it by emitting a pulse using the kernel
context.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_active.c | 21 ++++++++-
drivers/gpu/drm/i915/selftests/i915_active.c | 46 ++++++++++++++++++++
2 files changed, 65 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_active.c b/drivers/gpu/drm/i915/i915_active.c
index 5448f37c8102..268ccf7b916d 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -6,6 +6,7 @@
#include <linux/debugobjects.h>
+#include "gt/intel_engine_heartbeat.h"
#include "gt/intel_engine_pm.h"
#include "gt/intel_ring.h"
@@ -434,6 +435,21 @@ static void enable_signaling(struct i915_active_fence *active)
dma_fence_put(fence);
}
+static int flush_barrier(struct active_node *it)
+{
+ struct intel_engine_cs *engine;
+
+ if (!is_barrier(&it->base))
+ return 0;
+
+ engine = __barrier_to_engine(it);
+ smp_rmb(); /* serialise with add_active_barriers */
+ if (!is_barrier(&it->base))
+ return 0;
+
+ return intel_engine_flush_barriers(engine);
+}
+
int i915_active_wait(struct i915_active *ref)
{
struct active_node *it, *n;
@@ -447,8 +463,9 @@ int i915_active_wait(struct i915_active *ref)
/* Flush lazy signals */
enable_signaling(&ref->excl);
rbtree_postorder_for_each_entry_safe(it, n, &ref->tree, node) {
- if (is_barrier(&it->base)) /* unconnected idle barrier */
- continue;
+ err = flush_barrier(it); /* unconnected idle barrier? */
+ if (err)
+ break;
enable_signaling(&it->base);
}
diff --git a/drivers/gpu/drm/i915/selftests/i915_active.c b/drivers/gpu/drm/i915/selftests/i915_active.c
index 60290f78750d..df03bdfd278c 100644
--- a/drivers/gpu/drm/i915/selftests/i915_active.c
+++ b/drivers/gpu/drm/i915/selftests/i915_active.c
@@ -193,11 +193,57 @@ static int live_active_retire(void *arg)
return err;
}
+static int live_active_barrier(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct intel_engine_cs *engine;
+ struct live_active *active;
+ int err = 0;
+
+ /* Check that we get a callback when requests retire upon waiting */
+
+ active = __live_alloc(i915);
+ if (!active)
+ return -ENOMEM;
+
+ err = i915_active_acquire(&active->base);
+ if (err)
+ goto out;
+
+ for_each_uabi_engine(engine, i915) {
+ err = i915_active_acquire_preallocate_barrier(&active->base,
+ engine);
+ if (err)
+ break;
+
+ i915_active_acquire_barrier(&active->base);
+ }
+
+ i915_active_release(&active->base);
+
+ if (err == 0)
+ err = i915_active_wait(&active->base);
+
+ if (err == 0 && !READ_ONCE(active->retired)) {
+ pr_err("i915_active not retired after flushing barriers!\n");
+ err = -EINVAL;
+ }
+
+out:
+ __live_put(active);
+
+ if (igt_flush_test(i915))
+ err = -EIO;
+
+ return err;
+}
+
int i915_active_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_active_wait),
SUBTEST(live_active_retire),
+ SUBTEST(live_active_barrier),
};
if (intel_gt_is_wedged(&i915->gt))
--
2.24.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/3] drm/i915: Allow userspace to specify ringsize on construction
@ 2019-11-15 16:05 ` Chris Wilson
0 siblings, 0 replies; 18+ messages in thread
From: Chris Wilson @ 2019-11-15 16:05 UTC (permalink / raw)
To: intel-gfx
No good reason why we must always use a static ringsize, so let
userspace select one during construction.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 139 +++++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
include/uapi/drm/i915_drm.h | 19 +++
3 files changed, 153 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 1284f47303fa..ee9a4634fed8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -597,23 +597,30 @@ __create_context(struct drm_i915_private *i915)
return ERR_PTR(err);
}
-static void
+static int
context_apply_all(struct i915_gem_context *ctx,
- void (*fn)(struct intel_context *ce, void *data),
+ int (*fn)(struct intel_context *ce, void *data),
void *data)
{
struct i915_gem_engines_iter it;
struct intel_context *ce;
+ int err = 0;
- for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it)
- fn(ce, data);
+ for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
+ err = fn(ce, data);
+ if (err)
+ break;
+ }
i915_gem_context_unlock_engines(ctx);
+
+ return err;
}
-static void __apply_ppgtt(struct intel_context *ce, void *vm)
+static int __apply_ppgtt(struct intel_context *ce, void *vm)
{
i915_vm_put(ce->vm);
ce->vm = i915_vm_get(vm);
+ return 0;
}
static struct i915_address_space *
@@ -651,9 +658,10 @@ static void __set_timeline(struct intel_timeline **dst,
intel_timeline_put(old);
}
-static void __apply_timeline(struct intel_context *ce, void *timeline)
+static int __apply_timeline(struct intel_context *ce, void *timeline)
{
__set_timeline(&ce->timeline, timeline);
+ return 0;
}
static void __assign_timeline(struct i915_gem_context *ctx,
@@ -1223,6 +1231,104 @@ static int set_ppgtt(struct drm_i915_file_private *file_priv,
return err;
}
+static int __apply_ringsize(struct intel_context *ce, void *sz)
+{
+ int err;
+
+ err = i915_active_wait(&ce->active);
+ if (err < 0)
+ return err;
+
+ if (intel_context_lock_pinned(ce))
+ return -EINTR;
+
+ if (intel_context_is_pinned(ce)) {
+ err = -EBUSY; /* In active use, come back later! */
+ goto unlock;
+ }
+
+ if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
+ struct intel_ring *ring;
+
+ /* Replace the existing ringbuffer */
+ ring = intel_engine_create_ring(ce->engine,
+ (unsigned long)sz);
+ if (IS_ERR(ring)) {
+ err = PTR_ERR(ring);
+ goto unlock;
+ }
+
+ intel_ring_put(ce->ring);
+ ce->ring = ring;
+
+ /* Context image will be updated on next pin */
+ } else {
+ ce->ring = sz;
+ }
+
+unlock:
+ intel_context_unlock_pinned(ce);
+ return err;
+}
+
+static int set_ringsize(struct i915_gem_context *ctx,
+ struct drm_i915_gem_context_param *args)
+{
+ if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915))
+ return -ENODEV;
+
+ if (args->size)
+ return -EINVAL;
+
+ if (!IS_ALIGNED(args->value, I915_GTT_PAGE_SIZE))
+ return -EINVAL;
+
+ if (args->value < I915_GTT_PAGE_SIZE)
+ return -EINVAL;
+
+ if (args->value > 128 * I915_GTT_PAGE_SIZE)
+ return -EINVAL;
+
+ return context_apply_all(ctx,
+ __apply_ringsize,
+ __intel_context_ring_size(args->value));
+}
+
+static int __get_ringsize(struct intel_context *ce, void *arg)
+{
+ int num_pages;
+
+ if (intel_context_lock_pinned(ce))
+ return -EINTR;
+
+ if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags))
+ num_pages = ce->ring->size / I915_GTT_PAGE_SIZE;
+ else
+ num_pages = (uintptr_t)ce->ring / I915_GTT_PAGE_SIZE;
+
+ intel_context_unlock_pinned(ce);
+ return num_pages; /* stop on first engine */
+}
+
+static int get_ringsize(struct i915_gem_context *ctx,
+ struct drm_i915_gem_context_param *args)
+{
+ int num_pages;
+
+ if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915))
+ return -ENODEV;
+
+ if (args->size)
+ return -EINVAL;
+
+ num_pages = context_apply_all(ctx, __get_ringsize, NULL);
+ if (num_pages < 0)
+ return num_pages;
+
+ args->value = (u64)num_pages * I915_GTT_PAGE_SIZE;
+ return 0;
+}
+
static int gen8_emit_rpcs_config(struct i915_request *rq,
struct intel_context *ce,
struct intel_sseu sseu)
@@ -1935,6 +2041,10 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
ret = set_persistence(ctx, args);
break;
+ case I915_CONTEXT_PARAM_RINGSIZE:
+ ret = set_ringsize(ctx, args);
+ break;
+
case I915_CONTEXT_PARAM_BAN_PERIOD:
default:
ret = -EINVAL;
@@ -2003,6 +2113,19 @@ static int clone_engines(struct i915_gem_context *dst,
__free_engines(clone, n);
goto err_unlock;
}
+
+ /* Copy across the preferred ringsize */
+ clone->engines[n]->ring = e->engines[n]->ring;
+ if (test_bit(CONTEXT_ALLOC_BIT, &e->engines[n]->flags)) {
+ if (intel_context_lock_pinned(e->engines[n])) {
+ __free_engines(clone, n + 1);
+ goto err_unlock;
+ }
+
+ clone->engines[n]->ring =
+ __intel_context_ring_size(e->engines[n]->ring->size);
+ intel_context_unlock_pinned(e->engines[n]);
+ }
}
clone->num_engines = n;
@@ -2366,6 +2489,10 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
args->value = i915_gem_context_is_persistent(ctx);
break;
+ case I915_CONTEXT_PARAM_RINGSIZE:
+ ret = get_ringsize(ctx, args);
+ break;
+
case I915_CONTEXT_PARAM_BAN_PERIOD:
default:
ret = -EINVAL;
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 33ce258d484f..2649690a951e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2417,6 +2417,7 @@ __execlists_update_reg_state(const struct intel_context *ce,
regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
regs[CTX_RING_HEAD] = ring->head;
regs[CTX_RING_TAIL] = ring->tail;
+ regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
/* RPCS */
if (engine->class == RENDER_CLASS) {
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 5400d7e057f1..ae7cd681b075 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1587,6 +1587,25 @@ struct drm_i915_gem_context_param {
* By default, new contexts allow persistence.
*/
#define I915_CONTEXT_PARAM_PERSISTENCE 0xb
+
+/*
+ * I915_CONTEXT_PARAM_RINGSIZE:
+ *
+ * Sets the size of the CS ringbuffer to use for logical ring contexts. This
+ * applies a limit of how many batches can be queued to HW before the caller
+ * is blocked due to lack of space for more commands.
+ *
+ * Only reliably possible to be set prior to first use, i.e. during
+ * construction. At any later point, the current execution must be flushed as
+ * the ring can only be changed while the context is idle.
+ *
+ * Only applies to the current set of engine and lost when those engines
+ * are replaced by a new mapping (see I915_CONTEXT_PARAM_ENGINES).
+ *
+ * Must be between 4 - 512 KiB, in intervals of page size [4 KiB].
+ * Default is 16 KiB.
+ */
+#define I915_CONTEXT_PARAM_RINGSIZE 0xc
/* Must be kept compact -- no holes and well documented */
__u64 value;
--
2.24.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915: Allow userspace to specify ringsize on construction
@ 2019-11-15 16:05 ` Chris Wilson
0 siblings, 0 replies; 18+ messages in thread
From: Chris Wilson @ 2019-11-15 16:05 UTC (permalink / raw)
To: intel-gfx
No good reason why we must always use a static ringsize, so let
userspace select one during construction.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 139 +++++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
include/uapi/drm/i915_drm.h | 19 +++
3 files changed, 153 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 1284f47303fa..ee9a4634fed8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -597,23 +597,30 @@ __create_context(struct drm_i915_private *i915)
return ERR_PTR(err);
}
-static void
+static int
context_apply_all(struct i915_gem_context *ctx,
- void (*fn)(struct intel_context *ce, void *data),
+ int (*fn)(struct intel_context *ce, void *data),
void *data)
{
struct i915_gem_engines_iter it;
struct intel_context *ce;
+ int err = 0;
- for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it)
- fn(ce, data);
+ for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
+ err = fn(ce, data);
+ if (err)
+ break;
+ }
i915_gem_context_unlock_engines(ctx);
+
+ return err;
}
-static void __apply_ppgtt(struct intel_context *ce, void *vm)
+static int __apply_ppgtt(struct intel_context *ce, void *vm)
{
i915_vm_put(ce->vm);
ce->vm = i915_vm_get(vm);
+ return 0;
}
static struct i915_address_space *
@@ -651,9 +658,10 @@ static void __set_timeline(struct intel_timeline **dst,
intel_timeline_put(old);
}
-static void __apply_timeline(struct intel_context *ce, void *timeline)
+static int __apply_timeline(struct intel_context *ce, void *timeline)
{
__set_timeline(&ce->timeline, timeline);
+ return 0;
}
static void __assign_timeline(struct i915_gem_context *ctx,
@@ -1223,6 +1231,104 @@ static int set_ppgtt(struct drm_i915_file_private *file_priv,
return err;
}
+static int __apply_ringsize(struct intel_context *ce, void *sz)
+{
+ int err;
+
+ err = i915_active_wait(&ce->active);
+ if (err < 0)
+ return err;
+
+ if (intel_context_lock_pinned(ce))
+ return -EINTR;
+
+ if (intel_context_is_pinned(ce)) {
+ err = -EBUSY; /* In active use, come back later! */
+ goto unlock;
+ }
+
+ if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
+ struct intel_ring *ring;
+
+ /* Replace the existing ringbuffer */
+ ring = intel_engine_create_ring(ce->engine,
+ (unsigned long)sz);
+ if (IS_ERR(ring)) {
+ err = PTR_ERR(ring);
+ goto unlock;
+ }
+
+ intel_ring_put(ce->ring);
+ ce->ring = ring;
+
+ /* Context image will be updated on next pin */
+ } else {
+ ce->ring = sz;
+ }
+
+unlock:
+ intel_context_unlock_pinned(ce);
+ return err;
+}
+
+static int set_ringsize(struct i915_gem_context *ctx,
+ struct drm_i915_gem_context_param *args)
+{
+ if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915))
+ return -ENODEV;
+
+ if (args->size)
+ return -EINVAL;
+
+ if (!IS_ALIGNED(args->value, I915_GTT_PAGE_SIZE))
+ return -EINVAL;
+
+ if (args->value < I915_GTT_PAGE_SIZE)
+ return -EINVAL;
+
+ if (args->value > 128 * I915_GTT_PAGE_SIZE)
+ return -EINVAL;
+
+ return context_apply_all(ctx,
+ __apply_ringsize,
+ __intel_context_ring_size(args->value));
+}
+
+static int __get_ringsize(struct intel_context *ce, void *arg)
+{
+ int num_pages;
+
+ if (intel_context_lock_pinned(ce))
+ return -EINTR;
+
+ if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags))
+ num_pages = ce->ring->size / I915_GTT_PAGE_SIZE;
+ else
+ num_pages = (uintptr_t)ce->ring / I915_GTT_PAGE_SIZE;
+
+ intel_context_unlock_pinned(ce);
+ return num_pages; /* stop on first engine */
+}
+
+static int get_ringsize(struct i915_gem_context *ctx,
+ struct drm_i915_gem_context_param *args)
+{
+ int num_pages;
+
+ if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915))
+ return -ENODEV;
+
+ if (args->size)
+ return -EINVAL;
+
+ num_pages = context_apply_all(ctx, __get_ringsize, NULL);
+ if (num_pages < 0)
+ return num_pages;
+
+ args->value = (u64)num_pages * I915_GTT_PAGE_SIZE;
+ return 0;
+}
+
static int gen8_emit_rpcs_config(struct i915_request *rq,
struct intel_context *ce,
struct intel_sseu sseu)
@@ -1935,6 +2041,10 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
ret = set_persistence(ctx, args);
break;
+ case I915_CONTEXT_PARAM_RINGSIZE:
+ ret = set_ringsize(ctx, args);
+ break;
+
case I915_CONTEXT_PARAM_BAN_PERIOD:
default:
ret = -EINVAL;
@@ -2003,6 +2113,19 @@ static int clone_engines(struct i915_gem_context *dst,
__free_engines(clone, n);
goto err_unlock;
}
+
+ /* Copy across the preferred ringsize */
+ clone->engines[n]->ring = e->engines[n]->ring;
+ if (test_bit(CONTEXT_ALLOC_BIT, &e->engines[n]->flags)) {
+ if (intel_context_lock_pinned(e->engines[n])) {
+ __free_engines(clone, n + 1);
+ goto err_unlock;
+ }
+
+ clone->engines[n]->ring =
+ __intel_context_ring_size(e->engines[n]->ring->size);
+ intel_context_unlock_pinned(e->engines[n]);
+ }
}
clone->num_engines = n;
@@ -2366,6 +2489,10 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
args->value = i915_gem_context_is_persistent(ctx);
break;
+ case I915_CONTEXT_PARAM_RINGSIZE:
+ ret = get_ringsize(ctx, args);
+ break;
+
case I915_CONTEXT_PARAM_BAN_PERIOD:
default:
ret = -EINVAL;
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 33ce258d484f..2649690a951e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2417,6 +2417,7 @@ __execlists_update_reg_state(const struct intel_context *ce,
regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
regs[CTX_RING_HEAD] = ring->head;
regs[CTX_RING_TAIL] = ring->tail;
+ regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
/* RPCS */
if (engine->class == RENDER_CLASS) {
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 5400d7e057f1..ae7cd681b075 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1587,6 +1587,25 @@ struct drm_i915_gem_context_param {
* By default, new contexts allow persistence.
*/
#define I915_CONTEXT_PARAM_PERSISTENCE 0xb
+
+/*
+ * I915_CONTEXT_PARAM_RINGSIZE:
+ *
+ * Sets the size of the CS ringbuffer to use for logical ring contexts. This
+ * applies a limit of how many batches can be queued to HW before the caller
+ * is blocked due to lack of space for more commands.
+ *
+ * Only reliably possible to be set prior to first use, i.e. during
+ * construction. At any later point, the current execution must be flushed as
+ * the ring can only be changed while the context is idle.
+ *
+ * Only applies to the current set of engine and lost when those engines
+ * are replaced by a new mapping (see I915_CONTEXT_PARAM_ENGINES).
+ *
+ * Must be between 4 - 512 KiB, in intervals of page size [4 KiB].
+ * Default is 16 KiB.
+ */
+#define I915_CONTEXT_PARAM_RINGSIZE 0xc
/* Must be kept compact -- no holes and well documented */
__u64 value;
--
2.24.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 3/3] drm/i915/gem: Honour O_NONBLOCK before throttling execbuf submissions
@ 2019-11-15 16:05 ` Chris Wilson
0 siblings, 0 replies; 18+ messages in thread
From: Chris Wilson @ 2019-11-15 16:05 UTC (permalink / raw)
To: intel-gfx
Check the user's flags on the struct file before deciding whether or not
to stall before submitting a request. This allows us to reasonably
cheaply honour O_NONBLOCK without checking at more critical phases
during request submission.
Suggested-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 21 ++++++++++++-------
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index f0998f1225af..8da95772c8f2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2249,15 +2249,22 @@ static int __eb_pin_engine(struct i915_execbuffer *eb, struct intel_context *ce)
intel_context_timeline_unlock(tl);
if (rq) {
- if (i915_request_wait(rq,
- I915_WAIT_INTERRUPTIBLE,
- MAX_SCHEDULE_TIMEOUT) < 0) {
- i915_request_put(rq);
- err = -EINTR;
- goto err_exit;
- }
+ bool nonblock = eb->file->filp->f_flags & O_NONBLOCK;
+ long timeout;
+
+ timeout = MAX_SCHEDULE_TIMEOUT;
+ if (nonblock)
+ timeout = 0;
+ timeout = i915_request_wait(rq,
+ I915_WAIT_INTERRUPTIBLE,
+ timeout);
i915_request_put(rq);
+
+ if (timeout < 0) {
+ err = nonblock ? -EWOULDBLOCK : timeout;
+ goto err_exit;
+ }
}
eb->engine = ce->engine;
--
2.24.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/gem: Honour O_NONBLOCK before throttling execbuf submissions
@ 2019-11-15 16:05 ` Chris Wilson
0 siblings, 0 replies; 18+ messages in thread
From: Chris Wilson @ 2019-11-15 16:05 UTC (permalink / raw)
To: intel-gfx
Check the user's flags on the struct file before deciding whether or not
to stall before submitting a request. This allows us to reasonably
cheaply honour O_NONBLOCK without checking at more critical phases
during request submission.
Suggested-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 21 ++++++++++++-------
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index f0998f1225af..8da95772c8f2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2249,15 +2249,22 @@ static int __eb_pin_engine(struct i915_execbuffer *eb, struct intel_context *ce)
intel_context_timeline_unlock(tl);
if (rq) {
- if (i915_request_wait(rq,
- I915_WAIT_INTERRUPTIBLE,
- MAX_SCHEDULE_TIMEOUT) < 0) {
- i915_request_put(rq);
- err = -EINTR;
- goto err_exit;
- }
+ bool nonblock = eb->file->filp->f_flags & O_NONBLOCK;
+ long timeout;
+
+ timeout = MAX_SCHEDULE_TIMEOUT;
+ if (nonblock)
+ timeout = 0;
+ timeout = i915_request_wait(rq,
+ I915_WAIT_INTERRUPTIBLE,
+ timeout);
i915_request_put(rq);
+
+ if (timeout < 0) {
+ err = nonblock ? -EWOULDBLOCK : timeout;
+ goto err_exit;
+ }
}
eb->engine = ce->engine;
--
2.24.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Flush idle barriers when waiting
@ 2019-11-15 20:56 ` Patchwork
0 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2019-11-15 20:56 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915: Flush idle barriers when waiting
URL : https://patchwork.freedesktop.org/series/69546/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7356 -> Patchwork_15291
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/index.html
Known issues
------------
Here are the changes found in Patchwork_15291 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [PASS][1] -> [FAIL][2] ([fdo#108511])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
* igt@kms_busy@basic-flip-pipe-b:
- fi-skl-6770hq: [PASS][3] -> [DMESG-WARN][4] ([fdo#105541])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/fi-skl-6770hq/igt@kms_busy@basic-flip-pipe-b.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/fi-skl-6770hq/igt@kms_busy@basic-flip-pipe-b.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#103167])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic-small-copy:
- fi-icl-dsi: [DMESG-WARN][7] ([fdo#106107]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/fi-icl-dsi/igt@gem_mmap_gtt@basic-small-copy.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/fi-icl-dsi/igt@gem_mmap_gtt@basic-small-copy.html
* igt@i915_selftest@live_hangcheck:
- fi-bsw-n3050: [INCOMPLETE][9] ([fdo#105876]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/fi-bsw-n3050/igt@i915_selftest@live_hangcheck.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/fi-bsw-n3050/igt@i915_selftest@live_hangcheck.html
- fi-hsw-4770r: [DMESG-FAIL][11] ([fdo#111991]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2: [FAIL][13] ([fdo#109635 ] / [fdo#110387]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111045] / [fdo#111096]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: [FAIL][17] ([fdo#103167]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
[fdo#105876]: https://bugs.freedesktop.org/show_bug.cgi?id=105876
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#109964]: https://bugs.freedesktop.org/show_bug.cgi?id=109964
[fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111991]: https://bugs.freedesktop.org/show_bug.cgi?id=111991
[fdo#112298]: https://bugs.freedesktop.org/show_bug.cgi?id=112298
Participating hosts (52 -> 45)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7356 -> Patchwork_15291
CI-20190529: 20190529
CI_DRM_7356: 967093f255d4e9c64856f381722c80cf56c96d3d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5288: ff4551e36cd8e573ceb1e450d17a12e3298dc04c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15291: a75383f3d71a005763bca4188b18c74e1315b7e7 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a75383f3d71a drm/i915/gem: Honour O_NONBLOCK before throttling execbuf submissions
a9dbf01afb40 drm/i915: Allow userspace to specify ringsize on construction
7dc6d30a2e16 drm/i915: Flush idle barriers when waiting
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Flush idle barriers when waiting
@ 2019-11-15 20:56 ` Patchwork
0 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2019-11-15 20:56 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915: Flush idle barriers when waiting
URL : https://patchwork.freedesktop.org/series/69546/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7356 -> Patchwork_15291
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/index.html
Known issues
------------
Here are the changes found in Patchwork_15291 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [PASS][1] -> [FAIL][2] ([fdo#108511])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
* igt@kms_busy@basic-flip-pipe-b:
- fi-skl-6770hq: [PASS][3] -> [DMESG-WARN][4] ([fdo#105541])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/fi-skl-6770hq/igt@kms_busy@basic-flip-pipe-b.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/fi-skl-6770hq/igt@kms_busy@basic-flip-pipe-b.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#103167])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic-small-copy:
- fi-icl-dsi: [DMESG-WARN][7] ([fdo#106107]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/fi-icl-dsi/igt@gem_mmap_gtt@basic-small-copy.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/fi-icl-dsi/igt@gem_mmap_gtt@basic-small-copy.html
* igt@i915_selftest@live_hangcheck:
- fi-bsw-n3050: [INCOMPLETE][9] ([fdo#105876]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/fi-bsw-n3050/igt@i915_selftest@live_hangcheck.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/fi-bsw-n3050/igt@i915_selftest@live_hangcheck.html
- fi-hsw-4770r: [DMESG-FAIL][11] ([fdo#111991]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2: [FAIL][13] ([fdo#109635 ] / [fdo#110387]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111045] / [fdo#111096]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: [FAIL][17] ([fdo#103167]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
[fdo#105876]: https://bugs.freedesktop.org/show_bug.cgi?id=105876
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#109964]: https://bugs.freedesktop.org/show_bug.cgi?id=109964
[fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111991]: https://bugs.freedesktop.org/show_bug.cgi?id=111991
[fdo#112298]: https://bugs.freedesktop.org/show_bug.cgi?id=112298
Participating hosts (52 -> 45)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7356 -> Patchwork_15291
CI-20190529: 20190529
CI_DRM_7356: 967093f255d4e9c64856f381722c80cf56c96d3d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5288: ff4551e36cd8e573ceb1e450d17a12e3298dc04c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15291: a75383f3d71a005763bca4188b18c74e1315b7e7 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a75383f3d71a drm/i915/gem: Honour O_NONBLOCK before throttling execbuf submissions
a9dbf01afb40 drm/i915: Allow userspace to specify ringsize on construction
7dc6d30a2e16 drm/i915: Flush idle barriers when waiting
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: Flush idle barriers when waiting
@ 2019-11-17 9:27 ` Patchwork
0 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2019-11-17 9:27 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915: Flush idle barriers when waiting
URL : https://patchwork.freedesktop.org/series/69546/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7356_full -> Patchwork_15291_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15291_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15291_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15291_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_balancer@bonded-slice:
- shard-tglb: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb3/igt@gem_exec_balancer@bonded-slice.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb1/igt@gem_exec_balancer@bonded-slice.html
* igt@gem_exec_balancer@nop:
- shard-tglb: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb4/igt@gem_exec_balancer@nop.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb4/igt@gem_exec_balancer@nop.html
- shard-kbl: [PASS][5] -> [DMESG-FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-kbl2/igt@gem_exec_balancer@nop.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-kbl3/igt@gem_exec_balancer@nop.html
* igt@gem_exec_schedule@out-order-blt:
- shard-tglb: [PASS][7] -> [INCOMPLETE][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb9/igt@gem_exec_schedule@out-order-blt.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb6/igt@gem_exec_schedule@out-order-blt.html
* igt@runner@aborted:
- shard-kbl: NOTRUN -> [FAIL][9]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-kbl3/igt@runner@aborted.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_parse_blt@batch-invalid-length}:
- shard-tglb: NOTRUN -> [SKIP][10] +3 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb9/igt@gem_exec_parse_blt@batch-invalid-length.html
Known issues
------------
Here are the changes found in Patchwork_15291_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112080]) +8 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb2/igt@gem_busy@busy-vcs1.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb8/igt@gem_busy@busy-vcs1.html
* igt@gem_ctx_persistence@vcs1-mixed-process:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109276] / [fdo#112080]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb2/igt@gem_ctx_persistence@vcs1-mixed-process.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb7/igt@gem_ctx_persistence@vcs1-mixed-process.html
* igt@gem_eio@in-flight-suspend:
- shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#104108])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-skl2/igt@gem_eio@in-flight-suspend.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-skl5/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_balancer@bonded-slice:
- shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([fdo#110778])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-kbl2/igt@gem_exec_balancer@bonded-slice.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-kbl4/igt@gem_exec_balancer@bonded-slice.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#110854])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb4/igt@gem_exec_balancer@smoke.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb3/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_nop@basic-series:
- shard-tglb: [PASS][21] -> [INCOMPLETE][22] ([fdo#111747])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb8/igt@gem_exec_nop@basic-series.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb6/igt@gem_exec_nop@basic-series.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#112146]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb8/igt@gem_exec_schedule@preemptive-hang-bsd.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb4/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109276]) +20 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb4/igt@gem_exec_schedule@promotion-bsd1.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb3/igt@gem_exec_schedule@promotion-bsd1.html
* igt@gem_userptr_blits@sync-unmap:
- shard-snb: [PASS][27] -> [DMESG-WARN][28] ([fdo#111870]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-snb5/igt@gem_userptr_blits@sync-unmap.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-snb1/igt@gem_userptr_blits@sync-unmap.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([fdo#108566]) +4 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic:
- shard-hsw: [PASS][31] -> [FAIL][32] ([fdo#103355]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-hsw7/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: [PASS][33] -> [FAIL][34] ([fdo#105363])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-glk3/igt@kms_flip@flip-vs-expired-vblank.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-glk6/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [PASS][35] -> [FAIL][36] ([fdo#103167]) +5 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt:
- shard-tglb: [PASS][37] -> [FAIL][38] ([fdo#103167]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][39] -> [FAIL][40] ([fdo#108145])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][41] -> [FAIL][42] ([fdo#108145] / [fdo#110403])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [PASS][43] -> [FAIL][44] ([fdo#103166])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-y.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][45] -> [FAIL][46] ([fdo#108341])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb7/igt@kms_psr@no_drrs.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb1/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [PASS][47] -> [SKIP][48] ([fdo#109441]) +2 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb2/igt@kms_psr@psr2_basic.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb7/igt@kms_psr@psr2_basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][49] -> [DMESG-WARN][50] ([fdo#108566]) +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-apl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-apl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-tglb: [PASS][51] -> [INCOMPLETE][52] ([fdo#111832] / [fdo#111850]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb8/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs1-reset:
- shard-iclb: [SKIP][53] ([fdo#109276] / [fdo#112080]) -> [PASS][54] +2 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb8/igt@gem_ctx_isolation@vcs1-reset.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb4/igt@gem_ctx_isolation@vcs1-reset.html
* igt@gem_ctx_switch@queue-light:
- shard-tglb: [INCOMPLETE][55] ([fdo#111672]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb6/igt@gem_ctx_switch@queue-light.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb9/igt@gem_ctx_switch@queue-light.html
* igt@gem_ctx_switch@vcs1-heavy:
- shard-iclb: [SKIP][57] ([fdo#112080]) -> [PASS][58] +11 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb7/igt@gem_ctx_switch@vcs1-heavy.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb1/igt@gem_ctx_switch@vcs1-heavy.html
* igt@gem_eio@suspend:
- shard-tglb: [INCOMPLETE][59] ([fdo#111850]) -> [PASS][60] +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb5/igt@gem_eio@suspend.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb5/igt@gem_eio@suspend.html
* igt@gem_exec_flush@basic-batch-kernel-default-wb:
- shard-hsw: [INCOMPLETE][61] ([fdo#103540]) -> [PASS][62] +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-hsw5/igt@gem_exec_flush@basic-batch-kernel-default-wb.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-hsw2/igt@gem_exec_flush@basic-batch-kernel-default-wb.html
* igt@gem_exec_gttfill@basic:
- shard-tglb: [INCOMPLETE][63] ([fdo#111593]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb6/igt@gem_exec_gttfill@basic.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb5/igt@gem_exec_gttfill@basic.html
* igt@gem_exec_nop@basic-parallel:
- shard-tglb: [INCOMPLETE][65] ([fdo#111747]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb6/igt@gem_exec_nop@basic-parallel.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb3/igt@gem_exec_nop@basic-parallel.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [SKIP][67] ([fdo#112146]) -> [PASS][68] +7 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb2/igt@gem_exec_schedule@wide-bsd.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb7/igt@gem_exec_schedule@wide-bsd.html
* igt@gem_softpin@noreloc-s3:
- shard-tglb: [INCOMPLETE][69] ([fdo#111832]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb2/igt@gem_softpin@noreloc-s3.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb9/igt@gem_softpin@noreloc-s3.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [DMESG-WARN][71] ([fdo#111870]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-snb4/igt@gem_userptr_blits@sync-unmap-cycles.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-snb6/igt@gem_userptr_blits@sync-unmap-cycles.html
- shard-hsw: [DMESG-WARN][73] ([fdo#111870]) -> [PASS][74] +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-hsw5/igt@gem_userptr_blits@sync-unmap-cycles.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-hsw2/igt@gem_userptr_blits@sync-unmap-cycles.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-kbl: [SKIP][75] ([fdo#109271]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-kbl2/igt@i915_pm_rc6_residency@rc6-accuracy.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-kbl4/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@i915_suspend@fence-restore-untiled:
- shard-snb: [DMESG-WARN][77] ([fdo#102365]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-snb2/igt@i915_suspend@fence-restore-untiled.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-snb7/igt@i915_suspend@fence-restore-untiled.html
* igt@i915_suspend@sysfs-reader:
- shard-tglb: [INCOMPLETE][79] ([fdo#111832] / [fdo#111850]) -> [PASS][80] +4 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb4/igt@i915_suspend@sysfs-reader.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb7/igt@i915_suspend@sysfs-reader.html
- shard-apl: [DMESG-WARN][81] ([fdo#108566]) -> [PASS][82] +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-apl4/igt@i915_suspend@sysfs-reader.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-apl4/igt@i915_suspend@sysfs-reader.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][83] ([fdo#105363]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-skl4/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-kbl: [DMESG-WARN][85] ([fdo#108566]) -> [PASS][86] +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
- shard-tglb: [FAIL][87] ([fdo#103167]) -> [PASS][88] +2 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [FAIL][89] ([fdo#103167]) -> [PASS][90] +5 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [FAIL][91] ([fdo#103166]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-x.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][93] ([fdo#109441]) -> [PASS][94] +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb1/igt@kms_psr@psr2_no_drrs.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][95] ([fdo#109276]) -> [PASS][96] +12 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb7/igt@prime_vgem@fence-wait-bsd2.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [FAIL][97] ([fdo#111329]) -> [SKIP][98] ([fdo#109276] / [fdo#112080])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb3/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_ctx_isolation@vcs2-none:
- shard-tglb: [SKIP][99] ([fdo#112080]) -> [SKIP][100] ([fdo#111912] / [fdo#112080])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb9/igt@gem_ctx_isolation@vcs2-none.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb4/igt@gem_ctx_isolation@vcs2-none.html
* igt@gem_exec_schedule@deep-render:
- shard-tglb: [INCOMPLETE][101] ([fdo#111671]) -> [FAIL][102] ([fdo#111646])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb5/igt@gem_exec_schedule@deep-render.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb2/igt@gem_exec_schedule@deep-render.html
* igt@i915_pm_dc@dc6-dpms:
- shard-tglb: [SKIP][103] ([fdo#111865]) -> [FAIL][104] ([fdo#111830 ])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb6/igt@i915_pm_dc@dc6-dpms.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][105] ([fdo#107724]) -> [SKIP][106] ([fdo#109349])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb8/igt@kms_dp_dsc@basic-dsc-enable-edp.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: Flush idle barriers when waiting
@ 2019-11-17 9:27 ` Patchwork
0 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2019-11-17 9:27 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915: Flush idle barriers when waiting
URL : https://patchwork.freedesktop.org/series/69546/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7356_full -> Patchwork_15291_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15291_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15291_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15291_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_balancer@bonded-slice:
- shard-tglb: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb3/igt@gem_exec_balancer@bonded-slice.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb1/igt@gem_exec_balancer@bonded-slice.html
* igt@gem_exec_balancer@nop:
- shard-tglb: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb4/igt@gem_exec_balancer@nop.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb4/igt@gem_exec_balancer@nop.html
- shard-kbl: [PASS][5] -> [DMESG-FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-kbl2/igt@gem_exec_balancer@nop.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-kbl3/igt@gem_exec_balancer@nop.html
* igt@gem_exec_schedule@out-order-blt:
- shard-tglb: [PASS][7] -> [INCOMPLETE][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb9/igt@gem_exec_schedule@out-order-blt.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb6/igt@gem_exec_schedule@out-order-blt.html
* igt@runner@aborted:
- shard-kbl: NOTRUN -> [FAIL][9]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-kbl3/igt@runner@aborted.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_parse_blt@batch-invalid-length}:
- shard-tglb: NOTRUN -> [SKIP][10] +3 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb9/igt@gem_exec_parse_blt@batch-invalid-length.html
Known issues
------------
Here are the changes found in Patchwork_15291_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112080]) +8 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb2/igt@gem_busy@busy-vcs1.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb8/igt@gem_busy@busy-vcs1.html
* igt@gem_ctx_persistence@vcs1-mixed-process:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109276] / [fdo#112080]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb2/igt@gem_ctx_persistence@vcs1-mixed-process.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb7/igt@gem_ctx_persistence@vcs1-mixed-process.html
* igt@gem_eio@in-flight-suspend:
- shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#104108])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-skl2/igt@gem_eio@in-flight-suspend.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-skl5/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_balancer@bonded-slice:
- shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([fdo#110778])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-kbl2/igt@gem_exec_balancer@bonded-slice.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-kbl4/igt@gem_exec_balancer@bonded-slice.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#110854])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb4/igt@gem_exec_balancer@smoke.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb3/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_nop@basic-series:
- shard-tglb: [PASS][21] -> [INCOMPLETE][22] ([fdo#111747])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb8/igt@gem_exec_nop@basic-series.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb6/igt@gem_exec_nop@basic-series.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#112146]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb8/igt@gem_exec_schedule@preemptive-hang-bsd.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb4/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109276]) +20 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb4/igt@gem_exec_schedule@promotion-bsd1.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb3/igt@gem_exec_schedule@promotion-bsd1.html
* igt@gem_userptr_blits@sync-unmap:
- shard-snb: [PASS][27] -> [DMESG-WARN][28] ([fdo#111870]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-snb5/igt@gem_userptr_blits@sync-unmap.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-snb1/igt@gem_userptr_blits@sync-unmap.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([fdo#108566]) +4 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic:
- shard-hsw: [PASS][31] -> [FAIL][32] ([fdo#103355]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-hsw7/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: [PASS][33] -> [FAIL][34] ([fdo#105363])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-glk3/igt@kms_flip@flip-vs-expired-vblank.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-glk6/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [PASS][35] -> [FAIL][36] ([fdo#103167]) +5 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt:
- shard-tglb: [PASS][37] -> [FAIL][38] ([fdo#103167]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][39] -> [FAIL][40] ([fdo#108145])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][41] -> [FAIL][42] ([fdo#108145] / [fdo#110403])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [PASS][43] -> [FAIL][44] ([fdo#103166])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-y.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][45] -> [FAIL][46] ([fdo#108341])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb7/igt@kms_psr@no_drrs.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb1/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [PASS][47] -> [SKIP][48] ([fdo#109441]) +2 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb2/igt@kms_psr@psr2_basic.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb7/igt@kms_psr@psr2_basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][49] -> [DMESG-WARN][50] ([fdo#108566]) +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-apl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-apl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-tglb: [PASS][51] -> [INCOMPLETE][52] ([fdo#111832] / [fdo#111850]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb8/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs1-reset:
- shard-iclb: [SKIP][53] ([fdo#109276] / [fdo#112080]) -> [PASS][54] +2 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb8/igt@gem_ctx_isolation@vcs1-reset.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb4/igt@gem_ctx_isolation@vcs1-reset.html
* igt@gem_ctx_switch@queue-light:
- shard-tglb: [INCOMPLETE][55] ([fdo#111672]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb6/igt@gem_ctx_switch@queue-light.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb9/igt@gem_ctx_switch@queue-light.html
* igt@gem_ctx_switch@vcs1-heavy:
- shard-iclb: [SKIP][57] ([fdo#112080]) -> [PASS][58] +11 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb7/igt@gem_ctx_switch@vcs1-heavy.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb1/igt@gem_ctx_switch@vcs1-heavy.html
* igt@gem_eio@suspend:
- shard-tglb: [INCOMPLETE][59] ([fdo#111850]) -> [PASS][60] +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb5/igt@gem_eio@suspend.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb5/igt@gem_eio@suspend.html
* igt@gem_exec_flush@basic-batch-kernel-default-wb:
- shard-hsw: [INCOMPLETE][61] ([fdo#103540]) -> [PASS][62] +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-hsw5/igt@gem_exec_flush@basic-batch-kernel-default-wb.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-hsw2/igt@gem_exec_flush@basic-batch-kernel-default-wb.html
* igt@gem_exec_gttfill@basic:
- shard-tglb: [INCOMPLETE][63] ([fdo#111593]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb6/igt@gem_exec_gttfill@basic.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb5/igt@gem_exec_gttfill@basic.html
* igt@gem_exec_nop@basic-parallel:
- shard-tglb: [INCOMPLETE][65] ([fdo#111747]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb6/igt@gem_exec_nop@basic-parallel.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb3/igt@gem_exec_nop@basic-parallel.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [SKIP][67] ([fdo#112146]) -> [PASS][68] +7 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb2/igt@gem_exec_schedule@wide-bsd.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb7/igt@gem_exec_schedule@wide-bsd.html
* igt@gem_softpin@noreloc-s3:
- shard-tglb: [INCOMPLETE][69] ([fdo#111832]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb2/igt@gem_softpin@noreloc-s3.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb9/igt@gem_softpin@noreloc-s3.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [DMESG-WARN][71] ([fdo#111870]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-snb4/igt@gem_userptr_blits@sync-unmap-cycles.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-snb6/igt@gem_userptr_blits@sync-unmap-cycles.html
- shard-hsw: [DMESG-WARN][73] ([fdo#111870]) -> [PASS][74] +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-hsw5/igt@gem_userptr_blits@sync-unmap-cycles.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-hsw2/igt@gem_userptr_blits@sync-unmap-cycles.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-kbl: [SKIP][75] ([fdo#109271]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-kbl2/igt@i915_pm_rc6_residency@rc6-accuracy.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-kbl4/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@i915_suspend@fence-restore-untiled:
- shard-snb: [DMESG-WARN][77] ([fdo#102365]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-snb2/igt@i915_suspend@fence-restore-untiled.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-snb7/igt@i915_suspend@fence-restore-untiled.html
* igt@i915_suspend@sysfs-reader:
- shard-tglb: [INCOMPLETE][79] ([fdo#111832] / [fdo#111850]) -> [PASS][80] +4 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb4/igt@i915_suspend@sysfs-reader.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb7/igt@i915_suspend@sysfs-reader.html
- shard-apl: [DMESG-WARN][81] ([fdo#108566]) -> [PASS][82] +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-apl4/igt@i915_suspend@sysfs-reader.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-apl4/igt@i915_suspend@sysfs-reader.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][83] ([fdo#105363]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-skl4/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-kbl: [DMESG-WARN][85] ([fdo#108566]) -> [PASS][86] +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
- shard-tglb: [FAIL][87] ([fdo#103167]) -> [PASS][88] +2 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [FAIL][89] ([fdo#103167]) -> [PASS][90] +5 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [FAIL][91] ([fdo#103166]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-x.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][93] ([fdo#109441]) -> [PASS][94] +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb1/igt@kms_psr@psr2_no_drrs.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][95] ([fdo#109276]) -> [PASS][96] +12 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb7/igt@prime_vgem@fence-wait-bsd2.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [FAIL][97] ([fdo#111329]) -> [SKIP][98] ([fdo#109276] / [fdo#112080])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb3/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_ctx_isolation@vcs2-none:
- shard-tglb: [SKIP][99] ([fdo#112080]) -> [SKIP][100] ([fdo#111912] / [fdo#112080])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb9/igt@gem_ctx_isolation@vcs2-none.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb4/igt@gem_ctx_isolation@vcs2-none.html
* igt@gem_exec_schedule@deep-render:
- shard-tglb: [INCOMPLETE][101] ([fdo#111671]) -> [FAIL][102] ([fdo#111646])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb5/igt@gem_exec_schedule@deep-render.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb2/igt@gem_exec_schedule@deep-render.html
* igt@i915_pm_dc@dc6-dpms:
- shard-tglb: [SKIP][103] ([fdo#111865]) -> [FAIL][104] ([fdo#111830 ])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-tglb6/igt@i915_pm_dc@dc6-dpms.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][105] ([fdo#107724]) -> [SKIP][106] ([fdo#109349])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7356/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/shard-iclb8/igt@kms_dp_dsc@basic-dsc-enable-edp.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15291/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/3] drm/i915: Allow userspace to specify ringsize on construction
@ 2019-11-18 11:14 ` Janusz Krzysztofik
0 siblings, 0 replies; 18+ messages in thread
From: Janusz Krzysztofik @ 2019-11-18 11:14 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
Hi Chris,
Only some minor comments from me, mostly out of my curiosity.
On Friday, November 15, 2019 5:05:45 PM CET Chris Wilson wrote:
> No good reason why we must always use a static ringsize, so let
> userspace select one during construction.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 139 +++++++++++++++++++-
> drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
> include/uapi/drm/i915_drm.h | 19 +++
> 3 files changed, 153 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index 1284f47303fa..ee9a4634fed8 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -597,23 +597,30 @@ __create_context(struct drm_i915_private *i915)
> return ERR_PTR(err);
> }
>
> -static void
> +static int
> context_apply_all(struct i915_gem_context *ctx,
> - void (*fn)(struct intel_context *ce, void *data),
> + int (*fn)(struct intel_context *ce, void *data),
> void *data)
> {
> struct i915_gem_engines_iter it;
> struct intel_context *ce;
> + int err = 0;
>
> - for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it)
> - fn(ce, data);
> + for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
> + err = fn(ce, data);
> + if (err)
> + break;
> + }
> i915_gem_context_unlock_engines(ctx);
> +
> + return err;
> }
>
> -static void __apply_ppgtt(struct intel_context *ce, void *vm)
> +static int __apply_ppgtt(struct intel_context *ce, void *vm)
> {
> i915_vm_put(ce->vm);
> ce->vm = i915_vm_get(vm);
> + return 0;
> }
>
> static struct i915_address_space *
> @@ -651,9 +658,10 @@ static void __set_timeline(struct intel_timeline **dst,
> intel_timeline_put(old);
> }
>
> -static void __apply_timeline(struct intel_context *ce, void *timeline)
> +static int __apply_timeline(struct intel_context *ce, void *timeline)
> {
> __set_timeline(&ce->timeline, timeline);
> + return 0;
> }
>
> static void __assign_timeline(struct i915_gem_context *ctx,
> @@ -1223,6 +1231,104 @@ static int set_ppgtt(struct drm_i915_file_private *file_priv,
> return err;
> }
>
> +static int __apply_ringsize(struct intel_context *ce, void *sz)
> +{
> + int err;
> +
> + err = i915_active_wait(&ce->active);
> + if (err < 0)
> + return err;
> +
> + if (intel_context_lock_pinned(ce))
> + return -EINTR;
> +
> + if (intel_context_is_pinned(ce)) {
> + err = -EBUSY; /* In active use, come back later! */
> + goto unlock;
> + }
> +
> + if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
> + struct intel_ring *ring;
> +
> + /* Replace the existing ringbuffer */
> + ring = intel_engine_create_ring(ce->engine,
> + (unsigned long)sz);
> + if (IS_ERR(ring)) {
> + err = PTR_ERR(ring);
> + goto unlock;
> + }
> +
> + intel_ring_put(ce->ring);
> + ce->ring = ring;
> +
> + /* Context image will be updated on next pin */
> + } else {
> + ce->ring = sz;
> + }
> +
> +unlock:
> + intel_context_unlock_pinned(ce);
> + return err;
> +}
I'm wondering if this function (and __get_ringsize() below as well), with its
dependency on intel_context internals, especially on that dual meaning of
ce->ring which depends on (ce->flags & CONTEXT_ALLOC_BIT), would better fit
into drivers/gpu/drm/i915/gt/intel_context.c.
> +
> +static int set_ringsize(struct i915_gem_context *ctx,
> + struct drm_i915_gem_context_param *args)
> +{
> + if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915))
> + return -ENODEV;
> +
> + if (args->size)
> + return -EINVAL;
> +
> + if (!IS_ALIGNED(args->value, I915_GTT_PAGE_SIZE))
> + return -EINVAL;
> +
> + if (args->value < I915_GTT_PAGE_SIZE)
> + return -EINVAL;
> +
> + if (args->value > 128 * I915_GTT_PAGE_SIZE)
> + return -EINVAL;
> +
> + return context_apply_all(ctx,
> + __apply_ringsize,
> + __intel_context_ring_size(args->value));
> +}
> +
> +static int __get_ringsize(struct intel_context *ce, void *arg)
> +{
> + int num_pages;
> +
> + if (intel_context_lock_pinned(ce))
> + return -EINTR;
> +
> + if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags))
> + num_pages = ce->ring->size / I915_GTT_PAGE_SIZE;
> + else
> + num_pages = (uintptr_t)ce->ring / I915_GTT_PAGE_SIZE;
> +
> + intel_context_unlock_pinned(ce);
> + return num_pages; /* stop on first engine */
Location of this comment seems not perfect to me as it is not quite obvious
how that works without examining how this function is used, but having spent a
while looking around, I'm not able to suggest a better place.
> +}
> +
> +static int get_ringsize(struct i915_gem_context *ctx,
> + struct drm_i915_gem_context_param *args)
> +{
> + int num_pages;
> +
> + if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915))
> + return -ENODEV;
> +
> + if (args->size)
> + return -EINVAL;
> +
> + num_pages = context_apply_all(ctx, __get_ringsize, NULL);
> + if (num_pages < 0)
> + return num_pages;
> +
> + args->value = (u64)num_pages * I915_GTT_PAGE_SIZE;
Do you convert to num_pages inside __get_ringsize() then back to size in bytes
to avoid an overflow? Or any other reason? Something that may be useful in
the future?
> + return 0;
> +}
> +
> static int gen8_emit_rpcs_config(struct i915_request *rq,
> struct intel_context *ce,
> struct intel_sseu sseu)
> @@ -1935,6 +2041,10 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
> ret = set_persistence(ctx, args);
> break;
>
> + case I915_CONTEXT_PARAM_RINGSIZE:
> + ret = set_ringsize(ctx, args);
> + break;
> +
> case I915_CONTEXT_PARAM_BAN_PERIOD:
> default:
> ret = -EINVAL;
> @@ -2003,6 +2113,19 @@ static int clone_engines(struct i915_gem_context *dst,
> __free_engines(clone, n);
> goto err_unlock;
> }
> +
> + /* Copy across the preferred ringsize */
> + clone->engines[n]->ring = e->engines[n]->ring;
> + if (test_bit(CONTEXT_ALLOC_BIT, &e->engines[n]->flags)) {
> + if (intel_context_lock_pinned(e->engines[n])) {
> + __free_engines(clone, n + 1);
> + goto err_unlock;
> + }
> +
> + clone->engines[n]->ring =
> + __intel_context_ring_size(e->engines[n]->ring->size);
> + intel_context_unlock_pinned(e->engines[n]);
> + }
Another candidate for a helper located in
drivers/gpu/drm/i915/gt/intel_context.c?
> }
> clone->num_engines = n;
>
> @@ -2366,6 +2489,10 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
> args->value = i915_gem_context_is_persistent(ctx);
> break;
>
> + case I915_CONTEXT_PARAM_RINGSIZE:
> + ret = get_ringsize(ctx, args);
> + break;
> +
> case I915_CONTEXT_PARAM_BAN_PERIOD:
> default:
> ret = -EINVAL;
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 33ce258d484f..2649690a951e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2417,6 +2417,7 @@ __execlists_update_reg_state(const struct intel_context *ce,
> regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
> regs[CTX_RING_HEAD] = ring->head;
> regs[CTX_RING_TAIL] = ring->tail;
> + regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
>
> /* RPCS */
> if (engine->class == RENDER_CLASS) {
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 5400d7e057f1..ae7cd681b075 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1587,6 +1587,25 @@ struct drm_i915_gem_context_param {
> * By default, new contexts allow persistence.
> */
> #define I915_CONTEXT_PARAM_PERSISTENCE 0xb
> +
> +/*
> + * I915_CONTEXT_PARAM_RINGSIZE:
> + *
> + * Sets the size of the CS ringbuffer to use for logical ring contexts. This
> + * applies a limit of how many batches can be queued to HW before the caller
> + * is blocked due to lack of space for more commands.
> + *
> + * Only reliably possible to be set prior to first use, i.e. during
> + * construction. At any later point, the current execution must be flushed as
> + * the ring can only be changed while the context is idle.
> + *
> + * Only applies to the current set of engine and lost when those engines
> + * are replaced by a new mapping (see I915_CONTEXT_PARAM_ENGINES).
> + *
> + * Must be between 4 - 512 KiB, in intervals of page size [4 KiB].
> + * Default is 16 KiB.
> + */
> +#define I915_CONTEXT_PARAM_RINGSIZE 0xc
I know it looked like that already before, but having other documented flags
separated by blank lines from each other, Is there any reason for not putting
another blank line after the last one?
> /* Must be kept compact -- no holes and well documented */
>
> __u64 value;
>
None of the above comments are essential so with or without them addressed:
Reviewed-by: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
Thanks,
Janusz
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915: Allow userspace to specify ringsize on construction
@ 2019-11-18 11:14 ` Janusz Krzysztofik
0 siblings, 0 replies; 18+ messages in thread
From: Janusz Krzysztofik @ 2019-11-18 11:14 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
Hi Chris,
Only some minor comments from me, mostly out of my curiosity.
On Friday, November 15, 2019 5:05:45 PM CET Chris Wilson wrote:
> No good reason why we must always use a static ringsize, so let
> userspace select one during construction.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 139 +++++++++++++++++++-
> drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
> include/uapi/drm/i915_drm.h | 19 +++
> 3 files changed, 153 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index 1284f47303fa..ee9a4634fed8 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -597,23 +597,30 @@ __create_context(struct drm_i915_private *i915)
> return ERR_PTR(err);
> }
>
> -static void
> +static int
> context_apply_all(struct i915_gem_context *ctx,
> - void (*fn)(struct intel_context *ce, void *data),
> + int (*fn)(struct intel_context *ce, void *data),
> void *data)
> {
> struct i915_gem_engines_iter it;
> struct intel_context *ce;
> + int err = 0;
>
> - for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it)
> - fn(ce, data);
> + for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
> + err = fn(ce, data);
> + if (err)
> + break;
> + }
> i915_gem_context_unlock_engines(ctx);
> +
> + return err;
> }
>
> -static void __apply_ppgtt(struct intel_context *ce, void *vm)
> +static int __apply_ppgtt(struct intel_context *ce, void *vm)
> {
> i915_vm_put(ce->vm);
> ce->vm = i915_vm_get(vm);
> + return 0;
> }
>
> static struct i915_address_space *
> @@ -651,9 +658,10 @@ static void __set_timeline(struct intel_timeline **dst,
> intel_timeline_put(old);
> }
>
> -static void __apply_timeline(struct intel_context *ce, void *timeline)
> +static int __apply_timeline(struct intel_context *ce, void *timeline)
> {
> __set_timeline(&ce->timeline, timeline);
> + return 0;
> }
>
> static void __assign_timeline(struct i915_gem_context *ctx,
> @@ -1223,6 +1231,104 @@ static int set_ppgtt(struct drm_i915_file_private *file_priv,
> return err;
> }
>
> +static int __apply_ringsize(struct intel_context *ce, void *sz)
> +{
> + int err;
> +
> + err = i915_active_wait(&ce->active);
> + if (err < 0)
> + return err;
> +
> + if (intel_context_lock_pinned(ce))
> + return -EINTR;
> +
> + if (intel_context_is_pinned(ce)) {
> + err = -EBUSY; /* In active use, come back later! */
> + goto unlock;
> + }
> +
> + if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
> + struct intel_ring *ring;
> +
> + /* Replace the existing ringbuffer */
> + ring = intel_engine_create_ring(ce->engine,
> + (unsigned long)sz);
> + if (IS_ERR(ring)) {
> + err = PTR_ERR(ring);
> + goto unlock;
> + }
> +
> + intel_ring_put(ce->ring);
> + ce->ring = ring;
> +
> + /* Context image will be updated on next pin */
> + } else {
> + ce->ring = sz;
> + }
> +
> +unlock:
> + intel_context_unlock_pinned(ce);
> + return err;
> +}
I'm wondering if this function (and __get_ringsize() below as well), with its
dependency on intel_context internals, especially on that dual meaning of
ce->ring which depends on (ce->flags & CONTEXT_ALLOC_BIT), would better fit
into drivers/gpu/drm/i915/gt/intel_context.c.
> +
> +static int set_ringsize(struct i915_gem_context *ctx,
> + struct drm_i915_gem_context_param *args)
> +{
> + if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915))
> + return -ENODEV;
> +
> + if (args->size)
> + return -EINVAL;
> +
> + if (!IS_ALIGNED(args->value, I915_GTT_PAGE_SIZE))
> + return -EINVAL;
> +
> + if (args->value < I915_GTT_PAGE_SIZE)
> + return -EINVAL;
> +
> + if (args->value > 128 * I915_GTT_PAGE_SIZE)
> + return -EINVAL;
> +
> + return context_apply_all(ctx,
> + __apply_ringsize,
> + __intel_context_ring_size(args->value));
> +}
> +
> +static int __get_ringsize(struct intel_context *ce, void *arg)
> +{
> + int num_pages;
> +
> + if (intel_context_lock_pinned(ce))
> + return -EINTR;
> +
> + if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags))
> + num_pages = ce->ring->size / I915_GTT_PAGE_SIZE;
> + else
> + num_pages = (uintptr_t)ce->ring / I915_GTT_PAGE_SIZE;
> +
> + intel_context_unlock_pinned(ce);
> + return num_pages; /* stop on first engine */
Location of this comment seems not perfect to me as it is not quite obvious
how that works without examining how this function is used, but having spent a
while looking around, I'm not able to suggest a better place.
> +}
> +
> +static int get_ringsize(struct i915_gem_context *ctx,
> + struct drm_i915_gem_context_param *args)
> +{
> + int num_pages;
> +
> + if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915))
> + return -ENODEV;
> +
> + if (args->size)
> + return -EINVAL;
> +
> + num_pages = context_apply_all(ctx, __get_ringsize, NULL);
> + if (num_pages < 0)
> + return num_pages;
> +
> + args->value = (u64)num_pages * I915_GTT_PAGE_SIZE;
Do you convert to num_pages inside __get_ringsize() then back to size in bytes
to avoid an overflow? Or any other reason? Something that may be useful in
the future?
> + return 0;
> +}
> +
> static int gen8_emit_rpcs_config(struct i915_request *rq,
> struct intel_context *ce,
> struct intel_sseu sseu)
> @@ -1935,6 +2041,10 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
> ret = set_persistence(ctx, args);
> break;
>
> + case I915_CONTEXT_PARAM_RINGSIZE:
> + ret = set_ringsize(ctx, args);
> + break;
> +
> case I915_CONTEXT_PARAM_BAN_PERIOD:
> default:
> ret = -EINVAL;
> @@ -2003,6 +2113,19 @@ static int clone_engines(struct i915_gem_context *dst,
> __free_engines(clone, n);
> goto err_unlock;
> }
> +
> + /* Copy across the preferred ringsize */
> + clone->engines[n]->ring = e->engines[n]->ring;
> + if (test_bit(CONTEXT_ALLOC_BIT, &e->engines[n]->flags)) {
> + if (intel_context_lock_pinned(e->engines[n])) {
> + __free_engines(clone, n + 1);
> + goto err_unlock;
> + }
> +
> + clone->engines[n]->ring =
> + __intel_context_ring_size(e->engines[n]->ring->size);
> + intel_context_unlock_pinned(e->engines[n]);
> + }
Another candidate for a helper located in
drivers/gpu/drm/i915/gt/intel_context.c?
> }
> clone->num_engines = n;
>
> @@ -2366,6 +2489,10 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
> args->value = i915_gem_context_is_persistent(ctx);
> break;
>
> + case I915_CONTEXT_PARAM_RINGSIZE:
> + ret = get_ringsize(ctx, args);
> + break;
> +
> case I915_CONTEXT_PARAM_BAN_PERIOD:
> default:
> ret = -EINVAL;
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 33ce258d484f..2649690a951e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2417,6 +2417,7 @@ __execlists_update_reg_state(const struct intel_context *ce,
> regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
> regs[CTX_RING_HEAD] = ring->head;
> regs[CTX_RING_TAIL] = ring->tail;
> + regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
>
> /* RPCS */
> if (engine->class == RENDER_CLASS) {
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 5400d7e057f1..ae7cd681b075 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1587,6 +1587,25 @@ struct drm_i915_gem_context_param {
> * By default, new contexts allow persistence.
> */
> #define I915_CONTEXT_PARAM_PERSISTENCE 0xb
> +
> +/*
> + * I915_CONTEXT_PARAM_RINGSIZE:
> + *
> + * Sets the size of the CS ringbuffer to use for logical ring contexts. This
> + * applies a limit of how many batches can be queued to HW before the caller
> + * is blocked due to lack of space for more commands.
> + *
> + * Only reliably possible to be set prior to first use, i.e. during
> + * construction. At any later point, the current execution must be flushed as
> + * the ring can only be changed while the context is idle.
> + *
> + * Only applies to the current set of engine and lost when those engines
> + * are replaced by a new mapping (see I915_CONTEXT_PARAM_ENGINES).
> + *
> + * Must be between 4 - 512 KiB, in intervals of page size [4 KiB].
> + * Default is 16 KiB.
> + */
> +#define I915_CONTEXT_PARAM_RINGSIZE 0xc
I know it looked like that already before, but having other documented flags
separated by blank lines from each other, Is there any reason for not putting
another blank line after the last one?
> /* Must be kept compact -- no holes and well documented */
>
> __u64 value;
>
None of the above comments are essential so with or without them addressed:
Reviewed-by: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
Thanks,
Janusz
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/3] drm/i915: Allow userspace to specify ringsize on construction
@ 2019-11-18 11:28 ` Chris Wilson
0 siblings, 0 replies; 18+ messages in thread
From: Chris Wilson @ 2019-11-18 11:28 UTC (permalink / raw)
To: Janusz Krzysztofik; +Cc: intel-gfx
Quoting Janusz Krzysztofik (2019-11-18 11:14:12)
> Hi Chris,
>
> Only some minor comments from me, mostly out of my curiosity.
>
> On Friday, November 15, 2019 5:05:45 PM CET Chris Wilson wrote:
> > No good reason why we must always use a static ringsize, so let
> > userspace select one during construction.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > ---
> > +static int __apply_ringsize(struct intel_context *ce, void *sz)
> > +{
> > + int err;
> > +
> > + err = i915_active_wait(&ce->active);
> > + if (err < 0)
> > + return err;
> > +
> > + if (intel_context_lock_pinned(ce))
> > + return -EINTR;
> > +
> > + if (intel_context_is_pinned(ce)) {
> > + err = -EBUSY; /* In active use, come back later! */
> > + goto unlock;
> > + }
> > +
> > + if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
> > + struct intel_ring *ring;
> > +
> > + /* Replace the existing ringbuffer */
> > + ring = intel_engine_create_ring(ce->engine,
> > + (unsigned long)sz);
> > + if (IS_ERR(ring)) {
> > + err = PTR_ERR(ring);
> > + goto unlock;
> > + }
> > +
> > + intel_ring_put(ce->ring);
> > + ce->ring = ring;
> > +
> > + /* Context image will be updated on next pin */
> > + } else {
> > + ce->ring = sz;
> > + }
> > +
> > +unlock:
> > + intel_context_unlock_pinned(ce);
> > + return err;
> > +}
>
> I'm wondering if this function (and __get_ringsize() below as well), with its
> dependency on intel_context internals, especially on that dual meaning of
> ce->ring which depends on (ce->flags & CONTEXT_ALLOC_BIT), would better fit
> into drivers/gpu/drm/i915/gt/intel_context.c.
Possibly, but at the same time it's currently only implementing a
feature of the GEM context.
I hear you, I'm just resisting, mainly because I don't want to have to
think of a good name :)
intel_context_param.c
intel_context_ring.c
I might be able to find friends for either.
> > +static int set_ringsize(struct i915_gem_context *ctx,
> > + struct drm_i915_gem_context_param *args)
> > +{
> > + if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915))
> > + return -ENODEV;
> > +
> > + if (args->size)
> > + return -EINVAL;
> > +
> > + if (!IS_ALIGNED(args->value, I915_GTT_PAGE_SIZE))
> > + return -EINVAL;
> > +
> > + if (args->value < I915_GTT_PAGE_SIZE)
> > + return -EINVAL;
> > +
> > + if (args->value > 128 * I915_GTT_PAGE_SIZE)
> > + return -EINVAL;
> > +
> > + return context_apply_all(ctx,
> > + __apply_ringsize,
> > + __intel_context_ring_size(args->value));
> > +}
> > +
> > +static int __get_ringsize(struct intel_context *ce, void *arg)
> > +{
> > + int num_pages;
> > +
> > + if (intel_context_lock_pinned(ce))
> > + return -EINTR;
> > +
> > + if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags))
> > + num_pages = ce->ring->size / I915_GTT_PAGE_SIZE;
> > + else
> > + num_pages = (uintptr_t)ce->ring / I915_GTT_PAGE_SIZE;
> > +
> > + intel_context_unlock_pinned(ce);
> > + return num_pages; /* stop on first engine */
>
> Location of this comment seems not perfect to me as it is not quite obvious
> how that works without examining how this function is used, but having spent a
> while looking around, I'm not able to suggest a better place.
Yeah, the comment is for the intent of returning the positive, so
there's definitely a case for explaining the unusual pattern here.
The calling loop is just a standard if (err) return err; propagation so
that hardly merits a long winded explanation.
> > +static int get_ringsize(struct i915_gem_context *ctx,
> > + struct drm_i915_gem_context_param *args)
> > +{
> > + int num_pages;
> > +
> > + if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915))
> > + return -ENODEV;
> > +
> > + if (args->size)
> > + return -EINVAL;
> > +
> > + num_pages = context_apply_all(ctx, __get_ringsize, NULL);
> > + if (num_pages < 0)
> > + return num_pages;
> > +
> > + args->value = (u64)num_pages * I915_GTT_PAGE_SIZE;
>
> Do you convert to num_pages inside __get_ringsize() then back to size in bytes
> to avoid an overflow? Or any other reason? Something that may be useful in
> the future?
Just being prudent in making sure we have sufficient bits across all the
type-narrowing.
> > @@ -2003,6 +2113,19 @@ static int clone_engines(struct i915_gem_context *dst,
> > __free_engines(clone, n);
> > goto err_unlock;
> > }
> > +
> > + /* Copy across the preferred ringsize */
> > + clone->engines[n]->ring = e->engines[n]->ring;
> > + if (test_bit(CONTEXT_ALLOC_BIT, &e->engines[n]->flags)) {
> > + if (intel_context_lock_pinned(e->engines[n])) {
> > + __free_engines(clone, n + 1);
> > + goto err_unlock;
> > + }
> > +
> > + clone->engines[n]->ring =
> > + __intel_context_ring_size(e->engines[n]->ring->size);
> > + intel_context_unlock_pinned(e->engines[n]);
> > + }
>
> Another candidate for a helper located in
> drivers/gpu/drm/i915/gt/intel_context.c?
This is much less of a candidate for potential reuse as I feel it is very
peculiar to the GEM->engines[], and not a fit for ugpu. At least as
currently written; an intel_context_get_ring_size() to go along with
intel_context_set_ring_size(), maybe.
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index 5400d7e057f1..ae7cd681b075 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -1587,6 +1587,25 @@ struct drm_i915_gem_context_param {
> > * By default, new contexts allow persistence.
> > */
> > #define I915_CONTEXT_PARAM_PERSISTENCE 0xb
> > +
> > +/*
> > + * I915_CONTEXT_PARAM_RINGSIZE:
> > + *
> > + * Sets the size of the CS ringbuffer to use for logical ring contexts. This
> > + * applies a limit of how many batches can be queued to HW before the caller
> > + * is blocked due to lack of space for more commands.
> > + *
> > + * Only reliably possible to be set prior to first use, i.e. during
> > + * construction. At any later point, the current execution must be flushed as
> > + * the ring can only be changed while the context is idle.
> > + *
> > + * Only applies to the current set of engine and lost when those engines
> > + * are replaced by a new mapping (see I915_CONTEXT_PARAM_ENGINES).
> > + *
> > + * Must be between 4 - 512 KiB, in intervals of page size [4 KiB].
> > + * Default is 16 KiB.
> > + */
> > +#define I915_CONTEXT_PARAM_RINGSIZE 0xc
>
> I know it looked like that already before, but having other documented flags
> separated by blank lines from each other, Is there any reason for not putting
> another blank line after the last one?
>
> > /* Must be kept compact -- no holes and well documented */
You mean before the /* Must be... */? My intent is to make it conflict
and force people to take notice of the instruction.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915: Allow userspace to specify ringsize on construction
@ 2019-11-18 11:28 ` Chris Wilson
0 siblings, 0 replies; 18+ messages in thread
From: Chris Wilson @ 2019-11-18 11:28 UTC (permalink / raw)
To: Janusz Krzysztofik; +Cc: intel-gfx
Quoting Janusz Krzysztofik (2019-11-18 11:14:12)
> Hi Chris,
>
> Only some minor comments from me, mostly out of my curiosity.
>
> On Friday, November 15, 2019 5:05:45 PM CET Chris Wilson wrote:
> > No good reason why we must always use a static ringsize, so let
> > userspace select one during construction.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > ---
> > +static int __apply_ringsize(struct intel_context *ce, void *sz)
> > +{
> > + int err;
> > +
> > + err = i915_active_wait(&ce->active);
> > + if (err < 0)
> > + return err;
> > +
> > + if (intel_context_lock_pinned(ce))
> > + return -EINTR;
> > +
> > + if (intel_context_is_pinned(ce)) {
> > + err = -EBUSY; /* In active use, come back later! */
> > + goto unlock;
> > + }
> > +
> > + if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
> > + struct intel_ring *ring;
> > +
> > + /* Replace the existing ringbuffer */
> > + ring = intel_engine_create_ring(ce->engine,
> > + (unsigned long)sz);
> > + if (IS_ERR(ring)) {
> > + err = PTR_ERR(ring);
> > + goto unlock;
> > + }
> > +
> > + intel_ring_put(ce->ring);
> > + ce->ring = ring;
> > +
> > + /* Context image will be updated on next pin */
> > + } else {
> > + ce->ring = sz;
> > + }
> > +
> > +unlock:
> > + intel_context_unlock_pinned(ce);
> > + return err;
> > +}
>
> I'm wondering if this function (and __get_ringsize() below as well), with its
> dependency on intel_context internals, especially on that dual meaning of
> ce->ring which depends on (ce->flags & CONTEXT_ALLOC_BIT), would better fit
> into drivers/gpu/drm/i915/gt/intel_context.c.
Possibly, but at the same time it's currently only implementing a
feature of the GEM context.
I hear you, I'm just resisting, mainly because I don't want to have to
think of a good name :)
intel_context_param.c
intel_context_ring.c
I might be able to find friends for either.
> > +static int set_ringsize(struct i915_gem_context *ctx,
> > + struct drm_i915_gem_context_param *args)
> > +{
> > + if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915))
> > + return -ENODEV;
> > +
> > + if (args->size)
> > + return -EINVAL;
> > +
> > + if (!IS_ALIGNED(args->value, I915_GTT_PAGE_SIZE))
> > + return -EINVAL;
> > +
> > + if (args->value < I915_GTT_PAGE_SIZE)
> > + return -EINVAL;
> > +
> > + if (args->value > 128 * I915_GTT_PAGE_SIZE)
> > + return -EINVAL;
> > +
> > + return context_apply_all(ctx,
> > + __apply_ringsize,
> > + __intel_context_ring_size(args->value));
> > +}
> > +
> > +static int __get_ringsize(struct intel_context *ce, void *arg)
> > +{
> > + int num_pages;
> > +
> > + if (intel_context_lock_pinned(ce))
> > + return -EINTR;
> > +
> > + if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags))
> > + num_pages = ce->ring->size / I915_GTT_PAGE_SIZE;
> > + else
> > + num_pages = (uintptr_t)ce->ring / I915_GTT_PAGE_SIZE;
> > +
> > + intel_context_unlock_pinned(ce);
> > + return num_pages; /* stop on first engine */
>
> Location of this comment seems not perfect to me as it is not quite obvious
> how that works without examining how this function is used, but having spent a
> while looking around, I'm not able to suggest a better place.
Yeah, the comment is for the intent of returning the positive, so
there's definitely a case for explaining the unusual pattern here.
The calling loop is just a standard if (err) return err; propagation so
that hardly merits a long winded explanation.
> > +static int get_ringsize(struct i915_gem_context *ctx,
> > + struct drm_i915_gem_context_param *args)
> > +{
> > + int num_pages;
> > +
> > + if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915))
> > + return -ENODEV;
> > +
> > + if (args->size)
> > + return -EINVAL;
> > +
> > + num_pages = context_apply_all(ctx, __get_ringsize, NULL);
> > + if (num_pages < 0)
> > + return num_pages;
> > +
> > + args->value = (u64)num_pages * I915_GTT_PAGE_SIZE;
>
> Do you convert to num_pages inside __get_ringsize() then back to size in bytes
> to avoid an overflow? Or any other reason? Something that may be useful in
> the future?
Just being prudent in making sure we have sufficient bits across all the
type-narrowing.
> > @@ -2003,6 +2113,19 @@ static int clone_engines(struct i915_gem_context *dst,
> > __free_engines(clone, n);
> > goto err_unlock;
> > }
> > +
> > + /* Copy across the preferred ringsize */
> > + clone->engines[n]->ring = e->engines[n]->ring;
> > + if (test_bit(CONTEXT_ALLOC_BIT, &e->engines[n]->flags)) {
> > + if (intel_context_lock_pinned(e->engines[n])) {
> > + __free_engines(clone, n + 1);
> > + goto err_unlock;
> > + }
> > +
> > + clone->engines[n]->ring =
> > + __intel_context_ring_size(e->engines[n]->ring->size);
> > + intel_context_unlock_pinned(e->engines[n]);
> > + }
>
> Another candidate for a helper located in
> drivers/gpu/drm/i915/gt/intel_context.c?
This is much less of a candidate for potential reuse as I feel it is very
peculiar to the GEM->engines[], and not a fit for ugpu. At least as
currently written; an intel_context_get_ring_size() to go along with
intel_context_set_ring_size(), maybe.
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index 5400d7e057f1..ae7cd681b075 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -1587,6 +1587,25 @@ struct drm_i915_gem_context_param {
> > * By default, new contexts allow persistence.
> > */
> > #define I915_CONTEXT_PARAM_PERSISTENCE 0xb
> > +
> > +/*
> > + * I915_CONTEXT_PARAM_RINGSIZE:
> > + *
> > + * Sets the size of the CS ringbuffer to use for logical ring contexts. This
> > + * applies a limit of how many batches can be queued to HW before the caller
> > + * is blocked due to lack of space for more commands.
> > + *
> > + * Only reliably possible to be set prior to first use, i.e. during
> > + * construction. At any later point, the current execution must be flushed as
> > + * the ring can only be changed while the context is idle.
> > + *
> > + * Only applies to the current set of engine and lost when those engines
> > + * are replaced by a new mapping (see I915_CONTEXT_PARAM_ENGINES).
> > + *
> > + * Must be between 4 - 512 KiB, in intervals of page size [4 KiB].
> > + * Default is 16 KiB.
> > + */
> > +#define I915_CONTEXT_PARAM_RINGSIZE 0xc
>
> I know it looked like that already before, but having other documented flags
> separated by blank lines from each other, Is there any reason for not putting
> another blank line after the last one?
>
> > /* Must be kept compact -- no holes and well documented */
You mean before the /* Must be... */? My intent is to make it conflict
and force people to take notice of the instruction.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/3] drm/i915: Allow userspace to specify ringsize on construction
@ 2019-11-25 10:05 ` Chris Wilson
0 siblings, 0 replies; 18+ messages in thread
From: Chris Wilson @ 2019-11-25 10:05 UTC (permalink / raw)
To: intel-gfx
Quoting Chris Wilson (2019-11-15 16:05:45)
> No good reason why we must always use a static ringsize, so let
> userspace select one during construction.
Do we have any news on whether userspace has materialised for this yet?
It's literally just
--- a/runtime/os_interface/linux/drm_neo.cpp
+++ b/runtime/os_interface/linux/drm_neo.cpp
@@ -182,6 +182,15 @@ void setNonPersistent(uint32_t drmContextId) {
ioctl(DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &gcp);
}
+void setMaxRingSize(uint32_t drmContextId) {
+ drm_i915_gem_context_param gcp = {};
+ gcp.ctx_id = drmContextId;
+ gcp.param = 0xc; /* I915_CONTEXT_PARAM_RINGSIZE; */
+ gcp.value = 128 << 12; /* maximum ring size is 512KiB, or 128 pages */
+
+ ioctl(DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &gcp);
+}
+
uint32_t Drm::createDrmContext() {
drm_i915_gem_context_create gcc = {};
auto retVal = ioctl(DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &gcc);
@@ -190,6 +199,9 @@ uint32_t Drm::createDrmContext() {
/* enable cleanup of resources on process termination */
setNonPersistent(gcc.ctx_id);
+ /* Big rings for silly amounts of non-blocking work! */
+ setMaxRingSize(gcc.ctx_id);
with some justification.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915: Allow userspace to specify ringsize on construction
@ 2019-11-25 10:05 ` Chris Wilson
0 siblings, 0 replies; 18+ messages in thread
From: Chris Wilson @ 2019-11-25 10:05 UTC (permalink / raw)
To: intel-gfx
Quoting Chris Wilson (2019-11-15 16:05:45)
> No good reason why we must always use a static ringsize, so let
> userspace select one during construction.
Do we have any news on whether userspace has materialised for this yet?
It's literally just
--- a/runtime/os_interface/linux/drm_neo.cpp
+++ b/runtime/os_interface/linux/drm_neo.cpp
@@ -182,6 +182,15 @@ void setNonPersistent(uint32_t drmContextId) {
ioctl(DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &gcp);
}
+void setMaxRingSize(uint32_t drmContextId) {
+ drm_i915_gem_context_param gcp = {};
+ gcp.ctx_id = drmContextId;
+ gcp.param = 0xc; /* I915_CONTEXT_PARAM_RINGSIZE; */
+ gcp.value = 128 << 12; /* maximum ring size is 512KiB, or 128 pages */
+
+ ioctl(DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &gcp);
+}
+
uint32_t Drm::createDrmContext() {
drm_i915_gem_context_create gcc = {};
auto retVal = ioctl(DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &gcc);
@@ -190,6 +199,9 @@ uint32_t Drm::createDrmContext() {
/* enable cleanup of resources on process termination */
setNonPersistent(gcc.ctx_id);
+ /* Big rings for silly amounts of non-blocking work! */
+ setMaxRingSize(gcc.ctx_id);
with some justification.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✗ Fi.CI.BUILD: failure for series starting with [1/3] drm/i915: Flush idle barriers when waiting (rev2)
@ 2019-11-25 12:18 ` Patchwork
0 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2019-11-25 12:18 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915: Flush idle barriers when waiting (rev2)
URL : https://patchwork.freedesktop.org/series/69546/
State : failure
== Summary ==
Applying: drm/i915: Flush idle barriers when waiting
Applying: drm/i915: Allow userspace to specify ringsize on construction
error: corrupt patch at line 26
error: could not build fake ancestor
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0002 drm/i915: Allow userspace to specify ringsize on construction
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/3] drm/i915: Flush idle barriers when waiting (rev2)
@ 2019-11-25 12:18 ` Patchwork
0 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2019-11-25 12:18 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915: Flush idle barriers when waiting (rev2)
URL : https://patchwork.freedesktop.org/series/69546/
State : failure
== Summary ==
Applying: drm/i915: Flush idle barriers when waiting
Applying: drm/i915: Allow userspace to specify ringsize on construction
error: corrupt patch at line 26
error: could not build fake ancestor
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0002 drm/i915: Allow userspace to specify ringsize on construction
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2019-11-25 12:18 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-15 16:05 [PATCH 1/3] drm/i915: Flush idle barriers when waiting Chris Wilson
2019-11-15 16:05 ` [Intel-gfx] " Chris Wilson
2019-11-15 16:05 ` [PATCH 2/3] drm/i915: Allow userspace to specify ringsize on construction Chris Wilson
2019-11-15 16:05 ` [Intel-gfx] " Chris Wilson
2019-11-18 11:14 ` Janusz Krzysztofik
2019-11-18 11:14 ` [Intel-gfx] " Janusz Krzysztofik
2019-11-18 11:28 ` Chris Wilson
2019-11-18 11:28 ` [Intel-gfx] " Chris Wilson
2019-11-25 10:05 ` Chris Wilson
2019-11-25 10:05 ` [Intel-gfx] " Chris Wilson
2019-11-15 16:05 ` [PATCH 3/3] drm/i915/gem: Honour O_NONBLOCK before throttling execbuf submissions Chris Wilson
2019-11-15 16:05 ` [Intel-gfx] " Chris Wilson
2019-11-15 20:56 ` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Flush idle barriers when waiting Patchwork
2019-11-15 20:56 ` [Intel-gfx] " Patchwork
2019-11-17 9:27 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-11-17 9:27 ` [Intel-gfx] " Patchwork
2019-11-25 12:18 ` ✗ Fi.CI.BUILD: failure for series starting with [1/3] drm/i915: Flush idle barriers when waiting (rev2) Patchwork
2019-11-25 12:18 ` [Intel-gfx] " Patchwork
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