From: Radhakrishna Sripada <radhakrishna.sripada@intel.com> To: intel-gfx@lists.freedesktop.org Cc: nanley.g.chery@intel.com, dhinakaran.pandiyan@intel.com, ville.syrjala@intel.com Subject: [PATCH v7 3/7] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment Date: Mon, 25 Nov 2019 16:26:31 -0800 [thread overview] Message-ID: <20191126002635.5779-4-radhakrishna.sripada@intel.com> (raw) In-Reply-To: <20191126002635.5779-1-radhakrishna.sripada@intel.com> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Easier to read if all the alignment changes are in one place and contained within a function. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 31 ++++++++++---------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 2a4593afbe86..85f009500344 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2611,7 +2611,22 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) else return 64; } else { - return intel_tile_width_bytes(fb, color_plane); + u32 tile_width = intel_tile_width_bytes(fb, color_plane); + + /* + * Display WA #0531: skl,bxt,kbl,glk + * + * Render decompression and plane width > 3840 + * combined with horizontal panning requires the + * plane stride to be a multiple of 4. We'll just + * require the entire fb to accommodate that to avoid + * potential runtime errors at plane configuration time. + */ + if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) && + color_plane == 0 && fb->width > 3840) + tile_width *= 4; + + return tile_width; } } @@ -16463,20 +16478,6 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, } stride_alignment = intel_fb_stride_alignment(fb, i); - - /* - * Display WA #0531: skl,bxt,kbl,glk - * - * Render decompression and plane width > 3840 - * combined with horizontal panning requires the - * plane stride to be a multiple of 4. We'll just - * require the entire fb to accommodate that to avoid - * potential runtime errors at plane configuration time. - */ - if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 && - is_ccs_modifier(fb->modifier)) - stride_alignment *= 4; - if (fb->pitches[i] & (stride_alignment - 1)) { DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n", i, fb->pitches[i], stride_alignment); -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com> To: intel-gfx@lists.freedesktop.org Cc: nanley.g.chery@intel.com, dhinakaran.pandiyan@intel.com, ville.syrjala@intel.com Subject: [Intel-gfx] [PATCH v7 3/7] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment Date: Mon, 25 Nov 2019 16:26:31 -0800 [thread overview] Message-ID: <20191126002635.5779-4-radhakrishna.sripada@intel.com> (raw) Message-ID: <20191126002631.iloIwFHEWFp7sDyejn7P35EgR1SYWCW1g5j1JJwm6yA@z> (raw) In-Reply-To: <20191126002635.5779-1-radhakrishna.sripada@intel.com> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Easier to read if all the alignment changes are in one place and contained within a function. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 31 ++++++++++---------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 2a4593afbe86..85f009500344 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2611,7 +2611,22 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) else return 64; } else { - return intel_tile_width_bytes(fb, color_plane); + u32 tile_width = intel_tile_width_bytes(fb, color_plane); + + /* + * Display WA #0531: skl,bxt,kbl,glk + * + * Render decompression and plane width > 3840 + * combined with horizontal panning requires the + * plane stride to be a multiple of 4. We'll just + * require the entire fb to accommodate that to avoid + * potential runtime errors at plane configuration time. + */ + if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) && + color_plane == 0 && fb->width > 3840) + tile_width *= 4; + + return tile_width; } } @@ -16463,20 +16478,6 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, } stride_alignment = intel_fb_stride_alignment(fb, i); - - /* - * Display WA #0531: skl,bxt,kbl,glk - * - * Render decompression and plane width > 3840 - * combined with horizontal panning requires the - * plane stride to be a multiple of 4. We'll just - * require the entire fb to accommodate that to avoid - * potential runtime errors at plane configuration time. - */ - if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 && - is_ccs_modifier(fb->modifier)) - stride_alignment *= 4; - if (fb->pitches[i] & (stride_alignment - 1)) { DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n", i, fb->pitches[i], stride_alignment); -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-11-26 0:25 UTC|newest] Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-26 0:26 [PATCH v7 0/7] Clear Color Support for TGL Render Decompression Radhakrishna Sripada 2019-11-26 0:26 ` [Intel-gfx] " Radhakrishna Sripada 2019-11-26 0:26 ` [PATCH v7 1/7] drm/framebuffer: Format modifier for Intel Gen-12 render compression Radhakrishna Sripada 2019-11-26 0:26 ` [Intel-gfx] " Radhakrishna Sripada 2019-12-12 15:49 ` Radhakrishna Sripada 2019-11-26 0:26 ` [PATCH v7 2/7] drm/i915: Use intel_tile_height() instead of re-implementing Radhakrishna Sripada 2019-11-26 0:26 ` [Intel-gfx] " Radhakrishna Sripada 2019-12-12 15:51 ` Radhakrishna Sripada 2019-11-26 0:26 ` Radhakrishna Sripada [this message] 2019-11-26 0:26 ` [Intel-gfx] [PATCH v7 3/7] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment Radhakrishna Sripada 2019-12-12 15:53 ` Radhakrishna Sripada 2019-11-26 0:26 ` [PATCH v7 4/7] drm/i915/tgl: Gen-12 render decompression Radhakrishna Sripada 2019-11-26 0:26 ` [Intel-gfx] " Radhakrishna Sripada 2019-12-12 15:59 ` Radhakrishna Sripada 2019-11-26 0:26 ` [PATCH v7 5/7] drm/i915: Extract framebufer CCS offset checks into a function Radhakrishna Sripada 2019-11-26 0:26 ` [Intel-gfx] " Radhakrishna Sripada 2019-12-12 16:00 ` Radhakrishna Sripada 2019-11-26 0:26 ` [PATCH v7 6/7] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color Radhakrishna Sripada 2019-11-26 0:26 ` [Intel-gfx] " Radhakrishna Sripada 2019-11-26 0:26 ` [PATCH v7 7/7] drm/i915/tgl: Add Clear Color support for TGL Render Decompression Radhakrishna Sripada 2019-11-26 0:26 ` [Intel-gfx] " Radhakrishna Sripada 2019-11-26 20:48 ` Matt Roper 2019-11-26 20:48 ` [Intel-gfx] " Matt Roper 2019-11-26 21:52 ` Sripada, Radhakrishna 2019-11-26 21:52 ` [Intel-gfx] " Sripada, Radhakrishna 2019-11-26 22:00 ` Matt Roper 2019-11-26 22:00 ` [Intel-gfx] " Matt Roper 2019-11-26 22:29 ` Sripada, Radhakrishna 2019-11-26 22:29 ` [Intel-gfx] " Sripada, Radhakrishna 2019-11-27 6:49 ` Saarinen, Jani 2019-11-27 6:49 ` [Intel-gfx] " Saarinen, Jani 2019-11-27 0:26 ` [PATCH v8 " Radhakrishna Sripada 2019-11-27 0:26 ` [Intel-gfx] " Radhakrishna Sripada 2019-11-26 0:34 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev10) Patchwork 2019-11-26 0:34 ` [Intel-gfx] " Patchwork 2019-11-26 0:57 ` ✓ Fi.CI.BAT: success " Patchwork 2019-11-26 0:57 ` [Intel-gfx] " Patchwork 2019-11-27 2:39 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev11) Patchwork 2019-11-27 2:39 ` [Intel-gfx] " Patchwork 2019-11-27 3:03 ` ✓ Fi.CI.BAT: success " Patchwork 2019-11-27 3:03 ` [Intel-gfx] " Patchwork 2019-11-27 13:55 ` ✗ Fi.CI.IGT: failure " Patchwork 2019-11-27 13:55 ` [Intel-gfx] " Patchwork 2019-12-03 21:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev12) Patchwork 2019-12-03 21:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20191126002635.5779-4-radhakrishna.sripada@intel.com \ --to=radhakrishna.sripada@intel.com \ --cc=dhinakaran.pandiyan@intel.com \ --cc=intel-gfx@lists.freedesktop.org \ --cc=nanley.g.chery@intel.com \ --cc=ville.syrjala@intel.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.