From: Radhakrishna Sripada <radhakrishna.sripada@intel.com> To: intel-gfx@lists.freedesktop.org Cc: nanley.g.chery@intel.com, dhinakaran.pandiyan@intel.com, Kalyan Kondapally <kalyan.kondapally@intel.com>, ville.syrjala@intel.com Subject: [PATCH v7 6/7] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color Date: Mon, 25 Nov 2019 16:26:34 -0800 [thread overview] Message-ID: <20191126002635.5779-7-radhakrishna.sripada@intel.com> (raw) In-Reply-To: <20191126002635.5779-1-radhakrishna.sripada@intel.com> Gen12 display can decompress surfaces compressed by render engine with Clear Color, add a new modifier as the driver needs to know the surface was compressed by render engine. V2: Description changes as suggested by Rafael. V3: Mention the Clear Color size of 64 bits in the comments(DK) v4: Fix trailing whitespaces v5: Explain Clear Color in the documentation. v6: Documentation Nitpicks(Nanley) v7: Remove ambiguity in Clear Color structue explanation(Nanley) Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Kalyan Kondapally <kalyan.kondapally@intel.com> Cc: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> --- include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 5ba481f49931..c95dd3c40636 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -421,6 +421,25 @@ extern "C" { */ #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) +/* + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render + * compression. + * + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear + * and at index 1. The clear color is stored at index 2, and the pitch should + * be ignored. The clear color structure is 256 bits. The first 128 bits + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented + * by 32 bits. The 3D engine can use the raw clear color and the surface format + * to generate a converted clear color of size 64 bits. The first 32 bits store + * the Lower Converted Clear Color value and the next 32 bits store the Higher + * Converted Clear Color value when applicable. The Converted Clear Color values + * are consumed by the DE. The last 64 bits are used to store Color Discard + * Enable and Depth Clear Value Valid which are ignored by the DE. A CCS cache + * line corresponds to an area of 4x1 tiles in the main surface. The main + * surface pitch is required to be a multiple of 4 tile widths. + */ +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) + /* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks * -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com> To: intel-gfx@lists.freedesktop.org Cc: nanley.g.chery@intel.com, dhinakaran.pandiyan@intel.com, Kalyan Kondapally <kalyan.kondapally@intel.com>, ville.syrjala@intel.com Subject: [Intel-gfx] [PATCH v7 6/7] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color Date: Mon, 25 Nov 2019 16:26:34 -0800 [thread overview] Message-ID: <20191126002635.5779-7-radhakrishna.sripada@intel.com> (raw) Message-ID: <20191126002634.LPjglOCdOjfdbFn76eViy8PlqEe6FisWsglCGfJC2HI@z> (raw) In-Reply-To: <20191126002635.5779-1-radhakrishna.sripada@intel.com> Gen12 display can decompress surfaces compressed by render engine with Clear Color, add a new modifier as the driver needs to know the surface was compressed by render engine. V2: Description changes as suggested by Rafael. V3: Mention the Clear Color size of 64 bits in the comments(DK) v4: Fix trailing whitespaces v5: Explain Clear Color in the documentation. v6: Documentation Nitpicks(Nanley) v7: Remove ambiguity in Clear Color structue explanation(Nanley) Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Kalyan Kondapally <kalyan.kondapally@intel.com> Cc: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> --- include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 5ba481f49931..c95dd3c40636 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -421,6 +421,25 @@ extern "C" { */ #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) +/* + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render + * compression. + * + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear + * and at index 1. The clear color is stored at index 2, and the pitch should + * be ignored. The clear color structure is 256 bits. The first 128 bits + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented + * by 32 bits. The 3D engine can use the raw clear color and the surface format + * to generate a converted clear color of size 64 bits. The first 32 bits store + * the Lower Converted Clear Color value and the next 32 bits store the Higher + * Converted Clear Color value when applicable. The Converted Clear Color values + * are consumed by the DE. The last 64 bits are used to store Color Discard + * Enable and Depth Clear Value Valid which are ignored by the DE. A CCS cache + * line corresponds to an area of 4x1 tiles in the main surface. The main + * surface pitch is required to be a multiple of 4 tile widths. + */ +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) + /* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks * -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-11-26 0:25 UTC|newest] Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-26 0:26 [PATCH v7 0/7] Clear Color Support for TGL Render Decompression Radhakrishna Sripada 2019-11-26 0:26 ` [Intel-gfx] " Radhakrishna Sripada 2019-11-26 0:26 ` [PATCH v7 1/7] drm/framebuffer: Format modifier for Intel Gen-12 render compression Radhakrishna Sripada 2019-11-26 0:26 ` [Intel-gfx] " Radhakrishna Sripada 2019-12-12 15:49 ` Radhakrishna Sripada 2019-11-26 0:26 ` [PATCH v7 2/7] drm/i915: Use intel_tile_height() instead of re-implementing Radhakrishna Sripada 2019-11-26 0:26 ` [Intel-gfx] " Radhakrishna Sripada 2019-12-12 15:51 ` Radhakrishna Sripada 2019-11-26 0:26 ` [PATCH v7 3/7] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment Radhakrishna Sripada 2019-11-26 0:26 ` [Intel-gfx] " Radhakrishna Sripada 2019-12-12 15:53 ` Radhakrishna Sripada 2019-11-26 0:26 ` [PATCH v7 4/7] drm/i915/tgl: Gen-12 render decompression Radhakrishna Sripada 2019-11-26 0:26 ` [Intel-gfx] " Radhakrishna Sripada 2019-12-12 15:59 ` Radhakrishna Sripada 2019-11-26 0:26 ` [PATCH v7 5/7] drm/i915: Extract framebufer CCS offset checks into a function Radhakrishna Sripada 2019-11-26 0:26 ` [Intel-gfx] " Radhakrishna Sripada 2019-12-12 16:00 ` Radhakrishna Sripada 2019-11-26 0:26 ` Radhakrishna Sripada [this message] 2019-11-26 0:26 ` [Intel-gfx] [PATCH v7 6/7] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color Radhakrishna Sripada 2019-11-26 0:26 ` [PATCH v7 7/7] drm/i915/tgl: Add Clear Color support for TGL Render Decompression Radhakrishna Sripada 2019-11-26 0:26 ` [Intel-gfx] " Radhakrishna Sripada 2019-11-26 20:48 ` Matt Roper 2019-11-26 20:48 ` [Intel-gfx] " Matt Roper 2019-11-26 21:52 ` Sripada, Radhakrishna 2019-11-26 21:52 ` [Intel-gfx] " Sripada, Radhakrishna 2019-11-26 22:00 ` Matt Roper 2019-11-26 22:00 ` [Intel-gfx] " Matt Roper 2019-11-26 22:29 ` Sripada, Radhakrishna 2019-11-26 22:29 ` [Intel-gfx] " Sripada, Radhakrishna 2019-11-27 6:49 ` Saarinen, Jani 2019-11-27 6:49 ` [Intel-gfx] " Saarinen, Jani 2019-11-27 0:26 ` [PATCH v8 " Radhakrishna Sripada 2019-11-27 0:26 ` [Intel-gfx] " Radhakrishna Sripada 2019-11-26 0:34 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev10) Patchwork 2019-11-26 0:34 ` [Intel-gfx] " Patchwork 2019-11-26 0:57 ` ✓ Fi.CI.BAT: success " Patchwork 2019-11-26 0:57 ` [Intel-gfx] " Patchwork 2019-11-27 2:39 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev11) Patchwork 2019-11-27 2:39 ` [Intel-gfx] " Patchwork 2019-11-27 3:03 ` ✓ Fi.CI.BAT: success " Patchwork 2019-11-27 3:03 ` [Intel-gfx] " Patchwork 2019-11-27 13:55 ` ✗ Fi.CI.IGT: failure " Patchwork 2019-11-27 13:55 ` [Intel-gfx] " Patchwork 2019-12-03 21:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev12) Patchwork 2019-12-03 21:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
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