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From: David Gibson <david@gibson.dropbear.id.au>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org, Greg Kurz <groug@kaod.org>, qemu-devel@nongnu.org
Subject: Re: [PATCH v6 06/20] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper
Date: Wed, 27 Nov 2019 16:01:23 +1100	[thread overview]
Message-ID: <20191127050123.GO5582@umbus.fritz.box> (raw)
In-Reply-To: <20191125065820.927-7-clg@kaod.org>

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On Mon, Nov 25, 2019 at 07:58:06AM +0100, Cédric Le Goater wrote:
> and use this helper to exclude CPUs which are not enabled in the XIVE
> controller.
> 
> Signed-off-by: Cédric Le Goater <clg@kaod.org>

Applied 5..6 to ppc-for-5.0.

> ---
>  include/hw/ppc/pnv.h |  5 +++++
>  hw/intc/pnv_xive.c   | 19 +++++++++++++++++++
>  2 files changed, 24 insertions(+)
> 
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index 03cb429f2131..12b0169a4010 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -99,6 +99,11 @@ typedef struct Pnv9Chip {
>      PnvQuad      *quads;
>  } Pnv9Chip;
>  
> +/*
> + * A SMT8 fused core is a pair of SMT4 cores.
> + */
> +#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
> +
>  typedef struct PnvChipClass {
>      /*< private >*/
>      SysBusDeviceClass parent_class;
> diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
> index 9798bd9e729f..ec8349ee4a1f 100644
> --- a/hw/intc/pnv_xive.c
> +++ b/hw/intc/pnv_xive.c
> @@ -372,6 +372,21 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
>      return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas);
>  }
>  
> +/*
> + * One bit per thread id. The first register PC_THREAD_EN_REG0 covers
> + * the first cores 0-15 (normal) of the chip or 0-7 (fused). The
> + * second register covers cores 16-23 (normal) or 8-11 (fused).
> + */
> +static bool pnv_xive_is_cpu_enabled(PnvXive *xive, PowerPCCPU *cpu)
> +{
> +    int pir = ppc_cpu_pir(cpu);
> +    uint32_t fc = PNV9_PIR2FUSEDCORE(pir);
> +    uint64_t reg = fc < 8 ? PC_THREAD_EN_REG0 : PC_THREAD_EN_REG1;
> +    uint32_t bit = pir & 0x3f;
> +
> +    return xive->regs[reg >> 3] & PPC_BIT(bit);
> +}
> +
>  static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
>                                uint8_t nvt_blk, uint32_t nvt_idx,
>                                bool cam_ignore, uint8_t priority,
> @@ -391,6 +406,10 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
>              XiveTCTX *tctx;
>              int ring;
>  
> +            if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
> +                continue;
> +            }
> +
>              tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
>  
>              /*

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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  reply	other threads:[~2019-11-27  5:38 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-25  6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
2019-11-25  6:58 ` [PATCH v6 01/20] ppc/xive: Introduce a XivePresenter interface Cédric Le Goater
2019-11-25  6:58 ` [PATCH v6 02/20] ppc/xive: Implement the " Cédric Le Goater
2019-11-25  6:58 ` [PATCH v6 03/20] ppc/pnv: Instantiate cores separately Cédric Le Goater
2019-11-25  6:58 ` [PATCH v6 04/20] ppc/pnv: Loop on the threads of the chip to find a matching NVT Cédric Le Goater
2019-11-27  4:57   ` David Gibson
2019-11-25  6:58 ` [PATCH v6 05/20] ppc: Introduce a ppc_cpu_pir() helper Cédric Le Goater
2019-11-25  6:58 ` [PATCH v6 06/20] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper Cédric Le Goater
2019-11-27  5:01   ` David Gibson [this message]
2019-11-25  6:58 ` [PATCH v6 07/20] ppc/pnv: Fix TIMA indirect access Cédric Le Goater
2019-11-27  5:03   ` David Gibson
2019-11-25  6:58 ` [PATCH v6 08/20] ppc/xive: Introduce a XiveFabric interface Cédric Le Goater
2019-11-25  6:58 ` [PATCH v6 09/20] ppc/pnv: Implement the " Cédric Le Goater
2019-11-25  6:58 ` [PATCH v6 10/20] ppc/spapr: " Cédric Le Goater
2019-11-25  6:58 ` [PATCH v6 11/20] ppc/xive: Use the XiveFabric and XivePresenter interfaces Cédric Le Goater
2019-11-27  5:07   ` David Gibson
2019-11-25  6:58 ` [PATCH v6 12/20] ppc/xive: Extend the TIMA operation with a XivePresenter parameter Cédric Le Goater
2019-11-27  5:24   ` David Gibson
2019-11-25  6:58 ` [PATCH v6 13/20] ppc/pnv: Clarify how the TIMA is accessed on a multichip system Cédric Le Goater
2019-11-27  5:23   ` David Gibson
2019-11-27  6:57     ` Cédric Le Goater
2019-11-28  1:30       ` David Gibson
2019-11-25  6:58 ` [PATCH v6 14/20] ppc/xive: Move the TIMA operations to the controller model Cédric Le Goater
2019-11-25  6:58 ` [PATCH v6 15/20] ppc/xive: Remove the get_tctx() XiveRouter handler Cédric Le Goater
2019-11-28  1:32   ` David Gibson
2019-11-25  6:58 ` [PATCH v6 16/20] ppc/xive: Introduce a xive_tctx_ipb_update() helper Cédric Le Goater
2019-11-27  8:50   ` Greg Kurz
2019-11-28  1:35     ` David Gibson
2019-11-25  6:58 ` [PATCH v6 17/20] ppc/xive: Synthesize interrupt from the saved IPB in the NVT Cédric Le Goater
2019-11-25  6:58 ` [PATCH v6 18/20] ppc/pnv: Introduce a pnv_xive_block_id() helper Cédric Le Goater
2019-11-25  6:58 ` [PATCH v6 19/20] ppc/pnv: Extend XiveRouter with a get_block_id() handler Cédric Le Goater
2019-11-25  6:58 ` [PATCH v6 20/20] ppc/pnv: Dump the XIVE NVT table Cédric Le Goater
2019-11-28  2:18 ` [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests David Gibson

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