* [PATCH v6 01/20] ppc/xive: Introduce a XivePresenter interface
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
@ 2019-11-25 6:58 ` Cédric Le Goater
2019-11-25 6:58 ` [PATCH v6 02/20] ppc/xive: Implement the " Cédric Le Goater
` (19 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-25 6:58 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel
When the XIVE IVRE sub-engine (XiveRouter) looks for a Notification
Virtual Target (NVT) to notify, it broadcasts a message on the
PowerBUS to find an XIVE IVPE sub-engine (Presenter) with the NVT
dispatched on one of its HW threads, and then forwards the
notification if any response was received.
The current XIVE presenter model is sufficient for the pseries machine
because it has a single interrupt controller device, but the PowerNV
machine can have multiple chips each having its own interrupt
controller. In this case, the XIVE presenter model is too simple and
the CAM line matching should scan all chips of the system.
To start fixing this issue, we first extend the XIVE Router model with
a new XivePresenter QOM interface representing the XIVE IVPE
sub-engine. This interface exposes a 'match_nvt' handler which the
sPAPR and PowerNV XIVE Router models will need to implement to perform
the CAM line matching.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/xive.h | 32 ++++++++++++++++++++++++++++++++
hw/intc/xive.c | 26 +++++++++++++++++---------
2 files changed, 49 insertions(+), 9 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index fa7adf87feb2..f9aa0fa0dac3 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -367,6 +367,38 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs);
void xive_router_notify(XiveNotifier *xn, uint32_t lisn);
+/*
+ * XIVE Presenter
+ */
+
+typedef struct XiveTCTXMatch {
+ XiveTCTX *tctx;
+ uint8_t ring;
+} XiveTCTXMatch;
+
+typedef struct XivePresenter XivePresenter;
+
+#define TYPE_XIVE_PRESENTER "xive-presenter"
+#define XIVE_PRESENTER(obj) \
+ INTERFACE_CHECK(XivePresenter, (obj), TYPE_XIVE_PRESENTER)
+#define XIVE_PRESENTER_CLASS(klass) \
+ OBJECT_CLASS_CHECK(XivePresenterClass, (klass), TYPE_XIVE_PRESENTER)
+#define XIVE_PRESENTER_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(XivePresenterClass, (obj), TYPE_XIVE_PRESENTER)
+
+typedef struct XivePresenterClass {
+ InterfaceClass parent;
+ int (*match_nvt)(XivePresenter *xptr, uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint8_t priority,
+ uint32_t logic_serv, XiveTCTXMatch *match);
+} XivePresenterClass;
+
+int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
+ uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint32_t logic_serv);
+
/*
* XIVE END ESBs
*/
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 511e1a936347..344bb3f3bc4b 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1363,9 +1363,10 @@ static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx)
/*
* The thread context register words are in big-endian format.
*/
-static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format,
- uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint32_t logic_serv)
+int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
+ uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint32_t logic_serv)
{
uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx);
uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]);
@@ -1422,11 +1423,6 @@ static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format,
return -1;
}
-typedef struct XiveTCTXMatch {
- XiveTCTX *tctx;
- uint8_t ring;
-} XiveTCTXMatch;
-
static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint8_t priority,
@@ -1460,7 +1456,8 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
* Check the thread context CAM lines and record matches. We
* will handle CPU exception delivery later
*/
- ring = xive_presenter_tctx_match(tctx, format, nvt_blk, nvt_idx,
+ ring = xive_presenter_tctx_match(XIVE_PRESENTER(xrtr), tctx, format,
+ nvt_blk, nvt_idx,
cam_ignore, logic_serv);
/*
* Save the context and follow on to catch duplicates, that we
@@ -1754,6 +1751,7 @@ static const TypeInfo xive_router_info = {
.class_init = xive_router_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_XIVE_NOTIFIER },
+ { TYPE_XIVE_PRESENTER },
{ }
}
};
@@ -1923,10 +1921,20 @@ static const TypeInfo xive_notifier_info = {
.class_size = sizeof(XiveNotifierClass),
};
+/*
+ * XIVE Presenter
+ */
+static const TypeInfo xive_presenter_info = {
+ .name = TYPE_XIVE_PRESENTER,
+ .parent = TYPE_INTERFACE,
+ .class_size = sizeof(XivePresenterClass),
+};
+
static void xive_register_types(void)
{
type_register_static(&xive_source_info);
type_register_static(&xive_notifier_info);
+ type_register_static(&xive_presenter_info);
type_register_static(&xive_router_info);
type_register_static(&xive_end_source_info);
type_register_static(&xive_tctx_info);
--
2.21.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH v6 02/20] ppc/xive: Implement the XivePresenter interface
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
2019-11-25 6:58 ` [PATCH v6 01/20] ppc/xive: Introduce a XivePresenter interface Cédric Le Goater
@ 2019-11-25 6:58 ` Cédric Le Goater
2019-11-25 6:58 ` [PATCH v6 03/20] ppc/pnv: Instantiate cores separately Cédric Le Goater
` (18 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-25 6:58 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel
Each XIVE Router model, sPAPR and PowerNV, now implements the 'match_nvt'
handler of the XivePresenter QOM interface. This is simply moving code
and taking into account the new API.
To be noted that the xive_router_get_tctx() helper is not used anymore
when doing CAM matching and will be removed later on after other changes.
The XIVE presenter model is still too simple for the PowerNV machine
and the CAM matching algo is not correct on multichip system. Subsequent
patches will introduce more changes to scan all chips of the system.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/intc/pnv_xive.c | 41 +++++++++++++++++++++++++++++++++++
hw/intc/spapr_xive.c | 49 ++++++++++++++++++++++++++++++++++++++++++
hw/intc/xive.c | 51 ++++++--------------------------------------
3 files changed, 97 insertions(+), 44 deletions(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 9a771f640763..8055de89cf63 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -372,6 +372,45 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas);
}
+static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint8_t priority,
+ uint32_t logic_serv, XiveTCTXMatch *match)
+{
+ CPUState *cs;
+ int count = 0;
+
+ CPU_FOREACH(cs) {
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+ int ring;
+
+ /*
+ * Check the thread context CAM lines and record matches.
+ */
+ ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nvt_idx,
+ cam_ignore, logic_serv);
+ /*
+ * Save the context and follow on to catch duplicates, that we
+ * don't support yet.
+ */
+ if (ring != -1) {
+ if (match->tctx) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a "
+ "thread context NVT %x/%x\n",
+ nvt_blk, nvt_idx);
+ return -1;
+ }
+
+ match->ring = ring;
+ match->tctx = tctx;
+ count++;
+ }
+ }
+
+ return count;
+}
+
static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -1780,6 +1819,7 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data)
PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass);
XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass);
+ XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass);
xdc->dt_xscom = pnv_xive_dt_xscom;
@@ -1795,6 +1835,7 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data)
xrc->get_tctx = pnv_xive_get_tctx;
xnc->notify = pnv_xive_notify;
+ xpc->match_nvt = pnv_xive_match_nvt;
};
static const TypeInfo pnv_xive_info = {
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 729246e906c9..bb3b2dfdb77f 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -405,6 +405,52 @@ static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
return spapr_cpu_state(cpu)->tctx;
}
+static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint8_t priority,
+ uint32_t logic_serv, XiveTCTXMatch *match)
+{
+ CPUState *cs;
+ int count = 0;
+
+ CPU_FOREACH(cs) {
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx;
+ int ring;
+
+ /*
+ * Skip partially initialized vCPUs. This can happen when
+ * vCPUs are hotplugged.
+ */
+ if (!tctx) {
+ continue;
+ }
+
+ /*
+ * Check the thread context CAM lines and record matches.
+ */
+ ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nvt_idx,
+ cam_ignore, logic_serv);
+ /*
+ * Save the matching thread interrupt context and follow on to
+ * check for duplicates which are invalid.
+ */
+ if (ring != -1) {
+ if (match->tctx) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread "
+ "context NVT %x/%x\n", nvt_blk, nvt_idx);
+ return -1;
+ }
+
+ match->ring = ring;
+ match->tctx = tctx;
+ count++;
+ }
+ }
+
+ return count;
+}
+
static const VMStateDescription vmstate_spapr_xive_end = {
.name = TYPE_SPAPR_XIVE "/end",
.version_id = 1,
@@ -684,6 +730,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass);
SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass);
+ XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass);
dc->desc = "sPAPR XIVE Interrupt Controller";
dc->props = spapr_xive_properties;
@@ -708,6 +755,8 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
sicc->print_info = spapr_xive_print_info;
sicc->dt = spapr_xive_dt;
sicc->post_load = spapr_xive_post_load;
+
+ xpc->match_nvt = spapr_xive_match_nvt;
}
static const TypeInfo spapr_xive_info = {
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 344bb3f3bc4b..da6196ca958f 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1428,51 +1428,14 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
bool cam_ignore, uint8_t priority,
uint32_t logic_serv, XiveTCTXMatch *match)
{
- CPUState *cs;
+ XivePresenter *xptr = XIVE_PRESENTER(xrtr);
+ XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
+ int count;
- /*
- * TODO (PowerNV): handle chip_id overwrite of block field for
- * hardwired CAM compares
- */
-
- CPU_FOREACH(cs) {
- XiveTCTX *tctx = xive_router_get_tctx(xrtr, cs);
- int ring;
-
- /*
- * Skip partially initialized vCPUs. This can happen when
- * vCPUs are hotplugged.
- */
- if (!tctx) {
- continue;
- }
-
- /*
- * HW checks that the CPU is enabled in the Physical Thread
- * Enable Register (PTER).
- */
-
- /*
- * Check the thread context CAM lines and record matches. We
- * will handle CPU exception delivery later
- */
- ring = xive_presenter_tctx_match(XIVE_PRESENTER(xrtr), tctx, format,
- nvt_blk, nvt_idx,
- cam_ignore, logic_serv);
- /*
- * Save the context and follow on to catch duplicates, that we
- * don't support yet.
- */
- if (ring != -1) {
- if (match->tctx) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread "
- "context NVT %x/%x\n", nvt_blk, nvt_idx);
- return false;
- }
-
- match->ring = ring;
- match->tctx = tctx;
- }
+ count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
+ priority, logic_serv, match);
+ if (count < 0) {
+ return false;
}
if (!match->tctx) {
--
2.21.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH v6 03/20] ppc/pnv: Instantiate cores separately
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
2019-11-25 6:58 ` [PATCH v6 01/20] ppc/xive: Introduce a XivePresenter interface Cédric Le Goater
2019-11-25 6:58 ` [PATCH v6 02/20] ppc/xive: Implement the " Cédric Le Goater
@ 2019-11-25 6:58 ` Cédric Le Goater
2019-11-25 6:58 ` [PATCH v6 04/20] ppc/pnv: Loop on the threads of the chip to find a matching NVT Cédric Le Goater
` (17 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-25 6:58 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel
From: Greg Kurz <groug@kaod.org>
Allocating a big void * array to store multiple objects isn't a
recommended practice for various reasons:
- no compile time type checking
- potential dangling pointers if a reference on an individual is
taken and the array is freed later on
- duplicate boiler plate everywhere the array is browsed through
Allocate an array of pointers and populate it instead.
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/pnv.h | 2 +-
hw/ppc/pnv.c | 30 ++++++++++++------------------
2 files changed, 13 insertions(+), 19 deletions(-)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 90f1343ed07c..03cb429f2131 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -56,7 +56,7 @@ typedef struct PnvChip {
uint32_t nr_cores;
uint64_t cores_mask;
- void *cores;
+ PnvCore **cores;
MemoryRegion xscom_mmio;
MemoryRegion xscom;
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index f0adb06c8d65..d899c83e5255 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -280,14 +280,12 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
{
- const char *typename = pnv_chip_core_typename(chip);
- size_t typesize = object_type_get_instance_size(typename);
int i;
pnv_dt_xscom(chip, fdt, 0);
for (i = 0; i < chip->nr_cores; i++) {
- PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
+ PnvCore *pnv_core = chip->cores[i];
pnv_dt_core(chip, pnv_core, fdt);
@@ -302,14 +300,12 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
{
- const char *typename = pnv_chip_core_typename(chip);
- size_t typesize = object_type_get_instance_size(typename);
int i;
pnv_dt_xscom(chip, fdt, 0);
for (i = 0; i < chip->nr_cores; i++) {
- PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
+ PnvCore *pnv_core = chip->cores[i];
pnv_dt_core(chip, pnv_core, fdt);
}
@@ -913,8 +909,6 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
{
PnvChip *chip = PNV_CHIP(chip8);
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
- const char *typename = pnv_chip_core_typename(chip);
- size_t typesize = object_type_get_instance_size(typename);
int i, j;
char *name;
XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
@@ -928,7 +922,7 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
/* Map the ICP registers for each thread */
for (i = 0; i < chip->nr_cores; i++) {
- PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
+ PnvCore *pnv_core = chip->cores[i];
int core_hwid = CPU_CORE(pnv_core)->core_id;
for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
@@ -1108,8 +1102,6 @@ static void pnv_chip_power9_instance_init(Object *obj)
static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
{
PnvChip *chip = PNV_CHIP(chip9);
- const char *typename = pnv_chip_core_typename(chip);
- size_t typesize = object_type_get_instance_size(typename);
int i;
chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
@@ -1118,7 +1110,7 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
for (i = 0; i < chip9->nr_quads; i++) {
char eq_name[32];
PnvQuad *eq = &chip9->quads[i];
- PnvCore *pnv_core = PNV_CORE(chip->cores + (i * 4) * typesize);
+ PnvCore *pnv_core = chip->cores[i * 4];
int core_id = CPU_CORE(pnv_core)->core_id;
snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
@@ -1290,7 +1282,6 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
Error *error = NULL;
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
const char *typename = pnv_chip_core_typename(chip);
- size_t typesize = object_type_get_instance_size(typename);
int i, core_hwid;
if (!object_class_by_name(typename)) {
@@ -1305,21 +1296,24 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
return;
}
- chip->cores = g_malloc0(typesize * chip->nr_cores);
+ chip->cores = g_new0(PnvCore *, chip->nr_cores);
for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
&& (i < chip->nr_cores); core_hwid++) {
char core_name[32];
- void *pnv_core = chip->cores + i * typesize;
+ PnvCore *pnv_core;
uint64_t xscom_core_base;
if (!(chip->cores_mask & (1ull << core_hwid))) {
continue;
}
+ pnv_core = PNV_CORE(object_new(typename));
+
snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
- object_initialize_child(OBJECT(chip), core_name, pnv_core, typesize,
- typename, &error_fatal, NULL);
+ object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
+ &error_abort);
+ chip->cores[i] = pnv_core;
object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads",
&error_fatal);
object_property_set_int(OBJECT(pnv_core), core_hwid,
@@ -1340,7 +1334,7 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
}
pnv_xscom_add_subregion(chip, xscom_core_base,
- &PNV_CORE(pnv_core)->xscom_regs);
+ &pnv_core->xscom_regs);
i++;
}
}
--
2.21.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH v6 04/20] ppc/pnv: Loop on the threads of the chip to find a matching NVT
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
` (2 preceding siblings ...)
2019-11-25 6:58 ` [PATCH v6 03/20] ppc/pnv: Instantiate cores separately Cédric Le Goater
@ 2019-11-25 6:58 ` Cédric Le Goater
2019-11-27 4:57 ` David Gibson
2019-11-25 6:58 ` [PATCH v6 05/20] ppc: Introduce a ppc_cpu_pir() helper Cédric Le Goater
` (16 subsequent siblings)
20 siblings, 1 reply; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-25 6:58 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel
CPU_FOREACH() loops on all the CPUs of the machine which is incorrect.
Each XIVE Presenter should scan only the HW threads of the chip it
belongs to.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/intc/pnv_xive.c | 61 ++++++++++++++++++++++++++--------------------
1 file changed, 35 insertions(+), 26 deletions(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 8055de89cf63..9798bd9e729f 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -377,34 +377,43 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
bool cam_ignore, uint8_t priority,
uint32_t logic_serv, XiveTCTXMatch *match)
{
- CPUState *cs;
+ PnvXive *xive = PNV_XIVE(xptr);
+ PnvChip *chip = xive->chip;
int count = 0;
-
- CPU_FOREACH(cs) {
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
- int ring;
-
- /*
- * Check the thread context CAM lines and record matches.
- */
- ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nvt_idx,
- cam_ignore, logic_serv);
- /*
- * Save the context and follow on to catch duplicates, that we
- * don't support yet.
- */
- if (ring != -1) {
- if (match->tctx) {
- qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a "
- "thread context NVT %x/%x\n",
- nvt_blk, nvt_idx);
- return -1;
+ int i, j;
+
+ for (i = 0; i < chip->nr_cores; i++) {
+ PnvCore *pc = chip->cores[i];
+ CPUCore *cc = CPU_CORE(pc);
+
+ for (j = 0; j < cc->nr_threads; j++) {
+ PowerPCCPU *cpu = pc->threads[j];
+ XiveTCTX *tctx;
+ int ring;
+
+ tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+
+ /*
+ * Check the thread context CAM lines and record matches.
+ */
+ ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk,
+ nvt_idx, cam_ignore, logic_serv);
+ /*
+ * Save the context and follow on to catch duplicates, that we
+ * don't support yet.
+ */
+ if (ring != -1) {
+ if (match->tctx) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a "
+ "thread context NVT %x/%x\n",
+ nvt_blk, nvt_idx);
+ return -1;
+ }
+
+ match->ring = ring;
+ match->tctx = tctx;
+ count++;
}
-
- match->ring = ring;
- match->tctx = tctx;
- count++;
}
}
--
2.21.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH v6 04/20] ppc/pnv: Loop on the threads of the chip to find a matching NVT
2019-11-25 6:58 ` [PATCH v6 04/20] ppc/pnv: Loop on the threads of the chip to find a matching NVT Cédric Le Goater
@ 2019-11-27 4:57 ` David Gibson
0 siblings, 0 replies; 33+ messages in thread
From: David Gibson @ 2019-11-27 4:57 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, Greg Kurz, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 3539 bytes --]
On Mon, Nov 25, 2019 at 07:58:04AM +0100, Cédric Le Goater wrote:
> CPU_FOREACH() loops on all the CPUs of the machine which is incorrect.
> Each XIVE Presenter should scan only the HW threads of the chip it
> belongs to.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> Reviewed-by: Greg Kurz <groug@kaod.org>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Patches 1..4 applied to ppc-for-5.0.
> ---
> hw/intc/pnv_xive.c | 61 ++++++++++++++++++++++++++--------------------
> 1 file changed, 35 insertions(+), 26 deletions(-)
>
> diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
> index 8055de89cf63..9798bd9e729f 100644
> --- a/hw/intc/pnv_xive.c
> +++ b/hw/intc/pnv_xive.c
> @@ -377,34 +377,43 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
> bool cam_ignore, uint8_t priority,
> uint32_t logic_serv, XiveTCTXMatch *match)
> {
> - CPUState *cs;
> + PnvXive *xive = PNV_XIVE(xptr);
> + PnvChip *chip = xive->chip;
> int count = 0;
> -
> - CPU_FOREACH(cs) {
> - PowerPCCPU *cpu = POWERPC_CPU(cs);
> - XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
> - int ring;
> -
> - /*
> - * Check the thread context CAM lines and record matches.
> - */
> - ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nvt_idx,
> - cam_ignore, logic_serv);
> - /*
> - * Save the context and follow on to catch duplicates, that we
> - * don't support yet.
> - */
> - if (ring != -1) {
> - if (match->tctx) {
> - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a "
> - "thread context NVT %x/%x\n",
> - nvt_blk, nvt_idx);
> - return -1;
> + int i, j;
> +
> + for (i = 0; i < chip->nr_cores; i++) {
> + PnvCore *pc = chip->cores[i];
> + CPUCore *cc = CPU_CORE(pc);
> +
> + for (j = 0; j < cc->nr_threads; j++) {
> + PowerPCCPU *cpu = pc->threads[j];
> + XiveTCTX *tctx;
> + int ring;
> +
> + tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
> +
> + /*
> + * Check the thread context CAM lines and record matches.
> + */
> + ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk,
> + nvt_idx, cam_ignore, logic_serv);
> + /*
> + * Save the context and follow on to catch duplicates, that we
> + * don't support yet.
> + */
> + if (ring != -1) {
> + if (match->tctx) {
> + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a "
> + "thread context NVT %x/%x\n",
> + nvt_blk, nvt_idx);
> + return -1;
> + }
> +
> + match->ring = ring;
> + match->tctx = tctx;
> + count++;
> }
> -
> - match->ring = ring;
> - match->tctx = tctx;
> - count++;
> }
> }
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v6 05/20] ppc: Introduce a ppc_cpu_pir() helper
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
` (3 preceding siblings ...)
2019-11-25 6:58 ` [PATCH v6 04/20] ppc/pnv: Loop on the threads of the chip to find a matching NVT Cédric Le Goater
@ 2019-11-25 6:58 ` Cédric Le Goater
2019-11-25 6:58 ` [PATCH v6 06/20] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper Cédric Le Goater
` (15 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-25 6:58 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/ppc.h | 1 +
hw/ppc/ppc.c | 9 +++++++--
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
index 4bdcb8bacd4e..585be6ab98c5 100644
--- a/include/hw/ppc/ppc.h
+++ b/include/hw/ppc/ppc.h
@@ -5,6 +5,7 @@
void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);
PowerPCCPU *ppc_get_vcpu_by_pir(int pir);
+int ppc_cpu_pir(PowerPCCPU *cpu);
/* PowerPC hardware exceptions management helpers */
typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 52a18eb7d7a3..8dd982fc1e40 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -1495,15 +1495,20 @@ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
}
}
+int ppc_cpu_pir(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+ return env->spr_cb[SPR_PIR].default_value;
+}
+
PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
{
CPUState *cs;
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
- if (env->spr_cb[SPR_PIR].default_value == pir) {
+ if (ppc_cpu_pir(cpu) == pir) {
return cpu;
}
}
--
2.21.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH v6 06/20] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
` (4 preceding siblings ...)
2019-11-25 6:58 ` [PATCH v6 05/20] ppc: Introduce a ppc_cpu_pir() helper Cédric Le Goater
@ 2019-11-25 6:58 ` Cédric Le Goater
2019-11-27 5:01 ` David Gibson
2019-11-25 6:58 ` [PATCH v6 07/20] ppc/pnv: Fix TIMA indirect access Cédric Le Goater
` (14 subsequent siblings)
20 siblings, 1 reply; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-25 6:58 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel
and use this helper to exclude CPUs which are not enabled in the XIVE
controller.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/pnv.h | 5 +++++
hw/intc/pnv_xive.c | 19 +++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 03cb429f2131..12b0169a4010 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -99,6 +99,11 @@ typedef struct Pnv9Chip {
PnvQuad *quads;
} Pnv9Chip;
+/*
+ * A SMT8 fused core is a pair of SMT4 cores.
+ */
+#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
+
typedef struct PnvChipClass {
/*< private >*/
SysBusDeviceClass parent_class;
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 9798bd9e729f..ec8349ee4a1f 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -372,6 +372,21 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas);
}
+/*
+ * One bit per thread id. The first register PC_THREAD_EN_REG0 covers
+ * the first cores 0-15 (normal) of the chip or 0-7 (fused). The
+ * second register covers cores 16-23 (normal) or 8-11 (fused).
+ */
+static bool pnv_xive_is_cpu_enabled(PnvXive *xive, PowerPCCPU *cpu)
+{
+ int pir = ppc_cpu_pir(cpu);
+ uint32_t fc = PNV9_PIR2FUSEDCORE(pir);
+ uint64_t reg = fc < 8 ? PC_THREAD_EN_REG0 : PC_THREAD_EN_REG1;
+ uint32_t bit = pir & 0x3f;
+
+ return xive->regs[reg >> 3] & PPC_BIT(bit);
+}
+
static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint8_t priority,
@@ -391,6 +406,10 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
XiveTCTX *tctx;
int ring;
+ if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
+ continue;
+ }
+
tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
/*
--
2.21.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH v6 06/20] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper
2019-11-25 6:58 ` [PATCH v6 06/20] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper Cédric Le Goater
@ 2019-11-27 5:01 ` David Gibson
0 siblings, 0 replies; 33+ messages in thread
From: David Gibson @ 2019-11-27 5:01 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, Greg Kurz, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2512 bytes --]
On Mon, Nov 25, 2019 at 07:58:06AM +0100, Cédric Le Goater wrote:
> and use this helper to exclude CPUs which are not enabled in the XIVE
> controller.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Applied 5..6 to ppc-for-5.0.
> ---
> include/hw/ppc/pnv.h | 5 +++++
> hw/intc/pnv_xive.c | 19 +++++++++++++++++++
> 2 files changed, 24 insertions(+)
>
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index 03cb429f2131..12b0169a4010 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -99,6 +99,11 @@ typedef struct Pnv9Chip {
> PnvQuad *quads;
> } Pnv9Chip;
>
> +/*
> + * A SMT8 fused core is a pair of SMT4 cores.
> + */
> +#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
> +
> typedef struct PnvChipClass {
> /*< private >*/
> SysBusDeviceClass parent_class;
> diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
> index 9798bd9e729f..ec8349ee4a1f 100644
> --- a/hw/intc/pnv_xive.c
> +++ b/hw/intc/pnv_xive.c
> @@ -372,6 +372,21 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
> return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas);
> }
>
> +/*
> + * One bit per thread id. The first register PC_THREAD_EN_REG0 covers
> + * the first cores 0-15 (normal) of the chip or 0-7 (fused). The
> + * second register covers cores 16-23 (normal) or 8-11 (fused).
> + */
> +static bool pnv_xive_is_cpu_enabled(PnvXive *xive, PowerPCCPU *cpu)
> +{
> + int pir = ppc_cpu_pir(cpu);
> + uint32_t fc = PNV9_PIR2FUSEDCORE(pir);
> + uint64_t reg = fc < 8 ? PC_THREAD_EN_REG0 : PC_THREAD_EN_REG1;
> + uint32_t bit = pir & 0x3f;
> +
> + return xive->regs[reg >> 3] & PPC_BIT(bit);
> +}
> +
> static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
> uint8_t nvt_blk, uint32_t nvt_idx,
> bool cam_ignore, uint8_t priority,
> @@ -391,6 +406,10 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
> XiveTCTX *tctx;
> int ring;
>
> + if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
> + continue;
> + }
> +
> tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
>
> /*
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v6 07/20] ppc/pnv: Fix TIMA indirect access
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
` (5 preceding siblings ...)
2019-11-25 6:58 ` [PATCH v6 06/20] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper Cédric Le Goater
@ 2019-11-25 6:58 ` Cédric Le Goater
2019-11-27 5:03 ` David Gibson
2019-11-25 6:58 ` [PATCH v6 08/20] ppc/xive: Introduce a XiveFabric interface Cédric Le Goater
` (13 subsequent siblings)
20 siblings, 1 reply; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-25 6:58 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel
When the TIMA of a CPU needs to be accessed from the indirect page,
the thread id of the target CPU is first stored in the PC_TCTXT_INDIR0
register. This thread id is relative to the chip and not to the system.
Introduce a helper routine to look for a CPU of a given PIR and fix
pnv_xive_get_indirect_tctx() to scan only the threads of the local
chip and not the whole machine.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/pnv.h | 2 ++
hw/intc/pnv_xive.c | 13 +++++++------
hw/ppc/pnv.c | 17 +++++++++++++++++
3 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 12b0169a4010..a58cfea3f2fd 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -162,6 +162,8 @@ typedef struct PnvChipClass {
#define PNV_CHIP_INDEX(chip) \
(((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
+PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
+
#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
#define PNV_MACHINE(obj) \
OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index ec8349ee4a1f..b2ab2ccc91e7 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -1400,12 +1400,13 @@ static const MemoryRegionOps pnv_xive_ic_lsi_ops = {
*/
/*
- * When the TIMA is accessed from the indirect page, the thread id
- * (PIR) has to be configured in the IC registers before. This is used
- * for resets and for debug purpose also.
+ * When the TIMA is accessed from the indirect page, the thread id of
+ * the target CPU is configured in the PC_TCTXT_INDIR0 register before
+ * use. This is used for resets and for debug purpose also.
*/
static XiveTCTX *pnv_xive_get_indirect_tctx(PnvXive *xive)
{
+ PnvChip *chip = xive->chip;
uint64_t tctxt_indir = xive->regs[PC_TCTXT_INDIR0 >> 3];
PowerPCCPU *cpu = NULL;
int pir;
@@ -1415,15 +1416,15 @@ static XiveTCTX *pnv_xive_get_indirect_tctx(PnvXive *xive)
return NULL;
}
- pir = GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir) & 0xff;
- cpu = ppc_get_vcpu_by_pir(pir);
+ pir = (chip->chip_id << 8) | GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir);
+ cpu = pnv_chip_find_cpu(chip, pir);
if (!cpu) {
xive_error(xive, "IC: invalid PIR %x for indirect access", pir);
return NULL;
}
/* Check that HW thread is XIVE enabled */
- if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) {
+ if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
xive_error(xive, "IC: CPU %x is not enabled", pir);
}
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index d899c83e5255..8f688f4efc5a 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1371,6 +1371,23 @@ static void pnv_chip_class_init(ObjectClass *klass, void *data)
dc->desc = "PowerNV Chip";
}
+PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
+{
+ int i, j;
+
+ for (i = 0; i < chip->nr_cores; i++) {
+ PnvCore *pc = chip->cores[i];
+ CPUCore *cc = CPU_CORE(pc);
+
+ for (j = 0; j < cc->nr_threads; j++) {
+ if (ppc_cpu_pir(pc->threads[j]) == pir) {
+ return pc->threads[j];
+ }
+ }
+ }
+ return NULL;
+}
+
static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
{
PnvMachineState *pnv = PNV_MACHINE(xi);
--
2.21.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH v6 07/20] ppc/pnv: Fix TIMA indirect access
2019-11-25 6:58 ` [PATCH v6 07/20] ppc/pnv: Fix TIMA indirect access Cédric Le Goater
@ 2019-11-27 5:03 ` David Gibson
0 siblings, 0 replies; 33+ messages in thread
From: David Gibson @ 2019-11-27 5:03 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, Greg Kurz, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 3988 bytes --]
On Mon, Nov 25, 2019 at 07:58:07AM +0100, Cédric Le Goater wrote:
> When the TIMA of a CPU needs to be accessed from the indirect page,
> the thread id of the target CPU is first stored in the PC_TCTXT_INDIR0
> register. This thread id is relative to the chip and not to the system.
>
> Introduce a helper routine to look for a CPU of a given PIR and fix
> pnv_xive_get_indirect_tctx() to scan only the threads of the local
> chip and not the whole machine.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Applied to ppc-for-5.0.
> ---
> include/hw/ppc/pnv.h | 2 ++
> hw/intc/pnv_xive.c | 13 +++++++------
> hw/ppc/pnv.c | 17 +++++++++++++++++
> 3 files changed, 26 insertions(+), 6 deletions(-)
>
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index 12b0169a4010..a58cfea3f2fd 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -162,6 +162,8 @@ typedef struct PnvChipClass {
> #define PNV_CHIP_INDEX(chip) \
> (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
>
> +PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
> +
> #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
> #define PNV_MACHINE(obj) \
> OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE)
> diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
> index ec8349ee4a1f..b2ab2ccc91e7 100644
> --- a/hw/intc/pnv_xive.c
> +++ b/hw/intc/pnv_xive.c
> @@ -1400,12 +1400,13 @@ static const MemoryRegionOps pnv_xive_ic_lsi_ops = {
> */
>
> /*
> - * When the TIMA is accessed from the indirect page, the thread id
> - * (PIR) has to be configured in the IC registers before. This is used
> - * for resets and for debug purpose also.
> + * When the TIMA is accessed from the indirect page, the thread id of
> + * the target CPU is configured in the PC_TCTXT_INDIR0 register before
> + * use. This is used for resets and for debug purpose also.
> */
> static XiveTCTX *pnv_xive_get_indirect_tctx(PnvXive *xive)
> {
> + PnvChip *chip = xive->chip;
> uint64_t tctxt_indir = xive->regs[PC_TCTXT_INDIR0 >> 3];
> PowerPCCPU *cpu = NULL;
> int pir;
> @@ -1415,15 +1416,15 @@ static XiveTCTX *pnv_xive_get_indirect_tctx(PnvXive *xive)
> return NULL;
> }
>
> - pir = GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir) & 0xff;
> - cpu = ppc_get_vcpu_by_pir(pir);
> + pir = (chip->chip_id << 8) | GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir);
> + cpu = pnv_chip_find_cpu(chip, pir);
> if (!cpu) {
> xive_error(xive, "IC: invalid PIR %x for indirect access", pir);
> return NULL;
> }
>
> /* Check that HW thread is XIVE enabled */
> - if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) {
> + if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
> xive_error(xive, "IC: CPU %x is not enabled", pir);
> }
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index d899c83e5255..8f688f4efc5a 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1371,6 +1371,23 @@ static void pnv_chip_class_init(ObjectClass *klass, void *data)
> dc->desc = "PowerNV Chip";
> }
>
> +PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
> +{
> + int i, j;
> +
> + for (i = 0; i < chip->nr_cores; i++) {
> + PnvCore *pc = chip->cores[i];
> + CPUCore *cc = CPU_CORE(pc);
> +
> + for (j = 0; j < cc->nr_threads; j++) {
> + if (ppc_cpu_pir(pc->threads[j]) == pir) {
> + return pc->threads[j];
> + }
> + }
> + }
> + return NULL;
> +}
> +
> static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
> {
> PnvMachineState *pnv = PNV_MACHINE(xi);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v6 08/20] ppc/xive: Introduce a XiveFabric interface
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
` (6 preceding siblings ...)
2019-11-25 6:58 ` [PATCH v6 07/20] ppc/pnv: Fix TIMA indirect access Cédric Le Goater
@ 2019-11-25 6:58 ` Cédric Le Goater
2019-11-25 6:58 ` [PATCH v6 09/20] ppc/pnv: Implement the " Cédric Le Goater
` (12 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-25 6:58 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel
The XiveFabric QOM interface acts as the PowerBUS interface between
the interrupt controller and the system and should be implemented by
the QEMU machine. On HW, the XIVE sub-engine is responsible for the
communication with the other chip is the Common Queue (CQ) bridge
unit.
This interface offers a 'match_nvt' handler to perform the CAM line
matching when looking for a XIVE Presenter with a dispatched NVT.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/xive.h | 22 ++++++++++++++++++++++
hw/intc/xive.c | 10 ++++++++++
2 files changed, 32 insertions(+)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index f9aa0fa0dac3..b00af988779b 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -399,6 +399,28 @@ int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint32_t logic_serv);
+/*
+ * XIVE Fabric (Interface between Interrupt Controller and Machine)
+ */
+
+typedef struct XiveFabric XiveFabric;
+
+#define TYPE_XIVE_FABRIC "xive-fabric"
+#define XIVE_FABRIC(obj) \
+ INTERFACE_CHECK(XiveFabric, (obj), TYPE_XIVE_FABRIC)
+#define XIVE_FABRIC_CLASS(klass) \
+ OBJECT_CLASS_CHECK(XiveFabricClass, (klass), TYPE_XIVE_FABRIC)
+#define XIVE_FABRIC_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(XiveFabricClass, (obj), TYPE_XIVE_FABRIC)
+
+typedef struct XiveFabricClass {
+ InterfaceClass parent;
+ int (*match_nvt)(XiveFabric *xfb, uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint8_t priority,
+ uint32_t logic_serv, XiveTCTXMatch *match);
+} XiveFabricClass;
+
/*
* XIVE END ESBs
*/
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index da6196ca958f..1c9e58f8deac 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1893,8 +1893,18 @@ static const TypeInfo xive_presenter_info = {
.class_size = sizeof(XivePresenterClass),
};
+/*
+ * XIVE Fabric
+ */
+static const TypeInfo xive_fabric_info = {
+ .name = TYPE_XIVE_FABRIC,
+ .parent = TYPE_INTERFACE,
+ .class_size = sizeof(XiveFabricClass),
+};
+
static void xive_register_types(void)
{
+ type_register_static(&xive_fabric_info);
type_register_static(&xive_source_info);
type_register_static(&xive_notifier_info);
type_register_static(&xive_presenter_info);
--
2.21.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH v6 09/20] ppc/pnv: Implement the XiveFabric interface
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
` (7 preceding siblings ...)
2019-11-25 6:58 ` [PATCH v6 08/20] ppc/xive: Introduce a XiveFabric interface Cédric Le Goater
@ 2019-11-25 6:58 ` Cédric Le Goater
2019-11-25 6:58 ` [PATCH v6 10/20] ppc/spapr: " Cédric Le Goater
` (11 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-25 6:58 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel
The CAM line matching on the PowerNV machine now scans all chips of
the system and all CPUs of a chip to find a dispatched NVT in the
thread contexts.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/pnv.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 8f688f4efc5a..5b8b07f6aedc 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1443,6 +1443,35 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj,
}
}
+static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint8_t priority,
+ uint32_t logic_serv,
+ XiveTCTXMatch *match)
+{
+ PnvMachineState *pnv = PNV_MACHINE(xfb);
+ int total_count = 0;
+ int i;
+
+ for (i = 0; i < pnv->num_chips; i++) {
+ Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
+ XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
+ XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
+ int count;
+
+ count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
+ priority, logic_serv, match);
+
+ if (count < 0) {
+ return count;
+ }
+
+ total_count += count;
+ }
+
+ return total_count;
+}
+
static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
@@ -1506,9 +1535,11 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
+ XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
+ xfc->match_nvt = pnv_match_nvt;
mc->alias = "powernv";
}
@@ -1555,6 +1586,10 @@ static const TypeInfo types[] = {
.name = MACHINE_TYPE_NAME("powernv9"),
.parent = TYPE_PNV_MACHINE,
.class_init = pnv_machine_power9_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_XIVE_FABRIC },
+ { },
+ },
},
{
.name = MACHINE_TYPE_NAME("powernv8"),
--
2.21.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH v6 10/20] ppc/spapr: Implement the XiveFabric interface
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
` (8 preceding siblings ...)
2019-11-25 6:58 ` [PATCH v6 09/20] ppc/pnv: Implement the " Cédric Le Goater
@ 2019-11-25 6:58 ` Cédric Le Goater
2019-11-25 6:58 ` [PATCH v6 11/20] ppc/xive: Use the XiveFabric and XivePresenter interfaces Cédric Le Goater
` (10 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-25 6:58 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel
The CAM line matching sequence in the pseries machine does not change
much apart from the use of the new QOM interfaces. There is an extra
indirection because of the sPAPR IRQ backend of the machine. Only the
XIVE backend implements the new 'match_nvt' handler.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/spapr.c | 39 +++++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index e076f6023c73..2687bbac37eb 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -4275,6 +4275,42 @@ static void spapr_pic_print_info(InterruptStatsProvider *obj,
kvm_irqchip_in_kernel() ? "in-kernel" : "emulated");
}
+static int spapr_match_nvt(XiveFabric *xfb, uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint8_t priority,
+ uint32_t logic_serv, XiveTCTXMatch *match)
+{
+ SpaprMachineState *spapr = SPAPR_MACHINE(xfb);
+ XivePresenter *xptr = XIVE_PRESENTER(spapr->xive);
+ XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
+ int count;
+
+ /* This is a XIVE only operation */
+ assert(spapr->active_intc == SPAPR_INTC(spapr->xive));
+
+ count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
+ priority, logic_serv, match);
+ if (count < 0) {
+ return count;
+ }
+
+ /*
+ * When we implement the save and restore of the thread interrupt
+ * contexts in the enter/exit CPU handlers of the machine and the
+ * escalations in QEMU, we should be able to handle non dispatched
+ * vCPUs.
+ *
+ * Until this is done, the sPAPR machine should find at least one
+ * matching context always.
+ */
+ if (count == 0) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n",
+ nvt_blk, nvt_idx);
+ }
+
+ return count;
+}
+
int spapr_get_vcpu_id(PowerPCCPU *cpu)
{
return cpu->vcpu_id;
@@ -4371,6 +4407,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
+ XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
mc->desc = "pSeries Logical Partition (PAPR compliant)";
mc->ignore_boot_device_suffixes = true;
@@ -4447,6 +4484,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
smc->linux_pci_probe = true;
smc->smp_threads_vsmt = true;
smc->nr_xirqs = SPAPR_NR_XIRQS;
+ xfc->match_nvt = spapr_match_nvt;
}
static const TypeInfo spapr_machine_info = {
@@ -4465,6 +4503,7 @@ static const TypeInfo spapr_machine_info = {
{ TYPE_PPC_VIRTUAL_HYPERVISOR },
{ TYPE_XICS_FABRIC },
{ TYPE_INTERRUPT_STATS_PROVIDER },
+ { TYPE_XIVE_FABRIC },
{ }
},
};
--
2.21.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH v6 11/20] ppc/xive: Use the XiveFabric and XivePresenter interfaces
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
` (9 preceding siblings ...)
2019-11-25 6:58 ` [PATCH v6 10/20] ppc/spapr: " Cédric Le Goater
@ 2019-11-25 6:58 ` Cédric Le Goater
2019-11-27 5:07 ` David Gibson
2019-11-25 6:58 ` [PATCH v6 12/20] ppc/xive: Extend the TIMA operation with a XivePresenter parameter Cédric Le Goater
` (9 subsequent siblings)
20 siblings, 1 reply; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-25 6:58 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel
Now that the machines have handlers implementing the XiveFabric and
XivePresenter interfaces, remove xive_presenter_match() and make use
of the 'match_nvt' handler of the machine.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/intc/xive.c | 48 +++++++++++++++++-------------------------------
1 file changed, 17 insertions(+), 31 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 1c9e58f8deac..8e683847bf81 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1423,30 +1423,6 @@ int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
return -1;
}
-static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
- uint8_t nvt_blk, uint32_t nvt_idx,
- bool cam_ignore, uint8_t priority,
- uint32_t logic_serv, XiveTCTXMatch *match)
-{
- XivePresenter *xptr = XIVE_PRESENTER(xrtr);
- XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
- int count;
-
- count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
- priority, logic_serv, match);
- if (count < 0) {
- return false;
- }
-
- if (!match->tctx) {
- qemu_log_mask(LOG_UNIMP, "XIVE: NVT %x/%x is not dispatched\n",
- nvt_blk, nvt_idx);
- return false;
- }
-
- return true;
-}
-
/*
* This is our simple Xive Presenter Engine model. It is merged in the
* Router as it does not require an extra object.
@@ -1462,22 +1438,32 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
*
* The parameters represent what is sent on the PowerBus
*/
-static bool xive_presenter_notify(XiveRouter *xrtr, uint8_t format,
+static bool xive_presenter_notify(uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint8_t priority,
uint32_t logic_serv)
{
+ XiveFabric *xfb = XIVE_FABRIC(qdev_get_machine());
+ XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb);
XiveTCTXMatch match = { .tctx = NULL, .ring = 0 };
- bool found;
+ int count;
- found = xive_presenter_match(xrtr, format, nvt_blk, nvt_idx, cam_ignore,
- priority, logic_serv, &match);
- if (found) {
+ /*
+ * Ask the machine to scan the interrupt controllers for a match
+ */
+ count = xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore,
+ priority, logic_serv, &match);
+ if (count < 0) {
+ return false;
+ }
+
+ /* handle CPU exception delivery */
+ if (count) {
ipb_update(&match.tctx->regs[match.ring], priority);
xive_tctx_notify(match.tctx, match.ring);
}
- return found;
+ return !!count;
}
/*
@@ -1590,7 +1576,7 @@ static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk,
return;
}
- found = xive_presenter_notify(xrtr, format, nvt_blk, nvt_idx,
+ found = xive_presenter_notify(format, nvt_blk, nvt_idx,
xive_get_field32(END_W7_F0_IGNORE, end.w7),
priority,
xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7));
--
2.21.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH v6 11/20] ppc/xive: Use the XiveFabric and XivePresenter interfaces
2019-11-25 6:58 ` [PATCH v6 11/20] ppc/xive: Use the XiveFabric and XivePresenter interfaces Cédric Le Goater
@ 2019-11-27 5:07 ` David Gibson
0 siblings, 0 replies; 33+ messages in thread
From: David Gibson @ 2019-11-27 5:07 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, Greg Kurz, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 3906 bytes --]
On Mon, Nov 25, 2019 at 07:58:11AM +0100, Cédric Le Goater wrote:
> Now that the machines have handlers implementing the XiveFabric and
> XivePresenter interfaces, remove xive_presenter_match() and make use
> of the 'match_nvt' handler of the machine.
>
> Reviewed-by: Greg Kurz <groug@kaod.org>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
8..11 applied to ppc-for-5.0.
> ---
> hw/intc/xive.c | 48 +++++++++++++++++-------------------------------
> 1 file changed, 17 insertions(+), 31 deletions(-)
>
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index 1c9e58f8deac..8e683847bf81 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -1423,30 +1423,6 @@ int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
> return -1;
> }
>
> -static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
> - uint8_t nvt_blk, uint32_t nvt_idx,
> - bool cam_ignore, uint8_t priority,
> - uint32_t logic_serv, XiveTCTXMatch *match)
> -{
> - XivePresenter *xptr = XIVE_PRESENTER(xrtr);
> - XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
> - int count;
> -
> - count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
> - priority, logic_serv, match);
> - if (count < 0) {
> - return false;
> - }
> -
> - if (!match->tctx) {
> - qemu_log_mask(LOG_UNIMP, "XIVE: NVT %x/%x is not dispatched\n",
> - nvt_blk, nvt_idx);
> - return false;
> - }
> -
> - return true;
> -}
> -
> /*
> * This is our simple Xive Presenter Engine model. It is merged in the
> * Router as it does not require an extra object.
> @@ -1462,22 +1438,32 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
> *
> * The parameters represent what is sent on the PowerBus
> */
> -static bool xive_presenter_notify(XiveRouter *xrtr, uint8_t format,
> +static bool xive_presenter_notify(uint8_t format,
> uint8_t nvt_blk, uint32_t nvt_idx,
> bool cam_ignore, uint8_t priority,
> uint32_t logic_serv)
> {
> + XiveFabric *xfb = XIVE_FABRIC(qdev_get_machine());
> + XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb);
> XiveTCTXMatch match = { .tctx = NULL, .ring = 0 };
> - bool found;
> + int count;
>
> - found = xive_presenter_match(xrtr, format, nvt_blk, nvt_idx, cam_ignore,
> - priority, logic_serv, &match);
> - if (found) {
> + /*
> + * Ask the machine to scan the interrupt controllers for a match
> + */
> + count = xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore,
> + priority, logic_serv, &match);
> + if (count < 0) {
> + return false;
> + }
> +
> + /* handle CPU exception delivery */
> + if (count) {
> ipb_update(&match.tctx->regs[match.ring], priority);
> xive_tctx_notify(match.tctx, match.ring);
> }
>
> - return found;
> + return !!count;
> }
>
> /*
> @@ -1590,7 +1576,7 @@ static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk,
> return;
> }
>
> - found = xive_presenter_notify(xrtr, format, nvt_blk, nvt_idx,
> + found = xive_presenter_notify(format, nvt_blk, nvt_idx,
> xive_get_field32(END_W7_F0_IGNORE, end.w7),
> priority,
> xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7));
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v6 12/20] ppc/xive: Extend the TIMA operation with a XivePresenter parameter
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
` (10 preceding siblings ...)
2019-11-25 6:58 ` [PATCH v6 11/20] ppc/xive: Use the XiveFabric and XivePresenter interfaces Cédric Le Goater
@ 2019-11-25 6:58 ` Cédric Le Goater
2019-11-27 5:24 ` David Gibson
2019-11-25 6:58 ` [PATCH v6 13/20] ppc/pnv: Clarify how the TIMA is accessed on a multichip system Cédric Le Goater
` (8 subsequent siblings)
20 siblings, 1 reply; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-25 6:58 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel
The TIMA operations are performed on behalf of the XIVE IVPE sub-engine
(Presenter) on the thread interrupt context registers. The current
operations supported by the model are simple and do not require access
to the controller but more complex operations will need access to the
controller NVT table and to its configuration.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/xive.h | 7 +++---
hw/intc/pnv_xive.c | 4 +--
hw/intc/xive.c | 58 ++++++++++++++++++++++++-------------------
3 files changed, 38 insertions(+), 31 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index b00af988779b..97bbcddb381d 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -463,9 +463,10 @@ typedef struct XiveENDSource {
#define XIVE_TM_USER_PAGE 0x3
extern const MemoryRegionOps xive_tm_ops;
-void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
- unsigned size);
-uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size);
+void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
+ uint64_t value, unsigned size);
+uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
+ unsigned size);
void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp);
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index b2ab2ccc91e7..95e9de312cd9 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -1436,7 +1436,7 @@ static void xive_tm_indirect_write(void *opaque, hwaddr offset,
{
XiveTCTX *tctx = pnv_xive_get_indirect_tctx(PNV_XIVE(opaque));
- xive_tctx_tm_write(tctx, offset, value, size);
+ xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size);
}
static uint64_t xive_tm_indirect_read(void *opaque, hwaddr offset,
@@ -1444,7 +1444,7 @@ static uint64_t xive_tm_indirect_read(void *opaque, hwaddr offset,
{
XiveTCTX *tctx = pnv_xive_get_indirect_tctx(PNV_XIVE(opaque));
- return xive_tctx_tm_read(tctx, offset, size);
+ return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size);
}
static const MemoryRegionOps xive_tm_indirect_ops = {
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 8e683847bf81..9e7e5ea57c5c 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -144,19 +144,20 @@ static inline uint32_t xive_tctx_word2(uint8_t *ring)
* XIVE Thread Interrupt Management Area (TIMA)
*/
-static void xive_tm_set_hv_cppr(XiveTCTX *tctx, hwaddr offset,
- uint64_t value, unsigned size)
+static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
{
xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff);
}
-static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr offset, unsigned size)
+static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
{
return xive_tctx_accept(tctx, TM_QW3_HV_PHYS);
}
-static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset,
- unsigned size)
+static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
{
uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]);
uint32_t qw2w2;
@@ -166,13 +167,14 @@ static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset,
return qw2w2;
}
-static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset,
+static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
uint64_t value, unsigned size)
{
tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff;
}
-static uint64_t xive_tm_vt_poll(XiveTCTX *tctx, hwaddr offset, unsigned size)
+static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
{
return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff;
}
@@ -315,13 +317,14 @@ static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size)
* state changes (side effects) in addition to setting/returning the
* interrupt management area context of the processor thread.
*/
-static uint64_t xive_tm_ack_os_reg(XiveTCTX *tctx, hwaddr offset, unsigned size)
+static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
{
return xive_tctx_accept(tctx, TM_QW1_OS);
}
-static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr offset,
- uint64_t value, unsigned size)
+static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
{
xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff);
}
@@ -330,8 +333,8 @@ static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr offset,
* Adjust the IPB to allow a CPU to process event queues of other
* priorities during one physical interrupt cycle.
*/
-static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr offset,
- uint64_t value, unsigned size)
+static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
{
ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff);
xive_tctx_notify(tctx, TM_QW1_OS);
@@ -366,8 +369,8 @@ static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2)
memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
}
-static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset,
- unsigned size)
+static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
{
uint32_t qw1w2;
uint32_t qw1w2_new;
@@ -396,9 +399,11 @@ typedef struct XiveTmOp {
uint8_t page_offset;
uint32_t op_offset;
unsigned size;
- void (*write_handler)(XiveTCTX *tctx, hwaddr offset, uint64_t value,
- unsigned size);
- uint64_t (*read_handler)(XiveTCTX *tctx, hwaddr offset, unsigned size);
+ void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset,
+ uint64_t value, unsigned size);
+ uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
+ unsigned size);
} XiveTmOp;
static const XiveTmOp xive_tm_operations[] = {
@@ -444,8 +449,8 @@ static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write)
/*
* TIMA MMIO handlers
*/
-void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
- unsigned size)
+void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
+ uint64_t value, unsigned size)
{
const XiveTmOp *xto;
@@ -462,7 +467,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA "
"@%"HWADDR_PRIx"\n", offset);
} else {
- xto->write_handler(tctx, offset, value, size);
+ xto->write_handler(xptr, tctx, offset, value, size);
}
return;
}
@@ -472,7 +477,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
*/
xto = xive_tm_find_op(offset, size, true);
if (xto) {
- xto->write_handler(tctx, offset, value, size);
+ xto->write_handler(xptr, tctx, offset, value, size);
return;
}
@@ -482,7 +487,8 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
xive_tm_raw_write(tctx, offset, value, size);
}
-uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size)
+uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
+ unsigned size)
{
const XiveTmOp *xto;
@@ -500,7 +506,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size)
"@%"HWADDR_PRIx"\n", offset);
return -1;
}
- return xto->read_handler(tctx, offset, size);
+ return xto->read_handler(xptr, tctx, offset, size);
}
/*
@@ -508,7 +514,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size)
*/
xto = xive_tm_find_op(offset, size, false);
if (xto) {
- return xto->read_handler(tctx, offset, size);
+ return xto->read_handler(xptr, tctx, offset, size);
}
/*
@@ -522,14 +528,14 @@ static void xive_tm_write(void *opaque, hwaddr offset,
{
XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
- xive_tctx_tm_write(tctx, offset, value, size);
+ xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size);
}
static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size)
{
XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
- return xive_tctx_tm_read(tctx, offset, size);
+ return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size);
}
const MemoryRegionOps xive_tm_ops = {
--
2.21.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH v6 12/20] ppc/xive: Extend the TIMA operation with a XivePresenter parameter
2019-11-25 6:58 ` [PATCH v6 12/20] ppc/xive: Extend the TIMA operation with a XivePresenter parameter Cédric Le Goater
@ 2019-11-27 5:24 ` David Gibson
0 siblings, 0 replies; 33+ messages in thread
From: David Gibson @ 2019-11-27 5:24 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, Greg Kurz, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 10561 bytes --]
On Mon, Nov 25, 2019 at 07:58:12AM +0100, Cédric Le Goater wrote:
> The TIMA operations are performed on behalf of the XIVE IVPE sub-engine
> (Presenter) on the thread interrupt context registers. The current
> operations supported by the model are simple and do not require access
> to the controller but more complex operations will need access to the
> controller NVT table and to its configuration.
>
> Reviewed-by: Greg Kurz <groug@kaod.org>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Applied to ppc-for-5.0.
> ---
> include/hw/ppc/xive.h | 7 +++---
> hw/intc/pnv_xive.c | 4 +--
> hw/intc/xive.c | 58 ++++++++++++++++++++++++-------------------
> 3 files changed, 38 insertions(+), 31 deletions(-)
>
> diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
> index b00af988779b..97bbcddb381d 100644
> --- a/include/hw/ppc/xive.h
> +++ b/include/hw/ppc/xive.h
> @@ -463,9 +463,10 @@ typedef struct XiveENDSource {
> #define XIVE_TM_USER_PAGE 0x3
>
> extern const MemoryRegionOps xive_tm_ops;
> -void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
> - unsigned size);
> -uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size);
> +void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
> + uint64_t value, unsigned size);
> +uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
> + unsigned size);
>
> void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
> Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp);
> diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
> index b2ab2ccc91e7..95e9de312cd9 100644
> --- a/hw/intc/pnv_xive.c
> +++ b/hw/intc/pnv_xive.c
> @@ -1436,7 +1436,7 @@ static void xive_tm_indirect_write(void *opaque, hwaddr offset,
> {
> XiveTCTX *tctx = pnv_xive_get_indirect_tctx(PNV_XIVE(opaque));
>
> - xive_tctx_tm_write(tctx, offset, value, size);
> + xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size);
> }
>
> static uint64_t xive_tm_indirect_read(void *opaque, hwaddr offset,
> @@ -1444,7 +1444,7 @@ static uint64_t xive_tm_indirect_read(void *opaque, hwaddr offset,
> {
> XiveTCTX *tctx = pnv_xive_get_indirect_tctx(PNV_XIVE(opaque));
>
> - return xive_tctx_tm_read(tctx, offset, size);
> + return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size);
> }
>
> static const MemoryRegionOps xive_tm_indirect_ops = {
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index 8e683847bf81..9e7e5ea57c5c 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -144,19 +144,20 @@ static inline uint32_t xive_tctx_word2(uint8_t *ring)
> * XIVE Thread Interrupt Management Area (TIMA)
> */
>
> -static void xive_tm_set_hv_cppr(XiveTCTX *tctx, hwaddr offset,
> - uint64_t value, unsigned size)
> +static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx,
> + hwaddr offset, uint64_t value, unsigned size)
> {
> xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff);
> }
>
> -static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr offset, unsigned size)
> +static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx,
> + hwaddr offset, unsigned size)
> {
> return xive_tctx_accept(tctx, TM_QW3_HV_PHYS);
> }
>
> -static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset,
> - unsigned size)
> +static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx,
> + hwaddr offset, unsigned size)
> {
> uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]);
> uint32_t qw2w2;
> @@ -166,13 +167,14 @@ static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset,
> return qw2w2;
> }
>
> -static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset,
> +static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
> uint64_t value, unsigned size)
> {
> tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff;
> }
>
> -static uint64_t xive_tm_vt_poll(XiveTCTX *tctx, hwaddr offset, unsigned size)
> +static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx,
> + hwaddr offset, unsigned size)
> {
> return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff;
> }
> @@ -315,13 +317,14 @@ static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size)
> * state changes (side effects) in addition to setting/returning the
> * interrupt management area context of the processor thread.
> */
> -static uint64_t xive_tm_ack_os_reg(XiveTCTX *tctx, hwaddr offset, unsigned size)
> +static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx,
> + hwaddr offset, unsigned size)
> {
> return xive_tctx_accept(tctx, TM_QW1_OS);
> }
>
> -static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr offset,
> - uint64_t value, unsigned size)
> +static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,
> + hwaddr offset, uint64_t value, unsigned size)
> {
> xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff);
> }
> @@ -330,8 +333,8 @@ static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr offset,
> * Adjust the IPB to allow a CPU to process event queues of other
> * priorities during one physical interrupt cycle.
> */
> -static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr offset,
> - uint64_t value, unsigned size)
> +static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx,
> + hwaddr offset, uint64_t value, unsigned size)
> {
> ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff);
> xive_tctx_notify(tctx, TM_QW1_OS);
> @@ -366,8 +369,8 @@ static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2)
> memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
> }
>
> -static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset,
> - unsigned size)
> +static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
> + hwaddr offset, unsigned size)
> {
> uint32_t qw1w2;
> uint32_t qw1w2_new;
> @@ -396,9 +399,11 @@ typedef struct XiveTmOp {
> uint8_t page_offset;
> uint32_t op_offset;
> unsigned size;
> - void (*write_handler)(XiveTCTX *tctx, hwaddr offset, uint64_t value,
> - unsigned size);
> - uint64_t (*read_handler)(XiveTCTX *tctx, hwaddr offset, unsigned size);
> + void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx,
> + hwaddr offset,
> + uint64_t value, unsigned size);
> + uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
> + unsigned size);
> } XiveTmOp;
>
> static const XiveTmOp xive_tm_operations[] = {
> @@ -444,8 +449,8 @@ static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write)
> /*
> * TIMA MMIO handlers
> */
> -void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
> - unsigned size)
> +void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
> + uint64_t value, unsigned size)
> {
> const XiveTmOp *xto;
>
> @@ -462,7 +467,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
> qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA "
> "@%"HWADDR_PRIx"\n", offset);
> } else {
> - xto->write_handler(tctx, offset, value, size);
> + xto->write_handler(xptr, tctx, offset, value, size);
> }
> return;
> }
> @@ -472,7 +477,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
> */
> xto = xive_tm_find_op(offset, size, true);
> if (xto) {
> - xto->write_handler(tctx, offset, value, size);
> + xto->write_handler(xptr, tctx, offset, value, size);
> return;
> }
>
> @@ -482,7 +487,8 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
> xive_tm_raw_write(tctx, offset, value, size);
> }
>
> -uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size)
> +uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
> + unsigned size)
> {
> const XiveTmOp *xto;
>
> @@ -500,7 +506,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size)
> "@%"HWADDR_PRIx"\n", offset);
> return -1;
> }
> - return xto->read_handler(tctx, offset, size);
> + return xto->read_handler(xptr, tctx, offset, size);
> }
>
> /*
> @@ -508,7 +514,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size)
> */
> xto = xive_tm_find_op(offset, size, false);
> if (xto) {
> - return xto->read_handler(tctx, offset, size);
> + return xto->read_handler(xptr, tctx, offset, size);
> }
>
> /*
> @@ -522,14 +528,14 @@ static void xive_tm_write(void *opaque, hwaddr offset,
> {
> XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
>
> - xive_tctx_tm_write(tctx, offset, value, size);
> + xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size);
> }
>
> static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size)
> {
> XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
>
> - return xive_tctx_tm_read(tctx, offset, size);
> + return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size);
> }
>
> const MemoryRegionOps xive_tm_ops = {
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v6 13/20] ppc/pnv: Clarify how the TIMA is accessed on a multichip system
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
` (11 preceding siblings ...)
2019-11-25 6:58 ` [PATCH v6 12/20] ppc/xive: Extend the TIMA operation with a XivePresenter parameter Cédric Le Goater
@ 2019-11-25 6:58 ` Cédric Le Goater
2019-11-27 5:23 ` David Gibson
2019-11-25 6:58 ` [PATCH v6 14/20] ppc/xive: Move the TIMA operations to the controller model Cédric Le Goater
` (7 subsequent siblings)
20 siblings, 1 reply; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-25 6:58 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel
The TIMA region gives access to the thread interrupt context registers
of a CPU. It is mapped at the same address on all chips and can be
accessed by any CPU of the system. To identify the chip from which the
access is being done, the PowerBUS uses a 'chip' field in the
load/store messages. QEMU does not model these messages, instead, we
extract the chip id from the CPU PIR and do a lookup at the machine
level to fetch the targeted interrupt controller.
Introduce pnv_get_chip() and pnv_xive_tm_get_xive() helpers to clarify
this process in pnv_xive_get_tctx(). The latter will be removed in the
subsequent patches but the same principle will be kept.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/pnv.h | 3 +++
hw/intc/pnv_xive.c | 40 +++++++++++++++++++++++-----------------
hw/ppc/pnv.c | 14 ++++++++++++++
3 files changed, 40 insertions(+), 17 deletions(-)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index a58cfea3f2fd..3a7bc3c57e0d 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -103,6 +103,7 @@ typedef struct Pnv9Chip {
* A SMT8 fused core is a pair of SMT4 cores.
*/
#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
+#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
typedef struct PnvChipClass {
/*< private >*/
@@ -197,6 +198,8 @@ static inline bool pnv_is_power9(PnvMachineState *pnv)
return pnv_chip_is_power9(pnv->chips[0]);
}
+PnvChip *pnv_get_chip(uint32_t chip_id);
+
#define PNV_FDT_ADDR 0x01000000
#define PNV_TIMEBASE_FREQ 512000000ULL
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 95e9de312cd9..db9d9c11a8f4 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -439,31 +439,37 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
return count;
}
+/*
+ * The TIMA MMIO space is shared among the chips and to identify the
+ * chip from which the access is being done, we extract the chip id
+ * from the PIR.
+ */
+static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu)
+{
+ int pir = ppc_cpu_pir(cpu);
+ PnvChip *chip;
+ PnvXive *xive;
+
+ chip = pnv_get_chip(PNV9_PIR2CHIP(pir));
+ assert(chip);
+ xive = &PNV9_CHIP(chip)->xive;
+
+ if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
+ xive_error(xive, "IC: CPU %x is not enabled", pir);
+ }
+ return xive;
+}
+
static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
- XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
- PnvXive *xive = NULL;
- CPUPPCState *env = &cpu->env;
- int pir = env->spr_cb[SPR_PIR].default_value;
+ PnvXive *xive = pnv_xive_tm_get_xive(cpu);
- /*
- * Perform an extra check on the HW thread enablement.
- *
- * The TIMA is shared among the chips and to identify the chip
- * from which the access is being done, we extract the chip id
- * from the PIR.
- */
- xive = pnv_xive_get_ic((pir >> 8) & 0xf);
if (!xive) {
return NULL;
}
- if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) {
- xive_error(PNV_XIVE(xrtr), "IC: CPU %x is not enabled", pir);
- }
-
- return tctx;
+ return XIVE_TCTX(pnv_cpu_state(cpu)->intc);
}
/*
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 5b8b07f6aedc..fa656858b24a 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1472,6 +1472,20 @@ static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
return total_count;
}
+PnvChip *pnv_get_chip(uint32_t chip_id)
+{
+ PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
+ int i;
+
+ for (i = 0; i < pnv->num_chips; i++) {
+ PnvChip *chip = pnv->chips[i];
+ if (chip->chip_id == chip_id) {
+ return chip;
+ }
+ }
+ return NULL;
+}
+
static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
--
2.21.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH v6 13/20] ppc/pnv: Clarify how the TIMA is accessed on a multichip system
2019-11-25 6:58 ` [PATCH v6 13/20] ppc/pnv: Clarify how the TIMA is accessed on a multichip system Cédric Le Goater
@ 2019-11-27 5:23 ` David Gibson
2019-11-27 6:57 ` Cédric Le Goater
0 siblings, 1 reply; 33+ messages in thread
From: David Gibson @ 2019-11-27 5:23 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, Greg Kurz, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 4708 bytes --]
On Mon, Nov 25, 2019 at 07:58:13AM +0100, Cédric Le Goater wrote:
> The TIMA region gives access to the thread interrupt context registers
> of a CPU. It is mapped at the same address on all chips and can be
> accessed by any CPU of the system. To identify the chip from which the
> access is being done, the PowerBUS uses a 'chip' field in the
> load/store messages. QEMU does not model these messages, instead, we
> extract the chip id from the CPU PIR and do a lookup at the machine
> level to fetch the targeted interrupt controller.
>
> Introduce pnv_get_chip() and pnv_xive_tm_get_xive() helpers to clarify
> this process in pnv_xive_get_tctx(). The latter will be removed in the
> subsequent patches but the same principle will be kept.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> include/hw/ppc/pnv.h | 3 +++
> hw/intc/pnv_xive.c | 40 +++++++++++++++++++++++-----------------
> hw/ppc/pnv.c | 14 ++++++++++++++
> 3 files changed, 40 insertions(+), 17 deletions(-)
>
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index a58cfea3f2fd..3a7bc3c57e0d 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -103,6 +103,7 @@ typedef struct Pnv9Chip {
> * A SMT8 fused core is a pair of SMT4 cores.
> */
> #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
> +#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
>
> typedef struct PnvChipClass {
> /*< private >*/
> @@ -197,6 +198,8 @@ static inline bool pnv_is_power9(PnvMachineState *pnv)
> return pnv_chip_is_power9(pnv->chips[0]);
> }
>
> +PnvChip *pnv_get_chip(uint32_t chip_id);
> +
> #define PNV_FDT_ADDR 0x01000000
> #define PNV_TIMEBASE_FREQ 512000000ULL
>
> diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
> index 95e9de312cd9..db9d9c11a8f4 100644
> --- a/hw/intc/pnv_xive.c
> +++ b/hw/intc/pnv_xive.c
> @@ -439,31 +439,37 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
> return count;
> }
>
> +/*
> + * The TIMA MMIO space is shared among the chips and to identify the
> + * chip from which the access is being done, we extract the chip id
> + * from the PIR.
> + */
> +static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu)
> +{
> + int pir = ppc_cpu_pir(cpu);
> + PnvChip *chip;
> + PnvXive *xive;
> +
> + chip = pnv_get_chip(PNV9_PIR2CHIP(pir));
> + assert(chip);
> + xive = &PNV9_CHIP(chip)->xive;
> +
> + if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
> + xive_error(xive, "IC: CPU %x is not enabled", pir);
> + }
> + return xive;
> +}
> +
> static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
> {
> PowerPCCPU *cpu = POWERPC_CPU(cs);
> - XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
> - PnvXive *xive = NULL;
> - CPUPPCState *env = &cpu->env;
> - int pir = env->spr_cb[SPR_PIR].default_value;
> + PnvXive *xive = pnv_xive_tm_get_xive(cpu);
>
> - /*
> - * Perform an extra check on the HW thread enablement.
> - *
> - * The TIMA is shared among the chips and to identify the chip
> - * from which the access is being done, we extract the chip id
> - * from the PIR.
> - */
> - xive = pnv_xive_get_ic((pir >> 8) & 0xf);
> if (!xive) {
> return NULL;
> }
>
> - if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) {
I'm not seeing any code which will replace this check on the thread
enabled register. Is that really what you intend?
> - xive_error(PNV_XIVE(xrtr), "IC: CPU %x is not enabled", pir);
> - }
> -
> - return tctx;
> + return XIVE_TCTX(pnv_cpu_state(cpu)->intc);
> }
>
> /*
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 5b8b07f6aedc..fa656858b24a 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1472,6 +1472,20 @@ static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
> return total_count;
> }
>
> +PnvChip *pnv_get_chip(uint32_t chip_id)
> +{
> + PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
> + int i;
> +
> + for (i = 0; i < pnv->num_chips; i++) {
> + PnvChip *chip = pnv->chips[i];
> + if (chip->chip_id == chip_id) {
> + return chip;
> + }
> + }
> + return NULL;
> +}
> +
> static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
> void *opaque, Error **errp)
> {
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH v6 13/20] ppc/pnv: Clarify how the TIMA is accessed on a multichip system
2019-11-27 5:23 ` David Gibson
@ 2019-11-27 6:57 ` Cédric Le Goater
2019-11-28 1:30 ` David Gibson
0 siblings, 1 reply; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-27 6:57 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, Greg Kurz, qemu-devel
On 27/11/2019 06:23, David Gibson wrote:
> On Mon, Nov 25, 2019 at 07:58:13AM +0100, Cédric Le Goater wrote:
>> The TIMA region gives access to the thread interrupt context registers
>> of a CPU. It is mapped at the same address on all chips and can be
>> accessed by any CPU of the system. To identify the chip from which the
>> access is being done, the PowerBUS uses a 'chip' field in the
>> load/store messages. QEMU does not model these messages, instead, we
>> extract the chip id from the CPU PIR and do a lookup at the machine
>> level to fetch the targeted interrupt controller.
>>
>> Introduce pnv_get_chip() and pnv_xive_tm_get_xive() helpers to clarify
>> this process in pnv_xive_get_tctx(). The latter will be removed in the
>> subsequent patches but the same principle will be kept.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> include/hw/ppc/pnv.h | 3 +++
>> hw/intc/pnv_xive.c | 40 +++++++++++++++++++++++-----------------
>> hw/ppc/pnv.c | 14 ++++++++++++++
>> 3 files changed, 40 insertions(+), 17 deletions(-)
>>
>> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
>> index a58cfea3f2fd..3a7bc3c57e0d 100644
>> --- a/include/hw/ppc/pnv.h
>> +++ b/include/hw/ppc/pnv.h
>> @@ -103,6 +103,7 @@ typedef struct Pnv9Chip {
>> * A SMT8 fused core is a pair of SMT4 cores.
>> */
>> #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
>> +#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
>>
>> typedef struct PnvChipClass {
>> /*< private >*/
>> @@ -197,6 +198,8 @@ static inline bool pnv_is_power9(PnvMachineState *pnv)
>> return pnv_chip_is_power9(pnv->chips[0]);
>> }
>>
>> +PnvChip *pnv_get_chip(uint32_t chip_id);
>> +
>> #define PNV_FDT_ADDR 0x01000000
>> #define PNV_TIMEBASE_FREQ 512000000ULL
>>
>> diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
>> index 95e9de312cd9..db9d9c11a8f4 100644
>> --- a/hw/intc/pnv_xive.c
>> +++ b/hw/intc/pnv_xive.c
>> @@ -439,31 +439,37 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
>> return count;
>> }
>>
>> +/*
>> + * The TIMA MMIO space is shared among the chips and to identify the
>> + * chip from which the access is being done, we extract the chip id
>> + * from the PIR.
>> + */
>> +static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu)
>> +{
>> + int pir = ppc_cpu_pir(cpu);
>> + PnvChip *chip;
>> + PnvXive *xive;
>> +
>> + chip = pnv_get_chip(PNV9_PIR2CHIP(pir));
>> + assert(chip);
>> + xive = &PNV9_CHIP(chip)->xive;
>> +
>> + if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
>> + xive_error(xive, "IC: CPU %x is not enabled", pir);
>> + }
>> + return xive;
>> +}
>> +
>> static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
>> {
>> PowerPCCPU *cpu = POWERPC_CPU(cs);
>> - XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
>> - PnvXive *xive = NULL;
>> - CPUPPCState *env = &cpu->env;
>> - int pir = env->spr_cb[SPR_PIR].default_value;
>> + PnvXive *xive = pnv_xive_tm_get_xive(cpu);
>>
>> - /*
>> - * Perform an extra check on the HW thread enablement.
>> - *
>> - * The TIMA is shared among the chips and to identify the chip
>> - * from which the access is being done, we extract the chip id
>> - * from the PIR.
>> - */
>> - xive = pnv_xive_get_ic((pir >> 8) & 0xf);
>> if (!xive) {
>> return NULL;
>> }
>>
>> - if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) {
>
> I'm not seeing any code which will replace this check on the thread
> enabled register. Is that really what you intend?
it is calling pnv_xive_tm_get_xive() which calls pnv_xive_is_cpu_enabled()
which does the same check in better.
C.
>
>> - xive_error(PNV_XIVE(xrtr), "IC: CPU %x is not enabled", pir);
>> - }
>> -
>> - return tctx;
>> + return XIVE_TCTX(pnv_cpu_state(cpu)->intc);
>> }
>>
>> /*
>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
>> index 5b8b07f6aedc..fa656858b24a 100644
>> --- a/hw/ppc/pnv.c
>> +++ b/hw/ppc/pnv.c
>> @@ -1472,6 +1472,20 @@ static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
>> return total_count;
>> }
>>
>> +PnvChip *pnv_get_chip(uint32_t chip_id)
>> +{
>> + PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
>> + int i;
>> +
>> + for (i = 0; i < pnv->num_chips; i++) {
>> + PnvChip *chip = pnv->chips[i];
>> + if (chip->chip_id == chip_id) {
>> + return chip;
>> + }
>> + }
>> + return NULL;
>> +}
>> +
>> static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
>> void *opaque, Error **errp)
>> {
>
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH v6 13/20] ppc/pnv: Clarify how the TIMA is accessed on a multichip system
2019-11-27 6:57 ` Cédric Le Goater
@ 2019-11-28 1:30 ` David Gibson
0 siblings, 0 replies; 33+ messages in thread
From: David Gibson @ 2019-11-28 1:30 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, Greg Kurz, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 4350 bytes --]
On Wed, Nov 27, 2019 at 07:57:31AM +0100, Cédric Le Goater wrote:
> On 27/11/2019 06:23, David Gibson wrote:
> > On Mon, Nov 25, 2019 at 07:58:13AM +0100, Cédric Le Goater wrote:
> >> The TIMA region gives access to the thread interrupt context registers
> >> of a CPU. It is mapped at the same address on all chips and can be
> >> accessed by any CPU of the system. To identify the chip from which the
> >> access is being done, the PowerBUS uses a 'chip' field in the
> >> load/store messages. QEMU does not model these messages, instead, we
> >> extract the chip id from the CPU PIR and do a lookup at the machine
> >> level to fetch the targeted interrupt controller.
> >>
> >> Introduce pnv_get_chip() and pnv_xive_tm_get_xive() helpers to clarify
> >> this process in pnv_xive_get_tctx(). The latter will be removed in the
> >> subsequent patches but the same principle will be kept.
> >>
> >> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> >> ---
> >> include/hw/ppc/pnv.h | 3 +++
> >> hw/intc/pnv_xive.c | 40 +++++++++++++++++++++++-----------------
> >> hw/ppc/pnv.c | 14 ++++++++++++++
> >> 3 files changed, 40 insertions(+), 17 deletions(-)
> >>
> >> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> >> index a58cfea3f2fd..3a7bc3c57e0d 100644
> >> --- a/include/hw/ppc/pnv.h
> >> +++ b/include/hw/ppc/pnv.h
> >> @@ -103,6 +103,7 @@ typedef struct Pnv9Chip {
> >> * A SMT8 fused core is a pair of SMT4 cores.
> >> */
> >> #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
> >> +#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
> >>
> >> typedef struct PnvChipClass {
> >> /*< private >*/
> >> @@ -197,6 +198,8 @@ static inline bool pnv_is_power9(PnvMachineState *pnv)
> >> return pnv_chip_is_power9(pnv->chips[0]);
> >> }
> >>
> >> +PnvChip *pnv_get_chip(uint32_t chip_id);
> >> +
> >> #define PNV_FDT_ADDR 0x01000000
> >> #define PNV_TIMEBASE_FREQ 512000000ULL
> >>
> >> diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
> >> index 95e9de312cd9..db9d9c11a8f4 100644
> >> --- a/hw/intc/pnv_xive.c
> >> +++ b/hw/intc/pnv_xive.c
> >> @@ -439,31 +439,37 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
> >> return count;
> >> }
> >>
> >> +/*
> >> + * The TIMA MMIO space is shared among the chips and to identify the
> >> + * chip from which the access is being done, we extract the chip id
> >> + * from the PIR.
> >> + */
> >> +static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu)
> >> +{
> >> + int pir = ppc_cpu_pir(cpu);
> >> + PnvChip *chip;
> >> + PnvXive *xive;
> >> +
> >> + chip = pnv_get_chip(PNV9_PIR2CHIP(pir));
> >> + assert(chip);
> >> + xive = &PNV9_CHIP(chip)->xive;
> >> +
> >> + if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
> >> + xive_error(xive, "IC: CPU %x is not enabled", pir);
> >> + }
> >> + return xive;
> >> +}
> >> +
> >> static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
> >> {
> >> PowerPCCPU *cpu = POWERPC_CPU(cs);
> >> - XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
> >> - PnvXive *xive = NULL;
> >> - CPUPPCState *env = &cpu->env;
> >> - int pir = env->spr_cb[SPR_PIR].default_value;
> >> + PnvXive *xive = pnv_xive_tm_get_xive(cpu);
> >>
> >> - /*
> >> - * Perform an extra check on the HW thread enablement.
> >> - *
> >> - * The TIMA is shared among the chips and to identify the chip
> >> - * from which the access is being done, we extract the chip id
> >> - * from the PIR.
> >> - */
> >> - xive = pnv_xive_get_ic((pir >> 8) & 0xf);
> >> if (!xive) {
> >> return NULL;
> >> }
> >>
> >> - if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) {
> >
> > I'm not seeing any code which will replace this check on the thread
> > enabled register. Is that really what you intend?
>
> it is calling pnv_xive_tm_get_xive() which calls pnv_xive_is_cpu_enabled()
> which does the same check in better.
Ah, yes of course, thanks.
Applied to ppc-for-5.0.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v6 14/20] ppc/xive: Move the TIMA operations to the controller model
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
` (12 preceding siblings ...)
2019-11-25 6:58 ` [PATCH v6 13/20] ppc/pnv: Clarify how the TIMA is accessed on a multichip system Cédric Le Goater
@ 2019-11-25 6:58 ` Cédric Le Goater
2019-11-25 6:58 ` [PATCH v6 15/20] ppc/xive: Remove the get_tctx() XiveRouter handler Cédric Le Goater
` (6 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-25 6:58 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel
On the P9 Processor, the thread interrupt context registers of a CPU
can be accessed "directly" when by load/store from the CPU or
"indirectly" by the IC through an indirect TIMA page. This requires to
configure first the PC_TCTXT_INDIRx registers.
Today, we rely on the get_tctx() handler to deduce from the CPU PIR
the chip from which the TIMA access is being done. By handling the
TIMA memory ops under the interrupt controller model of each machine,
we can uniformize the TIMA direct and indirect ops under PowerNV. We
can also check that the CPUs have been enabled in the XIVE controller.
This prepares ground for the future versions of XIVE.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/xive.h | 1 -
hw/intc/pnv_xive.c | 35 ++++++++++++++++++++++++++++++++++-
hw/intc/spapr_xive.c | 33 +++++++++++++++++++++++++++++++--
hw/intc/xive.c | 29 -----------------------------
4 files changed, 65 insertions(+), 33 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 97bbcddb381d..dcf897451589 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -462,7 +462,6 @@ typedef struct XiveENDSource {
#define XIVE_TM_OS_PAGE 0x2
#define XIVE_TM_USER_PAGE 0x3
-extern const MemoryRegionOps xive_tm_ops;
void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
uint64_t value, unsigned size);
uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index db9d9c11a8f4..c14a2d186960 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -1467,6 +1467,39 @@ static const MemoryRegionOps xive_tm_indirect_ops = {
},
};
+static void pnv_xive_tm_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
+ PnvXive *xive = pnv_xive_tm_get_xive(cpu);
+ XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+
+ xive_tctx_tm_write(XIVE_PRESENTER(xive), tctx, offset, value, size);
+}
+
+static uint64_t pnv_xive_tm_read(void *opaque, hwaddr offset, unsigned size)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
+ PnvXive *xive = pnv_xive_tm_get_xive(cpu);
+ XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+
+ return xive_tctx_tm_read(XIVE_PRESENTER(xive), tctx, offset, size);
+}
+
+const MemoryRegionOps pnv_xive_tm_ops = {
+ .read = pnv_xive_tm_read,
+ .write = pnv_xive_tm_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+};
+
/*
* Interrupt controller XSCOM region.
*/
@@ -1809,7 +1842,7 @@ static void pnv_xive_realize(DeviceState *dev, Error **errp)
"xive-pc", PNV9_XIVE_PC_SIZE);
/* Thread Interrupt Management Area (Direct) */
- memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops,
+ memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &pnv_xive_tm_ops,
xive, "xive-tima", PNV9_XIVE_TM_SIZE);
qemu_register_reset(pnv_xive_reset, dev);
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index bb3b2dfdb77f..6292da58f62c 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -205,6 +205,35 @@ void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable)
memory_region_set_enabled(&xive->end_source.esb_mmio, false);
}
+static void spapr_xive_tm_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ XiveTCTX *tctx = spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx;
+
+ xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size);
+}
+
+static uint64_t spapr_xive_tm_read(void *opaque, hwaddr offset, unsigned size)
+{
+ XiveTCTX *tctx = spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx;
+
+ return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size);
+}
+
+const MemoryRegionOps spapr_xive_tm_ops = {
+ .read = spapr_xive_tm_read,
+ .write = spapr_xive_tm_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+};
+
static void spapr_xive_end_reset(XiveEND *end)
{
memset(end, 0, sizeof(*end));
@@ -314,8 +343,8 @@ static void spapr_xive_realize(DeviceState *dev, Error **errp)
qemu_register_reset(spapr_xive_reset, dev);
/* TIMA initialization */
- memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive,
- "xive.tima", 4ull << TM_SHIFT);
+ memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &spapr_xive_tm_ops,
+ xive, "xive.tima", 4ull << TM_SHIFT);
sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio);
/*
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 9e7e5ea57c5c..0ca7099f4e55 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -523,35 +523,6 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
return xive_tm_raw_read(tctx, offset, size);
}
-static void xive_tm_write(void *opaque, hwaddr offset,
- uint64_t value, unsigned size)
-{
- XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
-
- xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size);
-}
-
-static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size)
-{
- XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
-
- return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size);
-}
-
-const MemoryRegionOps xive_tm_ops = {
- .read = xive_tm_read,
- .write = xive_tm_write,
- .endianness = DEVICE_BIG_ENDIAN,
- .valid = {
- .min_access_size = 1,
- .max_access_size = 8,
- },
- .impl = {
- .min_access_size = 1,
- .max_access_size = 8,
- },
-};
-
static char *xive_tctx_ring_print(uint8_t *ring)
{
uint32_t w2 = xive_tctx_word2(ring);
--
2.21.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH v6 15/20] ppc/xive: Remove the get_tctx() XiveRouter handler
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
` (13 preceding siblings ...)
2019-11-25 6:58 ` [PATCH v6 14/20] ppc/xive: Move the TIMA operations to the controller model Cédric Le Goater
@ 2019-11-25 6:58 ` Cédric Le Goater
2019-11-28 1:32 ` David Gibson
2019-11-25 6:58 ` [PATCH v6 16/20] ppc/xive: Introduce a xive_tctx_ipb_update() helper Cédric Le Goater
` (5 subsequent siblings)
20 siblings, 1 reply; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-25 6:58 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel
It is now unused.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/xive.h | 2 --
hw/intc/pnv_xive.c | 13 -------------
hw/intc/spapr_xive.c | 8 --------
hw/intc/xive.c | 7 -------
4 files changed, 30 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index dcf897451589..24315480e7c2 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -351,7 +351,6 @@ typedef struct XiveRouterClass {
XiveNVT *nvt);
int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt, uint8_t word_number);
- XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs);
} XiveRouterClass;
int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
@@ -364,7 +363,6 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt);
int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt, uint8_t word_number);
-XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs);
void xive_router_notify(XiveNotifier *xn, uint32_t lisn);
/*
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index c14a2d186960..216ebc150a41 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -460,18 +460,6 @@ static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu)
return xive;
}
-static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
-{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- PnvXive *xive = pnv_xive_tm_get_xive(cpu);
-
- if (!xive) {
- return NULL;
- }
-
- return XIVE_TCTX(pnv_cpu_state(cpu)->intc);
-}
-
/*
* The internal sources (IPIs) of the interrupt controller have no
* knowledge of the XIVE chip on which they reside. Encode the block
@@ -1900,7 +1888,6 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data)
xrc->write_end = pnv_xive_write_end;
xrc->get_nvt = pnv_xive_get_nvt;
xrc->write_nvt = pnv_xive_write_nvt;
- xrc->get_tctx = pnv_xive_get_tctx;
xnc->notify = pnv_xive_notify;
xpc->match_nvt = pnv_xive_match_nvt;
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 6292da58f62c..1542cef91878 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -427,13 +427,6 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk,
g_assert_not_reached();
}
-static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
-{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
-
- return spapr_cpu_state(cpu)->tctx;
-}
-
static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint8_t priority,
@@ -771,7 +764,6 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
xrc->write_end = spapr_xive_write_end;
xrc->get_nvt = spapr_xive_get_nvt;
xrc->write_nvt = spapr_xive_write_nvt;
- xrc->get_tctx = spapr_xive_get_tctx;
sicc->activate = spapr_xive_activate;
sicc->deactivate = spapr_xive_deactivate;
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 0ca7099f4e55..4bff3abdc3eb 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1317,13 +1317,6 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number);
}
-XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs)
-{
- XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
-
- return xrc->get_tctx(xrtr, cs);
-}
-
/*
* Encode the HW CAM line in the block group mode format :
*
--
2.21.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH v6 15/20] ppc/xive: Remove the get_tctx() XiveRouter handler
2019-11-25 6:58 ` [PATCH v6 15/20] ppc/xive: Remove the get_tctx() XiveRouter handler Cédric Le Goater
@ 2019-11-28 1:32 ` David Gibson
0 siblings, 0 replies; 33+ messages in thread
From: David Gibson @ 2019-11-28 1:32 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, Greg Kurz, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 4356 bytes --]
On Mon, Nov 25, 2019 at 07:58:15AM +0100, Cédric Le Goater wrote:
> It is now unused.
>
> Reviewed-by: Greg Kurz <groug@kaod.org>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
14..15 applied to ppc-for-5.0.
> ---
> include/hw/ppc/xive.h | 2 --
> hw/intc/pnv_xive.c | 13 -------------
> hw/intc/spapr_xive.c | 8 --------
> hw/intc/xive.c | 7 -------
> 4 files changed, 30 deletions(-)
>
> diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
> index dcf897451589..24315480e7c2 100644
> --- a/include/hw/ppc/xive.h
> +++ b/include/hw/ppc/xive.h
> @@ -351,7 +351,6 @@ typedef struct XiveRouterClass {
> XiveNVT *nvt);
> int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
> XiveNVT *nvt, uint8_t word_number);
> - XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs);
> } XiveRouterClass;
>
> int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
> @@ -364,7 +363,6 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
> XiveNVT *nvt);
> int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
> XiveNVT *nvt, uint8_t word_number);
> -XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs);
> void xive_router_notify(XiveNotifier *xn, uint32_t lisn);
>
> /*
> diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
> index c14a2d186960..216ebc150a41 100644
> --- a/hw/intc/pnv_xive.c
> +++ b/hw/intc/pnv_xive.c
> @@ -460,18 +460,6 @@ static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu)
> return xive;
> }
>
> -static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
> -{
> - PowerPCCPU *cpu = POWERPC_CPU(cs);
> - PnvXive *xive = pnv_xive_tm_get_xive(cpu);
> -
> - if (!xive) {
> - return NULL;
> - }
> -
> - return XIVE_TCTX(pnv_cpu_state(cpu)->intc);
> -}
> -
> /*
> * The internal sources (IPIs) of the interrupt controller have no
> * knowledge of the XIVE chip on which they reside. Encode the block
> @@ -1900,7 +1888,6 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data)
> xrc->write_end = pnv_xive_write_end;
> xrc->get_nvt = pnv_xive_get_nvt;
> xrc->write_nvt = pnv_xive_write_nvt;
> - xrc->get_tctx = pnv_xive_get_tctx;
>
> xnc->notify = pnv_xive_notify;
> xpc->match_nvt = pnv_xive_match_nvt;
> diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
> index 6292da58f62c..1542cef91878 100644
> --- a/hw/intc/spapr_xive.c
> +++ b/hw/intc/spapr_xive.c
> @@ -427,13 +427,6 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk,
> g_assert_not_reached();
> }
>
> -static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
> -{
> - PowerPCCPU *cpu = POWERPC_CPU(cs);
> -
> - return spapr_cpu_state(cpu)->tctx;
> -}
> -
> static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format,
> uint8_t nvt_blk, uint32_t nvt_idx,
> bool cam_ignore, uint8_t priority,
> @@ -771,7 +764,6 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
> xrc->write_end = spapr_xive_write_end;
> xrc->get_nvt = spapr_xive_get_nvt;
> xrc->write_nvt = spapr_xive_write_nvt;
> - xrc->get_tctx = spapr_xive_get_tctx;
>
> sicc->activate = spapr_xive_activate;
> sicc->deactivate = spapr_xive_deactivate;
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index 0ca7099f4e55..4bff3abdc3eb 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -1317,13 +1317,6 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
> return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number);
> }
>
> -XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs)
> -{
> - XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
> -
> - return xrc->get_tctx(xrtr, cs);
> -}
> -
> /*
> * Encode the HW CAM line in the block group mode format :
> *
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v6 16/20] ppc/xive: Introduce a xive_tctx_ipb_update() helper
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
` (14 preceding siblings ...)
2019-11-25 6:58 ` [PATCH v6 15/20] ppc/xive: Remove the get_tctx() XiveRouter handler Cédric Le Goater
@ 2019-11-25 6:58 ` Cédric Le Goater
2019-11-27 8:50 ` Greg Kurz
2019-11-25 6:58 ` [PATCH v6 17/20] ppc/xive: Synthesize interrupt from the saved IPB in the NVT Cédric Le Goater
` (4 subsequent siblings)
20 siblings, 1 reply; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-25 6:58 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel
We will use it to resend missed interrupts when a vCPU context is
pushed on a HW thread.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/xive.h | 1 +
hw/intc/xive.c | 21 +++++++++++----------
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 24315480e7c2..9c0bf2c301e2 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -469,6 +469,7 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp);
void xive_tctx_reset(XiveTCTX *tctx);
void xive_tctx_destroy(XiveTCTX *tctx);
+void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb);
/*
* KVM XIVE device helpers
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 4bff3abdc3eb..7047e45daca1 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -47,12 +47,6 @@ static uint8_t ipb_to_pipr(uint8_t ibp)
return ibp ? clz32((uint32_t)ibp << 24) : 0xff;
}
-static void ipb_update(uint8_t *regs, uint8_t priority)
-{
- regs[TM_IPB] |= priority_to_ipb(priority);
- regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]);
-}
-
static uint8_t exception_mask(uint8_t ring)
{
switch (ring) {
@@ -135,6 +129,15 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
xive_tctx_notify(tctx, ring);
}
+void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb)
+{
+ uint8_t *regs = &tctx->regs[ring];
+
+ regs[TM_IPB] |= ipb;
+ regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]);
+ xive_tctx_notify(tctx, ring);
+}
+
static inline uint32_t xive_tctx_word2(uint8_t *ring)
{
return *((uint32_t *) &ring[TM_WORD2]);
@@ -336,8 +339,7 @@ static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,
static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx,
hwaddr offset, uint64_t value, unsigned size)
{
- ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff);
- xive_tctx_notify(tctx, TM_QW1_OS);
+ xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff));
}
static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk,
@@ -1429,8 +1431,7 @@ static bool xive_presenter_notify(uint8_t format,
/* handle CPU exception delivery */
if (count) {
- ipb_update(&match.tctx->regs[match.ring], priority);
- xive_tctx_notify(match.tctx, match.ring);
+ xive_tctx_ipb_update(match.tctx, match.ring, priority_to_ipb(priority));
}
return !!count;
--
2.21.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH v6 16/20] ppc/xive: Introduce a xive_tctx_ipb_update() helper
2019-11-25 6:58 ` [PATCH v6 16/20] ppc/xive: Introduce a xive_tctx_ipb_update() helper Cédric Le Goater
@ 2019-11-27 8:50 ` Greg Kurz
2019-11-28 1:35 ` David Gibson
0 siblings, 1 reply; 33+ messages in thread
From: Greg Kurz @ 2019-11-27 8:50 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel, David Gibson
On Mon, 25 Nov 2019 07:58:16 +0100
Cédric Le Goater <clg@kaod.org> wrote:
> We will use it to resend missed interrupts when a vCPU context is
> pushed on a HW thread.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> include/hw/ppc/xive.h | 1 +
> hw/intc/xive.c | 21 +++++++++++----------
> 2 files changed, 12 insertions(+), 10 deletions(-)
>
> diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
> index 24315480e7c2..9c0bf2c301e2 100644
> --- a/include/hw/ppc/xive.h
> +++ b/include/hw/ppc/xive.h
> @@ -469,6 +469,7 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
> Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp);
> void xive_tctx_reset(XiveTCTX *tctx);
> void xive_tctx_destroy(XiveTCTX *tctx);
> +void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb);
>
> /*
> * KVM XIVE device helpers
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index 4bff3abdc3eb..7047e45daca1 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -47,12 +47,6 @@ static uint8_t ipb_to_pipr(uint8_t ibp)
> return ibp ? clz32((uint32_t)ibp << 24) : 0xff;
> }
>
> -static void ipb_update(uint8_t *regs, uint8_t priority)
> -{
> - regs[TM_IPB] |= priority_to_ipb(priority);
> - regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]);
> -}
> -
> static uint8_t exception_mask(uint8_t ring)
> {
> switch (ring) {
> @@ -135,6 +129,15 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
> xive_tctx_notify(tctx, ring);
> }
>
> +void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb)
> +{
> + uint8_t *regs = &tctx->regs[ring];
> +
> + regs[TM_IPB] |= ipb;
> + regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]);
> + xive_tctx_notify(tctx, ring);
> +}
> +
Maybe rename the helper to xive_tctx_update_ipb_and_notify() to
make it clear this raises an irq in the end ?
This can be done as follow-up though and the rest looks good, so:
Reviewed-by: Greg Kurz <groug@kaod.org>
> static inline uint32_t xive_tctx_word2(uint8_t *ring)
> {
> return *((uint32_t *) &ring[TM_WORD2]);
> @@ -336,8 +339,7 @@ static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,
> static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx,
> hwaddr offset, uint64_t value, unsigned size)
> {
> - ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff);
> - xive_tctx_notify(tctx, TM_QW1_OS);
> + xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff));
> }
>
> static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk,
> @@ -1429,8 +1431,7 @@ static bool xive_presenter_notify(uint8_t format,
>
> /* handle CPU exception delivery */
> if (count) {
> - ipb_update(&match.tctx->regs[match.ring], priority);
> - xive_tctx_notify(match.tctx, match.ring);
> + xive_tctx_ipb_update(match.tctx, match.ring, priority_to_ipb(priority));
> }
>
> return !!count;
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH v6 16/20] ppc/xive: Introduce a xive_tctx_ipb_update() helper
2019-11-27 8:50 ` Greg Kurz
@ 2019-11-28 1:35 ` David Gibson
0 siblings, 0 replies; 33+ messages in thread
From: David Gibson @ 2019-11-28 1:35 UTC (permalink / raw)
To: Greg Kurz; +Cc: qemu-ppc, Cédric Le Goater, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 3755 bytes --]
On Wed, Nov 27, 2019 at 09:50:50AM +0100, Greg Kurz wrote:
65;5802;1c> On Mon, 25 Nov 2019 07:58:16 +0100
> Cédric Le Goater <clg@kaod.org> wrote:
>
> > We will use it to resend missed interrupts when a vCPU context is
> > pushed on a HW thread.
> >
> > Signed-off-by: Cédric Le Goater <clg@kaod.org>
> > ---
> > include/hw/ppc/xive.h | 1 +
> > hw/intc/xive.c | 21 +++++++++++----------
> > 2 files changed, 12 insertions(+), 10 deletions(-)
> >
> > diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
> > index 24315480e7c2..9c0bf2c301e2 100644
> > --- a/include/hw/ppc/xive.h
> > +++ b/include/hw/ppc/xive.h
> > @@ -469,6 +469,7 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
> > Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp);
> > void xive_tctx_reset(XiveTCTX *tctx);
> > void xive_tctx_destroy(XiveTCTX *tctx);
> > +void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb);
> >
> > /*
> > * KVM XIVE device helpers
> > diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> > index 4bff3abdc3eb..7047e45daca1 100644
> > --- a/hw/intc/xive.c
> > +++ b/hw/intc/xive.c
> > @@ -47,12 +47,6 @@ static uint8_t ipb_to_pipr(uint8_t ibp)
> > return ibp ? clz32((uint32_t)ibp << 24) : 0xff;
> > }
> >
> > -static void ipb_update(uint8_t *regs, uint8_t priority)
> > -{
> > - regs[TM_IPB] |= priority_to_ipb(priority);
> > - regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]);
> > -}
> > -
> > static uint8_t exception_mask(uint8_t ring)
> > {
> > switch (ring) {
> > @@ -135,6 +129,15 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
> > xive_tctx_notify(tctx, ring);
> > }
> >
> > +void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb)
> > +{
> > + uint8_t *regs = &tctx->regs[ring];
> > +
> > + regs[TM_IPB] |= ipb;
> > + regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]);
> > + xive_tctx_notify(tctx, ring);
> > +}
> > +
>
> Maybe rename the helper to xive_tctx_update_ipb_and_notify() to
> make it clear this raises an irq in the end ?
I'm actually happy enough with the name as is. I think it's
reasonable for "update" on a register which has active effects on the
real hardware to implicitly have the same effects in the qemu model.
Applied to ppc-for-5.0.
>
> This can be done as follow-up though and the rest looks good, so:
>
> Reviewed-by: Greg Kurz <groug@kaod.org>
>
> > static inline uint32_t xive_tctx_word2(uint8_t *ring)
> > {
> > return *((uint32_t *) &ring[TM_WORD2]);
> > @@ -336,8 +339,7 @@ static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,
> > static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx,
> > hwaddr offset, uint64_t value, unsigned size)
> > {
> > - ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff);
> > - xive_tctx_notify(tctx, TM_QW1_OS);
> > + xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff));
> > }
> >
> > static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk,
> > @@ -1429,8 +1431,7 @@ static bool xive_presenter_notify(uint8_t format,
> >
> > /* handle CPU exception delivery */
> > if (count) {
> > - ipb_update(&match.tctx->regs[match.ring], priority);
> > - xive_tctx_notify(match.tctx, match.ring);
> > + xive_tctx_ipb_update(match.tctx, match.ring, priority_to_ipb(priority));
> > }
> >
> > return !!count;
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v6 17/20] ppc/xive: Synthesize interrupt from the saved IPB in the NVT
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
` (15 preceding siblings ...)
2019-11-25 6:58 ` [PATCH v6 16/20] ppc/xive: Introduce a xive_tctx_ipb_update() helper Cédric Le Goater
@ 2019-11-25 6:58 ` Cédric Le Goater
2019-11-25 6:58 ` [PATCH v6 18/20] ppc/pnv: Introduce a pnv_xive_block_id() helper Cédric Le Goater
` (3 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-25 6:58 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel
When a vCPU is dispatched on a HW thread, its context is pushed in the
thread registers and it is activated by setting the VO bit in the CAM
line word2. The HW grabs the associated NVT, pulls the IPB bits and
merges them with the IPB of the new context. If interrupts were missed
while the vCPU was not dispatched, these are synthesized in this
sequence.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/intc/xive.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 7047e45daca1..e022bb7afd28 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -393,6 +393,57 @@ static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
return qw1w2;
}
+static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx,
+ uint8_t nvt_blk, uint32_t nvt_idx)
+{
+ XiveNVT nvt;
+ uint8_t ipb;
+
+ /*
+ * Grab the associated NVT to pull the pending bits, and merge
+ * them with the IPB of the thread interrupt context registers
+ */
+ if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n",
+ nvt_blk, nvt_idx);
+ return;
+ }
+
+ ipb = xive_get_field32(NVT_W4_IPB, nvt.w4);
+
+ if (ipb) {
+ /* Reset the NVT value */
+ nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, 0);
+ xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4);
+
+ /* Merge in current context */
+ xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb);
+ }
+}
+
+/*
+ * Updating the OS CAM line can trigger a resend of interrupt
+ */
+static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
+{
+ uint32_t cam = value;
+ uint32_t qw1w2 = cpu_to_be32(cam);
+ uint8_t nvt_blk;
+ uint32_t nvt_idx;
+ bool vo;
+
+ xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo);
+
+ /* First update the registers */
+ xive_tctx_set_os_cam(tctx, qw1w2);
+
+ /* Check the interrupt pending bits */
+ if (vo) {
+ xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx);
+ }
+}
+
/*
* Define a mapping of "special" operations depending on the TIMA page
* offset and the size of the operation.
@@ -414,6 +465,7 @@ static const XiveTmOp xive_tm_operations[] = {
* effects
*/
{ XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL },
+ { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, NULL },
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL },
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL },
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll },
--
2.21.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH v6 18/20] ppc/pnv: Introduce a pnv_xive_block_id() helper
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
` (16 preceding siblings ...)
2019-11-25 6:58 ` [PATCH v6 17/20] ppc/xive: Synthesize interrupt from the saved IPB in the NVT Cédric Le Goater
@ 2019-11-25 6:58 ` Cédric Le Goater
2019-11-25 6:58 ` [PATCH v6 19/20] ppc/pnv: Extend XiveRouter with a get_block_id() handler Cédric Le Goater
` (2 subsequent siblings)
20 siblings, 0 replies; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-25 6:58 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel
When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID field
overrides the hardwired chip ID in the Powerbus operations and for CAM
compares. This is typically used in the one block-per-chip configuration
to associate a unique block id number to each IC of the system.
Simplify the model with a pnv_xive_block_id() helper and remove
'tctx_chipid' which becomes useless.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/pnv_xive.h | 3 --
hw/intc/pnv_xive.c | 64 ++++++++++++++++++++-------------------
2 files changed, 33 insertions(+), 34 deletions(-)
diff --git a/include/hw/ppc/pnv_xive.h b/include/hw/ppc/pnv_xive.h
index 4fdaa9247d65..f4c7caad40ee 100644
--- a/include/hw/ppc/pnv_xive.h
+++ b/include/hw/ppc/pnv_xive.h
@@ -72,9 +72,6 @@ typedef struct PnvXive {
/* Interrupt controller registers */
uint64_t regs[0x300];
- /* Can be configured by FW */
- uint32_t tctx_chipid;
-
/*
* Virtual Structure Descriptor tables : EAT, SBE, ENDT, NVTT, IRQ
* These are in a SRAM protected by ECC.
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 216ebc150a41..23e73641f254 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -85,13 +85,30 @@ static inline uint64_t SETFIELD(uint64_t mask, uint64_t word,
return (word & ~mask) | ((value << ctz64(mask)) & mask);
}
+/*
+ * When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID
+ * field overrides the hardwired chip ID in the Powerbus operations
+ * and for CAM compares
+ */
+static uint8_t pnv_xive_block_id(PnvXive *xive)
+{
+ uint8_t blk = xive->chip->chip_id;
+ uint64_t cfg_val = xive->regs[PC_TCTXT_CFG >> 3];
+
+ if (cfg_val & PC_TCTXT_CHIPID_OVERRIDE) {
+ blk = GETFIELD(PC_TCTXT_CHIPID, cfg_val);
+ }
+
+ return blk;
+}
+
/*
* Remote access to controllers. HW uses MMIOs. For now, a simple scan
* of the chips is good enough.
*
* TODO: Block scope support
*/
-static PnvXive *pnv_xive_get_ic(uint8_t blk)
+static PnvXive *pnv_xive_get_remote(uint8_t blk)
{
PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
int i;
@@ -100,7 +117,7 @@ static PnvXive *pnv_xive_get_ic(uint8_t blk)
Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
PnvXive *xive = &chip9->xive;
- if (xive->chip->chip_id == blk) {
+ if (pnv_xive_block_id(xive) == blk) {
return xive;
}
}
@@ -216,7 +233,7 @@ static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32_t type, uint8_t blk,
/* Remote VST access */
if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) {
- xive = pnv_xive_get_ic(blk);
+ xive = pnv_xive_get_remote(blk);
return xive ? pnv_xive_vst_addr(xive, type, blk, idx) : 0;
}
@@ -364,7 +381,10 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
{
PnvXive *xive = PNV_XIVE(xrtr);
- if (pnv_xive_get_ic(blk) != xive) {
+ /*
+ * EAT lookups should be local to the IC
+ */
+ if (pnv_xive_block_id(xive) != blk) {
xive_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx));
return -1;
}
@@ -470,7 +490,7 @@ static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu)
static void pnv_xive_notify(XiveNotifier *xn, uint32_t srcno)
{
PnvXive *xive = PNV_XIVE(xn);
- uint8_t blk = xive->chip->chip_id;
+ uint8_t blk = pnv_xive_block_id(xive);
xive_router_notify(xn, XIVE_EAS(blk, srcno));
}
@@ -834,20 +854,7 @@ static void pnv_xive_ic_reg_write(void *opaque, hwaddr offset,
case PC_TCTXT_CFG:
/*
* TODO: block group support
- *
- * PC_TCTXT_CFG_BLKGRP_EN
- * PC_TCTXT_CFG_HARD_CHIPID_BLK :
- * Moves the chipid into block field for hardwired CAM compares.
- * Block offset value is adjusted to 0b0..01 & ThrdId
- *
- * Will require changes in xive_presenter_tctx_match(). I am
- * not sure how to handle that yet.
*/
-
- /* Overrides hardwired chip ID with the chip ID field */
- if (val & PC_TCTXT_CHIPID_OVERRIDE) {
- xive->tctx_chipid = GETFIELD(PC_TCTXT_CHIPID, val);
- }
break;
case PC_TCTXT_TRACK:
/*
@@ -1656,19 +1663,20 @@ static const MemoryRegionOps pnv_xive_pc_ops = {
void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
{
XiveRouter *xrtr = XIVE_ROUTER(xive);
- uint8_t blk = xive->chip->chip_id;
+ uint8_t blk = pnv_xive_block_id(xive);
+ uint8_t chip_id = xive->chip->chip_id;
uint32_t srcno0 = XIVE_EAS(blk, 0);
uint32_t nr_ipis = pnv_xive_nr_ipis(xive, blk);
XiveEAS eas;
XiveEND end;
int i;
- monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0,
- srcno0 + nr_ipis - 1);
+ monitor_printf(mon, "XIVE[%x] #%d Source %08x .. %08x\n", chip_id, blk,
+ srcno0, srcno0 + nr_ipis - 1);
xive_source_pic_print_info(&xive->ipi_source, srcno0, mon);
- monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0,
- srcno0 + nr_ipis - 1);
+ monitor_printf(mon, "XIVE[%x] #%d EAT %08x .. %08x\n", chip_id, blk,
+ srcno0, srcno0 + nr_ipis - 1);
for (i = 0; i < nr_ipis; i++) {
if (xive_router_get_eas(xrtr, blk, i, &eas)) {
break;
@@ -1678,13 +1686,13 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
}
}
- monitor_printf(mon, "XIVE[%x] ENDT\n", blk);
+ monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk);
i = 0;
while (!xive_router_get_end(xrtr, blk, i, &end)) {
xive_end_pic_print_info(&end, i++, mon);
}
- monitor_printf(mon, "XIVE[%x] END Escalation EAT\n", blk);
+ monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk);
i = 0;
while (!xive_router_get_end(xrtr, blk, i, &end)) {
xive_end_eas_pic_print_info(&end, i++, mon);
@@ -1697,12 +1705,6 @@ static void pnv_xive_reset(void *dev)
XiveSource *xsrc = &xive->ipi_source;
XiveENDSource *end_xsrc = &xive->end_source;
- /*
- * Use the PnvChip id to identify the XIVE interrupt controller.
- * It can be overriden by configuration at runtime.
- */
- xive->tctx_chipid = xive->chip->chip_id;
-
/* Default page size (Should be changed at runtime to 64k) */
xive->ic_shift = xive->vc_shift = xive->pc_shift = 12;
--
2.21.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH v6 19/20] ppc/pnv: Extend XiveRouter with a get_block_id() handler
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
` (17 preceding siblings ...)
2019-11-25 6:58 ` [PATCH v6 18/20] ppc/pnv: Introduce a pnv_xive_block_id() helper Cédric Le Goater
@ 2019-11-25 6:58 ` Cédric Le Goater
2019-11-25 6:58 ` [PATCH v6 20/20] ppc/pnv: Dump the XIVE NVT table Cédric Le Goater
2019-11-28 2:18 ` [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests David Gibson
20 siblings, 0 replies; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-25 6:58 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel
When doing CAM line compares, fetch the block id from the interrupt
controller which can have set the PC_TCTXT_CHIPID field.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/xive.h | 2 +-
hw/intc/pnv_xive.c | 6 ++++++
hw/intc/spapr_xive.c | 6 ++++++
hw/intc/xive.c | 21 ++++++++++++++++-----
4 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 9c0bf2c301e2..1b7b89098f71 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -351,6 +351,7 @@ typedef struct XiveRouterClass {
XiveNVT *nvt);
int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt, uint8_t word_number);
+ uint8_t (*get_block_id)(XiveRouter *xrtr);
} XiveRouterClass;
int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
@@ -431,7 +432,6 @@ typedef struct XiveENDSource {
DeviceState parent;
uint32_t nr_ends;
- uint8_t block_id;
/* ESB memory region */
uint32_t esb_shift;
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 23e73641f254..43c760efd137 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -459,6 +459,11 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
return count;
}
+static uint8_t pnv_xive_get_block_id(XiveRouter *xrtr)
+{
+ return pnv_xive_block_id(PNV_XIVE(xrtr));
+}
+
/*
* The TIMA MMIO space is shared among the chips and to identify the
* chip from which the access is being done, we extract the chip id
@@ -1890,6 +1895,7 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data)
xrc->write_end = pnv_xive_write_end;
xrc->get_nvt = pnv_xive_get_nvt;
xrc->write_nvt = pnv_xive_write_nvt;
+ xrc->get_block_id = pnv_xive_get_block_id;
xnc->notify = pnv_xive_notify;
xpc->match_nvt = pnv_xive_match_nvt;
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 1542cef91878..daa0656859a3 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -473,6 +473,11 @@ static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format,
return count;
}
+static uint8_t spapr_xive_get_block_id(XiveRouter *xrtr)
+{
+ return SPAPR_XIVE_BLOCK_ID;
+}
+
static const VMStateDescription vmstate_spapr_xive_end = {
.name = TYPE_SPAPR_XIVE "/end",
.version_id = 1,
@@ -764,6 +769,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
xrc->write_end = spapr_xive_write_end;
xrc->get_nvt = spapr_xive_get_nvt;
xrc->write_nvt = spapr_xive_write_nvt;
+ xrc->get_block_id = spapr_xive_get_block_id;
sicc->activate = spapr_xive_activate;
sicc->deactivate = spapr_xive_deactivate;
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index e022bb7afd28..d4c6e21703b3 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1371,17 +1371,25 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number);
}
+static int xive_router_get_block_id(XiveRouter *xrtr)
+{
+ XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
+
+ return xrc->get_block_id(xrtr);
+}
+
/*
* Encode the HW CAM line in the block group mode format :
*
* chip << 19 | 0000000 0 0001 thread (7Bit)
*/
-static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx)
+static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx)
{
CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
uint32_t pir = env->spr_cb[SPR_PIR].default_value;
+ uint8_t blk = xive_router_get_block_id(XIVE_ROUTER(xptr));
- return xive_nvt_cam_line((pir >> 8) & 0xf, 1 << 7 | (pir & 0x7f));
+ return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f));
}
/*
@@ -1418,7 +1426,7 @@ int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
/* PHYS ring */
if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) &&
- cam == xive_tctx_hw_cam_line(tctx)) {
+ cam == xive_tctx_hw_cam_line(xptr, tctx)) {
return TM_QW3_HV_PHYS;
}
@@ -1755,7 +1763,11 @@ static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size)
uint8_t pq;
uint64_t ret = -1;
- end_blk = xsrc->block_id;
+ /*
+ * The block id should be deduced from the load address on the END
+ * ESB MMIO but our model only supports a single block per XIVE chip.
+ */
+ end_blk = xive_router_get_block_id(xsrc->xrtr);
end_idx = addr >> (xsrc->esb_shift + 1);
if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) {
@@ -1855,7 +1867,6 @@ static void xive_end_source_realize(DeviceState *dev, Error **errp)
}
static Property xive_end_source_properties[] = {
- DEFINE_PROP_UINT8("block-id", XiveENDSource, block_id, 0),
DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0),
DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K),
DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER,
--
2.21.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH v6 20/20] ppc/pnv: Dump the XIVE NVT table
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
` (18 preceding siblings ...)
2019-11-25 6:58 ` [PATCH v6 19/20] ppc/pnv: Extend XiveRouter with a get_block_id() handler Cédric Le Goater
@ 2019-11-25 6:58 ` Cédric Le Goater
2019-11-28 2:18 ` [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests David Gibson
20 siblings, 0 replies; 33+ messages in thread
From: Cédric Le Goater @ 2019-11-25 6:58 UTC (permalink / raw)
To: David Gibson; +Cc: Cédric Le Goater, qemu-ppc, Greg Kurz, qemu-devel
This is useful to dump the saved contexts of the vCPUs : configuration
of the base END index of the vCPU and the Interrupt Pending Buffer
register, which is updated when an interrupt can not be presented.
When dumping the NVT table, we skip empty indirect pages which are not
necessarily allocated.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/xive_regs.h | 3 ++
hw/intc/pnv_xive.c | 64 ++++++++++++++++++++++++++++++++++++++
2 files changed, 67 insertions(+)
diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h
index 1a5622f8ded8..09f243600c5d 100644
--- a/include/hw/ppc/xive_regs.h
+++ b/include/hw/ppc/xive_regs.h
@@ -252,6 +252,8 @@ typedef struct XiveNVT {
uint32_t w0;
#define NVT_W0_VALID PPC_BIT32(0)
uint32_t w1;
+#define NVT_W1_EQ_BLOCK PPC_BITMASK32(0, 3)
+#define NVT_W1_EQ_INDEX PPC_BITMASK32(4, 31)
uint32_t w2;
uint32_t w3;
uint32_t w4;
@@ -277,6 +279,7 @@ typedef struct XiveNVT {
* field of the XIVE END
*/
#define XIVE_NVT_SHIFT 19
+#define XIVE_NVT_COUNT (1 << XIVE_NVT_SHIFT)
static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx)
{
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 43c760efd137..a0a69b98a713 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -527,6 +527,44 @@ static uint32_t pnv_xive_nr_ipis(PnvXive *xive, uint8_t blk)
return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE;
}
+/*
+ * Compute the number of entries per indirect subpage.
+ */
+static uint64_t pnv_xive_vst_per_subpage(PnvXive *xive, uint32_t type)
+{
+ uint8_t blk = pnv_xive_block_id(xive);
+ uint64_t vsd = xive->vsds[type][blk];
+ const XiveVstInfo *info = &vst_infos[type];
+ uint64_t vsd_addr;
+ uint32_t page_shift;
+
+ /* For direct tables, fake a valid value */
+ if (!(VSD_INDIRECT & vsd)) {
+ return 1;
+ }
+
+ /* Get the page size of the indirect table. */
+ vsd_addr = vsd & VSD_ADDRESS_MASK;
+ vsd = ldq_be_dma(&address_space_memory, vsd_addr);
+
+ if (!(vsd & VSD_ADDRESS_MASK)) {
+#ifdef XIVE_DEBUG
+ xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx);
+#endif
+ return 0;
+ }
+
+ page_shift = GETFIELD(VSD_TSIZE, vsd) + 12;
+
+ if (!pnv_xive_vst_page_size_allowed(page_shift)) {
+ xive_error(xive, "VST: invalid %s page shift %d", info->name,
+ page_shift);
+ return 0;
+ }
+
+ return (1ull << page_shift) / info->size;
+}
+
/*
* EDT Table
*
@@ -1665,6 +1703,21 @@ static const MemoryRegionOps pnv_xive_pc_ops = {
},
};
+static void xive_nvt_pic_print_info(XiveNVT *nvt, uint32_t nvt_idx,
+ Monitor *mon)
+{
+ uint8_t eq_blk = xive_get_field32(NVT_W1_EQ_BLOCK, nvt->w1);
+ uint32_t eq_idx = xive_get_field32(NVT_W1_EQ_INDEX, nvt->w1);
+
+ if (!xive_nvt_is_valid(nvt)) {
+ return;
+ }
+
+ monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x\n", nvt_idx,
+ eq_blk, eq_idx,
+ xive_get_field32(NVT_W4_IPB, nvt->w4));
+}
+
void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
{
XiveRouter *xrtr = XIVE_ROUTER(xive);
@@ -1674,7 +1727,9 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
uint32_t nr_ipis = pnv_xive_nr_ipis(xive, blk);
XiveEAS eas;
XiveEND end;
+ XiveNVT nvt;
int i;
+ uint64_t xive_nvt_per_subpage;
monitor_printf(mon, "XIVE[%x] #%d Source %08x .. %08x\n", chip_id, blk,
srcno0, srcno0 + nr_ipis - 1);
@@ -1702,6 +1757,15 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
while (!xive_router_get_end(xrtr, blk, i, &end)) {
xive_end_eas_pic_print_info(&end, i++, mon);
}
+
+ monitor_printf(mon, "XIVE[%x] #%d NVTT %08x .. %08x\n", chip_id, blk,
+ 0, XIVE_NVT_COUNT - 1);
+ xive_nvt_per_subpage = pnv_xive_vst_per_subpage(xive, VST_TSEL_VPDT);
+ for (i = 0; i < XIVE_NVT_COUNT; i += xive_nvt_per_subpage) {
+ while (!xive_router_get_nvt(xrtr, blk, i, &nvt)) {
+ xive_nvt_pic_print_info(&nvt, i++, mon);
+ }
+ }
}
static void pnv_xive_reset(void *dev)
--
2.21.0
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests
2019-11-25 6:58 [PATCH v6 00/20] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
` (19 preceding siblings ...)
2019-11-25 6:58 ` [PATCH v6 20/20] ppc/pnv: Dump the XIVE NVT table Cédric Le Goater
@ 2019-11-28 2:18 ` David Gibson
20 siblings, 0 replies; 33+ messages in thread
From: David Gibson @ 2019-11-28 2:18 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, Greg Kurz, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1739 bytes --]
On Mon, Nov 25, 2019 at 07:58:00AM +0100, Cédric Le Goater wrote:
> Hello,
>
> The QEMU PowerNV machine emulates a baremetal OpenPOWER system and
> acts as an hypervisor (L0). Supporting emulation of KVM to run guests
> (L1) requires a few more extensions, among which guest support for the
> XIVE interrupt controller on POWER9 processor.
>
> The following changes extend the XIVE models with the new XiveFabric
> and XivePresenter interfaces to provide support for XIVE escalations
> and interrupt resend. This mechanism is used by XIVE to notify the
> hypervisor that a vCPU is not dispatched on a HW thread. Tested on a
> QEMU PowerNV machine and a simple QEMU pseries guest doing network on
> a local bridge.
>
> The XIVE interrupt controller offers a way to increase the XIVE
> resources per chip by configuring multiple XIVE blocks on a chip. This
> is not currently supported by the model. However, some configurations,
> such as OPAL/skiboot, use one block-per-chip configuration with some
> optimizations. One of them is to override the hardwired chip ID by the
> block id in the PowerBUS operations and for CAM line compares. This
> patchset improves the support for this setup. Tested with 4 chips.
>
> A series from Suraj adding guest support in the Radix MMU model of the
> QEMU PowerNV machine is still required and will be send later. The
> whole patchset can be found under :
>
> https://github.com/legoater/qemu/tree/powernv-4.2
I now have all of this applied to the ppc-for-5.0 branch.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 33+ messages in thread