* [PATCH 1/2] drm/i915/dp: Define each HBR link rate
@ 2019-12-03 2:31 ` José Roberto de Souza
0 siblings, 0 replies; 14+ messages in thread
From: José Roberto de Souza @ 2019-12-03 2:31 UTC (permalink / raw)
To: intel-gfx
This is better than keep those values in the code that you always
need to check the DP spec to know what level of HBR it is.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a976606d21c7..914f0cc4d237 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -49,6 +49,10 @@
#include "intel_tc.h"
#include "intel_vdsc.h"
+#define HBR_RATE 270000
+#define HBR2_RATE 540000
+#define HBR3_RATE 810000
+
struct ddi_buf_trans {
u32 trans1; /* balance leg enable, de-emph level */
u32 trans2; /* vref sel, vswing */
@@ -888,7 +892,7 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
if (type == INTEL_OUTPUT_HDMI) {
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
return icl_combo_phy_ddi_translations_hdmi;
- } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
+ } else if (rate > HBR2_RATE && type == INTEL_OUTPUT_EDP) {
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
return icl_combo_phy_ddi_translations_edp_hbr3;
} else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
--
2.24.0
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915/dp: Define each HBR link rate
@ 2019-12-03 2:31 ` José Roberto de Souza
0 siblings, 0 replies; 14+ messages in thread
From: José Roberto de Souza @ 2019-12-03 2:31 UTC (permalink / raw)
To: intel-gfx
This is better than keep those values in the code that you always
need to check the DP spec to know what level of HBR it is.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a976606d21c7..914f0cc4d237 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -49,6 +49,10 @@
#include "intel_tc.h"
#include "intel_vdsc.h"
+#define HBR_RATE 270000
+#define HBR2_RATE 540000
+#define HBR3_RATE 810000
+
struct ddi_buf_trans {
u32 trans1; /* balance leg enable, de-emph level */
u32 trans2; /* vref sel, vswing */
@@ -888,7 +892,7 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
if (type == INTEL_OUTPUT_HDMI) {
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
return icl_combo_phy_ddi_translations_hdmi;
- } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
+ } else if (rate > HBR2_RATE && type == INTEL_OUTPUT_EDP) {
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
return icl_combo_phy_ddi_translations_edp_hbr3;
} else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
--
2.24.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/2] drm/i915/dp/tgl+: Update combo phy vswing tables
@ 2019-12-03 2:31 ` José Roberto de Souza
0 siblings, 0 replies; 14+ messages in thread
From: José Roberto de Souza @ 2019-12-03 2:31 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
TGL has now a table for RBR and HBR and another table for HBR2 over
combo phys. The HBR2 one has some small changes comparing to the ICL
one, so adding two new tables and adding a function to return TGL
combo phy tables.
BSpec: 49291
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 66 ++++++++++++++++++++++--
1 file changed, 62 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 914f0cc4d237..facf3dfa2a41 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -625,6 +625,34 @@ static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = {
{ 0x0, 0x0, 0xA }, /* 10 Full -3 dB */
};
+static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
+ { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
+ { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
+ { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
+ { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
+};
+
+static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
+ { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
+ { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
+ { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
+};
+
static const struct ddi_buf_trans *
bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
{
@@ -904,6 +932,32 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
return icl_combo_phy_ddi_translations_dp_hbr2;
}
+static const struct cnl_ddi_buf_trans *
+tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
+ int *n_entries)
+{
+ if (type == INTEL_OUTPUT_HDMI) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+ return icl_combo_phy_ddi_translations_hdmi;
+ } else if (type == INTEL_OUTPUT_EDP) {
+ if (rate > HBR2_RATE) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
+ return icl_combo_phy_ddi_translations_edp_hbr3;
+ } else if (dev_priv->vbt.edp.low_vswing) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
+ return icl_combo_phy_ddi_translations_edp_hbr2;
+ }
+ }
+
+ if (rate > HBR_RATE) {
+ *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
+ return tgl_combo_phy_ddi_translations_dp_hbr2;
+ }
+
+ *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
+ return tgl_combo_phy_ddi_translations_dp_hbr;
+}
+
static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
{
struct ddi_vbt_port_info *port_info = &dev_priv->vbt.ddi_port_info[port];
@@ -912,7 +966,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
if (INTEL_GEN(dev_priv) >= 12) {
if (intel_phy_is_combo(dev_priv, phy))
- icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
+ tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
0, &n_entries);
else
n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
@@ -2373,7 +2427,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
if (INTEL_GEN(dev_priv) >= 12) {
if (intel_phy_is_combo(dev_priv, phy))
- icl_get_combo_buf_trans(dev_priv, encoder->type,
+ tgl_get_combo_buf_trans(dev_priv, encoder->type,
intel_dp->link_rate, &n_entries);
else
n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
@@ -2568,8 +2622,12 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
u32 n_entries, val;
int ln;
- ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
- &n_entries);
+ if (INTEL_GEN(dev_priv) >= 12)
+ ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate,
+ &n_entries);
+ else
+ ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
+ &n_entries);
if (!ddi_translations)
return;
--
2.24.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/dp/tgl+: Update combo phy vswing tables
@ 2019-12-03 2:31 ` José Roberto de Souza
0 siblings, 0 replies; 14+ messages in thread
From: José Roberto de Souza @ 2019-12-03 2:31 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
TGL has now a table for RBR and HBR and another table for HBR2 over
combo phys. The HBR2 one has some small changes comparing to the ICL
one, so adding two new tables and adding a function to return TGL
combo phy tables.
BSpec: 49291
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 66 ++++++++++++++++++++++--
1 file changed, 62 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 914f0cc4d237..facf3dfa2a41 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -625,6 +625,34 @@ static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = {
{ 0x0, 0x0, 0xA }, /* 10 Full -3 dB */
};
+static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
+ { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
+ { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
+ { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
+ { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
+};
+
+static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
+ { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
+ { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
+ { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
+};
+
static const struct ddi_buf_trans *
bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
{
@@ -904,6 +932,32 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
return icl_combo_phy_ddi_translations_dp_hbr2;
}
+static const struct cnl_ddi_buf_trans *
+tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
+ int *n_entries)
+{
+ if (type == INTEL_OUTPUT_HDMI) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+ return icl_combo_phy_ddi_translations_hdmi;
+ } else if (type == INTEL_OUTPUT_EDP) {
+ if (rate > HBR2_RATE) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
+ return icl_combo_phy_ddi_translations_edp_hbr3;
+ } else if (dev_priv->vbt.edp.low_vswing) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
+ return icl_combo_phy_ddi_translations_edp_hbr2;
+ }
+ }
+
+ if (rate > HBR_RATE) {
+ *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
+ return tgl_combo_phy_ddi_translations_dp_hbr2;
+ }
+
+ *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
+ return tgl_combo_phy_ddi_translations_dp_hbr;
+}
+
static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
{
struct ddi_vbt_port_info *port_info = &dev_priv->vbt.ddi_port_info[port];
@@ -912,7 +966,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
if (INTEL_GEN(dev_priv) >= 12) {
if (intel_phy_is_combo(dev_priv, phy))
- icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
+ tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
0, &n_entries);
else
n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
@@ -2373,7 +2427,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
if (INTEL_GEN(dev_priv) >= 12) {
if (intel_phy_is_combo(dev_priv, phy))
- icl_get_combo_buf_trans(dev_priv, encoder->type,
+ tgl_get_combo_buf_trans(dev_priv, encoder->type,
intel_dp->link_rate, &n_entries);
else
n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
@@ -2568,8 +2622,12 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
u32 n_entries, val;
int ln;
- ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
- &n_entries);
+ if (INTEL_GEN(dev_priv) >= 12)
+ ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate,
+ &n_entries);
+ else
+ ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
+ &n_entries);
if (!ddi_translations)
return;
--
2.24.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dp: Define each HBR link rate
@ 2019-12-03 3:09 ` Patchwork
0 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-12-03 3:09 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: Define each HBR link rate
URL : https://patchwork.freedesktop.org/series/70323/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7467 -> Patchwork_15551
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15551:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@reload-with-fault-injection:
- {fi-kbl-7560u}: [DMESG-WARN][1] ([i915#109] / [i915#92]) -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
Known issues
------------
Here are the changes found in Patchwork_15551 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_blt:
- fi-hsw-4770r: [PASS][3] -> [DMESG-FAIL][4] ([i915#553])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-hsw-4770r/igt@i915_selftest@live_blt.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/fi-hsw-4770r/igt@i915_selftest@live_blt.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: [PASS][5] -> [FAIL][6] ([i915#49])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [DMESG-WARN][7] ([i915#592]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_blt:
- fi-ivb-3770: [DMESG-FAIL][9] ([i915#563]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-ivb-3770/igt@i915_selftest@live_blt.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/fi-ivb-3770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-skl-lmem: [INCOMPLETE][11] ([i915#424]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +4 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
[i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
[i915#592]: https://gitlab.freedesktop.org/drm/intel/issues/592
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (50 -> 45)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7467 -> Patchwork_15551
CI-20190529: 20190529
CI_DRM_7467: 14954f24e7251b067b2081aaa09a7da6840da0d5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5321: 9df50aef49e0da4413609d9866b41b82b725f2a0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15551: 2500c1251a86c57e9894105ec3056abd9cda88e1 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2500c1251a86 drm/i915/dp/tgl+: Update combo phy vswing tables
5f29a191967a drm/i915/dp: Define each HBR link rate
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dp: Define each HBR link rate
@ 2019-12-03 3:09 ` Patchwork
0 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-12-03 3:09 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: Define each HBR link rate
URL : https://patchwork.freedesktop.org/series/70323/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7467 -> Patchwork_15551
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15551:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@reload-with-fault-injection:
- {fi-kbl-7560u}: [DMESG-WARN][1] ([i915#109] / [i915#92]) -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
Known issues
------------
Here are the changes found in Patchwork_15551 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_blt:
- fi-hsw-4770r: [PASS][3] -> [DMESG-FAIL][4] ([i915#553])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-hsw-4770r/igt@i915_selftest@live_blt.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/fi-hsw-4770r/igt@i915_selftest@live_blt.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: [PASS][5] -> [FAIL][6] ([i915#49])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [DMESG-WARN][7] ([i915#592]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_blt:
- fi-ivb-3770: [DMESG-FAIL][9] ([i915#563]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-ivb-3770/igt@i915_selftest@live_blt.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/fi-ivb-3770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-skl-lmem: [INCOMPLETE][11] ([i915#424]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +4 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
[i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
[i915#592]: https://gitlab.freedesktop.org/drm/intel/issues/592
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (50 -> 45)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7467 -> Patchwork_15551
CI-20190529: 20190529
CI_DRM_7467: 14954f24e7251b067b2081aaa09a7da6840da0d5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5321: 9df50aef49e0da4413609d9866b41b82b725f2a0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15551: 2500c1251a86c57e9894105ec3056abd9cda88e1 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2500c1251a86 drm/i915/dp/tgl+: Update combo phy vswing tables
5f29a191967a drm/i915/dp: Define each HBR link rate
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/dp: Define each HBR link rate
2019-12-03 2:31 ` [Intel-gfx] " José Roberto de Souza
` (2 preceding siblings ...)
(?)
@ 2019-12-03 9:08 ` Jani Nikula
2019-12-03 13:11 ` Ville Syrjälä
-1 siblings, 1 reply; 14+ messages in thread
From: Jani Nikula @ 2019-12-03 9:08 UTC (permalink / raw)
To: José Roberto de Souza, intel-gfx
On Mon, 02 Dec 2019, José Roberto de Souza <jose.souza@intel.com> wrote:
> This is better than keep those values in the code that you always
> need to check the DP spec to know what level of HBR it is.
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a976606d21c7..914f0cc4d237 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -49,6 +49,10 @@
> #include "intel_tc.h"
> #include "intel_vdsc.h"
>
> +#define HBR_RATE 270000
> +#define HBR2_RATE 540000
> +#define HBR3_RATE 810000
> +
> struct ddi_buf_trans {
> u32 trans1; /* balance leg enable, de-emph level */
> u32 trans2; /* vref sel, vswing */
> @@ -888,7 +892,7 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> if (type == INTEL_OUTPUT_HDMI) {
> *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> return icl_combo_phy_ddi_translations_hdmi;
> - } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
> + } else if (rate > HBR2_RATE && type == INTEL_OUTPUT_EDP) {
I don't want a patch switching some random place to using a
macro. Either we stick to numbers or switch all.
And if switch all, add the rates to drm core, not locally to
intel_ddi.c. (And then wonder what to do with the intermediate rates in
intel_dp_set_source_rates()...)
Personally, HBR<N> is less useful to me in code, it's the actual rate
that helps me.
But I'll trust Ville's judgement on this one.
BR,
Jani.
> *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> return icl_combo_phy_ddi_translations_edp_hbr3;
> } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/dp: Define each HBR link rate
2019-12-03 2:31 ` [Intel-gfx] " José Roberto de Souza
` (3 preceding siblings ...)
(?)
@ 2019-12-03 9:21 ` Patchwork
-1 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-12-03 9:21 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: Define each HBR link rate
URL : https://patchwork.freedesktop.org/series/70323/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7467_full -> Patchwork_15551_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15551_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15551_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15551_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_blt:
- shard-hsw: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-hsw1/igt@i915_selftest@live_blt.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-hsw5/igt@i915_selftest@live_blt.html
* igt@kms_draw_crc@draw-method-rgb565-blt-xtiled:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-skl6/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-skl8/igt@kms_draw_crc@draw-method-rgb565-blt-xtiled.html
Known issues
------------
Here are the changes found in Patchwork_15551_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_parallel@vcs0-contexts:
- shard-hsw: [PASS][5] -> [TIMEOUT][6] ([i915#676]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-hsw2/igt@gem_exec_parallel@vcs0-contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-hsw4/igt@gem_exec_parallel@vcs0-contexts.html
* igt@gem_exec_schedule@preempt-contexts-bsd2:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-iclb4/igt@gem_exec_schedule@preempt-contexts-bsd2.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-iclb8/igt@gem_exec_schedule@preempt-contexts-bsd2.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-iclb3/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_sync@basic-store-all:
- shard-tglb: [PASS][11] -> [INCOMPLETE][12] ([i915#472])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-tglb4/igt@gem_sync@basic-store-all.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-tglb3/igt@gem_sync@basic-store-all.html
* igt@gem_workarounds@suspend-resume-context:
- shard-tglb: [PASS][13] -> [INCOMPLETE][14] ([i915#456] / [i915#460])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-tglb9/igt@gem_workarounds@suspend-resume-context.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-tglb3/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +3 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-kbl4/igt@i915_suspend@debugfs-reader.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-kbl7/igt@i915_suspend@debugfs-reader.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen:
- shard-hsw: [PASS][17] -> [DMESG-WARN][18] ([IGT#6])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-hsw4/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-hsw6/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-random:
- shard-iclb: [PASS][19] -> [DMESG-WARN][20] ([IGT#6])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-iclb6/igt@kms_cursor_crc@pipe-b-cursor-128x42-random.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-iclb3/igt@kms_cursor_crc@pipe-b-cursor-128x42-random.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-tglb: [PASS][21] -> [INCOMPLETE][22] ([i915#460])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-tglb1/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_flip_tiling@flip-to-x-tiled:
- shard-iclb: [PASS][23] -> [FAIL][24] ([i915#167])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-iclb3/igt@kms_flip_tiling@flip-to-x-tiled.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-iclb4/igt@kms_flip_tiling@flip-to-x-tiled.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
- shard-tglb: [PASS][25] -> [FAIL][26] ([i915#49]) +2 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-tglb9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render:
- shard-iclb: [PASS][27] -> [FAIL][28] ([i915#49]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt:
- shard-tglb: [PASS][29] -> [INCOMPLETE][30] ([fdo#112393] / [i915#435])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-tglb4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [PASS][31] -> [DMESG-WARN][32] ([i915#180])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_setmode@basic:
- shard-skl: [PASS][33] -> [FAIL][34] ([i915#31])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-skl8/igt@kms_setmode@basic.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-skl4/igt@kms_setmode@basic.html
* igt@perf_pmu@busy-idle-check-all-vcs1:
- shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#112080]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-iclb4/igt@perf_pmu@busy-idle-check-all-vcs1.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-iclb8/igt@perf_pmu@busy-idle-check-all-vcs1.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [SKIP][37] ([fdo#109276] / [fdo#112080]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-iclb3/igt@gem_ctx_isolation@vcs1-dirty-create.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-iclb4/igt@gem_ctx_isolation@vcs1-dirty-create.html
* igt@gem_exec_parallel@vcs0-fds:
- shard-hsw: [FAIL][39] ([i915#676]) -> [PASS][40] +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-hsw6/igt@gem_exec_parallel@vcs0-fds.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-hsw2/igt@gem_exec_parallel@vcs0-fds.html
* igt@gem_exec_schedule@preempt-queue-chain-vebox:
- shard-iclb: [INCOMPLETE][41] ([i915#140]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-iclb5/igt@gem_exec_schedule@preempt-queue-chain-vebox.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-iclb4/igt@gem_exec_schedule@preempt-queue-chain-vebox.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-snb: [DMESG-WARN][43] ([fdo#111870]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-snb7/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@i915_pm_dc@dc5-dpms:
- shard-iclb: [FAIL][45] ([i915#447]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-iclb5/igt@i915_pm_dc@dc5-dpms.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-skl: [INCOMPLETE][47] ([i915#151] / [i915#69]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-skl6/igt@i915_pm_rpm@system-suspend-execbuf.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-skl7/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@i915_suspend@forcewake:
- shard-kbl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +3 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-kbl2/igt@i915_suspend@forcewake.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-kbl3/igt@i915_suspend@forcewake.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-180:
- shard-tglb: [INCOMPLETE][51] ([i915#667]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-tglb1/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-tglb7/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
- shard-skl: [INCOMPLETE][53] ([fdo#112347] / [i915#655]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-skl2/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-skl7/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-90:
- shard-tglb: [INCOMPLETE][55] ([i915#435]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-tglb4/igt@kms_big_fb@y-tiled-16bpp-rotate-90.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-tglb7/igt@kms_big_fb@y-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
- shard-glk: [INCOMPLETE][57] ([i915#58] / [k.org#198133]) -> [PASS][58] +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-glk5/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-glk2/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-hsw: [FAIL][59] ([i915#57]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-hsw4/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][61] ([i915#79]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-skl4/igt@kms_flip@flip-vs-expired-vblank.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend:
- shard-hsw: [INCOMPLETE][63] ([i915#61]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-hsw5/igt@kms_flip@flip-vs-suspend.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-hsw4/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [DMESG-WARN][65] ([i915#180]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
- shard-tglb: [INCOMPLETE][67] ([i915#456] / [i915#460] / [i915#474]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-suspend.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render:
- shard-tglb: [FAIL][69] ([i915#49]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt:
- shard-iclb: [FAIL][71] ([i915#49]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt:
- shard-skl: [FAIL][73] ([i915#49]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_plane@pixel-format-pipe-a-planes:
- shard-kbl: [INCOMPLETE][75] ([fdo#103665]) -> [PASS][76] +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-kbl1/igt@kms_plane@pixel-format-pipe-a-planes.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-kbl3/igt@kms_plane@pixel-format-pipe-a-planes.html
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-iclb: [INCOMPLETE][77] ([i915#140] / [i915#246]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-iclb8/igt@kms_plane@pixel-format-pipe-c-planes-source-clamping.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-iclb8/igt@kms_plane@pixel-format-pipe-c-planes-source-clamping.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][79] ([fdo#108145]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][81] ([fdo#109642] / [fdo#111068]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-iclb6/igt@kms_psr2_su@frontbuffer.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [SKIP][83] ([fdo#109441]) -> [PASS][84] +2 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-iclb4/igt@kms_psr@psr2_primary_mmap_gtt.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_psr@psr2_suspend:
- shard-tglb: [INCOMPLETE][85] ([i915#456] / [i915#460]) -> [PASS][86] +2 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-tglb4/igt@kms_psr@psr2_suspend.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-tglb6/igt@kms_psr@psr2_suspend.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][87] ([i915#31]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-apl7/igt@kms_setmode@basic.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-apl1/igt@kms_setmode@basic.html
* igt@perf_pmu@busy-accuracy-98-vcs1:
- shard-iclb: [SKIP][89] ([fdo#112080]) -> [PASS][90] +6 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-iclb6/igt@perf_pmu@busy-accuracy-98-vcs1.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-iclb2/igt@perf_pmu@busy-accuracy-98-vcs1.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][91] ([fdo#109276]) -> [PASS][92] +9 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-iclb6/igt@prime_vgem@fence-wait-bsd2.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [SKIP][93] ([fdo#109276] / [fdo#112080]) -> [FAIL][94] ([IGT#28])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_ctx_isolation@vcs2-reset:
- shard-tglb: [SKIP][95] ([fdo#111912] / [fdo#112080]) -> [SKIP][96] ([fdo#112080])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-tglb7/igt@gem_ctx_isolation@vcs2-reset.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-tglb9/igt@gem_ctx_isolation@vcs2-reset.html
* igt@gem_softpin@noreloc-s3:
- shard-apl: [DMESG-WARN][97] ([i915#180]) -> [INCOMPLETE][98] ([fdo#103927])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-apl8/igt@gem_softpin@noreloc-s3.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-apl3/igt@gem_softpin@noreloc-s3.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-kbl: [DMESG-WARN][99] ([i915#180]) -> [INCOMPLETE][100] ([fdo#103665] / [i915#600])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-skl: [INCOMPLETE][101] ([fdo#112347] / [i915#648]) -> [INCOMPLETE][102] ([fdo#112347] / [fdo#112391] / [i915#648])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/shard-skl5/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/shard-skl7/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#111912]: https://bugs.freedesktop.org/show_bug.cgi?id=111912
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[fdo#112347]: https://bugs.freedesktop.org/show_bug.cgi?id=112347
[fdo#112391]: https://bugs.freedesktop.org/show_bug.cgi?id=112391
[fdo#112393]: https://bugs.freedesktop.org/show_bug.cgi?id=112393
[i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#167]: https://gitlab.freedesktop.org/drm/intel/issues/167
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#246]: https://gitlab.freedesktop.org/drm/intel/issues/246
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435
[i915#447]: https://gitlab.freedesktop.org/drm/intel/issues/447
[i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
[i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460
[i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
[i915#474]: https://gitlab.freedesktop.org/drm/intel/issues/474
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#57]: https://gitlab.freedesktop.org/drm/intel/issues/57
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#600]: https://gitlab.freedesktop.org/drm/intel/issues/600
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648
[i915#655]: https://gitlab.freedesktop.org/drm/intel/issues/655
[i915#667]: https://gitlab.freedesktop.org/drm/intel/issues/667
[i915#669]: https://gitlab.freedesktop.org/drm/intel/issues/669
[i915#676]: https://gitlab.freedesktop.org/drm/intel/issues/676
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7467 -> Patchwork_15551
CI-20190529: 20190529
CI_DRM_7467: 14954f24e7251b067b2081aaa09a7da6840da0d5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5321: 9df50aef49e0da4413609d9866b41b82b725f2a0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15551: 2500c1251a86c57e9894105ec3056abd9cda88e1 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15551/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/dp: Define each HBR link rate
2019-12-03 9:08 ` [Intel-gfx] [PATCH 1/2] " Jani Nikula
@ 2019-12-03 13:11 ` Ville Syrjälä
2019-12-03 21:48 ` Souza, Jose
2019-12-03 22:01 ` Manasi Navare
0 siblings, 2 replies; 14+ messages in thread
From: Ville Syrjälä @ 2019-12-03 13:11 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Dec 03, 2019 at 11:08:52AM +0200, Jani Nikula wrote:
> On Mon, 02 Dec 2019, José Roberto de Souza <jose.souza@intel.com> wrote:
> > This is better than keep those values in the code that you always
> > need to check the DP spec to know what level of HBR it is.
> >
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++++-
> > 1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index a976606d21c7..914f0cc4d237 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -49,6 +49,10 @@
> > #include "intel_tc.h"
> > #include "intel_vdsc.h"
> >
> > +#define HBR_RATE 270000
> > +#define HBR2_RATE 540000
> > +#define HBR3_RATE 810000
> > +
> > struct ddi_buf_trans {
> > u32 trans1; /* balance leg enable, de-emph level */
> > u32 trans2; /* vref sel, vswing */
> > @@ -888,7 +892,7 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> > if (type == INTEL_OUTPUT_HDMI) {
> > *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> > return icl_combo_phy_ddi_translations_hdmi;
> > - } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
> > + } else if (rate > HBR2_RATE && type == INTEL_OUTPUT_EDP) {
>
> I don't want a patch switching some random place to using a
> macro. Either we stick to numbers or switch all.
>
> And if switch all, add the rates to drm core, not locally to
> intel_ddi.c. (And then wonder what to do with the intermediate rates in
> intel_dp_set_source_rates()...)
Yeah, we'll still end up with a mix of defines and raw numbers.
>
> Personally, HBR<N> is less useful to me in code, it's the actual rate
> that helps me.
>
> But I'll trust Ville's judgement on this one.
I tend to prefer raw numbers for this sort of stuff. If we didn't have
the intermediate rates I might have a different opinion. The only thing
I really worry about with raw numbers is the potential for typos.
The original problem of bspec talking about hbr2 in the bug trans
tables we could probably solve with a comment.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/dp/tgl+: Update combo phy vswing tables
2019-12-03 2:31 ` [Intel-gfx] " José Roberto de Souza
(?)
@ 2019-12-03 13:18 ` Ville Syrjälä
-1 siblings, 0 replies; 14+ messages in thread
From: Ville Syrjälä @ 2019-12-03 13:18 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx, Lucas De Marchi
On Mon, Dec 02, 2019 at 06:31:10PM -0800, José Roberto de Souza wrote:
> TGL has now a table for RBR and HBR and another table for HBR2 over
> combo phys. The HBR2 one has some small changes comparing to the ICL
> one, so adding two new tables and adding a function to return TGL
> combo phy tables.
>
> BSpec: 49291
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 66 ++++++++++++++++++++++--
> 1 file changed, 62 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 914f0cc4d237..facf3dfa2a41 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -625,6 +625,34 @@ static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = {
> { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */
> };
>
> +static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = {
> + /* NT mV Trans mV db */
> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
> + { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
> + { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> + { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
> + { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
> + { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> +};
> +
> +static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = {
> + /* NT mV Trans mV db */
> + { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> + { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> +};
> +
> static const struct ddi_buf_trans *
> bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
> {
> @@ -904,6 +932,32 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> return icl_combo_phy_ddi_translations_dp_hbr2;
> }
>
> +static const struct cnl_ddi_buf_trans *
> +tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> + int *n_entries)
> +{
> + if (type == INTEL_OUTPUT_HDMI) {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> + return icl_combo_phy_ddi_translations_hdmi;
> + } else if (type == INTEL_OUTPUT_EDP) {
> + if (rate > HBR2_RATE) {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> + return icl_combo_phy_ddi_translations_edp_hbr3;
> + } else if (dev_priv->vbt.edp.low_vswing) {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
> + return icl_combo_phy_ddi_translations_edp_hbr2;
> + }
> + }
> +
> + if (rate > HBR_RATE) {
> + *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
> + return tgl_combo_phy_ddi_translations_dp_hbr2;
> + }
ICL uses just a single if-else ladder. IMO should do the same here for
consistency.
> +
> + *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
> + return tgl_combo_phy_ddi_translations_dp_hbr;
> +}
> +
> static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
> {
> struct ddi_vbt_port_info *port_info = &dev_priv->vbt.ddi_port_info[port];
> @@ -912,7 +966,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
>
> if (INTEL_GEN(dev_priv) >= 12) {
> if (intel_phy_is_combo(dev_priv, phy))
> - icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
> + tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
> 0, &n_entries);
> else
> n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
> @@ -2373,7 +2427,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
>
> if (INTEL_GEN(dev_priv) >= 12) {
> if (intel_phy_is_combo(dev_priv, phy))
> - icl_get_combo_buf_trans(dev_priv, encoder->type,
> + tgl_get_combo_buf_trans(dev_priv, encoder->type,
> intel_dp->link_rate, &n_entries);
> else
> n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
> @@ -2568,8 +2622,12 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> u32 n_entries, val;
> int ln;
>
> - ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
> - &n_entries);
> + if (INTEL_GEN(dev_priv) >= 12)
> + ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate,
> + &n_entries);
> + else
> + ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
> + &n_entries);
> if (!ddi_translations)
> return;
>
> --
> 2.24.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/dp: Define each HBR link rate
2019-12-03 2:31 ` [Intel-gfx] " José Roberto de Souza
` (4 preceding siblings ...)
(?)
@ 2019-12-03 16:17 ` Matt Roper
-1 siblings, 0 replies; 14+ messages in thread
From: Matt Roper @ 2019-12-03 16:17 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Mon, Dec 02, 2019 at 06:31:09PM -0800, José Roberto de Souza wrote:
> This is better than keep those values in the code that you always
> need to check the DP spec to know what level of HBR it is.
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
I think there are a bunch of other places where we could use these new
macros too, but that can be done in a followup.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
We might want to add RBR (162000) as well for completeness in the
future.
Matt
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a976606d21c7..914f0cc4d237 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -49,6 +49,10 @@
> #include "intel_tc.h"
> #include "intel_vdsc.h"
>
> +#define HBR_RATE 270000
> +#define HBR2_RATE 540000
> +#define HBR3_RATE 810000
> +
> struct ddi_buf_trans {
> u32 trans1; /* balance leg enable, de-emph level */
> u32 trans2; /* vref sel, vswing */
> @@ -888,7 +892,7 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> if (type == INTEL_OUTPUT_HDMI) {
> *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> return icl_combo_phy_ddi_translations_hdmi;
> - } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
> + } else if (rate > HBR2_RATE && type == INTEL_OUTPUT_EDP) {
> *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> return icl_combo_phy_ddi_translations_edp_hbr3;
> } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
> --
> 2.24.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/dp/tgl+: Update combo phy vswing tables
2019-12-03 2:31 ` [Intel-gfx] " José Roberto de Souza
(?)
(?)
@ 2019-12-03 16:35 ` Matt Roper
-1 siblings, 0 replies; 14+ messages in thread
From: Matt Roper @ 2019-12-03 16:35 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx, Lucas De Marchi
On Mon, Dec 02, 2019 at 06:31:10PM -0800, José Roberto de Souza wrote:
> TGL has now a table for RBR and HBR and another table for HBR2 over
> combo phys. The HBR2 one has some small changes comparing to the ICL
> one, so adding two new tables and adding a function to return TGL
> combo phy tables.
>
> BSpec: 49291
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 66 ++++++++++++++++++++++--
> 1 file changed, 62 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 914f0cc4d237..facf3dfa2a41 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -625,6 +625,34 @@ static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = {
> { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */
> };
>
> +static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = {
> + /* NT mV Trans mV db */
> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
> + { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
> + { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> + { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
> + { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
> + { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> +};
> +
> +static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = {
> + /* NT mV Trans mV db */
> + { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> + { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> +};
Maybe switch the order of these two tables so HBR comes first and HBR2
comes second? Doesn't really matter, but that will match the spec's
layout and also how we've ordered things in the past.
> +
> static const struct ddi_buf_trans *
> bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
> {
> @@ -904,6 +932,32 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> return icl_combo_phy_ddi_translations_dp_hbr2;
> }
>
> +static const struct cnl_ddi_buf_trans *
> +tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> + int *n_entries)
> +{
> + if (type == INTEL_OUTPUT_HDMI) {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> + return icl_combo_phy_ddi_translations_hdmi;
> + } else if (type == INTEL_OUTPUT_EDP) {
> + if (rate > HBR2_RATE) {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> + return icl_combo_phy_ddi_translations_edp_hbr3;
> + } else if (dev_priv->vbt.edp.low_vswing) {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
> + return icl_combo_phy_ddi_translations_edp_hbr2;
> + }
> + }
Maybe it would be simpler to do
if (type != INTEL_OUTPUT_DP)
return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);
rather than duplicating this if chain again? Up to you. Regardless,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> +
> + if (rate > HBR_RATE) {
> + *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
> + return tgl_combo_phy_ddi_translations_dp_hbr2;
> + }
> +
> + *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
> + return tgl_combo_phy_ddi_translations_dp_hbr;
> +}
> +
> static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
> {
> struct ddi_vbt_port_info *port_info = &dev_priv->vbt.ddi_port_info[port];
> @@ -912,7 +966,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
>
> if (INTEL_GEN(dev_priv) >= 12) {
> if (intel_phy_is_combo(dev_priv, phy))
> - icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
> + tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
> 0, &n_entries);
> else
> n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
> @@ -2373,7 +2427,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
>
> if (INTEL_GEN(dev_priv) >= 12) {
> if (intel_phy_is_combo(dev_priv, phy))
> - icl_get_combo_buf_trans(dev_priv, encoder->type,
> + tgl_get_combo_buf_trans(dev_priv, encoder->type,
> intel_dp->link_rate, &n_entries);
> else
> n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
> @@ -2568,8 +2622,12 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> u32 n_entries, val;
> int ln;
>
> - ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
> - &n_entries);
> + if (INTEL_GEN(dev_priv) >= 12)
> + ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate,
> + &n_entries);
> + else
> + ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
> + &n_entries);
> if (!ddi_translations)
> return;
>
> --
> 2.24.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/dp: Define each HBR link rate
2019-12-03 13:11 ` Ville Syrjälä
@ 2019-12-03 21:48 ` Souza, Jose
2019-12-03 22:01 ` Manasi Navare
1 sibling, 0 replies; 14+ messages in thread
From: Souza, Jose @ 2019-12-03 21:48 UTC (permalink / raw)
To: ville.syrjala, Roper, Matthew D, jani.nikula; +Cc: intel-gfx
On Tue, 2019-12-03 at 15:11 +0200, Ville Syrjälä wrote:
> On Tue, Dec 03, 2019 at 11:08:52AM +0200, Jani Nikula wrote:
> > On Mon, 02 Dec 2019, José Roberto de Souza <jose.souza@intel.com>
> > wrote:
> > > This is better than keep those values in the code that you always
> > > need to check the DP spec to know what level of HBR it is.
> > >
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++++-
> > > 1 file changed, 5 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index a976606d21c7..914f0cc4d237 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -49,6 +49,10 @@
> > > #include "intel_tc.h"
> > > #include "intel_vdsc.h"
> > >
> > > +#define HBR_RATE 270000
> > > +#define HBR2_RATE 540000
> > > +#define HBR3_RATE 810000
> > > +
> > > struct ddi_buf_trans {
> > > u32 trans1; /* balance leg enable, de-emph level */
> > > u32 trans2; /* vref sel, vswing */
> > > @@ -888,7 +892,7 @@ icl_get_combo_buf_trans(struct
> > > drm_i915_private *dev_priv, int type, int rate,
> > > if (type == INTEL_OUTPUT_HDMI) {
> > > *n_entries =
> > > ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> > > return icl_combo_phy_ddi_translations_hdmi;
> > > - } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
> > > + } else if (rate > HBR2_RATE && type == INTEL_OUTPUT_EDP) {
> >
> > I don't want a patch switching some random place to using a
> > macro. Either we stick to numbers or switch all.
> >
> > And if switch all, add the rates to drm core, not locally to
> > intel_ddi.c. (And then wonder what to do with the intermediate
> > rates in
> > intel_dp_set_source_rates()...)
>
> Yeah, we'll still end up with a mix of defines and raw numbers.
>
> > Personally, HBR<N> is less useful to me in code, it's the actual
> > rate
> > that helps me.
> >
> > But I'll trust Ville's judgement on this one.
>
> I tend to prefer raw numbers for this sort of stuff. If we didn't
> have
> the intermediate rates I might have a different opinion. The only
> thing
> I really worry about with raw numbers is the potential for typos.
>
> The original problem of bspec talking about hbr2 in the bug trans
> tables we could probably solve with a comment.
>
Okay, dropping this change.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/dp: Define each HBR link rate
2019-12-03 13:11 ` Ville Syrjälä
2019-12-03 21:48 ` Souza, Jose
@ 2019-12-03 22:01 ` Manasi Navare
1 sibling, 0 replies; 14+ messages in thread
From: Manasi Navare @ 2019-12-03 22:01 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, Dec 03, 2019 at 03:11:54PM +0200, Ville Syrjälä wrote:
> On Tue, Dec 03, 2019 at 11:08:52AM +0200, Jani Nikula wrote:
> > On Mon, 02 Dec 2019, José Roberto de Souza <jose.souza@intel.com> wrote:
> > > This is better than keep those values in the code that you always
> > > need to check the DP spec to know what level of HBR it is.
> > >
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++++-
> > > 1 file changed, 5 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index a976606d21c7..914f0cc4d237 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -49,6 +49,10 @@
> > > #include "intel_tc.h"
> > > #include "intel_vdsc.h"
> > >
> > > +#define HBR_RATE 270000
> > > +#define HBR2_RATE 540000
> > > +#define HBR3_RATE 810000
> > > +
> > > struct ddi_buf_trans {
> > > u32 trans1; /* balance leg enable, de-emph level */
> > > u32 trans2; /* vref sel, vswing */
> > > @@ -888,7 +892,7 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> > > if (type == INTEL_OUTPUT_HDMI) {
> > > *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> > > return icl_combo_phy_ddi_translations_hdmi;
> > > - } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
> > > + } else if (rate > HBR2_RATE && type == INTEL_OUTPUT_EDP) {
> >
> > I don't want a patch switching some random place to using a
> > macro. Either we stick to numbers or switch all.
> >
> > And if switch all, add the rates to drm core, not locally to
> > intel_ddi.c. (And then wonder what to do with the intermediate rates in
> > intel_dp_set_source_rates()...)
>
> Yeah, we'll still end up with a mix of defines and raw numbers.
>
> >
> > Personally, HBR<N> is less useful to me in code, it's the actual rate
> > that helps me.
> >
> > But I'll trust Ville's judgement on this one.
>
> I tend to prefer raw numbers for this sort of stuff. If we didn't have
> the intermediate rates I might have a different opinion. The only thing
> I really worry about with raw numbers is the potential for typos.
Yes, especially due to the typos and possibilities of missing or adding an extra 0
makes me wonder that it could be a good idea to add all the #defines RBR - HBR3
in drm_dp_helper.h somewhere with proper comments on which of the spec added which rate etc.
Regards
Manasi
>
> The original problem of bspec talking about hbr2 in the bug trans
> tables we could probably solve with a comment.
>
> --
> Ville Syrjälä
> Intel
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2019-12-03 21:57 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-03 2:31 [PATCH 1/2] drm/i915/dp: Define each HBR link rate José Roberto de Souza
2019-12-03 2:31 ` [Intel-gfx] " José Roberto de Souza
2019-12-03 2:31 ` [PATCH 2/2] drm/i915/dp/tgl+: Update combo phy vswing tables José Roberto de Souza
2019-12-03 2:31 ` [Intel-gfx] " José Roberto de Souza
2019-12-03 13:18 ` Ville Syrjälä
2019-12-03 16:35 ` Matt Roper
2019-12-03 3:09 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dp: Define each HBR link rate Patchwork
2019-12-03 3:09 ` [Intel-gfx] " Patchwork
2019-12-03 9:08 ` [Intel-gfx] [PATCH 1/2] " Jani Nikula
2019-12-03 13:11 ` Ville Syrjälä
2019-12-03 21:48 ` Souza, Jose
2019-12-03 22:01 ` Manasi Navare
2019-12-03 9:21 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] " Patchwork
2019-12-03 16:17 ` [Intel-gfx] [PATCH 1/2] " Matt Roper
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