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* The irq Affinity is changed after the patch(Fixes: b1a5a73e64e9 ("genirq/affinity: Spread vectors on node according to nr_cpu ratio"))
@ 2019-11-19  1:25 chenxiang (M)
  2019-11-19  1:42 ` Ming Lei
  0 siblings, 1 reply; 7+ messages in thread
From: chenxiang (M) @ 2019-11-19  1:25 UTC (permalink / raw)
  To: Ming Lei, lkml, tglx; +Cc: kbusch, axboe, linux-block, Linuxarm, John Garry

Hi,

There are 128 cpus and 16 irqs for SAS controller in my system, and 
there are 4 Nodes, every 32 cpus are for one node (cpu0-31 for node0, 
cpu32-63 for node1, cpu64-95 for node2, cpu96-127 for node3).
We use function pci_alloc_irq_vectors_affinity() to set the affinity of 
irqs.

I find that  before the patch (Fixes: b1a5a73e64e9 ("genirq/affinity: 
Spread vectors on node according to nr_cpu ratio")), the relationship 
between irqs and cpus is: irq0 bind to cpu0-7, irq1 bind to cpu8-15,
irq2 bind to cpu16-23, irq3 bind to cpu24-31,irq4 bind to cpu32-39... 
irq15 bind to cpu120-127. But after the patch, the relationship is 
changed: irq0 bind to cpu32-39,
irq1 bind to cpu40-47, ..., irq11 bind to cpu120-127, irq12 bind to 
cpu0-7, irq13 bind to cpu8-15, irq14 bind to cpu16-23, irq15 bind to 
cpu24-31.

I notice that before calling the sort() in function 
alloc_nodes_vectors(), the id of array node_vectors[] is from 0,1,2,3. 
But after function sort(), the index of array node_vectors[] is 1,2,3,0.
But i think it sorts according to the numbers of cpus in those nodes, so 
it should be the same as before calling sort() as the numbers of cpus in 
every node are 32.

Is it a bug of sort() or the usage of sort()?

Thanks,
Shawn


^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2019-12-09  2:58 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-19  1:25 The irq Affinity is changed after the patch(Fixes: b1a5a73e64e9 ("genirq/affinity: Spread vectors on node according to nr_cpu ratio")) chenxiang (M)
2019-11-19  1:42 ` Ming Lei
     [not found]   ` <a8a89884-8323-ff70-f35e-0fcf5d7afefc@hisilicon.com>
2019-11-19  3:17     ` Ming Lei
2019-11-19  3:32       ` chenxiang (M)
2019-11-19  6:56         ` Ming Lei
2019-12-08  7:42     ` George Spelvin
2019-12-09  2:58       ` chenxiang (M)

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