* [PULL 01/26] target/ppc: Remove unused PPC_INPUT_INT defines
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
@ 2020-01-08 5:22 ` David Gibson
2020-01-08 5:22 ` [PULL 02/26] target/ppc: Handle AIL=0 in ppc_excp_vector_offset David Gibson
` (25 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:22 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, Fabiano Rosas, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Fabiano Rosas <farosas@linux.ibm.com>
They were added in "16415335be Use correct input constant" with a
single use in kvm_arch_pre_run but that function's implementation was
removed by "1e8f51e856 ppc: remove idle_timer logic".
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20191218014616.686124-1-farosas@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/kvm.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index d1c334f0e3..5e4f219902 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -1325,12 +1325,6 @@ int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)
return 0;
}
-#if defined(TARGET_PPC64)
-#define PPC_INPUT_INT PPC970_INPUT_INT
-#else
-#define PPC_INPUT_INT PPC6xx_INPUT_INT
-#endif
-
void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
{
return;
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 02/26] target/ppc: Handle AIL=0 in ppc_excp_vector_offset
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
2020-01-08 5:22 ` [PULL 01/26] target/ppc: Remove unused PPC_INPUT_INT defines David Gibson
@ 2020-01-08 5:22 ` David Gibson
2020-01-08 5:22 ` [PULL 03/26] linux-headers: Update David Gibson
` (24 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:22 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, Fabiano Rosas, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Fabiano Rosas <farosas@linux.ibm.com>
The exception vector offset calculation was moved into a function but
the case when AIL=0 was not checked.
The reason we got away with this is that the sole caller of
ppc_excp_vector_offset checks the AIL before calling the function:
/* Handle AIL */
if (ail) {
...
vector |= ppc_excp_vector_offset(cs, ail);
}
Fixes: 2586a4d7a0 ("target/ppc: Move exception vector offset computation into a function")
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20191217142512.574075-1-farosas@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/excp_helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 50b004d00d..5752ed4a4d 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -112,6 +112,8 @@ static uint64_t ppc_excp_vector_offset(CPUState *cs, int ail)
uint64_t offset = 0;
switch (ail) {
+ case AIL_NONE:
+ break;
case AIL_0001_8000:
offset = 0x18000;
break;
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 03/26] linux-headers: Update
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
2020-01-08 5:22 ` [PULL 01/26] target/ppc: Remove unused PPC_INPUT_INT defines David Gibson
2020-01-08 5:22 ` [PULL 02/26] target/ppc: Handle AIL=0 in ppc_excp_vector_offset David Gibson
@ 2020-01-08 5:22 ` David Gibson
2020-01-08 5:22 ` [PULL 04/26] ppc/spapr: Support reboot of secure pseries guest David Gibson
` (23 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:22 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, qemu-devel, Bharata B Rao, groug, qemu-ppc, clg, David Gibson
From: Bharata B Rao <bharata@linux.ibm.com>
Update to mainline commit: d1eef1c61974 ("Linux 5.5-rc2")
Signed-off-by: Bharata B Rao <bharata@linux.ibm.com>
Message-Id: <20191219031445.8949-2-bharata@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
include/standard-headers/asm-x86/bootparam.h | 7 +-
.../infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h | 15 +++-
include/standard-headers/drm/drm_fourcc.h | 28 ++++++-
.../linux/input-event-codes.h | 77 +++++++++++++++++++
include/standard-headers/linux/pci_regs.h | 3 +
.../standard-headers/rdma/vmw_pvrdma-abi.h | 5 ++
| 1 +
7 files changed, 132 insertions(+), 4 deletions(-)
diff --git a/include/standard-headers/asm-x86/bootparam.h b/include/standard-headers/asm-x86/bootparam.h
index a6f7cf535e..072e2ed546 100644
--- a/include/standard-headers/asm-x86/bootparam.h
+++ b/include/standard-headers/asm-x86/bootparam.h
@@ -2,7 +2,7 @@
#ifndef _ASM_X86_BOOTPARAM_H
#define _ASM_X86_BOOTPARAM_H
-/* setup_data types */
+/* setup_data/setup_indirect types */
#define SETUP_NONE 0
#define SETUP_E820_EXT 1
#define SETUP_DTB 2
@@ -11,6 +11,11 @@
#define SETUP_APPLE_PROPERTIES 5
#define SETUP_JAILHOUSE 6
+#define SETUP_INDIRECT (1<<31)
+
+/* SETUP_INDIRECT | max(SETUP_*) */
+#define SETUP_TYPE_MAX (SETUP_INDIRECT | SETUP_JAILHOUSE)
+
/* ram_size flags */
#define RAMDISK_IMAGE_START_MASK 0x07FF
#define RAMDISK_PROMPT_FLAG 0x8000
diff --git a/include/standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h b/include/standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h
index d019872608..a5a1c8234e 100644
--- a/include/standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h
+++ b/include/standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h
@@ -58,7 +58,8 @@
#define PVRDMA_ROCEV1_VERSION 17
#define PVRDMA_ROCEV2_VERSION 18
#define PVRDMA_PPN64_VERSION 19
-#define PVRDMA_VERSION PVRDMA_PPN64_VERSION
+#define PVRDMA_QPHANDLE_VERSION 20
+#define PVRDMA_VERSION PVRDMA_QPHANDLE_VERSION
#define PVRDMA_BOARD_ID 1
#define PVRDMA_REV_ID 1
@@ -581,6 +582,17 @@ struct pvrdma_cmd_create_qp_resp {
uint32_t max_inline_data;
};
+struct pvrdma_cmd_create_qp_resp_v2 {
+ struct pvrdma_cmd_resp_hdr hdr;
+ uint32_t qpn;
+ uint32_t qp_handle;
+ uint32_t max_send_wr;
+ uint32_t max_recv_wr;
+ uint32_t max_send_sge;
+ uint32_t max_recv_sge;
+ uint32_t max_inline_data;
+};
+
struct pvrdma_cmd_modify_qp {
struct pvrdma_cmd_hdr hdr;
uint32_t qp_handle;
@@ -663,6 +675,7 @@ union pvrdma_cmd_resp {
struct pvrdma_cmd_create_cq_resp create_cq_resp;
struct pvrdma_cmd_resize_cq_resp resize_cq_resp;
struct pvrdma_cmd_create_qp_resp create_qp_resp;
+ struct pvrdma_cmd_create_qp_resp_v2 create_qp_resp_v2;
struct pvrdma_cmd_query_qp_resp query_qp_resp;
struct pvrdma_cmd_destroy_qp_resp destroy_qp_resp;
struct pvrdma_cmd_create_srq_resp create_srq_resp;
diff --git a/include/standard-headers/drm/drm_fourcc.h b/include/standard-headers/drm/drm_fourcc.h
index a308c91b4f..46d279f515 100644
--- a/include/standard-headers/drm/drm_fourcc.h
+++ b/include/standard-headers/drm/drm_fourcc.h
@@ -68,7 +68,7 @@ extern "C" {
#define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \
((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))
-#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
+#define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
/* Reserve 0 for the invalid format specifier */
#define DRM_FORMAT_INVALID 0
@@ -647,7 +647,21 @@ extern "C" {
* Further information on the use of AFBC modifiers can be found in
* Documentation/gpu/afbc.rst
*/
-#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)
+
+/*
+ * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
+ * modifiers) denote the category for modifiers. Currently we have only two
+ * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
+ * different categories.
+ */
+#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
+ fourcc_mod_code(ARM, ((uint64_t)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
+
+#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
+#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
+
+#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
+ DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
/*
* AFBC superblock size
@@ -741,6 +755,16 @@ extern "C" {
*/
#define AFBC_FORMAT_MOD_BCH (1ULL << 11)
+/*
+ * Arm 16x16 Block U-Interleaved modifier
+ *
+ * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
+ * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
+ * in the block are reordered.
+ */
+#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
+ DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
+
/*
* Allwinner tiled modifier
*
diff --git a/include/standard-headers/linux/input-event-codes.h b/include/standard-headers/linux/input-event-codes.h
index eb08cb8598..b484c25289 100644
--- a/include/standard-headers/linux/input-event-codes.h
+++ b/include/standard-headers/linux/input-event-codes.h
@@ -649,6 +649,83 @@
*/
#define KEY_DATA 0x277
#define KEY_ONSCREEN_KEYBOARD 0x278
+/* Electronic privacy screen control */
+#define KEY_PRIVACY_SCREEN_TOGGLE 0x279
+
+/*
+ * Some keyboards have keys which do not have a defined meaning, these keys
+ * are intended to be programmed / bound to macros by the user. For most
+ * keyboards with these macro-keys the key-sequence to inject, or action to
+ * take, is all handled by software on the host side. So from the kernel's
+ * point of view these are just normal keys.
+ *
+ * The KEY_MACRO# codes below are intended for such keys, which may be labeled
+ * e.g. G1-G18, or S1 - S30. The KEY_MACRO# codes MUST NOT be used for keys
+ * where the marking on the key does indicate a defined meaning / purpose.
+ *
+ * The KEY_MACRO# codes MUST also NOT be used as fallback for when no existing
+ * KEY_FOO define matches the marking / purpose. In this case a new KEY_FOO
+ * define MUST be added.
+ */
+#define KEY_MACRO1 0x290
+#define KEY_MACRO2 0x291
+#define KEY_MACRO3 0x292
+#define KEY_MACRO4 0x293
+#define KEY_MACRO5 0x294
+#define KEY_MACRO6 0x295
+#define KEY_MACRO7 0x296
+#define KEY_MACRO8 0x297
+#define KEY_MACRO9 0x298
+#define KEY_MACRO10 0x299
+#define KEY_MACRO11 0x29a
+#define KEY_MACRO12 0x29b
+#define KEY_MACRO13 0x29c
+#define KEY_MACRO14 0x29d
+#define KEY_MACRO15 0x29e
+#define KEY_MACRO16 0x29f
+#define KEY_MACRO17 0x2a0
+#define KEY_MACRO18 0x2a1
+#define KEY_MACRO19 0x2a2
+#define KEY_MACRO20 0x2a3
+#define KEY_MACRO21 0x2a4
+#define KEY_MACRO22 0x2a5
+#define KEY_MACRO23 0x2a6
+#define KEY_MACRO24 0x2a7
+#define KEY_MACRO25 0x2a8
+#define KEY_MACRO26 0x2a9
+#define KEY_MACRO27 0x2aa
+#define KEY_MACRO28 0x2ab
+#define KEY_MACRO29 0x2ac
+#define KEY_MACRO30 0x2ad
+
+/*
+ * Some keyboards with the macro-keys described above have some extra keys
+ * for controlling the host-side software responsible for the macro handling:
+ * -A macro recording start/stop key. Note that not all keyboards which emit
+ * KEY_MACRO_RECORD_START will also emit KEY_MACRO_RECORD_STOP if
+ * KEY_MACRO_RECORD_STOP is not advertised, then KEY_MACRO_RECORD_START
+ * should be interpreted as a recording start/stop toggle;
+ * -Keys for switching between different macro (pre)sets, either a key for
+ * cycling through the configured presets or keys to directly select a preset.
+ */
+#define KEY_MACRO_RECORD_START 0x2b0
+#define KEY_MACRO_RECORD_STOP 0x2b1
+#define KEY_MACRO_PRESET_CYCLE 0x2b2
+#define KEY_MACRO_PRESET1 0x2b3
+#define KEY_MACRO_PRESET2 0x2b4
+#define KEY_MACRO_PRESET3 0x2b5
+
+/*
+ * Some keyboards have a buildin LCD panel where the contents are controlled
+ * by the host. Often these have a number of keys directly below the LCD
+ * intended for controlling a menu shown on the LCD. These keys often don't
+ * have any labeling so we just name them KEY_KBD_LCD_MENU#
+ */
+#define KEY_KBD_LCD_MENU1 0x2b8
+#define KEY_KBD_LCD_MENU2 0x2b9
+#define KEY_KBD_LCD_MENU3 0x2ba
+#define KEY_KBD_LCD_MENU4 0x2bb
+#define KEY_KBD_LCD_MENU5 0x2bc
#define BTN_TRIGGER_HAPPY 0x2c0
#define BTN_TRIGGER_HAPPY1 0x2c0
diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h
index 29d6e93fd1..acb7d2bdb4 100644
--- a/include/standard-headers/linux/pci_regs.h
+++ b/include/standard-headers/linux/pci_regs.h
@@ -34,6 +34,7 @@
* of which the first 64 bytes are standardized as follows:
*/
#define PCI_STD_HEADER_SIZEOF 64
+#define PCI_STD_NUM_BARS 6 /* Number of standard BARs */
#define PCI_VENDOR_ID 0x00 /* 16 bits */
#define PCI_DEVICE_ID 0x02 /* 16 bits */
#define PCI_COMMAND 0x04 /* 16 bits */
@@ -673,6 +674,8 @@
#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
+#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
+#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
diff --git a/include/standard-headers/rdma/vmw_pvrdma-abi.h b/include/standard-headers/rdma/vmw_pvrdma-abi.h
index 336a8d596f..0989426a3f 100644
--- a/include/standard-headers/rdma/vmw_pvrdma-abi.h
+++ b/include/standard-headers/rdma/vmw_pvrdma-abi.h
@@ -179,6 +179,11 @@ struct pvrdma_create_qp {
uint64_t __attribute__((aligned(8))) qp_addr;
};
+struct pvrdma_create_qp_resp {
+ uint32_t qpn;
+ uint32_t qp_handle;
+};
+
/* PVRDMA masked atomic compare and swap */
struct pvrdma_ex_cmp_swap {
uint64_t __attribute__((aligned(8))) swap_val;
--git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 3b27a1ae85..9d647fad76 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -1348,6 +1348,7 @@ struct kvm_s390_ucas_mapping {
#define KVM_PPC_GET_CPU_CHAR _IOR(KVMIO, 0xb1, struct kvm_ppc_cpu_char)
/* Available with KVM_CAP_PMU_EVENT_FILTER */
#define KVM_SET_PMU_EVENT_FILTER _IOW(KVMIO, 0xb2, struct kvm_pmu_event_filter)
+#define KVM_PPC_SVM_OFF _IO(KVMIO, 0xb3)
/* ioctl for vm fd */
#define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device)
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 04/26] ppc/spapr: Support reboot of secure pseries guest
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (2 preceding siblings ...)
2020-01-08 5:22 ` [PULL 03/26] linux-headers: Update David Gibson
@ 2020-01-08 5:22 ` David Gibson
2020-01-08 5:22 ` [PULL 05/26] ppc/pnv: Modify the powerdown notifier to get the PowerNV machine David Gibson
` (22 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:22 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, qemu-devel, Bharata B Rao, groug, qemu-ppc, clg, David Gibson
From: Bharata B Rao <bharata@linux.ibm.com>
A pseries guest can be run as a secure guest on Ultravisor-enabled
POWER platforms. When such a secure guest is reset, we need to
release/reset a few resources both on ultravisor and hypervisor side.
This is achieved by invoking this new ioctl KVM_PPC_SVM_OFF from the
machine reset path.
As part of this ioctl, the secure guest is essentially transitioned
back to normal mode so that it can reboot like a regular guest and
become secure again.
This ioctl has no effect when invoked for a normal guest. If this ioctl
fails for a secure guest, the guest is terminated.
Signed-off-by: Bharata B Rao <bharata@linux.ibm.com>
Message-Id: <20191219031445.8949-3-bharata@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 1 +
target/ppc/kvm.c | 15 +++++++++++++++
target/ppc/kvm_ppc.h | 6 ++++++
3 files changed, 22 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index f11422fc41..e62c89b3dd 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1597,6 +1597,7 @@ static void spapr_machine_reset(MachineState *machine)
void *fdt;
int rc;
+ kvmppc_svm_off(&error_fatal);
spapr_caps_apply(spapr);
first_ppc_cpu = POWERPC_CPU(first_cpu);
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 5e4f219902..45a26c0fc6 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -2894,3 +2894,18 @@ void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset)
kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset);
}
}
+
+/*
+ * Don't set error if KVM_PPC_SVM_OFF ioctl is invoked on kernels
+ * that don't support this ioctl.
+ */
+void kvmppc_svm_off(Error **errp)
+{
+ int rc;
+ KVMState *s = KVM_STATE(current_machine->accelerator);
+
+ rc = kvm_vm_ioctl(s, KVM_PPC_SVM_OFF);
+ if (rc && rc != -ENOTTY) {
+ error_setg_errno(errp, -rc, "KVM_PPC_SVM_OFF ioctl failed");
+ }
+}
diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h
index f22daabf51..b713097bfb 100644
--- a/target/ppc/kvm_ppc.h
+++ b/target/ppc/kvm_ppc.h
@@ -37,6 +37,7 @@ int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu);
target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu,
bool radix, bool gtse,
uint64_t proc_tbl);
+void kvmppc_svm_off(Error **errp);
#ifndef CONFIG_USER_ONLY
bool kvmppc_spapr_use_multitce(void);
int kvmppc_spapr_enable_inkernel_multitce(void);
@@ -201,6 +202,11 @@ static inline target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu,
return 0;
}
+static inline void kvmppc_svm_off(Error **errp)
+{
+ return;
+}
+
static inline void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu,
unsigned int online)
{
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 05/26] ppc/pnv: Modify the powerdown notifier to get the PowerNV machine
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (3 preceding siblings ...)
2020-01-08 5:22 ` [PULL 04/26] ppc/spapr: Support reboot of secure pseries guest David Gibson
@ 2020-01-08 5:22 ` David Gibson
2020-01-08 5:22 ` [PULL 06/26] mos6522: remove anh register David Gibson
` (21 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:22 UTC (permalink / raw)
To: peter.maydell; +Cc: lvivier, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
Use container_of() instead of qdev_get_machine()
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191219181155.32530-2-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index f77e7ca84e..855254f282 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -561,7 +561,7 @@ static void *pnv_dt_create(MachineState *machine)
static void pnv_powerdown_notify(Notifier *n, void *opaque)
{
- PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
+ PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier);
if (pnv->bmc) {
pnv_bmc_powerdown(pnv->bmc);
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 06/26] mos6522: remove anh register
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (4 preceding siblings ...)
2020-01-08 5:22 ` [PULL 05/26] ppc/pnv: Modify the powerdown notifier to get the PowerNV machine David Gibson
@ 2020-01-08 5:22 ` David Gibson
2020-01-08 5:22 ` [PULL 07/26] spapr/xive: Use device_class_set_parent_realize() David Gibson
` (20 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:22 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, Laurent Vivier, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Laurent Vivier <laurent@vivier.eu>
Register addr 1 is defined as buffer A with handshake (vBufAH),
register addr 15 is also defined as buffer A without handshake (vBufA).
As both addresses access the same register, remove the definition of
'anh' and use only 'a' (with VIA_REG_ANH and VIA_REG_A).
Fixes: 51f233ec92cd ("misc: introduce new mos6522 VIA device and enable it for ppc builds")
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20191220214054.76525-1-laurent@vivier.eu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/misc/mos6522.c | 16 ++++++++--------
include/hw/misc/mos6522.h | 1 -
2 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index cecf0be59e..10b85bf751 100644
--- a/hw/misc/mos6522.c
+++ b/hw/misc/mos6522.c
@@ -244,6 +244,9 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size)
val = s->b;
break;
case VIA_REG_A:
+ qemu_log_mask(LOG_UNIMP, "Read access to register A with handshake");
+ /* fall through */
+ case VIA_REG_ANH:
val = s->a;
break;
case VIA_REG_DIRB:
@@ -297,9 +300,7 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size)
val = s->ier | 0x80;
break;
default:
- case VIA_REG_ANH:
- val = s->anh;
- break;
+ g_assert_not_reached();
}
if (addr != VIA_REG_IFR || val != 0) {
@@ -322,6 +323,9 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
mdc->portB_write(s);
break;
case VIA_REG_A:
+ qemu_log_mask(LOG_UNIMP, "Write access to register A with handshake");
+ /* fall through */
+ case VIA_REG_ANH:
s->a = (s->a & ~s->dira) | (val & s->dira);
mdc->portA_write(s);
break;
@@ -395,9 +399,7 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
break;
default:
- case VIA_REG_ANH:
- s->anh = val;
- break;
+ g_assert_not_reached();
}
}
@@ -439,7 +441,6 @@ const VMStateDescription vmstate_mos6522 = {
VMSTATE_UINT8(pcr, MOS6522State),
VMSTATE_UINT8(ifr, MOS6522State),
VMSTATE_UINT8(ier, MOS6522State),
- VMSTATE_UINT8(anh, MOS6522State),
VMSTATE_STRUCT_ARRAY(timers, MOS6522State, 2, 0,
vmstate_mos6522_timer, MOS6522Timer),
VMSTATE_END_OF_LIST()
@@ -460,7 +461,6 @@ static void mos6522_reset(DeviceState *dev)
s->ifr = 0;
s->ier = 0;
/* s->ier = T1_INT | SR_INT; */
- s->anh = 0;
s->timers[0].frequency = s->frequency;
s->timers[0].latch = 0xffff;
diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h
index 493c907537..97384c6e02 100644
--- a/include/hw/misc/mos6522.h
+++ b/include/hw/misc/mos6522.h
@@ -115,7 +115,6 @@ typedef struct MOS6522State {
uint8_t pcr;
uint8_t ifr;
uint8_t ier;
- uint8_t anh;
MOS6522Timer timers[2];
uint64_t frequency;
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 07/26] spapr/xive: Use device_class_set_parent_realize()
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (5 preceding siblings ...)
2020-01-08 5:22 ` [PULL 06/26] mos6522: remove anh register David Gibson
@ 2020-01-08 5:22 ` David Gibson
2020-01-08 5:22 ` [PULL 08/26] ppc/spapr: Don't call KVM_SVM_OFF ioctl on TCG David Gibson
` (19 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:22 UTC (permalink / raw)
To: peter.maydell; +Cc: lvivier, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The XIVE router base class currently inherits an empty realize hook
from the sysbus device base class, but it will soon implement one
of its own to perform some sanity checks. Do the preliminary plumbing
to have it called.
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191219181155.32530-6-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/spapr_xive.c | 12 +++++++++++-
include/hw/ppc/spapr_xive.h | 10 ++++++++++
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 57305c56d7..32322470a8 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -286,10 +286,17 @@ static void spapr_xive_instance_init(Object *obj)
static void spapr_xive_realize(DeviceState *dev, Error **errp)
{
SpaprXive *xive = SPAPR_XIVE(dev);
+ SpaprXiveClass *sxc = SPAPR_XIVE_GET_CLASS(xive);
XiveSource *xsrc = &xive->source;
XiveENDSource *end_xsrc = &xive->end_source;
Error *local_err = NULL;
+ sxc->parent_realize(dev, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
if (!xive->nr_irqs) {
error_setg(errp, "Number of interrupt needs to be greater 0");
return;
@@ -760,10 +767,12 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass);
SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass);
XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass);
+ SpaprXiveClass *sxc = SPAPR_XIVE_CLASS(klass);
dc->desc = "sPAPR XIVE Interrupt Controller";
dc->props = spapr_xive_properties;
- dc->realize = spapr_xive_realize;
+ device_class_set_parent_realize(dc, spapr_xive_realize,
+ &sxc->parent_realize);
dc->vmsd = &vmstate_spapr_xive;
xrc->get_eas = spapr_xive_get_eas;
@@ -794,6 +803,7 @@ static const TypeInfo spapr_xive_info = {
.instance_init = spapr_xive_instance_init,
.instance_size = sizeof(SpaprXive),
.class_init = spapr_xive_class_init,
+ .class_size = sizeof(SpaprXiveClass),
.interfaces = (InterfaceInfo[]) {
{ TYPE_SPAPR_INTC },
{ }
diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h
index 3a103c224d..93d09d68de 100644
--- a/include/hw/ppc/spapr_xive.h
+++ b/include/hw/ppc/spapr_xive.h
@@ -15,6 +15,10 @@
#define TYPE_SPAPR_XIVE "spapr-xive"
#define SPAPR_XIVE(obj) OBJECT_CHECK(SpaprXive, (obj), TYPE_SPAPR_XIVE)
+#define SPAPR_XIVE_CLASS(klass) \
+ OBJECT_CLASS_CHECK(SpaprXiveClass, (klass), TYPE_SPAPR_XIVE)
+#define SPAPR_XIVE_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(SpaprXiveClass, (obj), TYPE_SPAPR_XIVE)
typedef struct SpaprXive {
XiveRouter parent;
@@ -47,6 +51,12 @@ typedef struct SpaprXive {
VMChangeStateEntry *change;
} SpaprXive;
+typedef struct SpaprXiveClass {
+ XiveRouterClass parent;
+
+ DeviceRealize parent_realize;
+} SpaprXiveClass;
+
/*
* The sPAPR machine has a unique XIVE IC device. Assign a fixed value
* to the controller block id value. It can nevertheless be changed
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 08/26] ppc/spapr: Don't call KVM_SVM_OFF ioctl on TCG
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (6 preceding siblings ...)
2020-01-08 5:22 ` [PULL 07/26] spapr/xive: Use device_class_set_parent_realize() David Gibson
@ 2020-01-08 5:22 ` David Gibson
2020-01-08 5:22 ` [PULL 09/26] spapr.c: remove 'out' label in spapr_dt_cas_updates() David Gibson
` (18 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:22 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, Alexey Kardashevskiy, qemu-devel, Bharata B Rao, groug,
qemu-ppc, clg, David Gibson
From: Bharata B Rao <bharata@linux.ibm.com>
Invoking KVM_SVM_OFF ioctl for TCG guests will lead to a QEMU crash.
Fix this by ensuring that we don't call KVM_SVM_OFF ioctl on TCG.
Reported-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Fixes: 4930c1966249 ("ppc/spapr: Support reboot of secure pseries guest")
Signed-off-by: Bharata B Rao <bharata@linux.ibm.com>
Message-Id: <20200102054155.13175-1-bharata@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/kvm.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 45a26c0fc6..b5799e62b4 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -2902,9 +2902,12 @@ void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset)
void kvmppc_svm_off(Error **errp)
{
int rc;
- KVMState *s = KVM_STATE(current_machine->accelerator);
- rc = kvm_vm_ioctl(s, KVM_PPC_SVM_OFF);
+ if (!kvm_enabled()) {
+ return;
+ }
+
+ rc = kvm_vm_ioctl(KVM_STATE(current_machine->accelerator), KVM_PPC_SVM_OFF);
if (rc && rc != -ENOTTY) {
error_setg_errno(errp, -rc, "KVM_PPC_SVM_OFF ioctl failed");
}
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 09/26] spapr.c: remove 'out' label in spapr_dt_cas_updates()
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (7 preceding siblings ...)
2020-01-08 5:22 ` [PULL 08/26] ppc/spapr: Don't call KVM_SVM_OFF ioctl on TCG David Gibson
@ 2020-01-08 5:22 ` David Gibson
2020-01-08 5:22 ` [PULL 10/26] ppc440_bamboo.c: remove label from bamboo_load_device_tree() David Gibson
` (17 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:22 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, Daniel Henrique Barboza, qemu-devel, groug, qemu-ppc,
clg, David Gibson
From: Daniel Henrique Barboza <danielhb413@gmail.com>
'out' can be replaced by 'return' with the appropriate
return value.
CC: David Gibson <david@gibson.dropbear.id.au>
CC: qemu-ppc@nongnu.org
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20200106182425.20312-2-danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index e62c89b3dd..eb0b84d300 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -878,7 +878,7 @@ static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt,
g_assert(smc->dr_lmb_enabled);
ret = spapr_populate_drconf_memory(spapr, fdt);
if (ret) {
- goto out;
+ return ret;
}
}
@@ -889,11 +889,8 @@ static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt,
return offset;
}
}
- ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
- "ibm,architecture-vec-5");
-
-out:
- return ret;
+ return spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
+ "ibm,architecture-vec-5");
}
static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 10/26] ppc440_bamboo.c: remove label from bamboo_load_device_tree()
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (8 preceding siblings ...)
2020-01-08 5:22 ` [PULL 09/26] spapr.c: remove 'out' label in spapr_dt_cas_updates() David Gibson
@ 2020-01-08 5:22 ` David Gibson
2020-01-08 5:22 ` [PULL 11/26] ppc/pnv: Drop "num-chips" machine property David Gibson
` (16 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:22 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, Daniel Henrique Barboza, qemu-devel, groug, qemu-ppc,
clg, David Gibson
From: Daniel Henrique Barboza <danielhb413@gmail.com>
'out' label can be replaced by 'return -1' in all cases.
CC: David Gibson <david@gibson.dropbear.id.au>
CC: qemu-ppc@nongnu.org
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20200106182425.20312-3-danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc440_bamboo.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 4d95c0f8a8..b782641b23 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -71,12 +71,12 @@ static int bamboo_load_device_tree(hwaddr addr,
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
if (!filename) {
- goto out;
+ return -1;
}
fdt = load_device_tree(filename, &fdt_size);
g_free(filename);
if (fdt == NULL) {
- goto out;
+ return -1;
}
/* Manipulate device tree in memory. */
@@ -117,10 +117,6 @@ static int bamboo_load_device_tree(hwaddr addr,
rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
g_free(fdt);
return 0;
-
-out:
-
- return ret;
}
/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 11/26] ppc/pnv: Drop "num-chips" machine property
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (9 preceding siblings ...)
2020-01-08 5:22 ` [PULL 10/26] ppc440_bamboo.c: remove label from bamboo_load_device_tree() David Gibson
@ 2020-01-08 5:22 ` David Gibson
2020-01-08 5:22 ` [PULL 12/26] spapr/xive: remove redundant check in spapr_match_nvt() David Gibson
` (15 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:22 UTC (permalink / raw)
To: peter.maydell; +Cc: lvivier, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The number of CPU chips of the powernv machine is configurable through a
"num-chips" property. This doesn't fit well with the CPU topology, eg.
some configurations can come up with more CPUs than the maximum of CPUs
set in the toplogy. This causes assertion to be hit with mttcg:
-machine powernv,num-chips=2 -smp cores=2 -accel tcg,thread=multi
ERROR:
tcg/tcg.c:789:tcg_register_thread: assertion failed: (n < ms->smp.max_cpus)
Aborted (core dumped)
Mttcg mandates the CPU topology to be dimensioned to the actual number
of CPUs, depending on the number of chips the user asked for. That is,
'-machine num-chips=N' should always have a '-smp' companion with a
topology that meats the resulting number of CPUs, typically
'-smp sockets=N'.
It thus seems that "num-chips" doesn't bring anything but forcing the user
to specify the requested number of chips on the command line twice. Simplify
the command line by computing the number of chips based on the CPU topology
exclusively. The powernv machine isn't a production thing ; it is mostly
used by developpers to prepare the bringup of real HW. Because of this and
for simplicity, this deliberately ignores the official deprecation process
and dumps "num-chips" right away : '-smp sockets=N' is now the only way to
control the number of CPU chips.
This is done at machine init because smp_parse() is called after instance
init.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157830658266.533764.2214183961444213947.stgit@bahia.lan>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 62 ++++++++++------------------------------------------
1 file changed, 12 insertions(+), 50 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 855254f282..6d7bf9280e 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -768,6 +768,18 @@ static void pnv_init(MachineState *machine)
exit(1);
}
+ pnv->num_chips =
+ machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
+ /*
+ * TODO: should we decide on how many chips we can create based
+ * on #cores and Venice vs. Murano vs. Naples chip type etc...,
+ */
+ if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) {
+ error_report("invalid number of chips: '%d'", pnv->num_chips);
+ error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n");
+ exit(1);
+ }
+
pnv->chips = g_new0(PnvChip *, pnv->num_chips);
for (i = 0; i < pnv->num_chips; i++) {
char chip_name[32];
@@ -1696,53 +1708,6 @@ PnvChip *pnv_get_chip(uint32_t chip_id)
return NULL;
}
-static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp);
-}
-
-static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- PnvMachineState *pnv = PNV_MACHINE(obj);
- uint32_t num_chips;
- Error *local_err = NULL;
-
- visit_type_uint32(v, name, &num_chips, &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
- return;
- }
-
- /*
- * TODO: should we decide on how many chips we can create based
- * on #cores and Venice vs. Murano vs. Naples chip type etc...,
- */
- if (!is_power_of_2(num_chips) || num_chips > 4) {
- error_setg(errp, "invalid number of chips: '%d'", num_chips);
- return;
- }
-
- pnv->num_chips = num_chips;
-}
-
-static void pnv_machine_instance_init(Object *obj)
-{
- PnvMachineState *pnv = PNV_MACHINE(obj);
- pnv->num_chips = 1;
-}
-
-static void pnv_machine_class_props_init(ObjectClass *oc)
-{
- object_class_property_add(oc, "num-chips", "uint32",
- pnv_get_num_chips, pnv_set_num_chips,
- NULL, NULL, NULL);
- object_class_property_set_description(oc, "num-chips",
- "Specifies the number of processor chips",
- NULL);
-}
-
static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1812,8 +1777,6 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data)
*/
mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
ispc->print_info = pnv_pic_print_info;
-
- pnv_machine_class_props_init(oc);
}
#define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
@@ -1866,7 +1829,6 @@ static const TypeInfo types[] = {
.parent = TYPE_MACHINE,
.abstract = true,
.instance_size = sizeof(PnvMachineState),
- .instance_init = pnv_machine_instance_init,
.class_init = pnv_machine_class_init,
.class_size = sizeof(PnvMachineClass),
.interfaces = (InterfaceInfo[]) {
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 12/26] spapr/xive: remove redundant check in spapr_match_nvt()
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (10 preceding siblings ...)
2020-01-08 5:22 ` [PULL 11/26] ppc/pnv: Drop "num-chips" machine property David Gibson
@ 2020-01-08 5:22 ` David Gibson
2020-01-08 5:22 ` [PULL 13/26] ppc/pnv: Introduce a "xics" property alias under the PSI model David Gibson
` (14 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:22 UTC (permalink / raw)
To: peter.maydell; +Cc: lvivier, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
spapr_match_nvt() is a XIVE operation and is used by the machine to
look for a matching target when an event notification is being
delivered. An assert checks that spapr_match_nvt() is called only when
the machine has selected the XIVE interrupt mode but it is redundant
with the XIVE_PRESENTER() dynamic cast.
Apply the cast to spapr->active_intc and remove the assert.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200106163207.4608-1-clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index eb0b84d300..30a5fbd3be 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -4195,19 +4195,19 @@ static void spapr_pic_print_info(InterruptStatsProvider *obj,
kvm_irqchip_in_kernel() ? "in-kernel" : "emulated");
}
+/*
+ * This is a XIVE only operation
+ */
static int spapr_match_nvt(XiveFabric *xfb, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint8_t priority,
uint32_t logic_serv, XiveTCTXMatch *match)
{
SpaprMachineState *spapr = SPAPR_MACHINE(xfb);
- XivePresenter *xptr = XIVE_PRESENTER(spapr->xive);
+ XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc);
XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
int count;
- /* This is a XIVE only operation */
- assert(spapr->active_intc == SPAPR_INTC(spapr->xive));
-
count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
priority, logic_serv, match);
if (count < 0) {
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 13/26] ppc/pnv: Introduce a "xics" property alias under the PSI model
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (11 preceding siblings ...)
2020-01-08 5:22 ` [PULL 12/26] spapr/xive: remove redundant check in spapr_match_nvt() David Gibson
@ 2020-01-08 5:22 ` David Gibson
2020-01-08 5:23 ` [PULL 14/26] ppc/pnv: Introduce a "xics" property under the POWER8 chip David Gibson
` (13 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:22 UTC (permalink / raw)
To: peter.maydell; +Cc: lvivier, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
This removes the need of the intermediate link under PSI to pass the
XICS link to the underlying ICSState object.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Message-Id: <20200106145645.4539-2-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 4 ++--
hw/ppc/pnv_psi.c | 11 ++---------
2 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 6d7bf9280e..90e92e82c5 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1004,8 +1004,6 @@ static void pnv_chip_power8_instance_init(Object *obj)
object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi),
TYPE_PNV8_PSI, &error_abort, NULL);
- object_property_add_const_link(OBJECT(&chip8->psi), "xics",
- OBJECT(qdev_get_machine()), &error_abort);
object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc),
TYPE_PNV8_LPC, &error_abort, NULL);
@@ -1072,6 +1070,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
/* Processor Service Interface (PSI) Host Bridge */
object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip),
"bar", &error_fatal);
+ object_property_set_link(OBJECT(&chip8->psi), OBJECT(qdev_get_machine()),
+ ICS_PROP_XICS, &error_abort);
object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err);
if (local_err) {
error_propagate(errp, local_err);
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 75e20d9da0..4da3d25686 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -470,6 +470,8 @@ static void pnv_psi_power8_instance_init(Object *obj)
object_initialize_child(obj, "ics-psi", &psi8->ics, sizeof(psi8->ics),
TYPE_ICS, &error_abort, NULL);
+ object_property_add_alias(obj, ICS_PROP_XICS, OBJECT(&psi8->ics),
+ ICS_PROP_XICS, &error_abort);
}
static const uint8_t irq_to_xivr[] = {
@@ -485,19 +487,10 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
{
PnvPsi *psi = PNV_PSI(dev);
ICSState *ics = &PNV8_PSI(psi)->ics;
- Object *obj;
Error *err = NULL;
unsigned int i;
- obj = object_property_get_link(OBJECT(dev), "xics", &err);
- if (!obj) {
- error_setg(errp, "%s: required link 'xics' not found: %s",
- __func__, error_get_pretty(err));
- return;
- }
-
/* Create PSI interrupt control source */
- object_property_set_link(OBJECT(ics), obj, ICS_PROP_XICS, &error_abort);
object_property_set_int(OBJECT(ics), PSI_NUM_INTERRUPTS, "nr-irqs", &err);
if (err) {
error_propagate(errp, err);
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 14/26] ppc/pnv: Introduce a "xics" property under the POWER8 chip
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (12 preceding siblings ...)
2020-01-08 5:22 ` [PULL 13/26] ppc/pnv: Introduce a "xics" property alias under the PSI model David Gibson
@ 2020-01-08 5:23 ` David Gibson
2020-01-08 5:23 ` [PULL 15/26] pnv/xive: Use device_class_set_parent_realize() David Gibson
` (12 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:23 UTC (permalink / raw)
To: peter.maydell; +Cc: lvivier, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
POWER8 is the only chip using the XICS interface. Add a "xics" link
and a XICSFabric attribute under this chip to remove the use of
qdev_get_machine()
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20200106145645.4539-3-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 24 +++++++++++++++++++-----
include/hw/ppc/pnv.h | 2 ++
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 90e92e82c5..65cba84335 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -802,6 +802,13 @@ static void pnv_init(MachineState *machine)
&error_fatal);
object_property_set_int(chip, machine->smp.cores,
"nr-cores", &error_fatal);
+ /*
+ * The POWER8 machine use the XICS interrupt interface.
+ * Propagate the XICS fabric to the chip and its controllers.
+ */
+ if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
+ object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort);
+ }
object_property_set_bool(chip, true, "realized", &error_fatal);
}
g_free(chip_typename);
@@ -843,12 +850,12 @@ static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
Error **errp)
{
+ Pnv8Chip *chip8 = PNV8_CHIP(chip);
Error *local_err = NULL;
Object *obj;
PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
- obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()),
- &local_err);
+ obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
@@ -1002,6 +1009,12 @@ static void pnv_chip_power8_instance_init(Object *obj)
{
Pnv8Chip *chip8 = PNV8_CHIP(obj);
+ object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
+ (Object **)&chip8->xics,
+ object_property_allow_set_link,
+ OBJ_PROP_LINK_STRONG,
+ &error_abort);
+
object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi),
TYPE_PNV8_PSI, &error_abort, NULL);
@@ -1021,7 +1034,6 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
int i, j;
char *name;
- XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
name = g_strdup_printf("icp-%x", chip->chip_id);
memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
@@ -1037,7 +1049,7 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
- PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir));
+ PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
&icp->mmio);
@@ -1053,6 +1065,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
Pnv8Psi *psi8 = &chip8->psi;
Error *local_err = NULL;
+ assert(chip8->xics);
+
/* XSCOM bridge is first */
pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
if (local_err) {
@@ -1070,7 +1084,7 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
/* Processor Service Interface (PSI) Host Bridge */
object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip),
"bar", &error_fatal);
- object_property_set_link(OBJECT(&chip8->psi), OBJECT(qdev_get_machine()),
+ object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics),
ICS_PROP_XICS, &error_abort);
object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err);
if (local_err) {
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index f78fd0dd96..56277862dd 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -72,6 +72,8 @@ typedef struct Pnv8Chip {
Pnv8Psi psi;
PnvOCC occ;
PnvHomer homer;
+
+ XICSFabric *xics;
} Pnv8Chip;
#define TYPE_PNV9_CHIP "pnv9-chip"
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 15/26] pnv/xive: Use device_class_set_parent_realize()
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (13 preceding siblings ...)
2020-01-08 5:23 ` [PULL 14/26] ppc/pnv: Introduce a "xics" property under the POWER8 chip David Gibson
@ 2020-01-08 5:23 ` David Gibson
2020-01-08 5:23 ` [PULL 16/26] spapr, pnv, xive: Add a "xive-fabric" link to the XIVE router David Gibson
` (11 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:23 UTC (permalink / raw)
To: peter.maydell; +Cc: lvivier, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The XIVE router base class currently inherits an empty realize hook
from the sysbus device base class, but it will soon implement one
of its own to perform some sanity checks. Do the preliminary plumbing
to have it called.
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20200106145645.4539-4-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/pnv_xive.c | 10 ++++++++++
include/hw/ppc/pnv_xive.h | 10 ++++++++++
2 files changed, 20 insertions(+)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index a0a69b98a7..6412cf222e 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -1816,10 +1816,17 @@ static void pnv_xive_init(Object *obj)
static void pnv_xive_realize(DeviceState *dev, Error **errp)
{
PnvXive *xive = PNV_XIVE(dev);
+ PnvXiveClass *pxc = PNV_XIVE_GET_CLASS(dev);
XiveSource *xsrc = &xive->ipi_source;
XiveENDSource *end_xsrc = &xive->end_source;
Error *local_err = NULL;
+ pxc->parent_realize(dev, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
assert(xive->chip);
/*
@@ -1947,10 +1954,12 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data)
XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass);
XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass);
XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass);
+ PnvXiveClass *pxc = PNV_XIVE_CLASS(klass);
xdc->dt_xscom = pnv_xive_dt_xscom;
dc->desc = "PowerNV XIVE Interrupt Controller";
+ device_class_set_parent_realize(dc, pnv_xive_realize, &pxc->parent_realize);
dc->realize = pnv_xive_realize;
dc->props = pnv_xive_properties;
@@ -1971,6 +1980,7 @@ static const TypeInfo pnv_xive_info = {
.instance_init = pnv_xive_init,
.instance_size = sizeof(PnvXive),
.class_init = pnv_xive_class_init,
+ .class_size = sizeof(PnvXiveClass),
.interfaces = (InterfaceInfo[]) {
{ TYPE_PNV_XSCOM_INTERFACE },
{ }
diff --git a/include/hw/ppc/pnv_xive.h b/include/hw/ppc/pnv_xive.h
index f4c7caad40..76cf16f644 100644
--- a/include/hw/ppc/pnv_xive.h
+++ b/include/hw/ppc/pnv_xive.h
@@ -16,6 +16,10 @@ struct PnvChip;
#define TYPE_PNV_XIVE "pnv-xive"
#define PNV_XIVE(obj) OBJECT_CHECK(PnvXive, (obj), TYPE_PNV_XIVE)
+#define PNV_XIVE_CLASS(klass) \
+ OBJECT_CLASS_CHECK(PnvXiveClass, (klass), TYPE_PNV_XIVE)
+#define PNV_XIVE_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(PnvXiveClass, (obj), TYPE_PNV_XIVE)
#define XIVE_BLOCK_MAX 16
@@ -85,6 +89,12 @@ typedef struct PnvXive {
uint64_t edt[XIVE_TABLE_EDT_MAX];
} PnvXive;
+typedef struct PnvXiveClass {
+ XiveRouterClass parent_class;
+
+ DeviceRealize parent_realize;
+} PnvXiveClass;
+
void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon);
#endif /* PPC_PNV_XIVE_H */
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 16/26] spapr, pnv, xive: Add a "xive-fabric" link to the XIVE router
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (14 preceding siblings ...)
2020-01-08 5:23 ` [PULL 15/26] pnv/xive: Use device_class_set_parent_realize() David Gibson
@ 2020-01-08 5:23 ` David Gibson
2020-01-08 5:23 ` [PULL 17/26] xive: Use the XIVE fabric link under " David Gibson
` (10 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:23 UTC (permalink / raw)
To: peter.maydell; +Cc: lvivier, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
In order to get rid of qdev_get_machine(), first add a pointer to the
XIVE fabric under the XIVE router and make it configurable through a
QOM link property.
Configure it in the spapr and pnv machine. In the case of pnv, the XIVE
routers are under the chip, so this is done with a QOM alias property of
the POWER9 pnv chip.
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200106145645.4539-5-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/xive.c | 8 ++++++++
hw/ppc/pnv.c | 6 ++++++
hw/ppc/spapr_irq.c | 2 ++
include/hw/ppc/xive.h | 5 +++--
4 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index d4c6e21703..6df89b06da 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1714,12 +1714,19 @@ void xive_router_notify(XiveNotifier *xn, uint32_t lisn)
xive_get_field64(EAS_END_DATA, eas.w));
}
+static Property xive_router_properties[] = {
+ DEFINE_PROP_LINK("xive-fabric", XiveRouter, xfb,
+ TYPE_XIVE_FABRIC, XiveFabric *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void xive_router_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass);
dc->desc = "XIVE Router Engine";
+ dc->props = xive_router_properties;
xnc->notify = xive_router_notify;
}
@@ -1727,6 +1734,7 @@ static const TypeInfo xive_router_info = {
.name = TYPE_XIVE_ROUTER,
.parent = TYPE_SYS_BUS_DEVICE,
.abstract = true,
+ .instance_size = sizeof(XiveRouter),
.class_size = sizeof(XiveRouterClass),
.class_init = xive_router_class_init,
.interfaces = (InterfaceInfo[]) {
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 65cba84335..ead92d52b2 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -809,6 +809,10 @@ static void pnv_init(MachineState *machine)
if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort);
}
+ if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) {
+ object_property_set_link(chip, OBJECT(pnv), "xive-fabric",
+ &error_abort);
+ }
object_property_set_bool(chip, true, "realized", &error_fatal);
}
g_free(chip_typename);
@@ -1227,6 +1231,8 @@ static void pnv_chip_power9_instance_init(Object *obj)
object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive),
TYPE_PNV_XIVE, &error_abort, NULL);
+ object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive),
+ "xive-fabric", &error_abort);
object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi),
TYPE_PNV9_PSI, &error_abort, NULL);
diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
index 373505d28b..1f630f296b 100644
--- a/hw/ppc/spapr_irq.c
+++ b/hw/ppc/spapr_irq.c
@@ -332,6 +332,8 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp)
* priority
*/
qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3);
+ object_property_set_link(OBJECT(dev), OBJECT(spapr), "xive-fabric",
+ &error_abort);
qdev_init_nofail(dev);
spapr->xive = SPAPR_XIVE(dev);
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 1b7b89098f..1ded82b1cd 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -324,9 +324,12 @@ typedef struct XiveTCTX {
/*
* XIVE Router
*/
+typedef struct XiveFabric XiveFabric;
typedef struct XiveRouter {
SysBusDevice parent;
+
+ XiveFabric *xfb;
} XiveRouter;
#define TYPE_XIVE_ROUTER "xive-router"
@@ -402,8 +405,6 @@ int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
* XIVE Fabric (Interface between Interrupt Controller and Machine)
*/
-typedef struct XiveFabric XiveFabric;
-
#define TYPE_XIVE_FABRIC "xive-fabric"
#define XIVE_FABRIC(obj) \
INTERFACE_CHECK(XiveFabric, (obj), TYPE_XIVE_FABRIC)
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 17/26] xive: Use the XIVE fabric link under the XIVE router
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (15 preceding siblings ...)
2020-01-08 5:23 ` [PULL 16/26] spapr, pnv, xive: Add a "xive-fabric" link to the XIVE router David Gibson
@ 2020-01-08 5:23 ` David Gibson
2020-01-08 5:23 ` [PULL 18/26] ppc/pnv: Add an "nr-threads" property to the base chip class David Gibson
` (9 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:23 UTC (permalink / raw)
To: peter.maydell; +Cc: lvivier, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
Now that the spapr and pnv machines do set the "xive-fabric" link, the
use of the XIVE fabric pointer becomes mandatory. This is checked with
an assert() in a new realize hook. Since the XIVE router is realized at
machine init for the all the machine's life time, no risk to abort an
already running guest (ie. not a hotplug path).
This gets rid of a qdev_get_machine() call.
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200106145645.4539-6-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/xive.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 6df89b06da..12a362b681 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1378,6 +1378,13 @@ static int xive_router_get_block_id(XiveRouter *xrtr)
return xrc->get_block_id(xrtr);
}
+static void xive_router_realize(DeviceState *dev, Error **errp)
+{
+ XiveRouter *xrtr = XIVE_ROUTER(dev);
+
+ assert(xrtr->xfb);
+}
+
/*
* Encode the HW CAM line in the block group mode format :
*
@@ -1470,12 +1477,11 @@ int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
*
* The parameters represent what is sent on the PowerBus
*/
-static bool xive_presenter_notify(uint8_t format,
+static bool xive_presenter_notify(XiveFabric *xfb, uint8_t format,
uint8_t nvt_blk, uint32_t nvt_idx,
bool cam_ignore, uint8_t priority,
uint32_t logic_serv)
{
- XiveFabric *xfb = XIVE_FABRIC(qdev_get_machine());
XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb);
XiveTCTXMatch match = { .tctx = NULL, .ring = 0 };
int count;
@@ -1607,7 +1613,7 @@ static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk,
return;
}
- found = xive_presenter_notify(format, nvt_blk, nvt_idx,
+ found = xive_presenter_notify(xrtr->xfb, format, nvt_blk, nvt_idx,
xive_get_field32(END_W7_F0_IGNORE, end.w7),
priority,
xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7));
@@ -1727,6 +1733,8 @@ static void xive_router_class_init(ObjectClass *klass, void *data)
dc->desc = "XIVE Router Engine";
dc->props = xive_router_properties;
+ /* Parent is SysBusDeviceClass. No need to call its realize hook */
+ dc->realize = xive_router_realize;
xnc->notify = xive_router_notify;
}
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 18/26] ppc/pnv: Add an "nr-threads" property to the base chip class
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (16 preceding siblings ...)
2020-01-08 5:23 ` [PULL 17/26] xive: Use the XIVE fabric link under " David Gibson
@ 2020-01-08 5:23 ` David Gibson
2020-01-08 5:23 ` [PULL 19/26] ppc/pnv: Add a "pnor" const link property to the BMC internal simulator David Gibson
` (8 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:23 UTC (permalink / raw)
To: peter.maydell; +Cc: lvivier, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
Set it at chip creation and forward it to the cores. This allows to drop
a call to qdev_get_machine().
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20200106145645.4539-7-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 8 +++++---
include/hw/ppc/pnv.h | 1 +
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index ead92d52b2..6a0aa78d53 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -802,6 +802,8 @@ static void pnv_init(MachineState *machine)
&error_fatal);
object_property_set_int(chip, machine->smp.cores,
"nr-cores", &error_fatal);
+ object_property_set_int(chip, machine->smp.threads,
+ "nr-threads", &error_fatal);
/*
* The POWER8 machine use the XICS interrupt interface.
* Propagate the XICS fabric to the chip and its controllers.
@@ -1526,7 +1528,6 @@ static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
{
- MachineState *ms = MACHINE(qdev_get_machine());
Error *error = NULL;
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
const char *typename = pnv_chip_core_typename(chip);
@@ -1562,8 +1563,8 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
&error_abort);
chip->cores[i] = pnv_core;
- object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads",
- &error_fatal);
+ object_property_set_int(OBJECT(pnv_core), chip->nr_threads,
+ "nr-threads", &error_fatal);
object_property_set_int(OBJECT(pnv_core), core_hwid,
CPU_CORE_PROP_CORE_ID, &error_fatal);
object_property_set_int(OBJECT(pnv_core),
@@ -1602,6 +1603,7 @@ static Property pnv_chip_properties[] = {
DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
+ DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 56277862dd..4b9012f994 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -48,6 +48,7 @@ typedef struct PnvChip {
uint64_t ram_size;
uint32_t nr_cores;
+ uint32_t nr_threads;
uint64_t cores_mask;
PnvCore **cores;
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 19/26] ppc/pnv: Add a "pnor" const link property to the BMC internal simulator
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (17 preceding siblings ...)
2020-01-08 5:23 ` [PULL 18/26] ppc/pnv: Add an "nr-threads" property to the base chip class David Gibson
@ 2020-01-08 5:23 ` David Gibson
2020-01-08 5:23 ` [PULL 20/26] xive: Add a "presenter" link property to the TCTX object David Gibson
` (7 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:23 UTC (permalink / raw)
To: peter.maydell; +Cc: lvivier, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
This allows to get rid of a call to qdev_get_machine().
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200106145645.4539-8-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 2 +-
hw/ppc/pnv_bmc.c | 8 +++++---
include/hw/ppc/pnv.h | 2 +-
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 6a0aa78d53..f0b8f3ad26 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -820,7 +820,7 @@ static void pnv_init(MachineState *machine)
g_free(chip_typename);
/* Create the machine BMC simulator */
- pnv->bmc = pnv_bmc_create();
+ pnv->bmc = pnv_bmc_create(pnv->pnor);
/* Instantiate ISA bus on chip 0 */
pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
diff --git a/hw/ppc/pnv_bmc.c b/hw/ppc/pnv_bmc.c
index 07fa1e1c7e..8863354c1c 100644
--- a/hw/ppc/pnv_bmc.c
+++ b/hw/ppc/pnv_bmc.c
@@ -143,8 +143,8 @@ static uint16_t bytes_to_blocks(uint32_t bytes)
static void hiomap_cmd(IPMIBmcSim *ibs, uint8_t *cmd, unsigned int cmd_len,
RspBuffer *rsp)
{
- PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
- PnvPnor *pnor = pnv->pnor;
+ PnvPnor *pnor = PNV_PNOR(object_property_get_link(OBJECT(ibs), "pnor",
+ &error_abort));
uint32_t pnor_size = pnor->size;
uint32_t pnor_addr = PNOR_SPI_OFFSET;
bool readonly = false;
@@ -217,11 +217,13 @@ static const IPMINetfn hiomap_netfn = {
* Instantiate the machine BMC. PowerNV uses the QEMU internal
* simulator but it could also be external.
*/
-IPMIBmc *pnv_bmc_create(void)
+IPMIBmc *pnv_bmc_create(PnvPnor *pnor)
{
Object *obj;
obj = object_new(TYPE_IPMI_BMC_SIMULATOR);
+ object_ref(OBJECT(pnor));
+ object_property_add_const_link(obj, "pnor", OBJECT(pnor), &error_abort);
object_property_set_bool(obj, true, "realized", &error_fatal);
/* Install the HIOMAP protocol handlers to access the PNOR */
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 4b9012f994..2504d8cd4f 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -229,7 +229,7 @@ PnvChip *pnv_get_chip(uint32_t chip_id);
*/
void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
void pnv_bmc_powerdown(IPMIBmc *bmc);
-IPMIBmc *pnv_bmc_create(void);
+IPMIBmc *pnv_bmc_create(PnvPnor *pnor);
/*
* POWER8 MMIO base addresses
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 20/26] xive: Add a "presenter" link property to the TCTX object
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (18 preceding siblings ...)
2020-01-08 5:23 ` [PULL 19/26] ppc/pnv: Add a "pnor" const link property to the BMC internal simulator David Gibson
@ 2020-01-08 5:23 ` David Gibson
2020-01-08 5:23 ` [PULL 21/26] spapr/xive: Deduce the SpaprXive pointer from XiveTCTX::xptr David Gibson
` (6 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:23 UTC (permalink / raw)
To: peter.maydell; +Cc: lvivier, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Cédric Le Goater <clg@kaod.org>
This will be used in subsequent patches to access the XIVE associated to
a TCTX without reaching out to the machine through qdev_get_machine().
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[ groug: - split patch
- write subject and changelog ]
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200106145645.4539-9-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/spapr_xive.c | 2 +-
hw/intc/xive.c | 6 +++++-
hw/ppc/pnv.c | 3 ++-
include/hw/ppc/xive.h | 8 +++++---
4 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 32322470a8..7663123878 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -601,7 +601,7 @@ static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc,
Object *obj;
SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
- obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(xive), errp);
+ obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(xive), errp);
if (!obj) {
return -1;
}
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 12a362b681..bc8019c4c9 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -654,6 +654,7 @@ static void xive_tctx_realize(DeviceState *dev, Error **errp)
Error *local_err = NULL;
assert(tctx->cs);
+ assert(tctx->xptr);
cpu = POWERPC_CPU(tctx->cs);
env = &cpu->env;
@@ -727,6 +728,8 @@ static const VMStateDescription vmstate_xive_tctx = {
static Property xive_tctx_properties[] = {
DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *),
+ DEFINE_PROP_LINK("presenter", XiveTCTX, xptr, TYPE_XIVE_PRESENTER,
+ XivePresenter *),
DEFINE_PROP_END_OF_LIST(),
};
@@ -752,7 +755,7 @@ static const TypeInfo xive_tctx_info = {
.class_init = xive_tctx_class_init,
};
-Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp)
+Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp)
{
Error *local_err = NULL;
Object *obj;
@@ -761,6 +764,7 @@ Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp)
object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort);
object_unref(obj);
object_property_set_link(obj, cpu, "cpu", &error_abort);
+ object_property_set_link(obj, OBJECT(xptr), "presenter", &error_abort);
object_property_set_bool(obj, true, "realized", &local_err);
if (local_err) {
goto error;
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index f0b8f3ad26..19fc5d4ddb 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -925,7 +925,8 @@ static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
* controller object is initialized afterwards. Hopefully, it's
* only used at runtime.
*/
- obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err);
+ obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive),
+ &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 1ded82b1cd..705cf48176 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -311,6 +311,8 @@ void xive_source_set_irq(void *opaque, int srcno, int val);
#define XIVE_TM_RING_COUNT 4
#define XIVE_TM_RING_SIZE 0x10
+typedef struct XivePresenter XivePresenter;
+
typedef struct XiveTCTX {
DeviceState parent_obj;
@@ -319,6 +321,8 @@ typedef struct XiveTCTX {
qemu_irq os_output;
uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE];
+
+ XivePresenter *xptr;
} XiveTCTX;
/*
@@ -378,8 +382,6 @@ typedef struct XiveTCTXMatch {
uint8_t ring;
} XiveTCTXMatch;
-typedef struct XivePresenter XivePresenter;
-
#define TYPE_XIVE_PRESENTER "xive-presenter"
#define XIVE_PRESENTER(obj) \
INTERFACE_CHECK(XivePresenter, (obj), TYPE_XIVE_PRESENTER)
@@ -467,7 +469,7 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
unsigned size);
void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
-Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp);
+Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp);
void xive_tctx_reset(XiveTCTX *tctx);
void xive_tctx_destroy(XiveTCTX *tctx);
void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb);
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 21/26] spapr/xive: Deduce the SpaprXive pointer from XiveTCTX::xptr
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (19 preceding siblings ...)
2020-01-08 5:23 ` [PULL 20/26] xive: Add a "presenter" link property to the TCTX object David Gibson
@ 2020-01-08 5:23 ` David Gibson
2020-01-08 5:23 ` [PULL 22/26] pnv/xive: Deduce the PnvXive " David Gibson
` (5 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:23 UTC (permalink / raw)
To: peter.maydell; +Cc: lvivier, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
And use it instead of reaching out to the machine. This allows to get rid
of a call to qdev_get_machine() and to reduce the scope of another one so
that it is only used within the argument list of error_append_hint(). This
is an acceptable tradeoff compared to all it would require to know about
the maximum number of CPUs here without calling qdev_get_machine().
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200106145645.4539-10-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/spapr_xive_kvm.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c
index 32b2809210..edb7ee0e74 100644
--- a/hw/intc/spapr_xive_kvm.c
+++ b/hw/intc/spapr_xive_kvm.c
@@ -75,7 +75,7 @@ static void kvm_cpu_disable_all(void)
void kvmppc_xive_cpu_set_state(XiveTCTX *tctx, Error **errp)
{
- SpaprXive *xive = SPAPR_MACHINE(qdev_get_machine())->xive;
+ SpaprXive *xive = SPAPR_XIVE(tctx->xptr);
uint64_t state[2];
int ret;
@@ -97,7 +97,7 @@ void kvmppc_xive_cpu_set_state(XiveTCTX *tctx, Error **errp)
void kvmppc_xive_cpu_get_state(XiveTCTX *tctx, Error **errp)
{
- SpaprXive *xive = SPAPR_MACHINE(qdev_get_machine())->xive;
+ SpaprXive *xive = SPAPR_XIVE(tctx->xptr);
uint64_t state[2] = { 0 };
int ret;
@@ -152,8 +152,7 @@ void kvmppc_xive_cpu_synchronize_state(XiveTCTX *tctx, Error **errp)
void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp)
{
- MachineState *ms = MACHINE(qdev_get_machine());
- SpaprXive *xive = SPAPR_MACHINE(ms)->xive;
+ SpaprXive *xive = SPAPR_XIVE(tctx->xptr);
unsigned long vcpu_id;
int ret;
@@ -179,7 +178,7 @@ void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp)
vcpu_id, strerror(errno));
if (errno == ENOSPC) {
error_append_hint(&local_err, "Try -smp maxcpus=N with N < %u\n",
- ms->smp.max_cpus);
+ MACHINE(qdev_get_machine())->smp.max_cpus);
}
error_propagate(errp, local_err);
return;
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 22/26] pnv/xive: Deduce the PnvXive pointer from XiveTCTX::xptr
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (20 preceding siblings ...)
2020-01-08 5:23 ` [PULL 21/26] spapr/xive: Deduce the SpaprXive pointer from XiveTCTX::xptr David Gibson
@ 2020-01-08 5:23 ` David Gibson
2020-01-08 5:23 ` [PULL 23/26] pnv/psi: Add device reset hook David Gibson
` (4 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:23 UTC (permalink / raw)
To: peter.maydell; +Cc: lvivier, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
And use it instead of reaching out to the machine. This allows to get
rid of pnv_get_chip().
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200106145645.4539-11-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/pnv_xive.c | 8 ++------
hw/ppc/pnv.c | 14 --------------
include/hw/ppc/pnv.h | 2 --
3 files changed, 2 insertions(+), 22 deletions(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 6412cf222e..715fca61ae 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -472,12 +472,8 @@ static uint8_t pnv_xive_get_block_id(XiveRouter *xrtr)
static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu)
{
int pir = ppc_cpu_pir(cpu);
- PnvChip *chip;
- PnvXive *xive;
-
- chip = pnv_get_chip(PNV9_PIR2CHIP(pir));
- assert(chip);
- xive = &PNV9_CHIP(chip)->xive;
+ XivePresenter *xptr = XIVE_TCTX(pnv_cpu_state(cpu)->intc)->xptr;
+ PnvXive *xive = PNV_XIVE(xptr);
if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
xive_error(xive, "IC: CPU %x is not enabled", pir);
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 19fc5d4ddb..e2735bb8dd 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1717,20 +1717,6 @@ static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
return total_count;
}
-PnvChip *pnv_get_chip(uint32_t chip_id)
-{
- PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
- int i;
-
- for (i = 0; i < pnv->num_chips; i++) {
- PnvChip *chip = pnv->chips[i];
- if (chip->chip_id == chip_id) {
- return chip;
- }
- }
- return NULL;
-}
-
static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 2504d8cd4f..d65dd32036 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -219,8 +219,6 @@ struct PnvMachineState {
PnvPnor *pnor;
};
-PnvChip *pnv_get_chip(uint32_t chip_id);
-
#define PNV_FDT_ADDR 0x01000000
#define PNV_TIMEBASE_FREQ 512000000ULL
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 23/26] pnv/psi: Add device reset hook
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (21 preceding siblings ...)
2020-01-08 5:23 ` [PULL 22/26] pnv/xive: Deduce the PnvXive " David Gibson
@ 2020-01-08 5:23 ` David Gibson
2020-01-08 5:23 ` [PULL 24/26] pnv/psi: Consolidate some duplicated code in pnv_psi_realize() David Gibson
` (3 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:23 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, qemu-devel, groug, qemu-ppc, clg,
Philippe Mathieu-Daudé,
David Gibson
From: Greg Kurz <groug@kaod.org>
And call it from a QEMU reset handler. This allows each PNV child class to
override the reset hook if needed, eg. POWER8 doesn't but POWER9 does.
The proper way to do that would be to use device_class_set_parent_reset(),
but defining a Pnv8PsiClass and a Pnv9PsiClass types with a parent_reset
pointer adds a fair amount of code. Calling pnv_psi_reset() explicitely is
fine for now.
A subsequent patch will consolidate the call to qemu_register_reset() in
a single place.
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <157841476035.66386.17838417527621752518.stgit@bahia.tlslab.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv_psi.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 4da3d25686..846171914f 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -455,7 +455,7 @@ static const MemoryRegionOps pnv_psi_xscom_ops = {
}
};
-static void pnv_psi_reset(void *dev)
+static void pnv_psi_reset(DeviceState *dev)
{
PnvPsi *psi = PNV_PSI(dev);
@@ -464,6 +464,11 @@ static void pnv_psi_reset(void *dev)
psi->regs[PSIHB_XSCOM_BAR] = psi->bar | PSIHB_BAR_EN;
}
+static void pnv_psi_reset_handler(void *dev)
+{
+ device_reset(DEVICE(dev));
+}
+
static void pnv_psi_power8_instance_init(Object *obj)
{
Pnv8Psi *psi8 = PNV8_PSI(obj);
@@ -526,7 +531,7 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
((uint64_t) i << PSIHB_XIVR_SRC_SH);
}
- qemu_register_reset(pnv_psi_reset, dev);
+ qemu_register_reset(pnv_psi_reset_handler, dev);
}
static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
@@ -809,7 +814,7 @@ static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state)
qemu_set_irq(psi->qirqs[irq], state);
}
-static void pnv_psi_power9_reset(void *dev)
+static void pnv_psi_power9_reset(DeviceState *dev)
{
Pnv9Psi *psi = PNV9_PSI(dev);
@@ -863,7 +868,7 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN);
- qemu_register_reset(pnv_psi_power9_reset, dev);
+ qemu_register_reset(pnv_psi_reset_handler, dev);
}
static void pnv_psi_power9_class_init(ObjectClass *klass, void *data)
@@ -875,6 +880,7 @@ static void pnv_psi_power9_class_init(ObjectClass *klass, void *data)
dc->desc = "PowerNV PSI Controller POWER9";
dc->realize = pnv_psi_power9_realize;
+ dc->reset = pnv_psi_power9_reset;
ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE;
ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE;
@@ -927,6 +933,7 @@ static void pnv_psi_class_init(ObjectClass *klass, void *data)
dc->desc = "PowerNV PSI Controller";
dc->props = pnv_psi_properties;
+ dc->reset = pnv_psi_reset;
}
static const TypeInfo pnv_psi_info = {
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 24/26] pnv/psi: Consolidate some duplicated code in pnv_psi_realize()
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (22 preceding siblings ...)
2020-01-08 5:23 ` [PULL 23/26] pnv/psi: Add device reset hook David Gibson
@ 2020-01-08 5:23 ` David Gibson
2020-01-08 5:23 ` [PULL 25/26] ppc/pnv: check return value of blk_pwrite() David Gibson
` (2 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:23 UTC (permalink / raw)
To: peter.maydell; +Cc: lvivier, qemu-devel, groug, qemu-ppc, clg, David Gibson
From: Greg Kurz <groug@kaod.org>
The proper way to do that would be to use device_class_set_parent_realize(),
but defining a Pnv8PsiClass and a Pnv9PsiClass types with a parent_realize
pointer adds a fair amount of code. Calling pnv_psi_realize() explicitely
is fine for now.
This should probably be achieved with a device realize hook in the
PSI base class and device_class_set_parent_realize() in the children
classes.
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <157841476667.66386.13659183399113837990.stgit@bahia.tlslab.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv_psi.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 846171914f..1d8da31738 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -469,6 +469,16 @@ static void pnv_psi_reset_handler(void *dev)
device_reset(DEVICE(dev));
}
+static void pnv_psi_realize(DeviceState *dev, Error **errp)
+{
+ PnvPsi *psi = PNV_PSI(dev);
+
+ /* Default BAR for MMIO region */
+ pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN);
+
+ qemu_register_reset(pnv_psi_reset_handler, dev);
+}
+
static void pnv_psi_power8_instance_init(Object *obj)
{
Pnv8Psi *psi8 = PNV8_PSI(obj);
@@ -521,9 +531,6 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi,
"psihb", PNV_PSIHB_SIZE);
- /* Default BAR for MMIO region */
- pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN);
-
/* Default sources in XIVR */
for (i = 0; i < PSI_NUM_INTERRUPTS; i++) {
uint8_t xivr = irq_to_xivr[i];
@@ -531,7 +538,7 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
((uint64_t) i << PSIHB_XIVR_SRC_SH);
}
- qemu_register_reset(pnv_psi_reset_handler, dev);
+ pnv_psi_realize(dev, errp);
}
static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
@@ -866,9 +873,7 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
memory_region_init_io(&psi->regs_mr, OBJECT(dev), &pnv_psi_p9_mmio_ops, psi,
"psihb", PNV9_PSIHB_SIZE);
- pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN);
-
- qemu_register_reset(pnv_psi_reset_handler, dev);
+ pnv_psi_realize(dev, errp);
}
static void pnv_psi_power9_class_init(ObjectClass *klass, void *data)
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 25/26] ppc/pnv: check return value of blk_pwrite()
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (23 preceding siblings ...)
2020-01-08 5:23 ` [PULL 24/26] pnv/psi: Consolidate some duplicated code in pnv_psi_realize() David Gibson
@ 2020-01-08 5:23 ` David Gibson
2020-01-08 5:23 ` [PULL 26/26] ppc/pnv: fix check on return value of blk_getlength() David Gibson
2020-01-10 17:16 ` [PULL 00/26] ppc-for-5.0 queue 20200108 Peter Maydell
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:23 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, qemu-devel, groug, qemu-ppc, clg,
Philippe Mathieu-Daudé,
David Gibson
From: Cédric Le Goater <clg@kaod.org>
When updating the PNOR file contents, we should check for a possible
failure of blk_pwrite().
Fixes Coverity issue CID 1412228.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200107171809.15556-2-clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv_pnor.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/pnv_pnor.c b/hw/ppc/pnv_pnor.c
index bfb1e92b03..0e86ae2fea 100644
--- a/hw/ppc/pnv_pnor.c
+++ b/hw/ppc/pnv_pnor.c
@@ -33,6 +33,7 @@ static uint64_t pnv_pnor_read(void *opaque, hwaddr addr, unsigned size)
static void pnv_pnor_update(PnvPnor *s, int offset, int size)
{
int offset_end;
+ int ret;
if (s->blk) {
return;
@@ -42,8 +43,11 @@ static void pnv_pnor_update(PnvPnor *s, int offset, int size)
offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
- blk_pwrite(s->blk, offset, s->storage + offset,
- offset_end - offset, 0);
+ ret = blk_pwrite(s->blk, offset, s->storage + offset,
+ offset_end - offset, 0);
+ if (ret < 0) {
+ error_report("Could not update PNOR: %s", strerror(-ret));
+ }
}
static void pnv_pnor_write(void *opaque, hwaddr addr, uint64_t data,
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PULL 26/26] ppc/pnv: fix check on return value of blk_getlength()
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (24 preceding siblings ...)
2020-01-08 5:23 ` [PULL 25/26] ppc/pnv: check return value of blk_pwrite() David Gibson
@ 2020-01-08 5:23 ` David Gibson
2020-01-10 17:16 ` [PULL 00/26] ppc-for-5.0 queue 20200108 Peter Maydell
26 siblings, 0 replies; 28+ messages in thread
From: David Gibson @ 2020-01-08 5:23 UTC (permalink / raw)
To: peter.maydell
Cc: lvivier, qemu-devel, groug, qemu-ppc, clg,
Philippe Mathieu-Daudé,
David Gibson
From: Cédric Le Goater <clg@kaod.org>
blk_getlength() returns an int64_t but the result is stored in a
uint32_t. Errors (negative values) won't be caught by the check in
pnv_pnor_realize() and blk_blockalign() will allocate a very large
buffer in such cases.
Fixes Coverity issue CID 1412226.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200107171809.15556-3-clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv_pnor.c | 2 +-
include/hw/ppc/pnv_pnor.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/pnv_pnor.c b/hw/ppc/pnv_pnor.c
index 0e86ae2fea..b061106d1c 100644
--- a/hw/ppc/pnv_pnor.c
+++ b/hw/ppc/pnv_pnor.c
@@ -111,7 +111,7 @@ static void pnv_pnor_realize(DeviceState *dev, Error **errp)
}
static Property pnv_pnor_properties[] = {
- DEFINE_PROP_UINT32("size", PnvPnor, size, 128 << 20),
+ DEFINE_PROP_INT64("size", PnvPnor, size, 128 << 20),
DEFINE_PROP_DRIVE("drive", PnvPnor, blk),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/include/hw/ppc/pnv_pnor.h b/include/hw/ppc/pnv_pnor.h
index c3dd28643c..4f96abdfb4 100644
--- a/include/hw/ppc/pnv_pnor.h
+++ b/include/hw/ppc/pnv_pnor.h
@@ -23,7 +23,7 @@ typedef struct PnvPnor {
BlockBackend *blk;
uint8_t *storage;
- uint32_t size;
+ int64_t size;
MemoryRegion mmio;
} PnvPnor;
--
2.24.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PULL 00/26] ppc-for-5.0 queue 20200108
2020-01-08 5:22 [PULL 00/26] ppc-for-5.0 queue 20200108 David Gibson
` (25 preceding siblings ...)
2020-01-08 5:23 ` [PULL 26/26] ppc/pnv: fix check on return value of blk_getlength() David Gibson
@ 2020-01-10 17:16 ` Peter Maydell
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2020-01-10 17:16 UTC (permalink / raw)
To: David Gibson
Cc: Laurent Vivier, Cédric Le Goater, qemu-ppc, QEMU Developers,
Greg Kurz
On Wed, 8 Jan 2020 at 05:23, David Gibson <david@gibson.dropbear.id.au> wrote:
>
> The following changes since commit 035eed4c0d257c905a556fa0f4865a0c077b4e7f:
>
> Merge remote-tracking branch 'remotes/vivier/tags/q800-for-5.0-pull-request' into staging (2020-01-07 17:08:21 +0000)
>
> are available in the Git repository at:
>
> git://github.com/dgibson/qemu.git tags/ppc-for-5.0-20200108
>
> for you to fetch changes up to fc2527fb024abf92719952c939d751739455bd6b:
>
> ppc/pnv: fix check on return value of blk_getlength() (2020-01-08 12:01:14 +1100)
>
> ----------------------------------------------------------------
> ppc patch queue 2020-01-08
>
> Here's another pull request for qemu-5.0 of ppc related changes.
> Highlights are:
> * First parts of support for POWER Secure VMs
> * Rework to clean up how we pass context information to the various
> components of the pnv machine (reduces usage of qdev_get_machine())
> * Assorted cleanups and bugfixes
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 28+ messages in thread