* [PATCH 1/3] select gdb fpu xml by single or double float extension
@ 2020-01-10 8:12 ` LIU Zhiwei
0 siblings, 0 replies; 8+ messages in thread
From: LIU Zhiwei @ 2020-01-10 8:12 UTC (permalink / raw)
To: Alistair.Francis, palmer, chihmin.chao, jimw, bmeng.cn
Cc: wenmeng_zhang, qemu-riscv, qemu-devel, wxy194768, LIU Zhiwei
There is no reason why RISCV32 can't use RVD extension,
or RISCV64 can't just use RVF extension. And gdb will check
flen according to RVD or RVF feature in elf header.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
configure | 4 ++--
target/riscv/gdbstub.c | 14 ++++++--------
2 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/configure b/configure
index 0ce2c0354a..2757c0a5a5 100755
--- a/configure
+++ b/configure
@@ -7679,13 +7679,13 @@ case "$target_name" in
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
- gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml riscv-32bit-virtual.xml"
+ gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-csr.xml riscv-32bit-virtual.xml"
;;
riscv64)
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
- gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml"
+ gdb_xml_files="riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml"
;;
sh4|sh4eb)
TARGET_ARCH=sh4
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 1a7947e019..e3c9b320fb 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -403,23 +403,21 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
-#if defined(TARGET_RISCV32)
- if (env->misa & RVF) {
+ if (env->misa & RVD) {
+ gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
+ 36, "riscv-64bit-fpu.xml", 0);
+ } else if (env->misa & RVF) {
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
- 36, "riscv-32bit-fpu.xml", 0);
+ 36, "riscv-32bit-fpu.xml", 0);
}
+#if defined(TARGET_RISCV32)
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
240, "riscv-32bit-csr.xml", 0);
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
1, "riscv-32bit-virtual.xml", 0);
#elif defined(TARGET_RISCV64)
- if (env->misa & RVF) {
- gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
- 36, "riscv-64bit-fpu.xml", 0);
- }
-
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
240, "riscv-64bit-csr.xml", 0);
--
2.23.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 1/3] select gdb fpu xml by single or double float extension
@ 2020-01-10 8:12 ` LIU Zhiwei
0 siblings, 0 replies; 8+ messages in thread
From: LIU Zhiwei @ 2020-01-10 8:12 UTC (permalink / raw)
To: Alistair.Francis, palmer, chihmin.chao, jimw, bmeng.cn
Cc: wenmeng_zhang, wxy194768, qemu-devel, qemu-riscv, LIU Zhiwei
There is no reason why RISCV32 can't use RVD extension,
or RISCV64 can't just use RVF extension. And gdb will check
flen according to RVD or RVF feature in elf header.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
configure | 4 ++--
target/riscv/gdbstub.c | 14 ++++++--------
2 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/configure b/configure
index 0ce2c0354a..2757c0a5a5 100755
--- a/configure
+++ b/configure
@@ -7679,13 +7679,13 @@ case "$target_name" in
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
- gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml riscv-32bit-virtual.xml"
+ gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-csr.xml riscv-32bit-virtual.xml"
;;
riscv64)
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
- gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml"
+ gdb_xml_files="riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml"
;;
sh4|sh4eb)
TARGET_ARCH=sh4
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 1a7947e019..e3c9b320fb 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -403,23 +403,21 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
-#if defined(TARGET_RISCV32)
- if (env->misa & RVF) {
+ if (env->misa & RVD) {
+ gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
+ 36, "riscv-64bit-fpu.xml", 0);
+ } else if (env->misa & RVF) {
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
- 36, "riscv-32bit-fpu.xml", 0);
+ 36, "riscv-32bit-fpu.xml", 0);
}
+#if defined(TARGET_RISCV32)
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
240, "riscv-32bit-csr.xml", 0);
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
1, "riscv-32bit-virtual.xml", 0);
#elif defined(TARGET_RISCV64)
- if (env->misa & RVF) {
- gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
- 36, "riscv-64bit-fpu.xml", 0);
- }
-
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
240, "riscv-64bit-csr.xml", 0);
--
2.23.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/3] RISC-V: use FIELD macro to define tb flags
2020-01-10 8:12 ` LIU Zhiwei
@ 2020-01-10 8:12 ` LIU Zhiwei
-1 siblings, 0 replies; 8+ messages in thread
From: LIU Zhiwei @ 2020-01-10 8:12 UTC (permalink / raw)
To: Alistair.Francis, palmer, chihmin.chao, jimw, bmeng.cn
Cc: wenmeng_zhang, qemu-riscv, qemu-devel, wxy194768, LIU Zhiwei
FIELD is more unified to define tb flags. It is easier to add new
filed to tb flags.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.h | 15 +++++++++------
target/riscv/translate.c | 5 +++--
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index e59343e13c..8efd4c5904 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -282,22 +282,25 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
-#define TB_FLAGS_MMU_MASK 3
-#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
+FIELD(TB_FLAGS, MMU, 0, 2)
+FIELD(TB_FLAGS, FS, 13, 2)
static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
- target_ulong *cs_base, uint32_t *flags)
+ target_ulong *cs_base, uint32_t *pflags)
{
+ uint32_t flags = 0;
*pc = env->pc;
*cs_base = 0;
+
#ifdef CONFIG_USER_ONLY
- *flags = TB_FLAGS_MSTATUS_FS;
+ flags = FIELD_DP32(flags, TB_FLAGS, FS, MSTATUS_FS);
#else
- *flags = cpu_mmu_index(env, 0);
+ flags = FIELD_DP32(flags, TB_FLAGS, MMU, cpu_mmu_index(env, 0));
if (riscv_cpu_fp_enabled(env)) {
- *flags |= TB_FLAGS_MSTATUS_FS;
+ flags = FIELD_DP32(flags, TB_FLAGS, FS, (env->mstatus & MSTATUS_FS));
}
#endif
+ *pflags = flags;
}
int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ab6a891dc3..5de2d11d5c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -735,10 +735,11 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPURISCVState *env = cs->env_ptr;
RISCVCPU *cpu = RISCV_CPU(cs);
+ uint32_t tb_flags = ctx->base.tb->flags;
ctx->pc_succ_insn = ctx->base.pc_first;
- ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
- ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
+ ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MMU);
+ ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS);
ctx->priv_ver = env->priv_ver;
ctx->misa = env->misa;
ctx->frm = -1; /* unknown rounding mode */
--
2.23.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/3] RISC-V: use FIELD macro to define tb flags
@ 2020-01-10 8:12 ` LIU Zhiwei
0 siblings, 0 replies; 8+ messages in thread
From: LIU Zhiwei @ 2020-01-10 8:12 UTC (permalink / raw)
To: Alistair.Francis, palmer, chihmin.chao, jimw, bmeng.cn
Cc: wenmeng_zhang, wxy194768, qemu-devel, qemu-riscv, LIU Zhiwei
FIELD is more unified to define tb flags. It is easier to add new
filed to tb flags.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.h | 15 +++++++++------
target/riscv/translate.c | 5 +++--
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index e59343e13c..8efd4c5904 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -282,22 +282,25 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
-#define TB_FLAGS_MMU_MASK 3
-#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
+FIELD(TB_FLAGS, MMU, 0, 2)
+FIELD(TB_FLAGS, FS, 13, 2)
static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
- target_ulong *cs_base, uint32_t *flags)
+ target_ulong *cs_base, uint32_t *pflags)
{
+ uint32_t flags = 0;
*pc = env->pc;
*cs_base = 0;
+
#ifdef CONFIG_USER_ONLY
- *flags = TB_FLAGS_MSTATUS_FS;
+ flags = FIELD_DP32(flags, TB_FLAGS, FS, MSTATUS_FS);
#else
- *flags = cpu_mmu_index(env, 0);
+ flags = FIELD_DP32(flags, TB_FLAGS, MMU, cpu_mmu_index(env, 0));
if (riscv_cpu_fp_enabled(env)) {
- *flags |= TB_FLAGS_MSTATUS_FS;
+ flags = FIELD_DP32(flags, TB_FLAGS, FS, (env->mstatus & MSTATUS_FS));
}
#endif
+ *pflags = flags;
}
int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ab6a891dc3..5de2d11d5c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -735,10 +735,11 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPURISCVState *env = cs->env_ptr;
RISCVCPU *cpu = RISCV_CPU(cs);
+ uint32_t tb_flags = ctx->base.tb->flags;
ctx->pc_succ_insn = ctx->base.pc_first;
- ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
- ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
+ ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MMU);
+ ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS);
ctx->priv_ver = env->priv_ver;
ctx->misa = env->misa;
ctx->frm = -1; /* unknown rounding mode */
--
2.23.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/3] remove redundant check for fpu csr read and write interface
2020-01-10 8:12 ` LIU Zhiwei
@ 2020-01-10 8:12 ` LIU Zhiwei
-1 siblings, 0 replies; 8+ messages in thread
From: LIU Zhiwei @ 2020-01-10 8:12 UTC (permalink / raw)
To: Alistair.Francis, palmer, chihmin.chao, jimw, bmeng.cn
Cc: wenmeng_zhang, qemu-riscv, qemu-devel, wxy194768, LIU Zhiwei
The read or write interface must be called after the predicate fs return 0.
And the predicate will check (!env->debugger && !riscv_cpu_fp_enabled(env)),
S0 no need to check again.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/csr.c | 24 ------------------------
1 file changed, 24 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index da02f9f0b1..0c2b8fc8f6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -107,11 +107,6 @@ static int pmp(CPURISCVState *env, int csrno)
/* User Floating-Point CSRs */
static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
{
-#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
- }
-#endif
*val = riscv_cpu_get_fflags(env);
return 0;
}
@@ -119,9 +114,6 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
- }
env->mstatus |= MSTATUS_FS;
#endif
riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
@@ -130,11 +122,6 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
{
-#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
- }
-#endif
*val = env->frm;
return 0;
}
@@ -142,9 +129,6 @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
- }
env->mstatus |= MSTATUS_FS;
#endif
env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
@@ -153,11 +137,6 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
{
-#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
- }
-#endif
*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
| (env->frm << FSR_RD_SHIFT);
return 0;
@@ -166,9 +145,6 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
- }
env->mstatus |= MSTATUS_FS;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
--
2.23.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/3] remove redundant check for fpu csr read and write interface
@ 2020-01-10 8:12 ` LIU Zhiwei
0 siblings, 0 replies; 8+ messages in thread
From: LIU Zhiwei @ 2020-01-10 8:12 UTC (permalink / raw)
To: Alistair.Francis, palmer, chihmin.chao, jimw, bmeng.cn
Cc: wenmeng_zhang, wxy194768, qemu-devel, qemu-riscv, LIU Zhiwei
The read or write interface must be called after the predicate fs return 0.
And the predicate will check (!env->debugger && !riscv_cpu_fp_enabled(env)),
S0 no need to check again.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/csr.c | 24 ------------------------
1 file changed, 24 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index da02f9f0b1..0c2b8fc8f6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -107,11 +107,6 @@ static int pmp(CPURISCVState *env, int csrno)
/* User Floating-Point CSRs */
static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
{
-#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
- }
-#endif
*val = riscv_cpu_get_fflags(env);
return 0;
}
@@ -119,9 +114,6 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
- }
env->mstatus |= MSTATUS_FS;
#endif
riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
@@ -130,11 +122,6 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
{
-#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
- }
-#endif
*val = env->frm;
return 0;
}
@@ -142,9 +129,6 @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
- }
env->mstatus |= MSTATUS_FS;
#endif
env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
@@ -153,11 +137,6 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
{
-#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
- }
-#endif
*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
| (env->frm << FSR_RD_SHIFT);
return 0;
@@ -166,9 +145,6 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
- }
env->mstatus |= MSTATUS_FS;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
--
2.23.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] RISC-V: use FIELD macro to define tb flags
2020-01-10 8:12 ` LIU Zhiwei
(?)
@ 2020-01-14 2:22 ` Richard Henderson
-1 siblings, 0 replies; 8+ messages in thread
From: Richard Henderson @ 2020-01-14 2:22 UTC (permalink / raw)
To: LIU Zhiwei, Alistair.Francis, palmer, chihmin.chao, jimw, bmeng.cn
Cc: wenmeng_zhang, qemu-riscv, qemu-devel, wxy194768
On 1/9/20 10:12 PM, LIU Zhiwei wrote:
> if (riscv_cpu_fp_enabled(env)) {
> - *flags |= TB_FLAGS_MSTATUS_FS;
> + flags = FIELD_DP32(flags, TB_FLAGS, FS, (env->mstatus & MSTATUS_FS));
> }
This is wrong. You're inserting the low two bits of
env->mstatus & MSTATUS_FS
into TB_FLAGS. Which, knowing that MSTATUS_FS == 0x6000, is of course always 0.
Because of how TB_FLAGS_MSTATUS_FS is defined, overlapping MSTATUS_FS, you
could just have
*flags |= env->mstatus & MSTATUS_FS;
BTW, the *existing* code is wrong. This merges all non-disabled states to
dirty. This means that the code in mark_fs_dirty in translate.c that handles
initial and clean states is unreachable, and that the kernel's dirty state
tracking will not work.
Has the riscv kernel stopped doing lazy fp context switching? I would imagine
that it has if this code is to be believed...
BTW2, for the purpose of tb_flags, initial and clean states are identical. We
should probably fold them, to avoid generating two different TBs for the two
states.
r~
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] remove redundant check for fpu csr read and write interface
2020-01-10 8:12 ` LIU Zhiwei
(?)
@ 2020-01-14 2:24 ` Richard Henderson
-1 siblings, 0 replies; 8+ messages in thread
From: Richard Henderson @ 2020-01-14 2:24 UTC (permalink / raw)
To: LIU Zhiwei, Alistair.Francis, palmer, chihmin.chao, jimw, bmeng.cn
Cc: wenmeng_zhang, qemu-riscv, qemu-devel, wxy194768
On 1/9/20 10:12 PM, LIU Zhiwei wrote:
> The read or write interface must be called after the predicate fs return 0.
> And the predicate will check (!env->debugger && !riscv_cpu_fp_enabled(env)),
> S0 no need to check again.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
> target/riscv/csr.c | 24 ------------------------
> 1 file changed, 24 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-01-14 2:24 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-10 8:12 [PATCH 1/3] select gdb fpu xml by single or double float extension LIU Zhiwei
2020-01-10 8:12 ` LIU Zhiwei
2020-01-10 8:12 ` [PATCH 2/3] RISC-V: use FIELD macro to define tb flags LIU Zhiwei
2020-01-10 8:12 ` LIU Zhiwei
2020-01-14 2:22 ` Richard Henderson
2020-01-10 8:12 ` [PATCH 3/3] remove redundant check for fpu csr read and write interface LIU Zhiwei
2020-01-10 8:12 ` LIU Zhiwei
2020-01-14 2:24 ` Richard Henderson
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