From: Andre Przywara <andre.przywara@arm.com> To: "David S . Miller" <davem@davemloft.net>, Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com>, Robert Hancock <hancock@sedsystems.ca>, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, devicetree@vger.kernel.org Subject: [PATCH 13/14] net: axienet: Allow DMA to beyond 4GB Date: Fri, 10 Jan 2020 11:54:14 +0000 [thread overview] Message-ID: <20200110115415.75683-14-andre.przywara@arm.com> (raw) In-Reply-To: <20200110115415.75683-1-andre.przywara@arm.com> With all DMA address accesses wrapped, we can actually support 64-bit DMA if this option was chosen at IP integration time. Since there is no way to autodetect the actual address bus width, we make use of the existing "xlnx,addrwidth" DT property to let the driver know about the width. The value in this property should match the "Address Width" parameter used when synthesizing the IP. This increases the DMA mask to let the kernel choose buffers from memory at higher addresses. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- .../net/ethernet/xilinx/xilinx_axienet_main.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c index f7f593df0c11..e036834549b3 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -1786,6 +1786,7 @@ static int axienet_probe(struct platform_device *pdev) struct net_device *ndev; const void *mac_addr; struct resource *ethres; + int addr_width = 32; u32 value; ndev = alloc_etherdev(sizeof(*lp)); @@ -1915,6 +1916,8 @@ static int axienet_probe(struct platform_device *pdev) &dmares); lp->rx_irq = irq_of_parse_and_map(np, 1); lp->tx_irq = irq_of_parse_and_map(np, 0); + of_property_read_u32(np, "xlnx,addrwidth", &addr_width); + of_node_put(np); lp->eth_irq = platform_get_irq(pdev, 0); } else { @@ -1944,6 +1947,9 @@ static int axienet_probe(struct platform_device *pdev) * We can detect this case by writing all 1's to one such register * and see if that sticks: when the IP is configured for 32 bits * only, those registers are RES0. + * We can't autodetect the actual width this way, so we still use + * a 32-bit DMA mask and rely on the xlnk,addrwidth DT property + * to set this properly. * Those MSB registers were introduced in IP v7.1, which we check first. */ if ((axienet_ior(lp, XAE_ID_OFFSET) >> 24) >= 0x9) { @@ -1961,6 +1967,19 @@ static int axienet_probe(struct platform_device *pdev) } } + if (!(lp->features & XAE_FEATURE_DMA_64BIT)) { + if (addr_width > 32) + dev_warn(&pdev->dev, "trimming DMA width from %d to 32 bits\n", + addr_width); + addr_width = 32; + } + + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_width)); + if (ret) { + dev_err(&pdev->dev, "No suitable DMA available\n"); + goto free_netdev; + } + /* Check for Ethernet core IRQ (optional) */ if (lp->eth_irq <= 0) dev_info(&pdev->dev, "Ethernet core IRQ not defined\n"); -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Andre Przywara <andre.przywara@arm.com> To: "David S . Miller" <davem@davemloft.net>, Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Cc: Mark Rutland <mark.rutland@arm.com>, devicetree@vger.kernel.org, netdev@vger.kernel.org, Michal Simek <michal.simek@xilinx.com>, linux-kernel@vger.kernel.org, Robert Hancock <hancock@sedsystems.ca>, Rob Herring <robh+dt@kernel.org>, linux-arm-kernel@lists.infradead.org Subject: [PATCH 13/14] net: axienet: Allow DMA to beyond 4GB Date: Fri, 10 Jan 2020 11:54:14 +0000 [thread overview] Message-ID: <20200110115415.75683-14-andre.przywara@arm.com> (raw) In-Reply-To: <20200110115415.75683-1-andre.przywara@arm.com> With all DMA address accesses wrapped, we can actually support 64-bit DMA if this option was chosen at IP integration time. Since there is no way to autodetect the actual address bus width, we make use of the existing "xlnx,addrwidth" DT property to let the driver know about the width. The value in this property should match the "Address Width" parameter used when synthesizing the IP. This increases the DMA mask to let the kernel choose buffers from memory at higher addresses. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- .../net/ethernet/xilinx/xilinx_axienet_main.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c index f7f593df0c11..e036834549b3 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -1786,6 +1786,7 @@ static int axienet_probe(struct platform_device *pdev) struct net_device *ndev; const void *mac_addr; struct resource *ethres; + int addr_width = 32; u32 value; ndev = alloc_etherdev(sizeof(*lp)); @@ -1915,6 +1916,8 @@ static int axienet_probe(struct platform_device *pdev) &dmares); lp->rx_irq = irq_of_parse_and_map(np, 1); lp->tx_irq = irq_of_parse_and_map(np, 0); + of_property_read_u32(np, "xlnx,addrwidth", &addr_width); + of_node_put(np); lp->eth_irq = platform_get_irq(pdev, 0); } else { @@ -1944,6 +1947,9 @@ static int axienet_probe(struct platform_device *pdev) * We can detect this case by writing all 1's to one such register * and see if that sticks: when the IP is configured for 32 bits * only, those registers are RES0. + * We can't autodetect the actual width this way, so we still use + * a 32-bit DMA mask and rely on the xlnk,addrwidth DT property + * to set this properly. * Those MSB registers were introduced in IP v7.1, which we check first. */ if ((axienet_ior(lp, XAE_ID_OFFSET) >> 24) >= 0x9) { @@ -1961,6 +1967,19 @@ static int axienet_probe(struct platform_device *pdev) } } + if (!(lp->features & XAE_FEATURE_DMA_64BIT)) { + if (addr_width > 32) + dev_warn(&pdev->dev, "trimming DMA width from %d to 32 bits\n", + addr_width); + addr_width = 32; + } + + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_width)); + if (ret) { + dev_err(&pdev->dev, "No suitable DMA available\n"); + goto free_netdev; + } + /* Check for Ethernet core IRQ (optional) */ if (lp->eth_irq <= 0) dev_info(&pdev->dev, "Ethernet core IRQ not defined\n"); -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-01-10 11:54 UTC|newest] Thread overview: 130+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-01-10 11:54 [PATCH 00/14] net: axienet: Error handling, SGMII and 64-bit DMA fixes Andre Przywara 2020-01-10 11:54 ` Andre Przywara 2020-01-10 11:54 ` [PATCH 01/14] net: xilinx: temac: Relax Kconfig dependencies Andre Przywara 2020-01-10 11:54 ` Andre Przywara 2020-01-10 14:19 ` Radhey Shyam Pandey 2020-01-10 14:19 ` Radhey Shyam Pandey 2020-01-10 11:54 ` [PATCH 02/14] net: axienet: Propagate failure of DMA descriptor setup Andre Przywara 2020-01-10 11:54 ` Andre Przywara 2020-01-10 14:54 ` Radhey Shyam Pandey 2020-01-10 14:54 ` Radhey Shyam Pandey 2020-01-10 17:53 ` Radhey Shyam Pandey 2020-01-10 17:53 ` Radhey Shyam Pandey 2020-01-10 11:54 ` [PATCH 03/14] net: axienet: Fix DMA descriptor cleanup path Andre Przywara 2020-01-10 11:54 ` Andre Przywara 2020-01-10 15:14 ` Radhey Shyam Pandey 2020-01-10 15:14 ` Radhey Shyam Pandey 2020-01-10 15:43 ` Andre Przywara 2020-01-10 15:43 ` Andre Przywara 2020-01-10 17:05 ` Radhey Shyam Pandey 2020-01-10 17:05 ` Radhey Shyam Pandey 2020-01-16 18:03 ` Andre Przywara 2020-01-16 18:03 ` Andre Przywara 2020-01-20 18:32 ` Radhey Shyam Pandey 2020-01-20 18:32 ` Radhey Shyam Pandey 2020-01-10 11:54 ` [PATCH 04/14] net: axienet: Improve DMA error handling Andre Przywara 2020-01-10 11:54 ` Andre Przywara 2020-01-10 15:26 ` Radhey Shyam Pandey 2020-01-10 15:26 ` Radhey Shyam Pandey 2020-01-10 11:54 ` [PATCH 05/14] net: axienet: Factor out TX descriptor chain cleanup Andre Przywara 2020-01-10 11:54 ` Andre Przywara 2020-01-10 18:04 ` Radhey Shyam Pandey 2020-01-10 18:04 ` Radhey Shyam Pandey 2020-01-10 11:54 ` [PATCH 06/14] net: axienet: Check for DMA mapping errors Andre Przywara 2020-01-10 11:54 ` Andre Przywara 2020-01-13 5:54 ` Radhey Shyam Pandey 2020-01-13 5:54 ` Radhey Shyam Pandey 2020-01-10 11:54 ` [PATCH 07/14] net: axienet: Fix SGMII support Andre Przywara 2020-01-10 11:54 ` Andre Przywara 2020-01-10 14:04 ` Andrew Lunn 2020-01-10 14:04 ` Andrew Lunn 2020-01-10 14:20 ` Andre Przywara 2020-01-10 14:20 ` Andre Przywara 2020-01-10 14:26 ` Andrew Lunn 2020-01-10 14:26 ` Andrew Lunn 2020-01-10 15:04 ` Russell King - ARM Linux admin 2020-01-10 15:04 ` Russell King - ARM Linux admin 2020-01-10 15:22 ` Russell King - ARM Linux admin 2020-01-10 15:22 ` Russell King - ARM Linux admin 2020-01-10 17:04 ` Russell King - ARM Linux admin 2020-01-10 17:04 ` Russell King - ARM Linux admin 2020-01-18 11:22 ` Russell King - ARM Linux admin 2020-01-18 11:22 ` Russell King - ARM Linux admin 2020-01-20 14:50 ` Andre Przywara 2020-01-20 14:50 ` Andre Przywara 2020-01-20 15:45 ` Russell King - ARM Linux admin 2020-01-20 15:45 ` Russell King - ARM Linux admin 2020-01-27 17:04 ` Andre Przywara 2020-01-27 17:04 ` Andre Przywara 2020-01-27 17:20 ` Radhey Shyam Pandey 2020-01-27 17:20 ` Radhey Shyam Pandey 2020-01-27 18:53 ` Russell King - ARM Linux admin 2020-01-27 18:53 ` Russell King - ARM Linux admin 2020-04-22 1:45 ` Xilinx axienet 1000BaseX support (was: Re: [PATCH 07/14] net: axienet: Fix SGMII support) Robert Hancock 2020-04-22 1:45 ` Robert Hancock 2020-04-22 7:51 ` Russell King - ARM Linux admin 2020-04-22 7:51 ` Russell King - ARM Linux admin 2020-04-22 16:31 ` Xilinx axienet 1000BaseX support Robert Hancock 2020-04-22 16:31 ` Robert Hancock 2020-04-28 21:59 ` Robert Hancock 2020-04-28 21:59 ` Robert Hancock 2020-04-28 23:01 ` Russell King - ARM Linux admin 2020-04-28 23:01 ` Russell King - ARM Linux admin 2020-04-28 23:51 ` Robert Hancock 2020-04-28 23:51 ` Robert Hancock 2020-04-29 8:21 ` Russell King - ARM Linux admin 2020-04-29 8:21 ` Russell King - ARM Linux admin 2020-01-10 14:58 ` [PATCH 07/14] net: axienet: Fix SGMII support Russell King - ARM Linux admin 2020-01-10 14:58 ` Russell King - ARM Linux admin 2020-01-10 17:32 ` Andre Przywara 2020-01-10 17:32 ` Andre Przywara 2020-01-10 18:05 ` Russell King - ARM Linux admin 2020-01-10 18:05 ` Russell King - ARM Linux admin 2020-01-10 19:33 ` Andrew Lunn 2020-01-10 19:33 ` Andrew Lunn 2020-01-10 11:54 ` [PATCH 08/14] net: axienet: Drop MDIO interrupt registers from ethtools dump Andre Przywara 2020-01-10 11:54 ` Andre Przywara 2020-01-13 6:02 ` Radhey Shyam Pandey 2020-01-13 6:02 ` Radhey Shyam Pandey 2020-01-10 11:54 ` [PATCH 09/14] net: axienet: Add mii-tool support Andre Przywara 2020-01-10 11:54 ` Andre Przywara 2020-01-13 6:12 ` Radhey Shyam Pandey 2020-01-13 6:12 ` Radhey Shyam Pandey 2020-03-12 11:41 ` Andre Przywara 2020-03-12 11:41 ` Andre Przywara 2020-01-10 11:54 ` [PATCH 10/14] net: axienet: Wrap DMA pointer writes to prepare for 64 bit Andre Przywara 2020-01-10 11:54 ` Andre Przywara 2020-01-10 11:54 ` [PATCH 11/14] net: axienet: Upgrade descriptors to hold 64-bit addresses Andre Przywara 2020-01-10 11:54 ` Andre Przywara 2020-01-14 16:35 ` Radhey Shyam Pandey 2020-01-14 16:35 ` Radhey Shyam Pandey 2020-01-14 17:29 ` Andre Przywara 2020-01-14 17:29 ` Andre Przywara 2020-01-10 11:54 ` [PATCH 12/14] net: axienet: Autodetect 64-bit DMA capability Andre Przywara 2020-01-10 11:54 ` Andre Przywara 2020-01-10 14:08 ` Andrew Lunn 2020-01-10 14:08 ` Andrew Lunn 2020-01-10 14:13 ` Andre Przywara 2020-01-10 14:13 ` Andre Przywara 2020-01-10 14:22 ` Andrew Lunn 2020-01-10 14:22 ` Andrew Lunn 2020-01-10 15:08 ` Andre Przywara 2020-01-10 15:08 ` Andre Przywara 2020-01-10 15:22 ` Andrew Lunn 2020-01-10 15:22 ` Andrew Lunn 2020-01-14 17:03 ` Radhey Shyam Pandey 2020-01-14 17:03 ` Radhey Shyam Pandey 2020-01-14 17:41 ` Andre Przywara 2020-01-14 17:41 ` Andre Przywara 2020-01-15 6:02 ` Radhey Shyam Pandey 2020-01-15 6:02 ` Radhey Shyam Pandey 2020-01-10 11:54 ` Andre Przywara [this message] 2020-01-10 11:54 ` [PATCH 13/14] net: axienet: Allow DMA to beyond 4GB Andre Przywara 2020-01-10 11:54 ` [PATCH 14/14] net: axienet: Update devicetree binding documentation Andre Przywara 2020-01-10 11:54 ` Andre Przywara 2020-01-21 21:51 ` Rob Herring 2020-01-21 21:51 ` Rob Herring 2020-01-24 16:29 ` Andre Przywara 2020-01-24 16:29 ` Andre Przywara 2020-01-27 9:28 ` Radhey Shyam Pandey 2020-01-27 9:28 ` Radhey Shyam Pandey
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