From: Imre Deak <imre.deak@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 11/17] drm/i915: s/init_cdclk/init_cdclk_hw/
Date: Fri, 24 Jan 2020 17:08:59 +0200 [thread overview]
Message-ID: <20200124150859.GD32347@ideak-desk.fi.intel.com> (raw)
In-Reply-To: <20200120174728.21095-12-ville.syrjala@linux.intel.com>
On Mon, Jan 20, 2020 at 07:47:21PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Give the cdclk init/uninit functions a _hw suffix to make
> it clear they are about initializing the actual hardware.
> I'll be wanting to to add a intel_cdclk_init() which is
> purely initializing software structures.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 24 +++++++++----------
> drivers/gpu/drm/i915/display/intel_cdclk.h | 4 ++--
> .../drm/i915/display/intel_display_power.c | 16 ++++++-------
> 3 files changed, 22 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 002044e80868..701a63c3ca38 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1122,7 +1122,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> dev_priv->cdclk.hw.vco = -1;
> }
>
> -static void skl_init_cdclk(struct drm_i915_private *dev_priv)
> +static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
> {
> struct intel_cdclk_config cdclk_config;
>
> @@ -1151,7 +1151,7 @@ static void skl_init_cdclk(struct drm_i915_private *dev_priv)
> skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
> }
>
> -static void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
> +static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
> {
> struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
>
> @@ -1681,7 +1681,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
> dev_priv->cdclk.hw.vco = -1;
> }
>
> -static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
> +static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
> {
> struct intel_cdclk_config cdclk_config;
>
> @@ -1706,7 +1706,7 @@ static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
> bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
> }
>
> -static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
> +static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
> {
> struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
>
> @@ -1719,7 +1719,7 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
> }
>
> /**
> - * intel_cdclk_init - Initialize CDCLK
> + * intel_cdclk_init_hw - Initialize CDCLK hardware
> * @i915: i915 device
> *
> * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
> @@ -1727,27 +1727,27 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
> * during the display core initialization sequence, after which the DMC will
> * take care of turning CDCLK off/on as needed.
> */
> -void intel_cdclk_init(struct drm_i915_private *i915)
> +void intel_cdclk_init_hw(struct drm_i915_private *i915)
> {
> if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
> - bxt_init_cdclk(i915);
> + bxt_cdclk_init_hw(i915);
> else if (IS_GEN9_BC(i915))
> - skl_init_cdclk(i915);
> + skl_cdclk_init_hw(i915);
> }
>
> /**
> - * intel_cdclk_uninit - Uninitialize CDCLK
> + * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
> * @i915: i915 device
> *
> * Uninitialize CDCLK. This is done only during the display core
> * uninitialization sequence.
> */
> -void intel_cdclk_uninit(struct drm_i915_private *i915)
> +void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
> {
> if (INTEL_GEN(i915) >= 10 || IS_GEN9_LP(i915))
> - bxt_uninit_cdclk(i915);
> + bxt_cdclk_uninit_hw(i915);
> else if (IS_GEN9_BC(i915))
> - skl_uninit_cdclk(i915);
> + skl_cdclk_uninit_hw(i915);
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index a3fb7b8e8d31..4b965db07720 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -23,8 +23,8 @@ struct intel_cdclk_vals {
> };
>
> int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
> -void intel_cdclk_init(struct drm_i915_private *i915);
> -void intel_cdclk_uninit(struct drm_i915_private *i915);
> +void intel_cdclk_init_hw(struct drm_i915_private *i915);
> +void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
> void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
> void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
> void intel_update_cdclk(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 2dc00d4b115b..3412c56bea6d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -4763,7 +4763,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
>
> mutex_unlock(&power_domains->lock);
>
> - intel_cdclk_init(dev_priv);
> + intel_cdclk_init_hw(dev_priv);
>
> gen9_dbuf_enable(dev_priv);
>
> @@ -4780,7 +4780,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
>
> gen9_dbuf_disable(dev_priv);
>
> - intel_cdclk_uninit(dev_priv);
> + intel_cdclk_uninit_hw(dev_priv);
>
> /* The spec doesn't call for removing the reset handshake flag */
> /* disable PG1 and Misc I/O */
> @@ -4824,7 +4824,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
>
> mutex_unlock(&power_domains->lock);
>
> - intel_cdclk_init(dev_priv);
> + intel_cdclk_init_hw(dev_priv);
>
> gen9_dbuf_enable(dev_priv);
>
> @@ -4841,7 +4841,7 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
>
> gen9_dbuf_disable(dev_priv);
>
> - intel_cdclk_uninit(dev_priv);
> + intel_cdclk_uninit_hw(dev_priv);
>
> /* The spec doesn't call for removing the reset handshake flag */
>
> @@ -4883,7 +4883,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
> mutex_unlock(&power_domains->lock);
>
> /* 5. Enable CD clock */
> - intel_cdclk_init(dev_priv);
> + intel_cdclk_init_hw(dev_priv);
>
> /* 6. Enable DBUF */
> gen9_dbuf_enable(dev_priv);
> @@ -4905,7 +4905,7 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
> gen9_dbuf_disable(dev_priv);
>
> /* 3. Disable CD clock */
> - intel_cdclk_uninit(dev_priv);
> + intel_cdclk_uninit_hw(dev_priv);
>
> /*
> * 4. Disable Power Well 1 (PG1).
> @@ -4997,7 +4997,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> mutex_unlock(&power_domains->lock);
>
> /* 4. Enable CDCLK. */
> - intel_cdclk_init(dev_priv);
> + intel_cdclk_init_hw(dev_priv);
>
> /* 5. Enable DBUF. */
> icl_dbuf_enable(dev_priv);
> @@ -5026,7 +5026,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
> icl_dbuf_disable(dev_priv);
>
> /* 3. Disable CD clock */
> - intel_cdclk_uninit(dev_priv);
> + intel_cdclk_uninit_hw(dev_priv);
>
> /*
> * 4. Disable Power Well 1 (PG1).
> --
> 2.24.1
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2020-01-24 15:13 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
2020-01-20 17:47 ` [Intel-gfx] [PATCH 01/17] drm/i915: Polish WM_LINETIME register stuff Ville Syrjala
2020-01-20 17:47 ` [Intel-gfx] [PATCH 02/17] drm/i915: Move linetime wms into the crtc state Ville Syrjala
2020-01-29 14:05 ` Lisovskiy, Stanislav
2020-01-31 15:07 ` Ville Syrjälä
2020-01-20 17:47 ` [Intel-gfx] [PATCH 03/17] drm/i915: Nuke skl wm.dirty_pipes bitmask Ville Syrjala
2020-01-20 17:47 ` [Intel-gfx] [PATCH 04/17] drm/i915: Move more cdclk state handling into the cdclk code Ville Syrjala
2020-01-22 18:39 ` Souza, Jose
2020-01-20 17:47 ` [Intel-gfx] [PATCH 05/17] drm/i915: Collect more cdclk state under the same roof Ville Syrjala
2020-01-22 18:43 ` Souza, Jose
2020-01-20 17:47 ` [Intel-gfx] [PATCH 06/17] drm/i915: s/need_cd2x_updare/can_cd2x_update/ Ville Syrjala
2020-01-24 12:24 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 07/17] drm/i915: s/cdclk_state/cdclk_config/ Ville Syrjala
2020-01-22 18:51 ` Souza, Jose
2020-01-20 17:47 ` [Intel-gfx] [PATCH 08/17] drm/i915: Simplify intel_set_cdclk_{pre, post}_plane_update() calling convention Ville Syrjala
2020-01-22 18:51 ` Souza, Jose
2020-01-20 17:47 ` [Intel-gfx] [PATCH 09/17] drm/i915: Extract intel_cdclk_state Ville Syrjala
2020-01-22 18:51 ` Souza, Jose
2020-01-20 17:47 ` [Intel-gfx] [PATCH 10/17] drm/i915: swap() the entire cdclk state Ville Syrjala
2020-01-24 15:06 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 11/17] drm/i915: s/init_cdclk/init_cdclk_hw/ Ville Syrjala
2020-01-24 15:08 ` Imre Deak [this message]
2020-01-20 17:47 ` [Intel-gfx] [PATCH 12/17] drm/i915: Move intel_atomic_state_free() into intel_atomic.c Ville Syrjala
2020-01-24 15:19 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 13/17] drm/i915: Intrduce better global state handling Ville Syrjala
2020-01-28 14:44 ` Lisovskiy, Stanislav
2020-01-28 15:29 ` Ville Syrjälä
2020-01-20 17:47 ` [Intel-gfx] [PATCH 13/17] drm/i915: Introduce " Ville Syrjala
2020-01-22 19:00 ` Souza, Jose
2020-01-22 19:11 ` Ville Syrjälä
2020-01-27 15:02 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 14/17] drm/i915: Convert bandwidth state to global state Ville Syrjala
2020-01-27 15:21 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 15/17] drm/i915: Introduce intel_calc_active_pipes() Ville Syrjala
2020-01-27 15:25 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 16/17] drm/i915: Convert cdclk to global state Ville Syrjala
2020-01-21 14:03 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2020-01-27 17:03 ` Imre Deak
2020-01-27 17:15 ` Ville Syrjälä
2020-01-27 17:54 ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 17/17] drm/i915: Store active_pipes bitmask in cdclk state Ville Syrjala
2020-01-27 17:11 ` Imre Deak
2020-01-20 18:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Global state rework Patchwork
2020-01-21 2:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-01-21 13:32 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-01-21 17:58 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Global state rework (rev2) Patchwork
2020-01-21 18:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-01-23 0:02 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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