All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Souza, Jose" <jose.souza@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 04/17] drm/i915: Move more cdclk state handling into the cdclk code
Date: Wed, 22 Jan 2020 18:39:44 +0000	[thread overview]
Message-ID: <2ec65516cf9f62f2d8f551f5c242c662a68317c9.camel@intel.com> (raw)
In-Reply-To: <20200120174728.21095-5-ville.syrjala@linux.intel.com>

On Mon, 2020-01-20 at 19:47 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Move the initial setup of state-
> >{cdclk,min_cdclk[],min_voltage_level[]}
> into intel_modeset_calc_cdclk(), and we'll move the counterparts into
> intel_cdclk_swap_state(). This encapsulates the cdclk state much
> better.
> 

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c   | 26 +++++++++++++++---
> --
>  drivers/gpu/drm/i915/display/intel_display.c | 11 ---------
>  2 files changed, 20 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 0ce5926006ca..05f6c6456ddf 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1819,6 +1819,14 @@ void intel_cdclk_swap_state(struct
> intel_atomic_state *state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>  
> +	/* FIXME maybe swap() these too */
> +	memcpy(dev_priv->min_cdclk, state->min_cdclk,
> +	       sizeof(state->min_cdclk));
> +	memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
> +	       sizeof(state->min_voltage_level));
> +
> +	dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
> +
>  	swap(state->cdclk.logical, dev_priv->cdclk.logical);
>  	swap(state->cdclk.actual, dev_priv->cdclk.actual);
>  }
> @@ -2033,9 +2041,6 @@ static int intel_compute_min_cdclk(struct
> intel_atomic_state *state)
>  	int min_cdclk, i;
>  	enum pipe pipe;
>  
> -	memcpy(state->min_cdclk, dev_priv->min_cdclk,
> -	       sizeof(state->min_cdclk));
> -
>  	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
>  		int ret;
>  
> @@ -2082,9 +2087,6 @@ static int bxt_compute_min_voltage_level(struct
> intel_atomic_state *state)
>  	int i;
>  	enum pipe pipe;
>  
> -	memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
> -	       sizeof(state->min_voltage_level));
> -
>  	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
>  		int ret;
>  
> @@ -2339,6 +2341,18 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
>  	enum pipe pipe;
>  	int ret;
>  
> +	memcpy(state->min_cdclk, dev_priv->min_cdclk,
> +	       sizeof(state->min_cdclk));
> +	memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
> +	       sizeof(state->min_voltage_level));
> +
> +	/* keep the current setting */
> +	if (!state->cdclk.force_min_cdclk_changed)
> +		state->cdclk.force_min_cdclk = dev_priv-
> >cdclk.force_min_cdclk;
> +
> +	state->cdclk.logical = dev_priv->cdclk.logical;
> +	state->cdclk.actual = dev_priv->cdclk.actual;
> +
>  	ret = dev_priv->display.modeset_calc_cdclk(state);
>  	if (ret)
>  		return ret;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 8dcb86c51aaa..930e9256596c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14360,14 +14360,8 @@ static int intel_modeset_checks(struct
> intel_atomic_state *state)
>  	struct intel_crtc *crtc;
>  	int ret, i;
>  
> -	/* keep the current setting */
> -	if (!state->cdclk.force_min_cdclk_changed)
> -		state->cdclk.force_min_cdclk = dev_priv-
> >cdclk.force_min_cdclk;
> -
>  	state->modeset = true;
>  	state->active_pipes = dev_priv->active_pipes;
> -	state->cdclk.logical = dev_priv->cdclk.logical;
> -	state->cdclk.actual = dev_priv->cdclk.actual;
>  
>  	for_each_oldnew_intel_crtc_in_state(state, crtc,
> old_crtc_state,
>  					    new_crtc_state, i) {
> @@ -15673,12 +15667,7 @@ static int intel_atomic_commit(struct
> drm_device *dev,
>  	if (state->global_state_changed) {
>  		assert_global_state_locked(dev_priv);
>  
> -		memcpy(dev_priv->min_cdclk, state->min_cdclk,
> -		       sizeof(state->min_cdclk));
> -		memcpy(dev_priv->min_voltage_level, state-
> >min_voltage_level,
> -		       sizeof(state->min_voltage_level));
>  		dev_priv->active_pipes = state->active_pipes;
> -		dev_priv->cdclk.force_min_cdclk = state-
> >cdclk.force_min_cdclk;
>  
>  		intel_cdclk_swap_state(state);
>  	}
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2020-01-22 18:42 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-20 17:47 [Intel-gfx] [PATCH 00/17] drm/i915: Global state rework Ville Syrjala
2020-01-20 17:47 ` [Intel-gfx] [PATCH 01/17] drm/i915: Polish WM_LINETIME register stuff Ville Syrjala
2020-01-20 17:47 ` [Intel-gfx] [PATCH 02/17] drm/i915: Move linetime wms into the crtc state Ville Syrjala
2020-01-29 14:05   ` Lisovskiy, Stanislav
2020-01-31 15:07   ` Ville Syrjälä
2020-01-20 17:47 ` [Intel-gfx] [PATCH 03/17] drm/i915: Nuke skl wm.dirty_pipes bitmask Ville Syrjala
2020-01-20 17:47 ` [Intel-gfx] [PATCH 04/17] drm/i915: Move more cdclk state handling into the cdclk code Ville Syrjala
2020-01-22 18:39   ` Souza, Jose [this message]
2020-01-20 17:47 ` [Intel-gfx] [PATCH 05/17] drm/i915: Collect more cdclk state under the same roof Ville Syrjala
2020-01-22 18:43   ` Souza, Jose
2020-01-20 17:47 ` [Intel-gfx] [PATCH 06/17] drm/i915: s/need_cd2x_updare/can_cd2x_update/ Ville Syrjala
2020-01-24 12:24   ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 07/17] drm/i915: s/cdclk_state/cdclk_config/ Ville Syrjala
2020-01-22 18:51   ` Souza, Jose
2020-01-20 17:47 ` [Intel-gfx] [PATCH 08/17] drm/i915: Simplify intel_set_cdclk_{pre, post}_plane_update() calling convention Ville Syrjala
2020-01-22 18:51   ` Souza, Jose
2020-01-20 17:47 ` [Intel-gfx] [PATCH 09/17] drm/i915: Extract intel_cdclk_state Ville Syrjala
2020-01-22 18:51   ` Souza, Jose
2020-01-20 17:47 ` [Intel-gfx] [PATCH 10/17] drm/i915: swap() the entire cdclk state Ville Syrjala
2020-01-24 15:06   ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 11/17] drm/i915: s/init_cdclk/init_cdclk_hw/ Ville Syrjala
2020-01-24 15:08   ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 12/17] drm/i915: Move intel_atomic_state_free() into intel_atomic.c Ville Syrjala
2020-01-24 15:19   ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 13/17] drm/i915: Intrduce better global state handling Ville Syrjala
2020-01-28 14:44   ` Lisovskiy, Stanislav
2020-01-28 15:29     ` Ville Syrjälä
2020-01-20 17:47 ` [Intel-gfx] [PATCH 13/17] drm/i915: Introduce " Ville Syrjala
2020-01-22 19:00   ` Souza, Jose
2020-01-22 19:11     ` Ville Syrjälä
2020-01-27 15:02   ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 14/17] drm/i915: Convert bandwidth state to global state Ville Syrjala
2020-01-27 15:21   ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 15/17] drm/i915: Introduce intel_calc_active_pipes() Ville Syrjala
2020-01-27 15:25   ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 16/17] drm/i915: Convert cdclk to global state Ville Syrjala
2020-01-21 14:03   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2020-01-27 17:03     ` Imre Deak
2020-01-27 17:15       ` Ville Syrjälä
2020-01-27 17:54         ` Imre Deak
2020-01-20 17:47 ` [Intel-gfx] [PATCH 17/17] drm/i915: Store active_pipes bitmask in cdclk state Ville Syrjala
2020-01-27 17:11   ` Imre Deak
2020-01-20 18:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Global state rework Patchwork
2020-01-21  2:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-01-21 13:32 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-01-21 17:58 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Global state rework (rev2) Patchwork
2020-01-21 18:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-01-23  0:02 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=2ec65516cf9f62f2d8f551f5c242c662a68317c9.camel@intel.com \
    --to=jose.souza@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=ville.syrjala@linux.intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.