* [Intel-gfx] [PATCH v17 1/6] drm/i915: Remove skl_ddl_allocation struct
2020-02-02 23:06 [Intel-gfx] [PATCH v17 0/6] Enable second DBuf slice for ICL and TGL Stanislav Lisovskiy
@ 2020-02-02 23:06 ` Stanislav Lisovskiy
2020-02-02 23:06 ` [Intel-gfx] [PATCH v17 2/6] drm/i915: Move dbuf slice update to proper place Stanislav Lisovskiy
` (8 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-02 23:06 UTC (permalink / raw)
To: intel-gfx
Current consensus that it is redundant as
we already have skl_ddb_values struct out there,
also this struct contains only single member
which makes it unnecessary.
v2: As dirty_pipes soon going to be nuked away
from skl_ddb_values, evacuating enabled_slices
to safer in dev_priv.
v3: Changed "enabled_slices" to be "enabled_dbuf_slices_num"
(Matt Roper)
v4: - Wrapped the line getting number of dbuf slices(Matt Roper)
- Removed indeed redundant skl_ddb_values declaration(Matt Roper)
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 16 +++----
.../drm/i915/display/intel_display_power.c | 8 ++--
.../drm/i915/display/intel_display_types.h | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 11 +----
drivers/gpu/drm/i915/intel_pm.c | 45 +++++++++----------
drivers/gpu/drm/i915/intel_pm.h | 5 +--
6 files changed, 38 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b0af37fb6d4a..eadbde3996b7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14039,12 +14039,11 @@ static void verify_wm_state(struct intel_crtc *crtc,
struct skl_hw_state {
struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
- struct skl_ddb_allocation ddb;
struct skl_pipe_wm wm;
} *hw;
- struct skl_ddb_allocation *sw_ddb;
struct skl_pipe_wm *sw_wm;
struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
+ u8 hw_enabled_slices;
const enum pipe pipe = crtc->pipe;
int plane, level, max_level = ilk_wm_max_level(dev_priv);
@@ -14060,15 +14059,14 @@ static void verify_wm_state(struct intel_crtc *crtc,
skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
- skl_ddb_get_hw_state(dev_priv, &hw->ddb);
- sw_ddb = &dev_priv->wm.skl_hw.ddb;
+ hw_enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
if (INTEL_GEN(dev_priv) >= 11 &&
- hw->ddb.enabled_slices != sw_ddb->enabled_slices)
+ hw_enabled_slices != dev_priv->enabled_dbuf_slices_num)
drm_err(&dev_priv->drm,
"mismatch in DBUF Slices (expected %u, got %u)\n",
- sw_ddb->enabled_slices,
- hw->ddb.enabled_slices);
+ dev_priv->enabled_dbuf_slices_num,
+ hw_enabled_slices);
/* planes */
for_each_universal_plane(dev_priv, pipe, plane) {
@@ -15427,8 +15425,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc *crtc;
struct intel_crtc_state *old_crtc_state, *new_crtc_state;
- u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
- u8 required_slices = state->wm_results.ddb.enabled_slices;
+ u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_num;
+ u8 required_slices = state->enabled_dbuf_slices_num;
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
const u8 num_pipes = INTEL_NUM_PIPES(dev_priv);
u8 update_pipes = 0, modeset_pipes = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 64943179c05e..86e349bbc0af 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4436,7 +4436,7 @@ static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices)
{
- const u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
+ const u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_num;
bool ret;
if (req_slices > intel_dbuf_max_slices(dev_priv)) {
@@ -4454,7 +4454,7 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false);
if (ret)
- dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices;
+ dev_priv->enabled_dbuf_slices_num = req_slices;
}
static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
@@ -4475,7 +4475,7 @@ static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
* FIXME: for now pretend that we only have 1 slice, see
* intel_enabled_dbuf_slices_num().
*/
- dev_priv->wm.skl_hw.ddb.enabled_slices = 1;
+ dev_priv->enabled_dbuf_slices_num = 1;
}
static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
@@ -4496,7 +4496,7 @@ static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
* FIXME: for now pretend that the first slice is always
* enabled, see intel_enabled_dbuf_slices_num().
*/
- dev_priv->wm.skl_hw.ddb.enabled_slices = 1;
+ dev_priv->enabled_dbuf_slices_num = 1;
}
static void icl_mbus_init(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 7c6133a9c51b..ce1d9a917c5f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -495,8 +495,8 @@ struct intel_atomic_state {
*/
bool global_state_changed;
- /* Gen9+ only */
- struct skl_ddb_values wm_results;
+ /* Number of enabled DBuf slices */
+ u8 enabled_dbuf_slices_num;
struct i915_sw_fence commit_ready;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a71ff233cc55..ebebc4246e6c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -798,14 +798,6 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
return false;
}
-struct skl_ddb_allocation {
- u8 enabled_slices; /* GEN11 has configurable 2 slices */
-};
-
-struct skl_ddb_values {
- struct skl_ddb_allocation ddb;
-};
-
struct skl_wm_level {
u16 min_ddb_alloc;
u16 plane_res_b;
@@ -1173,7 +1165,6 @@ struct drm_i915_private {
/* current hardware state */
union {
struct ilk_wm_values hw;
- struct skl_ddb_values skl_hw;
struct vlv_wm_values vlv;
struct g4x_wm_values g4x;
};
@@ -1195,6 +1186,8 @@ struct drm_i915_private {
bool distrust_bios_wm;
} wm;
+ u8 enabled_dbuf_slices_num; /* GEN11 has configurable 2 slices */
+
struct dram_info {
bool valid;
bool is_16gb_dimm;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a2d2407af2ed..89aa188c8cf5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3597,16 +3597,16 @@ bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
}
-static u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
+u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
{
- u8 enabled_slices;
+ u8 enabled_dbuf_slices_num;
/* Slice 1 will always be enabled */
- enabled_slices = 1;
+ enabled_dbuf_slices_num = 1;
/* Gen prior to GEN11 have only one DBuf slice */
if (INTEL_GEN(dev_priv) < 11)
- return enabled_slices;
+ return enabled_dbuf_slices_num;
/*
* FIXME: for now we'll only ever use 1 slice; pretend that we have
@@ -3614,9 +3614,9 @@ static u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
* toggling of the second slice.
*/
if (0 && I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
- enabled_slices++;
+ enabled_dbuf_slices_num++;
- return enabled_slices;
+ return enabled_dbuf_slices_num;
}
/*
@@ -3820,9 +3820,10 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
const u64 total_data_rate,
- const int num_active,
- struct skl_ddb_allocation *ddb)
+ const int num_active)
{
+ struct drm_atomic_state *state = crtc_state->uapi.state;
+ struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
const struct drm_display_mode *adjusted_mode;
u64 total_data_bw;
u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
@@ -3844,9 +3845,9 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
* - should validate we stay within the hw bandwidth limits
*/
if (0 && (num_active > 1 || total_data_bw >= GBps(12))) {
- ddb->enabled_slices = 2;
+ intel_state->enabled_dbuf_slices_num = 2;
} else {
- ddb->enabled_slices = 1;
+ intel_state->enabled_dbuf_slices_num = 1;
ddb_size /= 2;
}
@@ -3857,7 +3858,6 @@ static void
skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
const u64 total_data_rate,
- struct skl_ddb_allocation *ddb,
struct skl_ddb_entry *alloc, /* out */
int *num_active /* out */)
{
@@ -3883,7 +3883,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
*num_active = hweight8(dev_priv->active_pipes);
ddb_size = intel_get_ddb_size(dev_priv, crtc_state, total_data_rate,
- *num_active, ddb);
+ *num_active);
/*
* If the state doesn't change the active CRTC's or there is no
@@ -4044,10 +4044,10 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
intel_display_power_put(dev_priv, power_domain, wakeref);
}
-void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
- struct skl_ddb_allocation *ddb /* out */)
+void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv)
{
- ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
+ dev_priv->enabled_dbuf_slices_num =
+ intel_enabled_dbuf_slices_num(dev_priv);
}
/*
@@ -4224,8 +4224,7 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
}
static int
-skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
- struct skl_ddb_allocation *ddb /* out */)
+skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
struct drm_atomic_state *state = crtc_state->uapi.state;
struct drm_crtc *crtc = crtc_state->uapi.crtc;
@@ -4267,7 +4266,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate,
- ddb, alloc, &num_active);
+ alloc, &num_active);
alloc_size = skl_ddb_entry_size(alloc);
if (alloc_size == 0)
return 0;
@@ -5150,18 +5149,17 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
static int
skl_compute_ddb(struct intel_atomic_state *state)
{
- const struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *old_crtc_state;
struct intel_crtc_state *new_crtc_state;
struct intel_crtc *crtc;
int ret, i;
- memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
+ state->enabled_dbuf_slices_num = dev_priv->enabled_dbuf_slices_num;
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
- ret = skl_allocate_pipe_ddb(new_crtc_state, ddb);
+ ret = skl_allocate_pipe_ddb(new_crtc_state);
if (ret)
return ret;
@@ -5589,11 +5587,10 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
{
- struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
- skl_ddb_get_hw_state(dev_priv, ddb);
+ skl_ddb_get_hw_state(dev_priv);
for_each_intel_crtc(&dev_priv->drm, crtc) {
crtc_state = to_intel_crtc_state(crtc->base.state);
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index c06c6a846d9a..22fd2daf608e 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -17,7 +17,6 @@ struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_plane;
-struct skl_ddb_allocation;
struct skl_ddb_entry;
struct skl_pipe_wm;
struct skl_wm_level;
@@ -33,11 +32,11 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
+u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv);
void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
struct skl_ddb_entry *ddb_y,
struct skl_ddb_entry *ddb_uv);
-void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
- struct skl_ddb_allocation *ddb /* out */);
+void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
struct skl_pipe_wm *out);
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
--
2.24.1.485.gad05a3d8e5
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^ permalink raw reply related [flat|nested] 14+ messages in thread* [Intel-gfx] [PATCH v17 2/6] drm/i915: Move dbuf slice update to proper place
2020-02-02 23:06 [Intel-gfx] [PATCH v17 0/6] Enable second DBuf slice for ICL and TGL Stanislav Lisovskiy
2020-02-02 23:06 ` [Intel-gfx] [PATCH v17 1/6] drm/i915: Remove skl_ddl_allocation struct Stanislav Lisovskiy
@ 2020-02-02 23:06 ` Stanislav Lisovskiy
2020-02-02 23:06 ` [Intel-gfx] [PATCH v17 3/6] drm/i915: Update dbuf slices only with full modeset Stanislav Lisovskiy
` (7 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-02 23:06 UTC (permalink / raw)
To: intel-gfx
Current DBuf slices update wasn't done in proper
place, especially its "post" part, which should
disable those only once vblank had passed and
all other changes are committed.
v2: Fix to use dev_priv and intel_atomic_state
instead of skl_ddb_values
(to be nuked in Villes patch)
v3: Renamed "enabled_slices" to "enabled_dbuf_slices_num"
(Matt Roper)
v4: - Rebase against drm-tip.
- Move post_update closer to optimize_watermarks,
to prevent unneeded noise from underrun reporting
(Ville Syrjälä)
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 37 +++++++++++++++-----
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index eadbde3996b7..d553de2c3f5e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15420,13 +15420,33 @@ static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
state);
}
+static void icl_dbuf_slice_pre_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_num;
+ u8 required_slices = state->enabled_dbuf_slices_num;
+
+ /* If 2nd DBuf slice required, enable it here */
+ if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
+ icl_dbuf_slices_update(dev_priv, required_slices);
+}
+
+static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_num;
+ u8 required_slices = state->enabled_dbuf_slices_num;
+
+ /* If 2nd DBuf slice is no more required disable it */
+ if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
+ icl_dbuf_slices_update(dev_priv, required_slices);
+}
+
static void skl_commit_modeset_enables(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc *crtc;
struct intel_crtc_state *old_crtc_state, *new_crtc_state;
- u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_num;
- u8 required_slices = state->enabled_dbuf_slices_num;
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
const u8 num_pipes = INTEL_NUM_PIPES(dev_priv);
u8 update_pipes = 0, modeset_pipes = 0;
@@ -15447,10 +15467,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
}
}
- /* If 2nd DBuf slice required, enable it here */
- if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
- icl_dbuf_slices_update(dev_priv, required_slices);
-
/*
* Whenever the number of active pipes changes, we need to make sure we
* update the pipes in the right order so that their ddb allocations
@@ -15552,9 +15568,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
WARN_ON(modeset_pipes);
- /* If 2nd DBuf slice is no more required disable it */
- if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
- icl_dbuf_slices_update(dev_priv, required_slices);
}
static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
@@ -15681,6 +15694,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
intel_encoders_update_prepare(state);
+ /* Enable all new slices, we might need */
+ icl_dbuf_slice_pre_update(state);
+
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
dev_priv->display.commit_modeset_enables(state);
@@ -15734,6 +15750,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
dev_priv->display.optimize_watermarks(state, crtc);
}
+ /* Disable all slices, we don't need */
+ icl_dbuf_slice_post_update(state);
+
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
intel_post_plane_update(state, crtc);
--
2.24.1.485.gad05a3d8e5
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^ permalink raw reply related [flat|nested] 14+ messages in thread* [Intel-gfx] [PATCH v17 3/6] drm/i915: Update dbuf slices only with full modeset
2020-02-02 23:06 [Intel-gfx] [PATCH v17 0/6] Enable second DBuf slice for ICL and TGL Stanislav Lisovskiy
2020-02-02 23:06 ` [Intel-gfx] [PATCH v17 1/6] drm/i915: Remove skl_ddl_allocation struct Stanislav Lisovskiy
2020-02-02 23:06 ` [Intel-gfx] [PATCH v17 2/6] drm/i915: Move dbuf slice update to proper place Stanislav Lisovskiy
@ 2020-02-02 23:06 ` Stanislav Lisovskiy
2020-02-02 23:06 ` [Intel-gfx] [PATCH v17 4/6] drm/i915: Introduce parameterized DBUF_CTL Stanislav Lisovskiy
` (6 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-02 23:06 UTC (permalink / raw)
To: intel-gfx
During full modeset, global state(i.e dev_priv) is protected
by locking the crtcs in state, otherwise global state is not
serialized. Also if it is not a full modeset, we anyway
don't need to change DBuf slice configuration as Pipe configuration
doesn't change.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d553de2c3f5e..27622ef069cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15695,7 +15695,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_encoders_update_prepare(state);
/* Enable all new slices, we might need */
- icl_dbuf_slice_pre_update(state);
+ if (state->modeset)
+ icl_dbuf_slice_pre_update(state);
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
dev_priv->display.commit_modeset_enables(state);
@@ -15751,7 +15752,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
}
/* Disable all slices, we don't need */
- icl_dbuf_slice_post_update(state);
+ if (state->modeset)
+ icl_dbuf_slice_post_update(state);
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
intel_post_plane_update(state, crtc);
--
2.24.1.485.gad05a3d8e5
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^ permalink raw reply related [flat|nested] 14+ messages in thread* [Intel-gfx] [PATCH v17 4/6] drm/i915: Introduce parameterized DBUF_CTL
2020-02-02 23:06 [Intel-gfx] [PATCH v17 0/6] Enable second DBuf slice for ICL and TGL Stanislav Lisovskiy
` (2 preceding siblings ...)
2020-02-02 23:06 ` [Intel-gfx] [PATCH v17 3/6] drm/i915: Update dbuf slices only with full modeset Stanislav Lisovskiy
@ 2020-02-02 23:06 ` Stanislav Lisovskiy
2020-02-02 23:06 ` [Intel-gfx] [PATCH v17 5/6] drm/i915: Manipulate DBuf slices properly Stanislav Lisovskiy
` (5 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-02 23:06 UTC (permalink / raw)
To: intel-gfx
Now start using parameterized DBUF_CTL instead
of hardcoded, this would allow shorter access
functions when reading or storing entire state.
Tried to implement it in a MMIO_PIPE manner, however
DBUF_CTL1 address is higher than DBUF_CTL2, which
implies that we have to now subtract from base
rather than add.
v2: - Removed unneeded DBUF_CTL_DIST and DBUF_CTL_ADDR
macros. Started to use _PICK construct as suggested
by Matt Roper.
v3: - _DBUF_CTL_S* to DBUF_CTL_S*, changed X to "slice"
in macro(Ville Syrjälä)
- Introduced enum for enumerating DBUF slices(Ville Syrjälä)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
.../drm/i915/display/intel_display_power.c | 40 ++++++++++---------
.../drm/i915/display/intel_display_power.h | 5 +++
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 6 +--
drivers/gpu/drm/i915/intel_pm.c | 2 +-
5 files changed, 31 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 86e349bbc0af..9f978c977dcb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1041,7 +1041,7 @@ static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
{
- u32 tmp = intel_de_read(dev_priv, DBUF_CTL);
+ u32 tmp = intel_de_read(dev_priv, DBUF_CTL_S(0));
WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
(DBUF_POWER_STATE | DBUF_POWER_REQUEST),
@@ -4418,12 +4418,12 @@ bool intel_dbuf_slice_set(struct drm_i915_private *dev_priv,
static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
{
- intel_dbuf_slice_set(dev_priv, DBUF_CTL, true);
+ intel_dbuf_slice_set(dev_priv, DBUF_CTL_S(0), true);
}
static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
{
- intel_dbuf_slice_set(dev_priv, DBUF_CTL, false);
+ intel_dbuf_slice_set(dev_priv, DBUF_CTL_S(0), false);
}
static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
@@ -4449,9 +4449,11 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
return;
if (req_slices > hw_enabled_slices)
- ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true);
+ ret = intel_dbuf_slice_set(dev_priv,
+ DBUF_CTL_S(DBUF_S2), true);
else
- ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false);
+ ret = intel_dbuf_slice_set(dev_priv,
+ DBUF_CTL_S(DBUF_S2), false);
if (ret)
dev_priv->enabled_dbuf_slices_num = req_slices;
@@ -4459,16 +4461,16 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
{
- intel_de_write(dev_priv, DBUF_CTL_S1,
- intel_de_read(dev_priv, DBUF_CTL_S1) | DBUF_POWER_REQUEST);
- intel_de_write(dev_priv, DBUF_CTL_S2,
- intel_de_read(dev_priv, DBUF_CTL_S2) | DBUF_POWER_REQUEST);
- intel_de_posting_read(dev_priv, DBUF_CTL_S2);
+ intel_de_write(dev_priv, DBUF_CTL_S(0),
+ intel_de_read(dev_priv, DBUF_CTL_S(0)) | DBUF_POWER_REQUEST);
+ intel_de_write(dev_priv, DBUF_CTL_S(1),
+ intel_de_read(dev_priv, DBUF_CTL_S(1)) | DBUF_POWER_REQUEST);
+ intel_de_posting_read(dev_priv, DBUF_CTL_S(1));
udelay(10);
- if (!(intel_de_read(dev_priv, DBUF_CTL_S1) & DBUF_POWER_STATE) ||
- !(intel_de_read(dev_priv, DBUF_CTL_S2) & DBUF_POWER_STATE))
+ if (!(intel_de_read(dev_priv, DBUF_CTL_S(0)) & DBUF_POWER_STATE) ||
+ !(intel_de_read(dev_priv, DBUF_CTL_S(1)) & DBUF_POWER_STATE))
drm_err(&dev_priv->drm, "DBuf power enable timeout\n");
else
/*
@@ -4480,16 +4482,16 @@ static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
{
- intel_de_write(dev_priv, DBUF_CTL_S1,
- intel_de_read(dev_priv, DBUF_CTL_S1) & ~DBUF_POWER_REQUEST);
- intel_de_write(dev_priv, DBUF_CTL_S2,
- intel_de_read(dev_priv, DBUF_CTL_S2) & ~DBUF_POWER_REQUEST);
- intel_de_posting_read(dev_priv, DBUF_CTL_S2);
+ intel_de_write(dev_priv, DBUF_CTL_S(0),
+ intel_de_read(dev_priv, DBUF_CTL_S(0)) & ~DBUF_POWER_REQUEST);
+ intel_de_write(dev_priv, DBUF_CTL_S(1),
+ intel_de_read(dev_priv, DBUF_CTL_S(1)) & ~DBUF_POWER_REQUEST);
+ intel_de_posting_read(dev_priv, DBUF_CTL_S(1));
udelay(10);
- if ((intel_de_read(dev_priv, DBUF_CTL_S1) & DBUF_POWER_STATE) ||
- (intel_de_read(dev_priv, DBUF_CTL_S2) & DBUF_POWER_STATE))
+ if ((intel_de_read(dev_priv, DBUF_CTL_S(0)) & DBUF_POWER_STATE) ||
+ (intel_de_read(dev_priv, DBUF_CTL_S(1)) & DBUF_POWER_STATE))
drm_err(&dev_priv->drm, "DBuf power disable timeout!\n");
else
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 2608a65af7fa..601e000ffd0d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -307,6 +307,11 @@ intel_display_power_put_async(struct drm_i915_private *i915,
}
#endif
+enum dbuf_slice {
+ DBUF_S1,
+ DBUF_S2,
+};
+
#define with_intel_display_power(i915, domain, wf) \
for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 18475dd377ed..ae6700dc9d73 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2902,7 +2902,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
- MMIO_DH(DBUF_CTL, D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
+ MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0bd431f6a011..dc206723f25e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7753,9 +7753,9 @@ enum {
#define DISP_ARB_CTL2 _MMIO(0x45004)
#define DISP_DATA_PARTITION_5_6 (1 << 6)
#define DISP_IPC_ENABLE (1 << 3)
-#define DBUF_CTL _MMIO(0x45008)
-#define DBUF_CTL_S1 _MMIO(0x45008)
-#define DBUF_CTL_S2 _MMIO(0x44FE8)
+#define _DBUF_CTL_S1 0x45008
+#define _DBUF_CTL_S2 0x44FE8
+#define DBUF_CTL_S(slice) _MMIO(_PICK_EVEN(slice, _DBUF_CTL_S1, _DBUF_CTL_S2))
#define DBUF_POWER_REQUEST (1 << 31)
#define DBUF_POWER_STATE (1 << 30)
#define GEN7_MSG_CTL _MMIO(0x45010)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 89aa188c8cf5..f9e00ca61302 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3613,7 +3613,7 @@ u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
* only that 1 slice enabled until we have a proper way for on-demand
* toggling of the second slice.
*/
- if (0 && I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
+ if (0 && I915_READ(DBUF_CTL_S(DBUF_S2)) & DBUF_POWER_STATE)
enabled_dbuf_slices_num++;
return enabled_dbuf_slices_num;
--
2.24.1.485.gad05a3d8e5
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Intel-gfx] [PATCH v17 5/6] drm/i915: Manipulate DBuf slices properly
2020-02-02 23:06 [Intel-gfx] [PATCH v17 0/6] Enable second DBuf slice for ICL and TGL Stanislav Lisovskiy
` (3 preceding siblings ...)
2020-02-02 23:06 ` [Intel-gfx] [PATCH v17 4/6] drm/i915: Introduce parameterized DBUF_CTL Stanislav Lisovskiy
@ 2020-02-02 23:06 ` Stanislav Lisovskiy
2020-02-02 23:06 ` [Intel-gfx] [PATCH v17 6/6] drm/i915: Correctly map DBUF slices to pipes Stanislav Lisovskiy
` (4 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-02 23:06 UTC (permalink / raw)
To: intel-gfx
Start manipulating DBuf slices as a mask,
but not as a total number, as current approach
doesn't give us full control on all combinations
of slices, which we might need(like enabling S2
only can't enabled by setting enabled_slices=1).
Removed wrong code from intel_get_ddb_size as
it doesn't match to BSpec. For now still just
use DBuf slice until proper algorithm is implemented.
Other minor code refactoring to get prepared
for major DBuf assignment changes landed:
- As now enabled slices contain a mask
we still need some value which should
reflect how much DBuf slices are supported
by the platform, now device info contains
num_supported_dbuf_slices.
- Removed unneeded assertion as we are now
manipulating slices in a more proper way.
v2: Start using enabled_slices in dev_priv
v3: "enabled_slices" is now "enabled_dbuf_slices_mask",
as this now sits in dev_priv independently.
v4: - Fixed debug print formatting to hex(Matt Roper)
- Optimized dbuf slice updates to be used only
if slice union is different from current conf(Matt Roper)
- Fixed some functions to be static(Matt Roper)
- Created a parameterized version for DBUF_CTL to
simplify DBuf programming cycle(Matt Roper)
- Removed unrequred field from GEN10_FEATURES(Matt Roper)
v5: - Removed redundant programming dbuf slices helper(Ville Syrjälä)
- Started to use parameterized loop for hw readout to get slices
(Ville Syrjälä)
- Added back assertion checking amount of DBUF slices enabled
after DC states 5/6 transition, also added new assertion
as starting from ICL DMC seems to restore the last DBuf
power state set, rather than power up all dbuf slices
as assertion was previously expecting(Ville Syrjälä)
v6: - Now using enum for DBuf slices in this patch (Ville Syrjälä)
- Removed gen11_assert_dbuf_enabled and put gen9_assert_dbuf_enabled
back, as we really need to have a single unified assert here
however currently enabling always slice 1 is enforced by BSpec,
so we will have to OR enabled slices mask with 1 in order
to be consistent with BSpec, that way we can unify that
assertion and against the actual state from the driver, but
not some hardcoded value.(concluded with Ville)
- Remove parameterized DBUF_CTL version, to extract it to another
patch.(Ville Syrjälä)
v7:
- Removed unneeded hardcoded return value for older gens from
intel_enabled_dbuf_slices_mask - this now is handled in a
unified manner since device info anyway returns max dbuf slices
as 1 for older platforms(Matthew Roper)
- Now using INTEL_INFO(dev_priv)->num_supported_dbuf_slices instead
of intel_dbuf_max_slices function as it is trivial(Matthew Roper)
v8: - Fixed icl_dbuf_disable to disable all dbufs still(Ville Syrjälä)
v9: - Renamed _DBUF_CTL_S to DBUF_CTL_S(Ville Syrjälä)
- Now using power_domain mutex to protect from race condition, which
can occur because intel_dbuf_slices_update might be running in
parallel to gen9_dc_off_power_well_enable being called from
intel_dp_detect for instance, which causes assertion triggered by
race condition, as gen9_assert_dbuf_enabled might preempt this
when registers were already updated, while dev_priv was not.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 23 ++--
.../drm/i915/display/intel_display_power.c | 102 +++++++-----------
.../drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 5 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 53 +++------
drivers/gpu/drm/i915/intel_pm.h | 2 +-
8 files changed, 72 insertions(+), 118 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 27622ef069cf..a1bf4e937814 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14059,13 +14059,13 @@ static void verify_wm_state(struct intel_crtc *crtc,
skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
- hw_enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
+ hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
if (INTEL_GEN(dev_priv) >= 11 &&
- hw_enabled_slices != dev_priv->enabled_dbuf_slices_num)
+ hw_enabled_slices != dev_priv->enabled_dbuf_slices_mask)
drm_err(&dev_priv->drm,
- "mismatch in DBUF Slices (expected %u, got %u)\n",
- dev_priv->enabled_dbuf_slices_num,
+ "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
+ dev_priv->enabled_dbuf_slices_mask,
hw_enabled_slices);
/* planes */
@@ -15423,22 +15423,23 @@ static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
static void icl_dbuf_slice_pre_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_num;
- u8 required_slices = state->enabled_dbuf_slices_num;
+ u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_mask;
+ u8 required_slices = state->enabled_dbuf_slices_mask;
+ u8 slices_union = hw_enabled_slices | required_slices;
/* If 2nd DBuf slice required, enable it here */
- if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
- icl_dbuf_slices_update(dev_priv, required_slices);
+ if (INTEL_GEN(dev_priv) >= 11 && slices_union != hw_enabled_slices)
+ icl_dbuf_slices_update(dev_priv, slices_union);
}
static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_num;
- u8 required_slices = state->enabled_dbuf_slices_num;
+ u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_mask;
+ u8 required_slices = state->enabled_dbuf_slices_mask;
/* If 2nd DBuf slice is no more required disable it */
- if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
+ if (INTEL_GEN(dev_priv) >= 11 && required_slices != hw_enabled_slices)
icl_dbuf_slices_update(dev_priv, required_slices);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 9f978c977dcb..1e464b191c2f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -15,6 +15,7 @@
#include "intel_display_types.h"
#include "intel_dpio_phy.h"
#include "intel_hotplug.h"
+#include "intel_pm.h"
#include "intel_sideband.h"
#include "intel_tc.h"
#include "intel_vga.h"
@@ -1041,11 +1042,13 @@ static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
{
- u32 tmp = intel_de_read(dev_priv, DBUF_CTL_S(0));
+ u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv);
+ u8 enabled_dbuf_slices = dev_priv->enabled_dbuf_slices_mask;
- WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
- (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
- "Unexpected DBuf power power state (0x%08x)\n", tmp);
+ WARN(hw_enabled_dbuf_slices != enabled_dbuf_slices,
+ "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n",
+ hw_enabled_dbuf_slices,
+ enabled_dbuf_slices);
}
static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
@@ -4418,87 +4421,58 @@ bool intel_dbuf_slice_set(struct drm_i915_private *dev_priv,
static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
{
- intel_dbuf_slice_set(dev_priv, DBUF_CTL_S(0), true);
+ icl_dbuf_slices_update(dev_priv, BIT(DBUF_S1));
}
static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
{
- intel_dbuf_slice_set(dev_priv, DBUF_CTL_S(0), false);
-}
-
-static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
-{
- if (INTEL_GEN(dev_priv) < 11)
- return 1;
- return 2;
+ icl_dbuf_slices_update(dev_priv, 0);
}
void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices)
{
- const u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_num;
- bool ret;
+ int i;
+ int max_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
+ struct i915_power_domains *power_domains = &dev_priv->power_domains;
- if (req_slices > intel_dbuf_max_slices(dev_priv)) {
- drm_err(&dev_priv->drm,
- "Invalid number of dbuf slices requested\n");
- return;
- }
+ WARN(hweight8(req_slices) > max_slices,
+ "Invalid number of dbuf slices requested\n");
- if (req_slices == hw_enabled_slices || req_slices == 0)
- return;
+ DRM_DEBUG_KMS("Updating dbuf slices to 0x%x\n", req_slices);
- if (req_slices > hw_enabled_slices)
- ret = intel_dbuf_slice_set(dev_priv,
- DBUF_CTL_S(DBUF_S2), true);
- else
- ret = intel_dbuf_slice_set(dev_priv,
- DBUF_CTL_S(DBUF_S2), false);
+ /*
+ * Might be running this in parallel to gen9_dc_off_power_well_enable
+ * being called from intel_dp_detect for instance,
+ * which causes assertion triggered by race condition,
+ * as gen9_assert_dbuf_enabled might preempt this when registers
+ * were already updated, while dev_priv was not.
+ */
+ mutex_lock(&power_domains->lock);
+
+ for (i = 0; i < max_slices; i++) {
+ intel_dbuf_slice_set(dev_priv,
+ DBUF_CTL_S(i),
+ (req_slices & BIT(i)) != 0);
+ }
- if (ret)
- dev_priv->enabled_dbuf_slices_num = req_slices;
+ dev_priv->enabled_dbuf_slices_mask = req_slices;
+
+ mutex_unlock(&power_domains->lock);
}
static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
{
- intel_de_write(dev_priv, DBUF_CTL_S(0),
- intel_de_read(dev_priv, DBUF_CTL_S(0)) | DBUF_POWER_REQUEST);
- intel_de_write(dev_priv, DBUF_CTL_S(1),
- intel_de_read(dev_priv, DBUF_CTL_S(1)) | DBUF_POWER_REQUEST);
- intel_de_posting_read(dev_priv, DBUF_CTL_S(1));
-
- udelay(10);
-
- if (!(intel_de_read(dev_priv, DBUF_CTL_S(0)) & DBUF_POWER_STATE) ||
- !(intel_de_read(dev_priv, DBUF_CTL_S(1)) & DBUF_POWER_STATE))
- drm_err(&dev_priv->drm, "DBuf power enable timeout\n");
- else
- /*
- * FIXME: for now pretend that we only have 1 slice, see
- * intel_enabled_dbuf_slices_num().
- */
- dev_priv->enabled_dbuf_slices_num = 1;
+ /*
+ * Just power up 1 slice, we will
+ * figure out later which slices we have and what we need.
+ */
+ icl_dbuf_slices_update(dev_priv, BIT(DBUF_S1));
}
static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
{
- intel_de_write(dev_priv, DBUF_CTL_S(0),
- intel_de_read(dev_priv, DBUF_CTL_S(0)) & ~DBUF_POWER_REQUEST);
- intel_de_write(dev_priv, DBUF_CTL_S(1),
- intel_de_read(dev_priv, DBUF_CTL_S(1)) & ~DBUF_POWER_REQUEST);
- intel_de_posting_read(dev_priv, DBUF_CTL_S(1));
-
- udelay(10);
-
- if ((intel_de_read(dev_priv, DBUF_CTL_S(0)) & DBUF_POWER_STATE) ||
- (intel_de_read(dev_priv, DBUF_CTL_S(1)) & DBUF_POWER_STATE))
- drm_err(&dev_priv->drm, "DBuf power disable timeout!\n");
- else
- /*
- * FIXME: for now pretend that the first slice is always
- * enabled, see intel_enabled_dbuf_slices_num().
- */
- dev_priv->enabled_dbuf_slices_num = 1;
+ icl_dbuf_slices_update(dev_priv, 0);
}
static void icl_mbus_init(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ce1d9a917c5f..1783429e3d78 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -496,7 +496,7 @@ struct intel_atomic_state {
bool global_state_changed;
/* Number of enabled DBuf slices */
- u8 enabled_dbuf_slices_num;
+ u8 enabled_dbuf_slices_mask;
struct i915_sw_fence commit_ready;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ebebc4246e6c..3452926d7b77 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1186,7 +1186,7 @@ struct drm_i915_private {
bool distrust_bios_wm;
} wm;
- u8 enabled_dbuf_slices_num; /* GEN11 has configurable 2 slices */
+ u8 enabled_dbuf_slices_mask; /* GEN11 has configurable 2 slices */
struct dram_info {
bool valid;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 741bffc22867..c87f6a213d0d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -615,7 +615,8 @@ static const struct intel_device_info chv_info = {
.has_gt_uc = 1, \
.display.has_hdcp = 1, \
.display.has_ipc = 1, \
- .ddb_size = 896
+ .ddb_size = 896, \
+ .num_supported_dbuf_slices = 1
#define SKL_PLATFORM \
GEN9_FEATURES, \
@@ -650,6 +651,7 @@ static const struct intel_device_info skl_gt4_info = {
#define GEN9_LP_FEATURES \
GEN(9), \
.is_lp = 1, \
+ .num_supported_dbuf_slices = 1, \
.display.has_hotplug = 1, \
.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
@@ -774,6 +776,7 @@ static const struct intel_device_info cnl_info = {
}, \
GEN(11), \
.ddb_size = 2048, \
+ .num_supported_dbuf_slices = 2, \
.has_logical_ring_elsq = 1, \
.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 2725cb7fc169..7d4d122d2182 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -180,6 +180,7 @@ struct intel_device_info {
} display;
u16 ddb_size; /* in blocks */
+ u8 num_supported_dbuf_slices; /* number of DBuf slices */
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f9e00ca61302..4c87abcdb622 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3597,26 +3597,18 @@ bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
}
-u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
+u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
{
- u8 enabled_dbuf_slices_num;
-
- /* Slice 1 will always be enabled */
- enabled_dbuf_slices_num = 1;
-
- /* Gen prior to GEN11 have only one DBuf slice */
- if (INTEL_GEN(dev_priv) < 11)
- return enabled_dbuf_slices_num;
+ int i;
+ int max_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
+ u8 enabled_slices_mask = 0;
- /*
- * FIXME: for now we'll only ever use 1 slice; pretend that we have
- * only that 1 slice enabled until we have a proper way for on-demand
- * toggling of the second slice.
- */
- if (0 && I915_READ(DBUF_CTL_S(DBUF_S2)) & DBUF_POWER_STATE)
- enabled_dbuf_slices_num++;
+ for (i = 0; i < max_slices; i++) {
+ if (I915_READ(DBUF_CTL_S(i)) & DBUF_POWER_STATE)
+ enabled_slices_mask |= BIT(i);
+ }
- return enabled_dbuf_slices_num;
+ return enabled_slices_mask;
}
/*
@@ -3824,8 +3816,6 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
{
struct drm_atomic_state *state = crtc_state->uapi.state;
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
- const struct drm_display_mode *adjusted_mode;
- u64 total_data_bw;
u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
drm_WARN_ON(&dev_priv->drm, ddb_size == 0);
@@ -3833,23 +3823,8 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) < 11)
return ddb_size - 4; /* 4 blocks for bypass path allocation */
- adjusted_mode = &crtc_state->hw.adjusted_mode;
- total_data_bw = total_data_rate * drm_mode_vrefresh(adjusted_mode);
-
- /*
- * 12GB/s is maximum BW supported by single DBuf slice.
- *
- * FIXME dbuf slice code is broken:
- * - must wait for planes to stop using the slice before powering it off
- * - plane straddling both slices is illegal in multi-pipe scenarios
- * - should validate we stay within the hw bandwidth limits
- */
- if (0 && (num_active > 1 || total_data_bw >= GBps(12))) {
- intel_state->enabled_dbuf_slices_num = 2;
- } else {
- intel_state->enabled_dbuf_slices_num = 1;
- ddb_size /= 2;
- }
+ intel_state->enabled_dbuf_slices_mask = BIT(DBUF_S1);
+ ddb_size /= 2;
return ddb_size;
}
@@ -4046,8 +4021,8 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv)
{
- dev_priv->enabled_dbuf_slices_num =
- intel_enabled_dbuf_slices_num(dev_priv);
+ dev_priv->enabled_dbuf_slices_mask =
+ intel_enabled_dbuf_slices_mask(dev_priv);
}
/*
@@ -5155,7 +5130,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
struct intel_crtc *crtc;
int ret, i;
- state->enabled_dbuf_slices_num = dev_priv->enabled_dbuf_slices_num;
+ state->enabled_dbuf_slices_mask = dev_priv->enabled_dbuf_slices_mask;
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 22fd2daf608e..d60a85421c5a 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -32,7 +32,7 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
-u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv);
+u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
struct skl_ddb_entry *ddb_y,
struct skl_ddb_entry *ddb_uv);
--
2.24.1.485.gad05a3d8e5
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^ permalink raw reply related [flat|nested] 14+ messages in thread* [Intel-gfx] [PATCH v17 6/6] drm/i915: Correctly map DBUF slices to pipes
2020-02-02 23:06 [Intel-gfx] [PATCH v17 0/6] Enable second DBuf slice for ICL and TGL Stanislav Lisovskiy
` (4 preceding siblings ...)
2020-02-02 23:06 ` [Intel-gfx] [PATCH v17 5/6] drm/i915: Manipulate DBuf slices properly Stanislav Lisovskiy
@ 2020-02-02 23:06 ` Stanislav Lisovskiy
2020-02-02 23:47 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Enable second DBuf slice for ICL and TGL (rev23) Patchwork
` (3 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-02 23:06 UTC (permalink / raw)
To: intel-gfx
Added proper DBuf slice mapping to correspondent
pipes, depending on pipe configuration as stated
in BSpec.
v2:
- Remove unneeded braces
- Stop using macro for DBuf assignments as
it seems to reduce readability.
v3: Start using enabled slices mask in dev_priv
v4: Renamed "enabled_slices" used in dev_priv
to "enabled_dbuf_slices_mask"(Matt Roper)
v5: - Removed redundant parameters from
intel_get_ddb_size function.(Matt Roper)
- Made i915_possible_dbuf_slices static(Matt Roper)
- Renamed total_width into total_width_in_range
so that it now reflects that this is not
a total pipe width but the one in current
dbuf slice allowed range for pipe.(Matt Roper)
- Removed 4th pipe for ICL in DBuf assignment
table(Matt Roper)
- Fixed wrong DBuf slice in DBuf table for TGL
(Matt Roper)
- Added comment regarding why we currently not
using pipe ratio for DBuf assignment for ICL
v6: - Changed u32 to unsigned int in
icl_get_first_dbuf_slice_offset function signature
(Ville Syrjälä)
- Changed also u32 to u8 in dbuf slice mask structure
(Ville Syrjälä)
- Switched from DBUF_S1_BIT to enum + explicit
BIT(DBUF_S1) access(Ville Syrjälä)
- Switched to named initializers in DBuf assignment
arrays(Ville Syrjälä)
- DBuf assignment arrays now use autogeneration tool
from
https://patchwork.freedesktop.org/series/70493/
to avoid typos.
- Renamed i915_find_pipe_conf to *_compute_dbuf_slices
(Ville Syrjälä)
- Changed platforms ordering in skl_compute_dbuf_slices
to be from newest to oldest(Ville Syrjälä)
v7: - Now ORing assigned DBuf slice config always with DBUF_S1
because slice 1 has to be constantly powered on.
(Ville Syrjälä)
v8: - Added pipe_name for neater printing(Ville Syrjälä)
- Renamed width_before_pipe to width_before_pipe_in_range,
to better reflect that now all the calculations are happening
inside DBuf range allowed by current pipe configuration mask
(Ville Syrjälä)
- Shortened FIXME comment message, regarding constant ORing with
DBUF_S1(Ville Syrjälä)
- Added .dbuf_mask named initializer to pipe assignment array
(Ville Syrjälä)
- Edited pipe assignment array to use only single DBuf slice
for gen11 single pipe configurations, until "pipe ratio"
thing is finally sorted out(Ville Syrjälä)
- Removed unused parameter crtc_state for now(Ville Syrjälä)
from icl/tgl_compute_dbuf_slices function
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 385 ++++++++++++++++++++++++++++++--
1 file changed, 366 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4c87abcdb622..ffac0b862ca5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3809,13 +3809,29 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
return true;
}
-static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
- const struct intel_crtc_state *crtc_state,
- const u64 total_data_rate,
- const int num_active)
+/*
+ * Calculate initial DBuf slice offset, based on slice size
+ * and mask(i.e if slice size is 1024 and second slice is enabled
+ * offset would be 1024)
+ */
+static unsigned int
+icl_get_first_dbuf_slice_offset(u32 dbuf_slice_mask,
+ u32 slice_size,
+ u32 ddb_size)
+{
+ unsigned int offset = 0;
+
+ if (!dbuf_slice_mask)
+ return 0;
+
+ offset = (ffs(dbuf_slice_mask) - 1) * slice_size;
+
+ WARN_ON(offset >= ddb_size);
+ return offset;
+}
+
+static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv)
{
- struct drm_atomic_state *state = crtc_state->uapi.state;
- struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
drm_WARN_ON(&dev_priv->drm, ddb_size == 0);
@@ -3823,12 +3839,12 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) < 11)
return ddb_size - 4; /* 4 blocks for bypass path allocation */
- intel_state->enabled_dbuf_slices_mask = BIT(DBUF_S1);
- ddb_size /= 2;
-
return ddb_size;
}
+static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state,
+ u32 active_pipes);
+
static void
skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
@@ -3840,10 +3856,17 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
struct drm_crtc *for_crtc = crtc_state->uapi.crtc;
const struct intel_crtc *crtc;
- u32 pipe_width = 0, total_width = 0, width_before_pipe = 0;
+ u32 pipe_width = 0, total_width_in_range = 0, width_before_pipe_in_range = 0;
enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
u16 ddb_size;
+ u32 ddb_range_size;
u32 i;
+ u32 dbuf_slice_mask;
+ u32 active_pipes;
+ u32 offset;
+ u32 slice_size;
+ u32 total_slice_mask;
+ u32 start, end;
if (drm_WARN_ON(&dev_priv->drm, !state) || !crtc_state->hw.active) {
alloc->start = 0;
@@ -3853,12 +3876,15 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
}
if (intel_state->active_pipe_changes)
- *num_active = hweight8(intel_state->active_pipes);
+ active_pipes = intel_state->active_pipes;
else
- *num_active = hweight8(dev_priv->active_pipes);
+ active_pipes = dev_priv->active_pipes;
+
+ *num_active = hweight8(active_pipes);
+
+ ddb_size = intel_get_ddb_size(dev_priv);
- ddb_size = intel_get_ddb_size(dev_priv, crtc_state, total_data_rate,
- *num_active);
+ slice_size = ddb_size / INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
/*
* If the state doesn't change the active CRTC's or there is no
@@ -3877,31 +3903,96 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
return;
}
+ /*
+ * Get allowed DBuf slices for correspondent pipe and platform.
+ */
+ dbuf_slice_mask = skl_compute_dbuf_slices(crtc_state, active_pipes);
+
+ DRM_DEBUG_KMS("DBuf slice mask %x pipe %c active pipes %x\n",
+ dbuf_slice_mask,
+ pipe_name(for_pipe), active_pipes);
+
+ /*
+ * Figure out at which DBuf slice we start, i.e if we start at Dbuf S2
+ * and slice size is 1024, the offset would be 1024
+ */
+ offset = icl_get_first_dbuf_slice_offset(dbuf_slice_mask,
+ slice_size, ddb_size);
+
+ /*
+ * Figure out total size of allowed DBuf slices, which is basically
+ * a number of allowed slices for that pipe multiplied by slice size.
+ * Inside of this
+ * range ddb entries are still allocated in proportion to display width.
+ */
+ ddb_range_size = hweight8(dbuf_slice_mask) * slice_size;
+
/*
* Watermark/ddb requirement highly depends upon width of the
* framebuffer, So instead of allocating DDB equally among pipes
* distribute DDB based on resolution/width of the display.
*/
+ total_slice_mask = dbuf_slice_mask;
for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
enum pipe pipe = crtc->pipe;
int hdisplay, vdisplay;
+ u32 pipe_dbuf_slice_mask;
- if (!crtc_state->hw.enable)
+ if (!crtc_state->hw.active)
+ continue;
+
+ pipe_dbuf_slice_mask = skl_compute_dbuf_slices(crtc_state,
+ active_pipes);
+
+ /*
+ * According to BSpec pipe can share one dbuf slice with another
+ * pipes or pipe can use multiple dbufs, in both cases we
+ * account for other pipes only if they have exactly same mask.
+ * However we need to account how many slices we should enable
+ * in total.
+ */
+ total_slice_mask |= pipe_dbuf_slice_mask;
+
+ /*
+ * Do not account pipes using other slice sets
+ * luckily as of current BSpec slice sets do not partially
+ * intersect(pipes share either same one slice or same slice set
+ * i.e no partial intersection), so it is enough to check for
+ * equality for now.
+ */
+ if (dbuf_slice_mask != pipe_dbuf_slice_mask)
continue;
drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
- total_width += hdisplay;
+
+ total_width_in_range += hdisplay;
if (pipe < for_pipe)
- width_before_pipe += hdisplay;
+ width_before_pipe_in_range += hdisplay;
else if (pipe == for_pipe)
pipe_width = hdisplay;
}
- alloc->start = ddb_size * width_before_pipe / total_width;
- alloc->end = ddb_size * (width_before_pipe + pipe_width) / total_width;
+ /*
+ * FIXME: For now we always enable slice S1 as per
+ * the Bspec display initialization sequence.
+ */
+ intel_state->enabled_dbuf_slices_mask = total_slice_mask | BIT(DBUF_S1);
+
+ start = ddb_range_size * width_before_pipe_in_range / total_width_in_range;
+ end = ddb_range_size *
+ (width_before_pipe_in_range + pipe_width) / total_width_in_range;
+
+ alloc->start = offset + start;
+ alloc->end = offset + end;
+
+ DRM_DEBUG_KMS("Pipe %d ddb %d-%d\n", for_pipe,
+ alloc->start, alloc->end);
+ DRM_DEBUG_KMS("Enabled ddb slices mask %x num supported %d\n",
+ intel_state->enabled_dbuf_slices_mask,
+ INTEL_INFO(dev_priv)->num_supported_dbuf_slices);
}
static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
@@ -4072,6 +4163,262 @@ skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
return mul_fixed16(downscale_w, downscale_h);
}
+struct dbuf_slice_conf_entry {
+ u8 active_pipes;
+ u8 dbuf_mask[I915_MAX_PIPES];
+};
+
+/*
+ * Table taken from Bspec 12716
+ * Pipes do have some preferred DBuf slice affinity,
+ * plus there are some hardcoded requirements on how
+ * those should be distributed for multipipe scenarios.
+ * For more DBuf slices algorithm can get even more messy
+ * and less readable, so decided to use a table almost
+ * as is from BSpec itself - that way it is at least easier
+ * to compare, change and check.
+ */
+static struct dbuf_slice_conf_entry icl_allowed_dbufs[] =
+/* Autogenerated with igt/tools/intel_dbuf_map tool: */
+{
+ {
+ .active_pipes = BIT(PIPE_A),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1)
+ }
+ },
+ {
+ .active_pipes = BIT(PIPE_B),
+ .dbuf_mask = {
+ [PIPE_B] = BIT(DBUF_S1)
+ }
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1),
+ [PIPE_B] = BIT(DBUF_S2)
+ }
+ },
+ {
+ .active_pipes = BIT(PIPE_C),
+ .dbuf_mask = {
+ [PIPE_C] = BIT(DBUF_S2)
+ }
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1),
+ [PIPE_C] = BIT(DBUF_S2)
+ }
+ },
+ {
+ .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
+ .dbuf_mask = {
+ [PIPE_B] = BIT(DBUF_S1),
+ [PIPE_C] = BIT(DBUF_S2)
+ }
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1),
+ [PIPE_B] = BIT(DBUF_S1),
+ [PIPE_C] = BIT(DBUF_S2)
+ }
+ },
+};
+
+/*
+ * Table taken from Bspec 49255
+ * Pipes do have some preferred DBuf slice affinity,
+ * plus there are some hardcoded requirements on how
+ * those should be distributed for multipipe scenarios.
+ * For more DBuf slices algorithm can get even more messy
+ * and less readable, so decided to use a table almost
+ * as is from BSpec itself - that way it is at least easier
+ * to compare, change and check.
+ */
+static struct dbuf_slice_conf_entry tgl_allowed_dbufs[] =
+/* Autogenerated with igt/tools/intel_dbuf_map tool: */
+{
+ {
+ .active_pipes = BIT(PIPE_A),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2)
+ }
+ },
+ {
+ .active_pipes = BIT(PIPE_B),
+ .dbuf_mask = {
+ [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2)
+ }
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S2),
+ [PIPE_B] = BIT(DBUF_S1)
+ }
+ },
+ {
+ .active_pipes = BIT(PIPE_C),
+ .dbuf_mask = {
+ [PIPE_C] = BIT(DBUF_S2) | BIT(DBUF_S1)
+ }
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1),
+ [PIPE_C] = BIT(DBUF_S2)
+ }
+ },
+ {
+ .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
+ .dbuf_mask = {
+ [PIPE_B] = BIT(DBUF_S1),
+ [PIPE_C] = BIT(DBUF_S2)
+ }
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1),
+ [PIPE_B] = BIT(DBUF_S1),
+ [PIPE_C] = BIT(DBUF_S2)
+ }
+ },
+ {
+ .active_pipes = BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_D] = BIT(DBUF_S2) | BIT(DBUF_S1)
+ }
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1),
+ [PIPE_D] = BIT(DBUF_S2)
+ }
+ },
+ {
+ .active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_B] = BIT(DBUF_S1),
+ [PIPE_D] = BIT(DBUF_S2)
+ }
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1),
+ [PIPE_B] = BIT(DBUF_S1),
+ [PIPE_D] = BIT(DBUF_S2)
+ }
+ },
+ {
+ .active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_C] = BIT(DBUF_S1),
+ [PIPE_D] = BIT(DBUF_S2)
+ }
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1),
+ [PIPE_C] = BIT(DBUF_S2),
+ [PIPE_D] = BIT(DBUF_S2)
+ }
+ },
+ {
+ .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_B] = BIT(DBUF_S1),
+ [PIPE_C] = BIT(DBUF_S2),
+ [PIPE_D] = BIT(DBUF_S2)
+ }
+ },
+ {
+ .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+ .dbuf_mask = {
+ [PIPE_A] = BIT(DBUF_S1),
+ [PIPE_B] = BIT(DBUF_S1),
+ [PIPE_C] = BIT(DBUF_S2),
+ [PIPE_D] = BIT(DBUF_S2)
+ }
+ },
+};
+
+static u8 compute_dbuf_slices(enum pipe pipe,
+ u32 active_pipes,
+ const struct dbuf_slice_conf_entry *dbuf_slices,
+ int size)
+{
+ int i;
+
+ for (i = 0; i < size; i++) {
+ if (dbuf_slices[i].active_pipes == active_pipes)
+ return dbuf_slices[i].dbuf_mask[pipe];
+ }
+ return 0;
+}
+
+/*
+ * This function finds an entry with same enabled pipe configuration and
+ * returns correspondent DBuf slice mask as stated in BSpec for particular
+ * platform.
+ */
+static u32 icl_compute_dbuf_slices(enum pipe pipe,
+ u32 active_pipes)
+{
+ /*
+ * FIXME: For ICL this is still a bit unclear as prev BSpec revision
+ * required calculating "pipe ratio" in order to determine
+ * if one or two slices can be used for single pipe configurations
+ * as additional constraint to the existing table.
+ * However based on recent info, it should be not "pipe ratio"
+ * but rather ratio between pixel_rate and cdclk with additional
+ * constants, so for now we are using only table until this is
+ * clarified. Also this is the reason why crtc_state param is
+ * still here - we will need it once those additional constraints
+ * pop up.
+ */
+ return compute_dbuf_slices(pipe, active_pipes,
+ icl_allowed_dbufs,
+ ARRAY_SIZE(icl_allowed_dbufs));
+}
+
+static u32 tgl_compute_dbuf_slices(enum pipe pipe,
+ u32 active_pipes)
+{
+ return compute_dbuf_slices(pipe, active_pipes,
+ tgl_allowed_dbufs,
+ ARRAY_SIZE(tgl_allowed_dbufs));
+}
+
+static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state,
+ u32 active_pipes)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ if (IS_GEN(dev_priv, 12))
+ return tgl_compute_dbuf_slices(pipe,
+ active_pipes);
+ else if (IS_GEN(dev_priv, 11))
+ return icl_compute_dbuf_slices(pipe,
+ active_pipes);
+ /*
+ * For anything else just return one slice yet.
+ * Should be extended for other platforms.
+ */
+ return BIT(DBUF_S1);
+}
+
static u64
skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for Enable second DBuf slice for ICL and TGL (rev23)
2020-02-02 23:06 [Intel-gfx] [PATCH v17 0/6] Enable second DBuf slice for ICL and TGL Stanislav Lisovskiy
` (5 preceding siblings ...)
2020-02-02 23:06 ` [Intel-gfx] [PATCH v17 6/6] drm/i915: Correctly map DBUF slices to pipes Stanislav Lisovskiy
@ 2020-02-02 23:47 ` Patchwork
2020-02-05 11:33 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (2 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2020-02-02 23:47 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL (rev23)
URL : https://patchwork.freedesktop.org/series/70059/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7857 -> Patchwork_16386
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_16386 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16386, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16386:
### IGT changes ###
#### Warnings ####
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-guc: [INCOMPLETE][1] ([fdo#106070] / [i915#424]) -> [TIMEOUT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
Known issues
------------
Here are the changes found in Patchwork_16386 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_close_race@basic-threads:
- fi-hsw-peppy: [PASS][3] -> [TIMEOUT][4] ([fdo#112271] / [i915#1084])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/fi-hsw-peppy/igt@gem_close_race@basic-threads.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/fi-hsw-peppy/igt@gem_close_race@basic-threads.html
#### Possible fixes ####
* igt@gem_exec_parallel@contexts:
- fi-byt-n2820: [FAIL][5] ([i915#694]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/fi-byt-n2820/igt@gem_exec_parallel@contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/fi-byt-n2820/igt@gem_exec_parallel@contexts.html
* igt@i915_selftest@live_blt:
- fi-hsw-4770r: [DMESG-FAIL][7] ([i915#553] / [i915#725]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/fi-hsw-4770r/igt@i915_selftest@live_blt.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/fi-hsw-4770r/igt@i915_selftest@live_blt.html
- fi-hsw-4770: [DMESG-FAIL][9] ([i915#553] / [i915#725]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/fi-hsw-4770/igt@i915_selftest@live_blt.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/fi-hsw-4770/igt@i915_selftest@live_blt.html
#### Warnings ####
* igt@gem_exec_parallel@fds:
- fi-byt-n2820: [FAIL][11] ([i915#694]) -> [TIMEOUT][12] ([fdo#112271] / [i915#1084])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/fi-byt-n2820/igt@gem_exec_parallel@fds.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/fi-byt-n2820/igt@gem_exec_parallel@fds.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111096] / [i915#323]) -> [FAIL][14] ([fdo#111407])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
Participating hosts (47 -> 39)
------------------------------
Additional (3): fi-skl-6770hq fi-bwr-2160 fi-bsw-nick
Missing (11): fi-bsw-n3050 fi-byt-j1900 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-gdg-551 fi-bsw-kefka fi-skl-lmem fi-byt-clapper fi-bdw-samus fi-snb-2600
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7857 -> Patchwork_16386
CI-20190529: 20190529
CI_DRM_7857: 8ec40a15b9a930df9e445f17c5e01cdb6f80353a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5411: 86c6ab8a0b6696bdb2153febd350af7fa02fbb00 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16386: cdd031c39303872425a3e2b3a8adfe73b0274a27 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cdd031c39303 drm/i915: Correctly map DBUF slices to pipes
4628e4d548af drm/i915: Manipulate DBuf slices properly
73e393255372 drm/i915: Introduce parameterized DBUF_CTL
08e938d22fc7 drm/i915: Update dbuf slices only with full modeset
1290912f0082 drm/i915: Move dbuf slice update to proper place
50710da9ba57 drm/i915: Remove skl_ddl_allocation struct
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev23)
2020-02-02 23:06 [Intel-gfx] [PATCH v17 0/6] Enable second DBuf slice for ICL and TGL Stanislav Lisovskiy
` (6 preceding siblings ...)
2020-02-02 23:47 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Enable second DBuf slice for ICL and TGL (rev23) Patchwork
@ 2020-02-05 11:33 ` Patchwork
2020-02-05 12:57 ` Lisovskiy, Stanislav
2020-02-05 18:40 ` [Intel-gfx] [PATCH v17 0/6] Enable second DBuf slice for ICL and TGL Ville Syrjälä
2020-02-06 8:40 ` [Intel-gfx] ✓ Fi.CI.IGT: success for Enable second DBuf slice for ICL and TGL (rev23) Patchwork
9 siblings, 1 reply; 14+ messages in thread
From: Patchwork @ 2020-02-05 11:33 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL (rev23)
URL : https://patchwork.freedesktop.org/series/70059/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7857_full -> Patchwork_16386_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16386_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16386_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16386_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_plane_cursor@pipe-a-viewport-size-128:
- shard-tglb: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb6/igt@kms_plane_cursor@pipe-a-viewport-size-128.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb2/igt@kms_plane_cursor@pipe-a-viewport-size-128.html
Known issues
------------
Here are the changes found in Patchwork_16386_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_eio@in-flight-suspend:
- shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-apl6/igt@gem_eio@in-flight-suspend.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-apl2/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +18 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb1/igt@gem_exec_schedule@out-order-bsd2.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb7/igt@gem_exec_schedule@out-order-bsd2.html
* igt@gem_exec_schedule@pi-distinct-iova-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([i915#677])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb7/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb2/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +6 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb6/igt@gem_exec_schedule@wide-bsd.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb4/igt@gem_exec_schedule@wide-bsd.html
* igt@gem_exec_store@pages-vcs1:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112080]) +8 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb4/igt@gem_exec_store@pages-vcs1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb8/igt@gem_exec_store@pages-vcs1.html
* igt@gem_exec_suspend@basic-s4-devices:
- shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([fdo#107139] / [i915#62] / [i915#92])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl7/igt@gem_exec_suspend@basic-s4-devices.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-kbl6/igt@gem_exec_suspend@basic-s4-devices.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#454])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb2/igt@i915_pm_dc@dc6-dpms.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_busy@extended-pageflip-hang-oldfb-render-pipe-b:
- shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +15 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl3/igt@kms_busy@extended-pageflip-hang-oldfb-render-pipe-b.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-kbl6/igt@kms_busy@extended-pageflip-hang-oldfb-render-pipe-b.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen:
- shard-tglb: [PASS][21] -> [FAIL][22] ([fdo#111703])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb5/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb2/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled:
- shard-tglb: [PASS][23] -> [FAIL][24] ([i915#559])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb6/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb3/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled:
- shard-tglb: [PASS][25] -> [DMESG-FAIL][26] ([i915#402]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb3/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb3/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled.html
* igt@kms_fbcon_fbt@psr:
- shard-skl: [PASS][27] -> [DMESG-WARN][28] ([i915#109]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl1/igt@kms_fbcon_fbt@psr.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl2/igt@kms_fbcon_fbt@psr.html
* igt@kms_flip@absolute-wf_vblank:
- shard-glk: [PASS][29] -> [INCOMPLETE][30] ([CI#80] / [i915#58] / [k.org#198133])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-glk6/igt@kms_flip@absolute-wf_vblank.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-glk6/igt@kms_flip@absolute-wf_vblank.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][31] -> [FAIL][32] ([i915#79]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [PASS][33] -> [DMESG-WARN][34] ([i915#180]) +9 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-snb: [PASS][35] -> [SKIP][36] ([fdo#109271])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-snb1/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-snb6/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][37] -> [FAIL][38] ([fdo#108145])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][39] -> [FAIL][40] ([fdo#108145] / [i915#265])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][41] -> [SKIP][42] ([fdo#109441]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb8/igt@kms_psr@psr2_no_drrs.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][43] -> [FAIL][44] ([i915#31])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-apl7/igt@kms_setmode@basic.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-apl7/igt@kms_setmode@basic.html
- shard-skl: [PASS][45] -> [FAIL][46] ([i915#31])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl2/igt@kms_setmode@basic.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl1/igt@kms_setmode@basic.html
* igt@prime_mmap_coherency@read:
- shard-hsw: [PASS][47] -> [FAIL][48] ([i915#914])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-hsw7/igt@prime_mmap_coherency@read.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-hsw1/igt@prime_mmap_coherency@read.html
#### Possible fixes ####
* igt@gem_exec_balancer@smoke:
- shard-iclb: [SKIP][49] ([fdo#110854]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb8/igt@gem_exec_balancer@smoke.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb4/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_reloc@basic-write-cpu-active:
- shard-skl: [DMESG-WARN][51] ([i915#109]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl2/igt@gem_exec_reloc@basic-write-cpu-active.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl10/igt@gem_exec_reloc@basic-write-cpu-active.html
* igt@gem_exec_schedule@pi-common-bsd:
- shard-iclb: [SKIP][53] ([i915#677]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb1/igt@gem_exec_schedule@pi-common-bsd.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb7/igt@gem_exec_schedule@pi-common-bsd.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [SKIP][55] ([fdo#112146]) -> [PASS][56] +4 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb3/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_partial_pwrite_pread@reads-display:
- shard-hsw: [FAIL][57] ([i915#694]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-hsw7/igt@gem_partial_pwrite_pread@reads-display.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-hsw1/igt@gem_partial_pwrite_pread@reads-display.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +4 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_flip@plain-flip-fb-recreate:
- shard-skl: [FAIL][61] ([i915#34]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl7/igt@kms_flip@plain-flip-fb-recreate.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl10/igt@kms_flip@plain-flip-fb-recreate.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite:
- shard-tglb: [SKIP][63] ([i915#668]) -> [PASS][64] +3 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: [DMESG-WARN][65] ([i915#180]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][67] ([fdo#108145] / [i915#265]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][69] ([fdo#109441]) -> [PASS][70] +2 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-skl: [INCOMPLETE][71] ([i915#69]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl8/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl5/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
* igt@perf_pmu@busy-no-semaphores-vcs1:
- shard-iclb: [SKIP][73] ([fdo#112080]) -> [PASS][74] +17 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb6/igt@perf_pmu@busy-no-semaphores-vcs1.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][75] ([fdo#109276]) -> [PASS][76] +15 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb8/igt@prime_vgem@fence-wait-bsd2.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [FAIL][77] ([IGT#28]) -> [SKIP][78] ([fdo#112080])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb3/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_tiled_blits@interruptible:
- shard-hsw: [FAIL][79] ([i915#818]) -> [FAIL][80] ([i915#694])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-hsw2/igt@gem_tiled_blits@interruptible.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-hsw8/igt@gem_tiled_blits@interruptible.html
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: [FAIL][81] ([i915#454]) -> [DMESG-FAIL][82] ([i915#402])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb3/igt@i915_pm_dc@dc6-psr.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb6/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@legacy-planes:
- shard-snb: [INCOMPLETE][83] ([i915#82]) -> [SKIP][84] ([fdo#109271])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-snb6/igt@i915_pm_rpm@legacy-planes.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-snb4/igt@i915_pm_rpm@legacy-planes.html
* igt@i915_selftest@live_blt:
- shard-hsw: [DMESG-FAIL][85] ([i915#770]) -> [DMESG-FAIL][86] ([i915#553] / [i915#725])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-hsw1/igt@i915_selftest@live_blt.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-hsw5/igt@i915_selftest@live_blt.html
[CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111703]: https://bugs.freedesktop.org/show_bug.cgi?id=111703
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#559]: https://gitlab.freedesktop.org/drm/intel/issues/559
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#770]: https://gitlab.freedesktop.org/drm/intel/issues/770
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#818]: https://gitlab.freedesktop.org/drm/intel/issues/818
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#914]: https://gitlab.freedesktop.org/drm/intel/issues/914
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7857 -> Patchwork_16386
CI-20190529: 20190529
CI_DRM_7857: 8ec40a15b9a930df9e445f17c5e01cdb6f80353a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5411: 86c6ab8a0b6696bdb2153febd350af7fa02fbb00 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16386: cdd031c39303872425a3e2b3a8adfe73b0274a27 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev23)
2020-02-05 11:33 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-02-05 12:57 ` Lisovskiy, Stanislav
2020-02-05 13:05 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 14+ messages in thread
From: Lisovskiy, Stanislav @ 2020-02-05 12:57 UTC (permalink / raw)
To: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 20720 bytes --]
That is a crc mismatch which has nothing to do with DBuf:
Starting subtest: pipe-A-viewport-size-128
(kms_plane_cursor:1056) igt_debugfs-CRITICAL: Test assertion failure function igt_assert_crc_equal, file ../lib/igt_debugfs.c:423:
(kms_plane_cursor:1056) igt_debugfs-CRITICAL: Failed assertion: !mismatch || igt_skip_crc_compare
Subtest pipe-A-viewport-size-128 failed.
I guess we really need to push that already.
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________
From: Patchwork <patchwork@emeril.freedesktop.org>
Sent: Wednesday, February 5, 2020 1:33:28 PM
To: Lisovskiy, Stanislav
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev23)
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL (rev23)
URL : https://patchwork.freedesktop.org/series/70059/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7857_full -> Patchwork_16386_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16386_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16386_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16386_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_plane_cursor@pipe-a-viewport-size-128:
- shard-tglb: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb6/igt@kms_plane_cursor@pipe-a-viewport-size-128.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb2/igt@kms_plane_cursor@pipe-a-viewport-size-128.html
Known issues
------------
Here are the changes found in Patchwork_16386_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_eio@in-flight-suspend:
- shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-apl6/igt@gem_eio@in-flight-suspend.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-apl2/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +18 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb1/igt@gem_exec_schedule@out-order-bsd2.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb7/igt@gem_exec_schedule@out-order-bsd2.html
* igt@gem_exec_schedule@pi-distinct-iova-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([i915#677])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb7/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb2/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +6 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb6/igt@gem_exec_schedule@wide-bsd.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb4/igt@gem_exec_schedule@wide-bsd.html
* igt@gem_exec_store@pages-vcs1:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112080]) +8 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb4/igt@gem_exec_store@pages-vcs1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb8/igt@gem_exec_store@pages-vcs1.html
* igt@gem_exec_suspend@basic-s4-devices:
- shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([fdo#107139] / [i915#62] / [i915#92])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl7/igt@gem_exec_suspend@basic-s4-devices.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-kbl6/igt@gem_exec_suspend@basic-s4-devices.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#454])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb2/igt@i915_pm_dc@dc6-dpms.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_busy@extended-pageflip-hang-oldfb-render-pipe-b:
- shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +15 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl3/igt@kms_busy@extended-pageflip-hang-oldfb-render-pipe-b.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-kbl6/igt@kms_busy@extended-pageflip-hang-oldfb-render-pipe-b.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen:
- shard-tglb: [PASS][21] -> [FAIL][22] ([fdo#111703])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb5/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb2/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled:
- shard-tglb: [PASS][23] -> [FAIL][24] ([i915#559])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb6/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb3/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled:
- shard-tglb: [PASS][25] -> [DMESG-FAIL][26] ([i915#402]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb3/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb3/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled.html
* igt@kms_fbcon_fbt@psr:
- shard-skl: [PASS][27] -> [DMESG-WARN][28] ([i915#109]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl1/igt@kms_fbcon_fbt@psr.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl2/igt@kms_fbcon_fbt@psr.html
* igt@kms_flip@absolute-wf_vblank:
- shard-glk: [PASS][29] -> [INCOMPLETE][30] ([CI#80] / [i915#58] / [k.org#198133])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-glk6/igt@kms_flip@absolute-wf_vblank.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-glk6/igt@kms_flip@absolute-wf_vblank.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][31] -> [FAIL][32] ([i915#79]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [PASS][33] -> [DMESG-WARN][34] ([i915#180]) +9 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-snb: [PASS][35] -> [SKIP][36] ([fdo#109271])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-snb1/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-snb6/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][37] -> [FAIL][38] ([fdo#108145])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][39] -> [FAIL][40] ([fdo#108145] / [i915#265])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][41] -> [SKIP][42] ([fdo#109441]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb8/igt@kms_psr@psr2_no_drrs.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][43] -> [FAIL][44] ([i915#31])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-apl7/igt@kms_setmode@basic.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-apl7/igt@kms_setmode@basic.html
- shard-skl: [PASS][45] -> [FAIL][46] ([i915#31])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl2/igt@kms_setmode@basic.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl1/igt@kms_setmode@basic.html
* igt@prime_mmap_coherency@read:
- shard-hsw: [PASS][47] -> [FAIL][48] ([i915#914])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-hsw7/igt@prime_mmap_coherency@read.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-hsw1/igt@prime_mmap_coherency@read.html
#### Possible fixes ####
* igt@gem_exec_balancer@smoke:
- shard-iclb: [SKIP][49] ([fdo#110854]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb8/igt@gem_exec_balancer@smoke.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb4/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_reloc@basic-write-cpu-active:
- shard-skl: [DMESG-WARN][51] ([i915#109]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl2/igt@gem_exec_reloc@basic-write-cpu-active.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl10/igt@gem_exec_reloc@basic-write-cpu-active.html
* igt@gem_exec_schedule@pi-common-bsd:
- shard-iclb: [SKIP][53] ([i915#677]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb1/igt@gem_exec_schedule@pi-common-bsd.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb7/igt@gem_exec_schedule@pi-common-bsd.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [SKIP][55] ([fdo#112146]) -> [PASS][56] +4 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb3/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_partial_pwrite_pread@reads-display:
- shard-hsw: [FAIL][57] ([i915#694]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-hsw7/igt@gem_partial_pwrite_pread@reads-display.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-hsw1/igt@gem_partial_pwrite_pread@reads-display.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +4 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_flip@plain-flip-fb-recreate:
- shard-skl: [FAIL][61] ([i915#34]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl7/igt@kms_flip@plain-flip-fb-recreate.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl10/igt@kms_flip@plain-flip-fb-recreate.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite:
- shard-tglb: [SKIP][63] ([i915#668]) -> [PASS][64] +3 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: [DMESG-WARN][65] ([i915#180]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][67] ([fdo#108145] / [i915#265]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][69] ([fdo#109441]) -> [PASS][70] +2 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-skl: [INCOMPLETE][71] ([i915#69]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl8/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl5/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
* igt@perf_pmu@busy-no-semaphores-vcs1:
- shard-iclb: [SKIP][73] ([fdo#112080]) -> [PASS][74] +17 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb6/igt@perf_pmu@busy-no-semaphores-vcs1.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][75] ([fdo#109276]) -> [PASS][76] +15 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb8/igt@prime_vgem@fence-wait-bsd2.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [FAIL][77] ([IGT#28]) -> [SKIP][78] ([fdo#112080])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb3/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_tiled_blits@interruptible:
- shard-hsw: [FAIL][79] ([i915#818]) -> [FAIL][80] ([i915#694])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-hsw2/igt@gem_tiled_blits@interruptible.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-hsw8/igt@gem_tiled_blits@interruptible.html
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: [FAIL][81] ([i915#454]) -> [DMESG-FAIL][82] ([i915#402])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb3/igt@i915_pm_dc@dc6-psr.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb6/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@legacy-planes:
- shard-snb: [INCOMPLETE][83] ([i915#82]) -> [SKIP][84] ([fdo#109271])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-snb6/igt@i915_pm_rpm@legacy-planes.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-snb4/igt@i915_pm_rpm@legacy-planes.html
* igt@i915_selftest@live_blt:
- shard-hsw: [DMESG-FAIL][85] ([i915#770]) -> [DMESG-FAIL][86] ([i915#553] / [i915#725])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-hsw1/igt@i915_selftest@live_blt.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-hsw5/igt@i915_selftest@live_blt.html
[CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111703]: https://bugs.freedesktop.org/show_bug.cgi?id=111703
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#559]: https://gitlab.freedesktop.org/drm/intel/issues/559
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#770]: https://gitlab.freedesktop.org/drm/intel/issues/770
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#818]: https://gitlab.freedesktop.org/drm/intel/issues/818
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#914]: https://gitlab.freedesktop.org/drm/intel/issues/914
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7857 -> Patchwork_16386
CI-20190529: 20190529
CI_DRM_7857: 8ec40a15b9a930df9e445f17c5e01cdb6f80353a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5411: 86c6ab8a0b6696bdb2153febd350af7fa02fbb00 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16386: cdd031c39303872425a3e2b3a8adfe73b0274a27 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/index.html
[-- Attachment #1.2: Type: text/html, Size: 40678 bytes --]
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev23)
2020-02-05 12:57 ` Lisovskiy, Stanislav
@ 2020-02-05 13:05 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 14+ messages in thread
From: Lisovskiy, Stanislav @ 2020-02-05 13:05 UTC (permalink / raw)
To: intel-gfx, Vudum, Lakshminarayana
[-- Attachment #1.1: Type: text/plain, Size: 21268 bytes --]
Added Lakshmi to cc, I guess we should have a bug somewhere about crc mismatch,
as it can't be caused by changes in DBuf in absence of underruns and especially
for single pipe.
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________
From: Lisovskiy, Stanislav
Sent: Wednesday, February 5, 2020 2:57:23 PM
To: intel-gfx@lists.freedesktop.org
Subject: Re: ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev23)
That is a crc mismatch which has nothing to do with DBuf:
Starting subtest: pipe-A-viewport-size-128
(kms_plane_cursor:1056) igt_debugfs-CRITICAL: Test assertion failure function igt_assert_crc_equal, file ../lib/igt_debugfs.c:423:
(kms_plane_cursor:1056) igt_debugfs-CRITICAL: Failed assertion: !mismatch || igt_skip_crc_compare
Subtest pipe-A-viewport-size-128 failed.
I guess we really need to push that already.
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________
From: Patchwork <patchwork@emeril.freedesktop.org>
Sent: Wednesday, February 5, 2020 1:33:28 PM
To: Lisovskiy, Stanislav
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev23)
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL (rev23)
URL : https://patchwork.freedesktop.org/series/70059/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7857_full -> Patchwork_16386_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16386_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16386_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16386_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_plane_cursor@pipe-a-viewport-size-128:
- shard-tglb: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb6/igt@kms_plane_cursor@pipe-a-viewport-size-128.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb2/igt@kms_plane_cursor@pipe-a-viewport-size-128.html
Known issues
------------
Here are the changes found in Patchwork_16386_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_eio@in-flight-suspend:
- shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-apl6/igt@gem_eio@in-flight-suspend.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-apl2/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +18 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb1/igt@gem_exec_schedule@out-order-bsd2.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb7/igt@gem_exec_schedule@out-order-bsd2.html
* igt@gem_exec_schedule@pi-distinct-iova-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([i915#677])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb7/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb2/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +6 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb6/igt@gem_exec_schedule@wide-bsd.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb4/igt@gem_exec_schedule@wide-bsd.html
* igt@gem_exec_store@pages-vcs1:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112080]) +8 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb4/igt@gem_exec_store@pages-vcs1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb8/igt@gem_exec_store@pages-vcs1.html
* igt@gem_exec_suspend@basic-s4-devices:
- shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([fdo#107139] / [i915#62] / [i915#92])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl7/igt@gem_exec_suspend@basic-s4-devices.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-kbl6/igt@gem_exec_suspend@basic-s4-devices.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#454])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb2/igt@i915_pm_dc@dc6-dpms.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_busy@extended-pageflip-hang-oldfb-render-pipe-b:
- shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +15 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl3/igt@kms_busy@extended-pageflip-hang-oldfb-render-pipe-b.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-kbl6/igt@kms_busy@extended-pageflip-hang-oldfb-render-pipe-b.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen:
- shard-tglb: [PASS][21] -> [FAIL][22] ([fdo#111703])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb5/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb2/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled:
- shard-tglb: [PASS][23] -> [FAIL][24] ([i915#559])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb6/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb3/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled:
- shard-tglb: [PASS][25] -> [DMESG-FAIL][26] ([i915#402]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb3/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb3/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled.html
* igt@kms_fbcon_fbt@psr:
- shard-skl: [PASS][27] -> [DMESG-WARN][28] ([i915#109]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl1/igt@kms_fbcon_fbt@psr.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl2/igt@kms_fbcon_fbt@psr.html
* igt@kms_flip@absolute-wf_vblank:
- shard-glk: [PASS][29] -> [INCOMPLETE][30] ([CI#80] / [i915#58] / [k.org#198133])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-glk6/igt@kms_flip@absolute-wf_vblank.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-glk6/igt@kms_flip@absolute-wf_vblank.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][31] -> [FAIL][32] ([i915#79]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [PASS][33] -> [DMESG-WARN][34] ([i915#180]) +9 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-snb: [PASS][35] -> [SKIP][36] ([fdo#109271])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-snb1/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-snb6/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][37] -> [FAIL][38] ([fdo#108145])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][39] -> [FAIL][40] ([fdo#108145] / [i915#265])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][41] -> [SKIP][42] ([fdo#109441]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb8/igt@kms_psr@psr2_no_drrs.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][43] -> [FAIL][44] ([i915#31])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-apl7/igt@kms_setmode@basic.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-apl7/igt@kms_setmode@basic.html
- shard-skl: [PASS][45] -> [FAIL][46] ([i915#31])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl2/igt@kms_setmode@basic.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl1/igt@kms_setmode@basic.html
* igt@prime_mmap_coherency@read:
- shard-hsw: [PASS][47] -> [FAIL][48] ([i915#914])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-hsw7/igt@prime_mmap_coherency@read.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-hsw1/igt@prime_mmap_coherency@read.html
#### Possible fixes ####
* igt@gem_exec_balancer@smoke:
- shard-iclb: [SKIP][49] ([fdo#110854]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb8/igt@gem_exec_balancer@smoke.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb4/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_reloc@basic-write-cpu-active:
- shard-skl: [DMESG-WARN][51] ([i915#109]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl2/igt@gem_exec_reloc@basic-write-cpu-active.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl10/igt@gem_exec_reloc@basic-write-cpu-active.html
* igt@gem_exec_schedule@pi-common-bsd:
- shard-iclb: [SKIP][53] ([i915#677]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb1/igt@gem_exec_schedule@pi-common-bsd.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb7/igt@gem_exec_schedule@pi-common-bsd.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [SKIP][55] ([fdo#112146]) -> [PASS][56] +4 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb3/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_partial_pwrite_pread@reads-display:
- shard-hsw: [FAIL][57] ([i915#694]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-hsw7/igt@gem_partial_pwrite_pread@reads-display.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-hsw1/igt@gem_partial_pwrite_pread@reads-display.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +4 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_flip@plain-flip-fb-recreate:
- shard-skl: [FAIL][61] ([i915#34]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl7/igt@kms_flip@plain-flip-fb-recreate.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl10/igt@kms_flip@plain-flip-fb-recreate.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite:
- shard-tglb: [SKIP][63] ([i915#668]) -> [PASS][64] +3 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: [DMESG-WARN][65] ([i915#180]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][67] ([fdo#108145] / [i915#265]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][69] ([fdo#109441]) -> [PASS][70] +2 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-skl: [INCOMPLETE][71] ([i915#69]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl8/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl5/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
* igt@perf_pmu@busy-no-semaphores-vcs1:
- shard-iclb: [SKIP][73] ([fdo#112080]) -> [PASS][74] +17 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb6/igt@perf_pmu@busy-no-semaphores-vcs1.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][75] ([fdo#109276]) -> [PASS][76] +15 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb8/igt@prime_vgem@fence-wait-bsd2.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [FAIL][77] ([IGT#28]) -> [SKIP][78] ([fdo#112080])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb3/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_tiled_blits@interruptible:
- shard-hsw: [FAIL][79] ([i915#818]) -> [FAIL][80] ([i915#694])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-hsw2/igt@gem_tiled_blits@interruptible.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-hsw8/igt@gem_tiled_blits@interruptible.html
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: [FAIL][81] ([i915#454]) -> [DMESG-FAIL][82] ([i915#402])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb3/igt@i915_pm_dc@dc6-psr.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb6/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@legacy-planes:
- shard-snb: [INCOMPLETE][83] ([i915#82]) -> [SKIP][84] ([fdo#109271])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-snb6/igt@i915_pm_rpm@legacy-planes.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-snb4/igt@i915_pm_rpm@legacy-planes.html
* igt@i915_selftest@live_blt:
- shard-hsw: [DMESG-FAIL][85] ([i915#770]) -> [DMESG-FAIL][86] ([i915#553] / [i915#725])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-hsw1/igt@i915_selftest@live_blt.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-hsw5/igt@i915_selftest@live_blt.html
[CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111703]: https://bugs.freedesktop.org/show_bug.cgi?id=111703
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#559]: https://gitlab.freedesktop.org/drm/intel/issues/559
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#770]: https://gitlab.freedesktop.org/drm/intel/issues/770
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#818]: https://gitlab.freedesktop.org/drm/intel/issues/818
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#914]: https://gitlab.freedesktop.org/drm/intel/issues/914
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7857 -> Patchwork_16386
CI-20190529: 20190529
CI_DRM_7857: 8ec40a15b9a930df9e445f17c5e01cdb6f80353a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5411: 86c6ab8a0b6696bdb2153febd350af7fa02fbb00 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16386: cdd031c39303872425a3e2b3a8adfe73b0274a27 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH v17 0/6] Enable second DBuf slice for ICL and TGL
2020-02-02 23:06 [Intel-gfx] [PATCH v17 0/6] Enable second DBuf slice for ICL and TGL Stanislav Lisovskiy
` (7 preceding siblings ...)
2020-02-05 11:33 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-02-05 18:40 ` Ville Syrjälä
2020-02-06 8:40 ` [Intel-gfx] ✓ Fi.CI.IGT: success for Enable second DBuf slice for ICL and TGL (rev23) Patchwork
9 siblings, 0 replies; 14+ messages in thread
From: Ville Syrjälä @ 2020-02-05 18:40 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Mon, Feb 03, 2020 at 01:06:24AM +0200, Stanislav Lisovskiy wrote:
> Those patch series, do some initial preparation DBuf manipulating code
> cleanups, i.e remove redundant structures/code, switch to mask
> based DBuf manupulation, get into use DBuf assignment according to
> BSpec rules.
>
> Stanislav Lisovskiy (6):
> drm/i915: Remove skl_ddl_allocation struct
> drm/i915: Move dbuf slice update to proper place
> drm/i915: Update dbuf slices only with full modeset
> drm/i915: Introduce parameterized DBUF_CTL
> drm/i915: Manipulate DBuf slices properly
> drm/i915: Correctly map DBUF slices to pipes
Pushed the lot to dinq. Thanks for the patches and reviews.
>
> drivers/gpu/drm/i915/display/intel_display.c | 54 ++-
> .../drm/i915/display/intel_display_power.c | 100 ++--
> .../drm/i915/display/intel_display_power.h | 5 +
> .../drm/i915/display/intel_display_types.h | 4 +-
> drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 11 +-
> drivers/gpu/drm/i915/i915_pci.c | 5 +-
> drivers/gpu/drm/i915/i915_reg.h | 6 +-
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 449 +++++++++++++++---
> drivers/gpu/drm/i915/intel_pm.h | 5 +-
> 11 files changed, 479 insertions(+), 163 deletions(-)
>
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for Enable second DBuf slice for ICL and TGL (rev23)
2020-02-02 23:06 [Intel-gfx] [PATCH v17 0/6] Enable second DBuf slice for ICL and TGL Stanislav Lisovskiy
` (8 preceding siblings ...)
2020-02-05 18:40 ` [Intel-gfx] [PATCH v17 0/6] Enable second DBuf slice for ICL and TGL Ville Syrjälä
@ 2020-02-06 8:40 ` Patchwork
9 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2020-02-06 8:40 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL (rev23)
URL : https://patchwork.freedesktop.org/series/70059/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7857_full -> Patchwork_16386_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_16386_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110841])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_eio@in-flight-suspend:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#180])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-apl6/igt@gem_eio@in-flight-suspend.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-apl2/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +18 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb1/igt@gem_exec_schedule@out-order-bsd2.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb7/igt@gem_exec_schedule@out-order-bsd2.html
* igt@gem_exec_schedule@pi-distinct-iova-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([i915#677])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb7/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb2/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +6 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb6/igt@gem_exec_schedule@wide-bsd.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb4/igt@gem_exec_schedule@wide-bsd.html
* igt@gem_exec_store@pages-vcs1:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112080]) +8 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb4/igt@gem_exec_store@pages-vcs1.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb8/igt@gem_exec_store@pages-vcs1.html
* igt@gem_exec_suspend@basic-s4-devices:
- shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([fdo#107139] / [i915#62] / [i915#92])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl7/igt@gem_exec_suspend@basic-s4-devices.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-kbl6/igt@gem_exec_suspend@basic-s4-devices.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][15] -> [FAIL][16] ([i915#454])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb2/igt@i915_pm_dc@dc6-dpms.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_busy@extended-pageflip-hang-oldfb-render-pipe-b:
- shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +15 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl3/igt@kms_busy@extended-pageflip-hang-oldfb-render-pipe-b.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-kbl6/igt@kms_busy@extended-pageflip-hang-oldfb-render-pipe-b.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen:
- shard-tglb: [PASS][19] -> [FAIL][20] ([fdo#111703])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb5/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb2/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled:
- shard-tglb: [PASS][21] -> [FAIL][22] ([i915#559])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb6/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb3/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled:
- shard-tglb: [PASS][23] -> [DMESG-FAIL][24] ([i915#402]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb3/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb3/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled.html
* igt@kms_fbcon_fbt@psr:
- shard-skl: [PASS][25] -> [DMESG-WARN][26] ([i915#109]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl1/igt@kms_fbcon_fbt@psr.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl2/igt@kms_fbcon_fbt@psr.html
* igt@kms_flip@absolute-wf_vblank:
- shard-glk: [PASS][27] -> [INCOMPLETE][28] ([CI#80] / [i915#58] / [k.org#198133])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-glk6/igt@kms_flip@absolute-wf_vblank.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-glk6/igt@kms_flip@absolute-wf_vblank.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][29] -> [FAIL][30] ([i915#79]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [PASS][31] -> [DMESG-WARN][32] ([i915#180]) +9 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-snb: [PASS][33] -> [SKIP][34] ([fdo#109271])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-snb1/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-snb6/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][35] -> [FAIL][36] ([fdo#108145])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][37] -> [FAIL][38] ([fdo#108145] / [i915#265])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_cursor@pipe-a-viewport-size-128:
- shard-tglb: [PASS][39] -> [FAIL][40] ([i915#1139])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb6/igt@kms_plane_cursor@pipe-a-viewport-size-128.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb2/igt@kms_plane_cursor@pipe-a-viewport-size-128.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][41] -> [SKIP][42] ([fdo#109441]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb8/igt@kms_psr@psr2_no_drrs.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][43] -> [FAIL][44] ([i915#31])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-apl7/igt@kms_setmode@basic.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-apl7/igt@kms_setmode@basic.html
- shard-skl: [PASS][45] -> [FAIL][46] ([i915#31])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl2/igt@kms_setmode@basic.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl1/igt@kms_setmode@basic.html
* igt@prime_mmap_coherency@read:
- shard-hsw: [PASS][47] -> [FAIL][48] ([i915#914])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-hsw7/igt@prime_mmap_coherency@read.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-hsw1/igt@prime_mmap_coherency@read.html
#### Possible fixes ####
* igt@gem_exec_balancer@smoke:
- shard-iclb: [SKIP][49] ([fdo#110854]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb8/igt@gem_exec_balancer@smoke.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb4/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_reloc@basic-write-cpu-active:
- shard-skl: [DMESG-WARN][51] ([i915#109]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl2/igt@gem_exec_reloc@basic-write-cpu-active.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl10/igt@gem_exec_reloc@basic-write-cpu-active.html
* igt@gem_exec_schedule@pi-common-bsd:
- shard-iclb: [SKIP][53] ([i915#677]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb1/igt@gem_exec_schedule@pi-common-bsd.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb7/igt@gem_exec_schedule@pi-common-bsd.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [SKIP][55] ([fdo#112146]) -> [PASS][56] +4 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb3/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_partial_pwrite_pread@reads-display:
- shard-hsw: [FAIL][57] ([i915#694]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-hsw7/igt@gem_partial_pwrite_pread@reads-display.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-hsw1/igt@gem_partial_pwrite_pread@reads-display.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +4 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_flip@plain-flip-fb-recreate:
- shard-skl: [FAIL][61] ([i915#34]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl7/igt@kms_flip@plain-flip-fb-recreate.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl10/igt@kms_flip@plain-flip-fb-recreate.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite:
- shard-tglb: [SKIP][63] ([i915#668]) -> [PASS][64] +3 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: [DMESG-WARN][65] ([i915#180]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][67] ([fdo#108145] / [i915#265]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][69] ([fdo#109441]) -> [PASS][70] +2 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-skl: [INCOMPLETE][71] ([i915#69]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-skl8/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-skl5/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
* igt@perf_pmu@busy-no-semaphores-vcs1:
- shard-iclb: [SKIP][73] ([fdo#112080]) -> [PASS][74] +17 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb6/igt@perf_pmu@busy-no-semaphores-vcs1.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][75] ([fdo#109276]) -> [PASS][76] +15 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb8/igt@prime_vgem@fence-wait-bsd2.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [FAIL][77] ([IGT#28]) -> [SKIP][78] ([fdo#112080])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-iclb3/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_tiled_blits@interruptible:
- shard-hsw: [FAIL][79] ([i915#818]) -> [FAIL][80] ([i915#694])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-hsw2/igt@gem_tiled_blits@interruptible.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-hsw8/igt@gem_tiled_blits@interruptible.html
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: [FAIL][81] ([i915#454]) -> [DMESG-FAIL][82] ([i915#402])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-tglb3/igt@i915_pm_dc@dc6-psr.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-tglb6/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@legacy-planes:
- shard-snb: [INCOMPLETE][83] ([i915#82]) -> [SKIP][84] ([fdo#109271])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-snb6/igt@i915_pm_rpm@legacy-planes.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-snb4/igt@i915_pm_rpm@legacy-planes.html
* igt@i915_selftest@live_blt:
- shard-hsw: [DMESG-FAIL][85] ([i915#770]) -> [DMESG-FAIL][86] ([i915#553] / [i915#725])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7857/shard-hsw1/igt@i915_selftest@live_blt.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/shard-hsw5/igt@i915_selftest@live_blt.html
[CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111703]: https://bugs.freedesktop.org/show_bug.cgi?id=111703
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
[i915#1139]: https://gitlab.freedesktop.org/drm/intel/issues/1139
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#559]: https://gitlab.freedesktop.org/drm/intel/issues/559
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#770]: https://gitlab.freedesktop.org/drm/intel/issues/770
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#818]: https://gitlab.freedesktop.org/drm/intel/issues/818
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#914]: https://gitlab.freedesktop.org/drm/intel/issues/914
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7857 -> Patchwork_16386
CI-20190529: 20190529
CI_DRM_7857: 8ec40a15b9a930df9e445f17c5e01cdb6f80353a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5411: 86c6ab8a0b6696bdb2153febd350af7fa02fbb00 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16386: cdd031c39303872425a3e2b3a8adfe73b0274a27 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16386/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH v17 4/6] drm/i915: Introduce parameterized DBUF_CTL
2020-02-02 22:59 [Intel-gfx] [PATCH v17 0/6] Enable second DBuf slice for ICL and TGL Stanislav Lisovskiy
@ 2020-02-02 22:59 ` Stanislav Lisovskiy
0 siblings, 0 replies; 14+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-02 22:59 UTC (permalink / raw)
To: intel-gfx
Now start using parameterized DBUF_CTL instead
of hardcoded, this would allow shorter access
functions when reading or storing entire state.
Tried to implement it in a MMIO_PIPE manner, however
DBUF_CTL1 address is higher than DBUF_CTL2, which
implies that we have to now subtract from base
rather than add.
v2: - Removed unneeded DBUF_CTL_DIST and DBUF_CTL_ADDR
macros. Started to use _PICK construct as suggested
by Matt Roper.
v3: - _DBUF_CTL_S* to DBUF_CTL_S*, changed X to "slice"
in macro(Ville Syrjälä)
- Introduced enum for enumerating DBUF slices(Ville Syrjälä)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
.../drm/i915/display/intel_display_power.c | 40 ++++++++++---------
.../drm/i915/display/intel_display_power.h | 5 +++
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 6 +--
drivers/gpu/drm/i915/intel_pm.c | 2 +-
5 files changed, 31 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 86e349bbc0af..9f978c977dcb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1041,7 +1041,7 @@ static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
{
- u32 tmp = intel_de_read(dev_priv, DBUF_CTL);
+ u32 tmp = intel_de_read(dev_priv, DBUF_CTL_S(0));
WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
(DBUF_POWER_STATE | DBUF_POWER_REQUEST),
@@ -4418,12 +4418,12 @@ bool intel_dbuf_slice_set(struct drm_i915_private *dev_priv,
static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
{
- intel_dbuf_slice_set(dev_priv, DBUF_CTL, true);
+ intel_dbuf_slice_set(dev_priv, DBUF_CTL_S(0), true);
}
static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
{
- intel_dbuf_slice_set(dev_priv, DBUF_CTL, false);
+ intel_dbuf_slice_set(dev_priv, DBUF_CTL_S(0), false);
}
static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
@@ -4449,9 +4449,11 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
return;
if (req_slices > hw_enabled_slices)
- ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true);
+ ret = intel_dbuf_slice_set(dev_priv,
+ DBUF_CTL_S(DBUF_S2), true);
else
- ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false);
+ ret = intel_dbuf_slice_set(dev_priv,
+ DBUF_CTL_S(DBUF_S2), false);
if (ret)
dev_priv->enabled_dbuf_slices_num = req_slices;
@@ -4459,16 +4461,16 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
{
- intel_de_write(dev_priv, DBUF_CTL_S1,
- intel_de_read(dev_priv, DBUF_CTL_S1) | DBUF_POWER_REQUEST);
- intel_de_write(dev_priv, DBUF_CTL_S2,
- intel_de_read(dev_priv, DBUF_CTL_S2) | DBUF_POWER_REQUEST);
- intel_de_posting_read(dev_priv, DBUF_CTL_S2);
+ intel_de_write(dev_priv, DBUF_CTL_S(0),
+ intel_de_read(dev_priv, DBUF_CTL_S(0)) | DBUF_POWER_REQUEST);
+ intel_de_write(dev_priv, DBUF_CTL_S(1),
+ intel_de_read(dev_priv, DBUF_CTL_S(1)) | DBUF_POWER_REQUEST);
+ intel_de_posting_read(dev_priv, DBUF_CTL_S(1));
udelay(10);
- if (!(intel_de_read(dev_priv, DBUF_CTL_S1) & DBUF_POWER_STATE) ||
- !(intel_de_read(dev_priv, DBUF_CTL_S2) & DBUF_POWER_STATE))
+ if (!(intel_de_read(dev_priv, DBUF_CTL_S(0)) & DBUF_POWER_STATE) ||
+ !(intel_de_read(dev_priv, DBUF_CTL_S(1)) & DBUF_POWER_STATE))
drm_err(&dev_priv->drm, "DBuf power enable timeout\n");
else
/*
@@ -4480,16 +4482,16 @@ static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
{
- intel_de_write(dev_priv, DBUF_CTL_S1,
- intel_de_read(dev_priv, DBUF_CTL_S1) & ~DBUF_POWER_REQUEST);
- intel_de_write(dev_priv, DBUF_CTL_S2,
- intel_de_read(dev_priv, DBUF_CTL_S2) & ~DBUF_POWER_REQUEST);
- intel_de_posting_read(dev_priv, DBUF_CTL_S2);
+ intel_de_write(dev_priv, DBUF_CTL_S(0),
+ intel_de_read(dev_priv, DBUF_CTL_S(0)) & ~DBUF_POWER_REQUEST);
+ intel_de_write(dev_priv, DBUF_CTL_S(1),
+ intel_de_read(dev_priv, DBUF_CTL_S(1)) & ~DBUF_POWER_REQUEST);
+ intel_de_posting_read(dev_priv, DBUF_CTL_S(1));
udelay(10);
- if ((intel_de_read(dev_priv, DBUF_CTL_S1) & DBUF_POWER_STATE) ||
- (intel_de_read(dev_priv, DBUF_CTL_S2) & DBUF_POWER_STATE))
+ if ((intel_de_read(dev_priv, DBUF_CTL_S(0)) & DBUF_POWER_STATE) ||
+ (intel_de_read(dev_priv, DBUF_CTL_S(1)) & DBUF_POWER_STATE))
drm_err(&dev_priv->drm, "DBuf power disable timeout!\n");
else
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 2608a65af7fa..601e000ffd0d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -307,6 +307,11 @@ intel_display_power_put_async(struct drm_i915_private *i915,
}
#endif
+enum dbuf_slice {
+ DBUF_S1,
+ DBUF_S2,
+};
+
#define with_intel_display_power(i915, domain, wf) \
for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 18475dd377ed..ae6700dc9d73 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2902,7 +2902,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
- MMIO_DH(DBUF_CTL, D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
+ MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0bd431f6a011..dc206723f25e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7753,9 +7753,9 @@ enum {
#define DISP_ARB_CTL2 _MMIO(0x45004)
#define DISP_DATA_PARTITION_5_6 (1 << 6)
#define DISP_IPC_ENABLE (1 << 3)
-#define DBUF_CTL _MMIO(0x45008)
-#define DBUF_CTL_S1 _MMIO(0x45008)
-#define DBUF_CTL_S2 _MMIO(0x44FE8)
+#define _DBUF_CTL_S1 0x45008
+#define _DBUF_CTL_S2 0x44FE8
+#define DBUF_CTL_S(slice) _MMIO(_PICK_EVEN(slice, _DBUF_CTL_S1, _DBUF_CTL_S2))
#define DBUF_POWER_REQUEST (1 << 31)
#define DBUF_POWER_STATE (1 << 30)
#define GEN7_MSG_CTL _MMIO(0x45010)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 89aa188c8cf5..f9e00ca61302 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3613,7 +3613,7 @@ u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
* only that 1 slice enabled until we have a proper way for on-demand
* toggling of the second slice.
*/
- if (0 && I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
+ if (0 && I915_READ(DBUF_CTL_S(DBUF_S2)) & DBUF_POWER_STATE)
enabled_dbuf_slices_num++;
return enabled_dbuf_slices_num;
--
2.24.1.485.gad05a3d8e5
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread