From: Ville Syrjala <ville.syrjala@linux.intel.com> To: dri-devel@lists.freedesktop.org Cc: intel-gfx@lists.freedesktop.org Subject: [PATCH 18/26] drm/dp: Add drm_dp_downstream_mode() Date: Mon, 3 Feb 2020 17:13:35 +0200 [thread overview] Message-ID: <20200203151343.14378-19-ville.syrjala@linux.intel.com> (raw) In-Reply-To: <20200203151343.14378-1-ville.syrjala@linux.intel.com> From: Ville Syrjälä <ville.syrjala@linux.intel.com> The downstream facing port caps in the DPCD can give us a hint as to what kind of display mode the sink can use if it doesn't have an EDID. Use that information to pick a suitable mode. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 54 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/drm_edid.c | 21 +++++++++++++ include/drm/drm_dp_helper.h | 12 ++++++++ include/drm/drm_edid.h | 4 +++ 4 files changed, 91 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 31ca550467ed..507282dc79ac 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -615,6 +615,60 @@ int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], } EXPORT_SYMBOL(drm_dp_downstream_max_bpc); +/** + * drm_dp_downstream_mode() - return a mode for downstream facing port + * @dpcd: DisplayPort configuration data + * @port_cap: port capabilities + * + * Provides a suitable mode for downstream facing ports without EDID. + * + * Returns a new drm_display_mode on success or NULL on failure + */ +struct drm_display_mode * +drm_dp_downstream_mode(struct drm_device *dev, + const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4]) + +{ + u8 vic; + + if (!drm_dp_is_branch(dpcd)) + return NULL; + + if (dpcd[DP_DPCD_REV] < 0x11) + return NULL; + + switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { + case DP_DS_PORT_TYPE_NON_EDID: + switch (port_cap[0] & DP_DS_NON_EDID_MASK) { + case DP_DS_NON_EDID_720x480i_60: + vic = 6; + break; + case DP_DS_NON_EDID_720x480i_50: + vic = 21; + break; + case DP_DS_NON_EDID_1920x1080i_60: + vic = 5; + break; + case DP_DS_NON_EDID_1920x1080i_50: + vic = 20; + break; + case DP_DS_NON_EDID_1280x720_60: + vic = 4; + break; + case DP_DS_NON_EDID_1280x720_50: + vic = 19; + break; + default: + return NULL; + } + return drm_display_mode_from_cea_vic(dev, vic); + default: + return NULL; + } +} +EXPORT_SYMBOL(drm_dp_downstream_mode); + /** * drm_dp_downstream_id() - identify branch device * @aux: DisplayPort AUX channel diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 99769d6c9f84..4894a00b0711 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -3633,6 +3633,27 @@ drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) bitmap_set(hdmi->y420_cmdb_modes, vic, 1); } +struct drm_display_mode * +drm_display_mode_from_cea_vic(struct drm_device *dev, + u8 video_code) +{ + const struct drm_display_mode *cea_mode; + struct drm_display_mode *newmode; + + cea_mode = cea_mode_for_vic(video_code); + if (!cea_mode) + return NULL; + + newmode = drm_mode_duplicate(dev, cea_mode); + if (!newmode) + return NULL; + + newmode->vrefresh = 0; + + return newmode; +} +EXPORT_SYMBOL(drm_display_mode_from_cea_vic); + static int do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) { diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 89683a3a9af1..be4a5ffe4252 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -27,6 +27,8 @@ #include <linux/i2c.h> #include <linux/types.h> +struct drm_device; + /* * Unless otherwise noted, all values are from the DP 1.1a spec. Note that * DP and DPCD versions are independent. Differences from 1.0 are not noted, @@ -384,6 +386,13 @@ # define DP_DS_PORT_TYPE_DP_DUALMODE 5 # define DP_DS_PORT_TYPE_WIRELESS 6 # define DP_DS_PORT_HPD (1 << 3) +# define DP_DS_NON_EDID_MASK (0xf << 4) +# define DP_DS_NON_EDID_720x480i_60 (1 << 4) +# define DP_DS_NON_EDID_720x480i_50 (2 << 4) +# define DP_DS_NON_EDID_1920x1080i_60 (3 << 4) +# define DP_DS_NON_EDID_1920x1080i_50 (4 << 4) +# define DP_DS_NON_EDID_1280x720_60 (5 << 4) +# define DP_DS_NON_EDID_1280x720_50 (7 << 4) /* offset 1 for VGA is maximum megapixels per second / 8 */ /* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */ /* offset 2 for VGA/DVI/HDMI */ @@ -1491,6 +1500,9 @@ int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], const struct edid *edid); +struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev, + const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4]); int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]); void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE], diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index f0b03d401c27..cb1be3f5840a 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -503,4 +503,8 @@ void drm_edid_get_monitor_name(struct edid *edid, char *name, struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, int hsize, int vsize, int fresh, bool rb); +struct drm_display_mode * +drm_display_mode_from_cea_vic(struct drm_device *dev, + u8 video_code); + #endif /* __DRM_EDID_H__ */ -- 2.24.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Ville Syrjala <ville.syrjala@linux.intel.com> To: dri-devel@lists.freedesktop.org Cc: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 18/26] drm/dp: Add drm_dp_downstream_mode() Date: Mon, 3 Feb 2020 17:13:35 +0200 [thread overview] Message-ID: <20200203151343.14378-19-ville.syrjala@linux.intel.com> (raw) In-Reply-To: <20200203151343.14378-1-ville.syrjala@linux.intel.com> From: Ville Syrjälä <ville.syrjala@linux.intel.com> The downstream facing port caps in the DPCD can give us a hint as to what kind of display mode the sink can use if it doesn't have an EDID. Use that information to pick a suitable mode. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 54 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/drm_edid.c | 21 +++++++++++++ include/drm/drm_dp_helper.h | 12 ++++++++ include/drm/drm_edid.h | 4 +++ 4 files changed, 91 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 31ca550467ed..507282dc79ac 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -615,6 +615,60 @@ int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], } EXPORT_SYMBOL(drm_dp_downstream_max_bpc); +/** + * drm_dp_downstream_mode() - return a mode for downstream facing port + * @dpcd: DisplayPort configuration data + * @port_cap: port capabilities + * + * Provides a suitable mode for downstream facing ports without EDID. + * + * Returns a new drm_display_mode on success or NULL on failure + */ +struct drm_display_mode * +drm_dp_downstream_mode(struct drm_device *dev, + const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4]) + +{ + u8 vic; + + if (!drm_dp_is_branch(dpcd)) + return NULL; + + if (dpcd[DP_DPCD_REV] < 0x11) + return NULL; + + switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { + case DP_DS_PORT_TYPE_NON_EDID: + switch (port_cap[0] & DP_DS_NON_EDID_MASK) { + case DP_DS_NON_EDID_720x480i_60: + vic = 6; + break; + case DP_DS_NON_EDID_720x480i_50: + vic = 21; + break; + case DP_DS_NON_EDID_1920x1080i_60: + vic = 5; + break; + case DP_DS_NON_EDID_1920x1080i_50: + vic = 20; + break; + case DP_DS_NON_EDID_1280x720_60: + vic = 4; + break; + case DP_DS_NON_EDID_1280x720_50: + vic = 19; + break; + default: + return NULL; + } + return drm_display_mode_from_cea_vic(dev, vic); + default: + return NULL; + } +} +EXPORT_SYMBOL(drm_dp_downstream_mode); + /** * drm_dp_downstream_id() - identify branch device * @aux: DisplayPort AUX channel diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 99769d6c9f84..4894a00b0711 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -3633,6 +3633,27 @@ drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) bitmap_set(hdmi->y420_cmdb_modes, vic, 1); } +struct drm_display_mode * +drm_display_mode_from_cea_vic(struct drm_device *dev, + u8 video_code) +{ + const struct drm_display_mode *cea_mode; + struct drm_display_mode *newmode; + + cea_mode = cea_mode_for_vic(video_code); + if (!cea_mode) + return NULL; + + newmode = drm_mode_duplicate(dev, cea_mode); + if (!newmode) + return NULL; + + newmode->vrefresh = 0; + + return newmode; +} +EXPORT_SYMBOL(drm_display_mode_from_cea_vic); + static int do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) { diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 89683a3a9af1..be4a5ffe4252 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -27,6 +27,8 @@ #include <linux/i2c.h> #include <linux/types.h> +struct drm_device; + /* * Unless otherwise noted, all values are from the DP 1.1a spec. Note that * DP and DPCD versions are independent. Differences from 1.0 are not noted, @@ -384,6 +386,13 @@ # define DP_DS_PORT_TYPE_DP_DUALMODE 5 # define DP_DS_PORT_TYPE_WIRELESS 6 # define DP_DS_PORT_HPD (1 << 3) +# define DP_DS_NON_EDID_MASK (0xf << 4) +# define DP_DS_NON_EDID_720x480i_60 (1 << 4) +# define DP_DS_NON_EDID_720x480i_50 (2 << 4) +# define DP_DS_NON_EDID_1920x1080i_60 (3 << 4) +# define DP_DS_NON_EDID_1920x1080i_50 (4 << 4) +# define DP_DS_NON_EDID_1280x720_60 (5 << 4) +# define DP_DS_NON_EDID_1280x720_50 (7 << 4) /* offset 1 for VGA is maximum megapixels per second / 8 */ /* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */ /* offset 2 for VGA/DVI/HDMI */ @@ -1491,6 +1500,9 @@ int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], const struct edid *edid); +struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev, + const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4]); int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]); void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE], diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index f0b03d401c27..cb1be3f5840a 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -503,4 +503,8 @@ void drm_edid_get_monitor_name(struct edid *edid, char *name, struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, int hsize, int vsize, int fresh, bool rb); +struct drm_display_mode * +drm_display_mode_from_cea_vic(struct drm_device *dev, + u8 video_code); + #endif /* __DRM_EDID_H__ */ -- 2.24.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-02-03 15:14 UTC|newest] Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-02-03 15:13 [PATCH 00/26] drm/i915: Pimp DP DFP handling Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 01/26] drm/i915: Nuke pre-production GLK HDMI w/a 1139 Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 02/26] drm/i915: Limit display Wa_1405510057 to gen11 Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 03/26] drm/i915: Drop WaDDIIOTimeout:glk Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 04/26] drm/i915: Add glk to intel_detect_preproduction_hw() Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 05/26] drm/dp: Include the AUX CH name in the debug messages Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 06/26] drm/i915/lspcon: Do not send infoframes to non-HDMI sinks Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 07/26] drm/dp: Define protocol converter DPCD registers Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 08/26] drm/dp: Define more downstream facing port caps Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 09/26] drm/i915: Reworkd DFP max bpc handling Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 10/26] drm/dp: Add helpers to identify downstream facing port types Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 11/26] drm/dp: Pimp drm_dp_downstream_max_bpc() Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 12/26] drm/dp: Redo drm_dp_downstream_max_clock() as drm_dp_downstream_max_dotclock() Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 13/26] drm/i915: Reworkd DP DFP clock handling Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 14/26] drm/i915: Dump downstream facing port caps Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 15/26] drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock() Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] [PATCH 15/26] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Ville Syrjala 2020-02-03 15:13 ` [PATCH 16/26] drm/i915: Deal with TMDS DFP clock limits Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 17/26] drm/i915: Configure DP 1.3+ protocol converted HDMI mode Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` Ville Syrjala [this message] 2020-02-03 15:13 ` [Intel-gfx] [PATCH 18/26] drm/dp: Add drm_dp_downstream_mode() Ville Syrjala 2020-02-03 15:13 ` [PATCH 19/26] drm/i915: Handle downstream facing ports w/o EDID Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 20/26] drm/i915: Extract intel_hdmi_has_audio() Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 21/26] drm/i915: DP->HDMI TMDS clock limits vs. deep color Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 22/26] drm/dp: Add helpers for DFP YCbCr 4:2:0 handling Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 23/26] drm/i915: Do YCbCr 444->420 conversion via DP protocol converters Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 24/26] drm/i915: Decouple DP++ from the HDMI code Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 25/26] drm/i915: Try to probe DP++ dongles on DP++ downstream facing ports Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 26/26] drm/i915: Try to frob the TMDS buffer enable knob on DP++ dongles on DP DFPs Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-04 19:20 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Pimp DP DFP handling Patchwork
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