From: Ville Syrjala <ville.syrjala@linux.intel.com> To: dri-devel@lists.freedesktop.org Cc: intel-gfx@lists.freedesktop.org Subject: [PATCH 26/26] drm/i915: Try to frob the TMDS buffer enable knob on DP++ dongles on DP DFPs Date: Mon, 3 Feb 2020 17:13:43 +0200 [thread overview] Message-ID: <20200203151343.14378-27-ville.syrjala@linux.intel.com> (raw) In-Reply-To: <20200203151343.14378-1-ville.syrjala@linux.intel.com> From: Ville Syrjälä <ville.syrjala@linux.intel.com> To save a bit of power let's try to power down the TMDS buffers on DP++ dongles hooked to downstream facing DP++ ports. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++++ drivers/gpu/drm/i915/display/intel_dp.c | 25 ++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 92c280905f31..5daa52909980 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3512,6 +3512,9 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder, else WARN_ON(is_mst && port == PORT_A); + intel_dp_dual_mode_set_tmds_output(encoder, + &intel_dp->dp_dual_mode, true); + intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count, is_mst); @@ -3757,6 +3760,9 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, dig_port->ddi_io_power_domain); intel_ddi_clk_disable(encoder); + + intel_dp_dual_mode_set_tmds_output(encoder, + &intel_dp->dp_dual_mode, false); } static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 5143c1b0fd92..0452cc9423e6 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3510,19 +3510,28 @@ static void g4x_post_disable_dp(struct intel_encoder *encoder, /* Only ilk+ has port A */ if (port == PORT_A) ilk_edp_pll_off(intel_dp, old_crtc_state); + + intel_dp_dual_mode_set_tmds_output(encoder, + &intel_dp->dp_dual_mode, false); } static void vlv_post_disable_dp(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + intel_dp_link_down(encoder, old_crtc_state); + + intel_dp_dual_mode_set_tmds_output(encoder, + &intel_dp->dp_dual_mode, false); } static void chv_post_disable_dp(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); intel_dp_link_down(encoder, old_crtc_state); @@ -3533,6 +3542,9 @@ static void chv_post_disable_dp(struct intel_encoder *encoder, chv_data_lane_soft_reset(encoder, old_crtc_state, true); vlv_dpio_put(dev_priv); + + intel_dp_dual_mode_set_tmds_output(encoder, + &intel_dp->dp_dual_mode, false); } static void @@ -3748,6 +3760,9 @@ static void g4x_pre_enable_dp(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); enum port port = encoder->port; + intel_dp_dual_mode_set_tmds_output(encoder, + &intel_dp->dp_dual_mode, true); + intel_dp_prepare(encoder, pipe_config); /* Only ilk+ has port A */ @@ -3865,6 +3880,11 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + intel_dp_dual_mode_set_tmds_output(encoder, + &intel_dp->dp_dual_mode, true); + vlv_phy_pre_encoder_enable(encoder, pipe_config); intel_enable_dp(encoder, pipe_config, conn_state); @@ -3883,6 +3903,11 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + intel_dp_dual_mode_set_tmds_output(encoder, + &intel_dp->dp_dual_mode, true); + chv_phy_pre_encoder_enable(encoder, pipe_config); intel_enable_dp(encoder, pipe_config, conn_state); -- 2.24.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Ville Syrjala <ville.syrjala@linux.intel.com> To: dri-devel@lists.freedesktop.org Cc: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 26/26] drm/i915: Try to frob the TMDS buffer enable knob on DP++ dongles on DP DFPs Date: Mon, 3 Feb 2020 17:13:43 +0200 [thread overview] Message-ID: <20200203151343.14378-27-ville.syrjala@linux.intel.com> (raw) In-Reply-To: <20200203151343.14378-1-ville.syrjala@linux.intel.com> From: Ville Syrjälä <ville.syrjala@linux.intel.com> To save a bit of power let's try to power down the TMDS buffers on DP++ dongles hooked to downstream facing DP++ ports. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++++ drivers/gpu/drm/i915/display/intel_dp.c | 25 ++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 92c280905f31..5daa52909980 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3512,6 +3512,9 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder, else WARN_ON(is_mst && port == PORT_A); + intel_dp_dual_mode_set_tmds_output(encoder, + &intel_dp->dp_dual_mode, true); + intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count, is_mst); @@ -3757,6 +3760,9 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, dig_port->ddi_io_power_domain); intel_ddi_clk_disable(encoder); + + intel_dp_dual_mode_set_tmds_output(encoder, + &intel_dp->dp_dual_mode, false); } static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 5143c1b0fd92..0452cc9423e6 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3510,19 +3510,28 @@ static void g4x_post_disable_dp(struct intel_encoder *encoder, /* Only ilk+ has port A */ if (port == PORT_A) ilk_edp_pll_off(intel_dp, old_crtc_state); + + intel_dp_dual_mode_set_tmds_output(encoder, + &intel_dp->dp_dual_mode, false); } static void vlv_post_disable_dp(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + intel_dp_link_down(encoder, old_crtc_state); + + intel_dp_dual_mode_set_tmds_output(encoder, + &intel_dp->dp_dual_mode, false); } static void chv_post_disable_dp(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); intel_dp_link_down(encoder, old_crtc_state); @@ -3533,6 +3542,9 @@ static void chv_post_disable_dp(struct intel_encoder *encoder, chv_data_lane_soft_reset(encoder, old_crtc_state, true); vlv_dpio_put(dev_priv); + + intel_dp_dual_mode_set_tmds_output(encoder, + &intel_dp->dp_dual_mode, false); } static void @@ -3748,6 +3760,9 @@ static void g4x_pre_enable_dp(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); enum port port = encoder->port; + intel_dp_dual_mode_set_tmds_output(encoder, + &intel_dp->dp_dual_mode, true); + intel_dp_prepare(encoder, pipe_config); /* Only ilk+ has port A */ @@ -3865,6 +3880,11 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + intel_dp_dual_mode_set_tmds_output(encoder, + &intel_dp->dp_dual_mode, true); + vlv_phy_pre_encoder_enable(encoder, pipe_config); intel_enable_dp(encoder, pipe_config, conn_state); @@ -3883,6 +3903,11 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + intel_dp_dual_mode_set_tmds_output(encoder, + &intel_dp->dp_dual_mode, true); + chv_phy_pre_encoder_enable(encoder, pipe_config); intel_enable_dp(encoder, pipe_config, conn_state); -- 2.24.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-02-03 15:15 UTC|newest] Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-02-03 15:13 [PATCH 00/26] drm/i915: Pimp DP DFP handling Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 01/26] drm/i915: Nuke pre-production GLK HDMI w/a 1139 Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 02/26] drm/i915: Limit display Wa_1405510057 to gen11 Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 03/26] drm/i915: Drop WaDDIIOTimeout:glk Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 04/26] drm/i915: Add glk to intel_detect_preproduction_hw() Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 05/26] drm/dp: Include the AUX CH name in the debug messages Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 06/26] drm/i915/lspcon: Do not send infoframes to non-HDMI sinks Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 07/26] drm/dp: Define protocol converter DPCD registers Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 08/26] drm/dp: Define more downstream facing port caps Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 09/26] drm/i915: Reworkd DFP max bpc handling Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 10/26] drm/dp: Add helpers to identify downstream facing port types Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 11/26] drm/dp: Pimp drm_dp_downstream_max_bpc() Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 12/26] drm/dp: Redo drm_dp_downstream_max_clock() as drm_dp_downstream_max_dotclock() Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 13/26] drm/i915: Reworkd DP DFP clock handling Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 14/26] drm/i915: Dump downstream facing port caps Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 15/26] drm/dp: Add drm_dp_downstream_{min,max}_tmds_clock() Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] [PATCH 15/26] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Ville Syrjala 2020-02-03 15:13 ` [PATCH 16/26] drm/i915: Deal with TMDS DFP clock limits Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 17/26] drm/i915: Configure DP 1.3+ protocol converted HDMI mode Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 18/26] drm/dp: Add drm_dp_downstream_mode() Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 19/26] drm/i915: Handle downstream facing ports w/o EDID Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 20/26] drm/i915: Extract intel_hdmi_has_audio() Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 21/26] drm/i915: DP->HDMI TMDS clock limits vs. deep color Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 22/26] drm/dp: Add helpers for DFP YCbCr 4:2:0 handling Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 23/26] drm/i915: Do YCbCr 444->420 conversion via DP protocol converters Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 24/26] drm/i915: Decouple DP++ from the HDMI code Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` [PATCH 25/26] drm/i915: Try to probe DP++ dongles on DP++ downstream facing ports Ville Syrjala 2020-02-03 15:13 ` [Intel-gfx] " Ville Syrjala 2020-02-03 15:13 ` Ville Syrjala [this message] 2020-02-03 15:13 ` [Intel-gfx] [PATCH 26/26] drm/i915: Try to frob the TMDS buffer enable knob on DP++ dongles on DP DFPs Ville Syrjala 2020-02-04 19:20 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Pimp DP DFP handling Patchwork
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