* [PULL] u-boot-socfpga/master
@ 2020-02-02 17:18 Marek Vasut
2020-02-02 20:26 ` Tom Rini
0 siblings, 1 reply; 27+ messages in thread
From: Marek Vasut @ 2020-02-02 17:18 UTC (permalink / raw)
To: u-boot
The following changes since commit 80e99adbe47d1c8590f9b971ac52257fdc51a5ec:
Merge tag 'uniphier-v2020.04-2' of
https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier (2020-01-31
13:26:28 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to 56c24875d92adcf214d97f5798e11c1b7b5e27fa:
ddr: altera: Add DDR2 support to Gen5 driver (2020-02-02 18:18:05 +0100)
----------------------------------------------------------------
Ley Foon Tan (1):
reset: socfpga: Poll for reset status after deassert reset
Marek Vasut (5):
ARM: socfpga: Drop last use of socfpga_reset_manager
watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig
watchdog: designware: Convert to DM and DT probing
watchdog: designware: Optionally fetch clock and reset from DT
ddr: altera: Add DDR2 support to Gen5 driver
arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 4 ++
arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 4 ++
arch/arm/mach-socfpga/include/mach/sdram_gen5.h | 46
+++++++++++++++----
arch/arm/mach-socfpga/qts-filter.sh | 2 +-
arch/arm/mach-socfpga/spl_gen5.c | 5 +--
arch/arm/mach-socfpga/wrap_sdram_config.c | 64
+++++++++++++++++---------
configs/socfpga_stratix10_defconfig | 3 ++
configs/socfpga_vining_fpga_defconfig | 2 +
drivers/ddr/altera/sdram_gen5.c | 6 ++-
drivers/ddr/altera/sequencer.c | 193
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++---------------
drivers/ddr/altera/sequencer.h | 1 +
drivers/reset/reset-socfpga.c | 6 ++-
drivers/watchdog/Kconfig | 7 +++
drivers/watchdog/designware_wdt.c | 150
+++++++++++++++++++++++++++++++++++++++++++++++++++----------
include/configs/socfpga_common.h | 3 --
include/configs/socfpga_soc64_common.h | 7 ++-
scripts/config_whitelist.txt | 1 -
17 files changed, 399 insertions(+), 105 deletions(-)
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL] u-boot-socfpga/master
2020-02-02 17:18 [PULL] u-boot-socfpga/master Marek Vasut
@ 2020-02-02 20:26 ` Tom Rini
2020-02-03 8:24 ` Marek Vasut
0 siblings, 1 reply; 27+ messages in thread
From: Tom Rini @ 2020-02-02 20:26 UTC (permalink / raw)
To: u-boot
On Sun, Feb 02, 2020 at 06:18:53PM +0100, Marek Vasut wrote:
> The following changes since commit 80e99adbe47d1c8590f9b971ac52257fdc51a5ec:
>
> Merge tag 'uniphier-v2020.04-2' of
> https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier (2020-01-31
> 13:26:28 -0500)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-socfpga.git master
>
> for you to fetch changes up to 56c24875d92adcf214d97f5798e11c1b7b5e27fa:
>
> ddr: altera: Add DDR2 support to Gen5 driver (2020-02-02 18:18:05 +0100)
>
A see a ton of failures:
aarch64: + socfpga_agilex
arm: + socfpga_is1 socfpga_cyclone5 socfpga_de10_nano socfpga_mcvevk socfpga_dbm_soc1 socfpga_arria5 socfpga_de1_soc socfpga_sr1500 socfpga_socrates socfpga_sockit socfpga_vining_fpga socfpga_de0_nano_soc
Thanks!
--
Tom
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* [PULL] u-boot-socfpga/master
2020-02-02 20:26 ` Tom Rini
@ 2020-02-03 8:24 ` Marek Vasut
2020-02-03 8:47 ` Marek Vasut
0 siblings, 1 reply; 27+ messages in thread
From: Marek Vasut @ 2020-02-03 8:24 UTC (permalink / raw)
To: u-boot
On 2/2/20 9:26 PM, Tom Rini wrote:
> On Sun, Feb 02, 2020 at 06:18:53PM +0100, Marek Vasut wrote:
>
>> The following changes since commit 80e99adbe47d1c8590f9b971ac52257fdc51a5ec:
>>
>> Merge tag 'uniphier-v2020.04-2' of
>> https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier (2020-01-31
>> 13:26:28 -0500)
>>
>> are available in the Git repository at:
>>
>> git://git.denx.de/u-boot-socfpga.git master
>>
>> for you to fetch changes up to 56c24875d92adcf214d97f5798e11c1b7b5e27fa:
>>
>> ddr: altera: Add DDR2 support to Gen5 driver (2020-02-02 18:18:05 +0100)
>>
>
> A see a ton of failures:
> aarch64: + socfpga_agilex
> arm: + socfpga_is1 socfpga_cyclone5 socfpga_de10_nano socfpga_mcvevk socfpga_dbm_soc1 socfpga_arria5 socfpga_de1_soc socfpga_sr1500 socfpga_socrates socfpga_sockit socfpga_vining_fpga socfpga_de0_nano_soc
I don't see those failures locally.
> Thanks!
Thanks!
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL] u-boot-socfpga/master
2020-02-03 8:24 ` Marek Vasut
@ 2020-02-03 8:47 ` Marek Vasut
2020-02-04 4:13 ` Tom Rini
0 siblings, 1 reply; 27+ messages in thread
From: Marek Vasut @ 2020-02-03 8:47 UTC (permalink / raw)
To: u-boot
On 2/3/20 9:24 AM, Marek Vasut wrote:
> On 2/2/20 9:26 PM, Tom Rini wrote:
>> On Sun, Feb 02, 2020 at 06:18:53PM +0100, Marek Vasut wrote:
>>
>>> The following changes since commit 80e99adbe47d1c8590f9b971ac52257fdc51a5ec:
>>>
>>> Merge tag 'uniphier-v2020.04-2' of
>>> https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier (2020-01-31
>>> 13:26:28 -0500)
>>>
>>> are available in the Git repository at:
>>>
>>> git://git.denx.de/u-boot-socfpga.git master
>>>
>>> for you to fetch changes up to 56c24875d92adcf214d97f5798e11c1b7b5e27fa:
>>>
>>> ddr: altera: Add DDR2 support to Gen5 driver (2020-02-02 18:18:05 +0100)
>>>
>>
>> A see a ton of failures:
>> aarch64: + socfpga_agilex
OK, this one I see, let's add this patch
diff --git a/include/configs/socfpga_soc64_common.h
b/include/configs/socfpga_soc64_common.h
index da81137e84..87c73457a0 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -150,10 +150,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
/*
* L4 Watchdog
*/
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_WATCHDOG
-#define CONFIG_HW_WATCHDOG
-#else
+#ifndef CONFIG_SPL_BUILD
#undef CONFIG_HW_WATCHDOG
#undef CONFIG_DESIGNWARE_WATCHDOG
#endif
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PULL] u-boot-socfpga/master
2020-02-03 8:47 ` Marek Vasut
@ 2020-02-04 4:13 ` Tom Rini
2020-02-05 6:58 ` Marek Vasut
0 siblings, 1 reply; 27+ messages in thread
From: Tom Rini @ 2020-02-04 4:13 UTC (permalink / raw)
To: u-boot
On Mon, Feb 03, 2020 at 09:47:04AM +0100, Marek Vasut wrote:
> On 2/3/20 9:24 AM, Marek Vasut wrote:
> > On 2/2/20 9:26 PM, Tom Rini wrote:
> >> On Sun, Feb 02, 2020 at 06:18:53PM +0100, Marek Vasut wrote:
> >>
> >>> The following changes since commit 80e99adbe47d1c8590f9b971ac52257fdc51a5ec:
> >>>
> >>> Merge tag 'uniphier-v2020.04-2' of
> >>> https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier (2020-01-31
> >>> 13:26:28 -0500)
> >>>
> >>> are available in the Git repository at:
> >>>
> >>> git://git.denx.de/u-boot-socfpga.git master
> >>>
> >>> for you to fetch changes up to 56c24875d92adcf214d97f5798e11c1b7b5e27fa:
> >>>
> >>> ddr: altera: Add DDR2 support to Gen5 driver (2020-02-02 18:18:05 +0100)
> >>>
> >>
> >> A see a ton of failures:
> >> aarch64: + socfpga_agilex
>
> OK, this one I see, let's add this patch
>
> diff --git a/include/configs/socfpga_soc64_common.h
> b/include/configs/socfpga_soc64_common.h
> index da81137e84..87c73457a0 100644
> --- a/include/configs/socfpga_soc64_common.h
> +++ b/include/configs/socfpga_soc64_common.h
> @@ -150,10 +150,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
> /*
> * L4 Watchdog
> */
> -#ifdef CONFIG_SPL_BUILD
> -#undef CONFIG_WATCHDOG
> -#define CONFIG_HW_WATCHDOG
> -#else
> +#ifndef CONFIG_SPL_BUILD
> #undef CONFIG_HW_WATCHDOG
> #undef CONFIG_DESIGNWARE_WATCHDOG
> #endif
To be clear, I'm expecting a new PR, thanks.
--
Tom
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* [PULL] u-boot-socfpga/master
2020-02-04 4:13 ` Tom Rini
@ 2020-02-05 6:58 ` Marek Vasut
2020-02-07 18:51 ` Tom Rini
0 siblings, 1 reply; 27+ messages in thread
From: Marek Vasut @ 2020-02-05 6:58 UTC (permalink / raw)
To: u-boot
The following changes since commit 31a790bee939e227dfc7e6a6a323b2b13180707f:
Merge branch 'master' of git://git.denx.de/u-boot-usb (2020-02-02
15:26:53 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to 9a5a90ad9b3234c4739427cbe11219c51f0e9bd1:
ddr: altera: Add DDR2 support to Gen5 driver (2020-02-05 03:01:57 +0100)
----------------------------------------------------------------
Ley Foon Tan (1):
reset: socfpga: Poll for reset status after deassert reset
Marek Vasut (5):
ARM: socfpga: Drop last use of socfpga_reset_manager
watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig
watchdog: designware: Convert to DM and DT probing
watchdog: designware: Optionally fetch clock and reset from DT
ddr: altera: Add DDR2 support to Gen5 driver
arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 4 ++
arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 4 ++
arch/arm/mach-socfpga/include/mach/sdram_gen5.h | 46
+++++++++++++++----
arch/arm/mach-socfpga/qts-filter.sh | 2 +-
arch/arm/mach-socfpga/spl_gen5.c | 5 +--
arch/arm/mach-socfpga/wrap_sdram_config.c | 64
+++++++++++++++++---------
configs/socfpga_stratix10_defconfig | 2 +
configs/socfpga_vining_fpga_defconfig | 3 +-
drivers/ddr/altera/sdram_gen5.c | 6 ++-
drivers/ddr/altera/sequencer.c | 194
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++---------------
drivers/ddr/altera/sequencer.h | 1 +
drivers/reset/reset-socfpga.c | 6 ++-
drivers/watchdog/Kconfig | 7 +++
drivers/watchdog/designware_wdt.c | 150
+++++++++++++++++++++++++++++++++++++++++++++++++++----------
include/configs/socfpga_common.h | 3 --
include/configs/socfpga_soc64_common.h | 8 ++--
scripts/config_whitelist.txt | 1 -
17 files changed, 398 insertions(+), 108 deletions(-)
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL] u-boot-socfpga/master
2020-02-05 6:58 ` Marek Vasut
@ 2020-02-07 18:51 ` Tom Rini
0 siblings, 0 replies; 27+ messages in thread
From: Tom Rini @ 2020-02-07 18:51 UTC (permalink / raw)
To: u-boot
On Wed, Feb 05, 2020 at 07:58:12AM +0100, Marek Vasut wrote:
> The following changes since commit 31a790bee939e227dfc7e6a6a323b2b13180707f:
>
> Merge branch 'master' of git://git.denx.de/u-boot-usb (2020-02-02
> 15:26:53 -0500)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-socfpga.git master
>
> for you to fetch changes up to 9a5a90ad9b3234c4739427cbe11219c51f0e9bd1:
>
> ddr: altera: Add DDR2 support to Gen5 driver (2020-02-05 03:01:57 +0100)
>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PULL] u-boot-socfpga/master
2023-02-22 1:04 Marek Vasut
@ 2023-02-22 22:51 ` Tom Rini
0 siblings, 0 replies; 27+ messages in thread
From: Tom Rini @ 2023-02-22 22:51 UTC (permalink / raw)
To: Marek Vasut; +Cc: u-boot, Paweł Anikiel
[-- Attachment #1: Type: text/plain, Size: 595 bytes --]
On Wed, Feb 22, 2023 at 02:04:43AM +0100, Marek Vasut wrote:
> The following changes since commit 4eb7c5030d3f3c707c02a64dc8ea90de3da89928:
>
> Merge tag 'efi-2023-04-rc3' of
> https://source.denx.de/u-boot/custodians/u-boot-efi (2023-02-19 17:03:30
> -0500)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-socfpga.git master
>
> for you to fetch changes up to 52b8fca7178afdcacb31cfcdfea9429779d084a1:
>
> chameleonv3: Convert CONFIG_SPL_MAX_SIZE to Kconfig (2023-02-22 00:28:39
> +0100)
>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL] u-boot-socfpga/master
@ 2023-02-22 1:04 Marek Vasut
2023-02-22 22:51 ` Tom Rini
0 siblings, 1 reply; 27+ messages in thread
From: Marek Vasut @ 2023-02-22 1:04 UTC (permalink / raw)
To: Tom Rini, u-boot, Paweł Anikiel
The following changes since commit 4eb7c5030d3f3c707c02a64dc8ea90de3da89928:
Merge tag 'efi-2023-04-rc3' of
https://source.denx.de/u-boot/custodians/u-boot-efi (2023-02-19 17:03:30
-0500)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to 52b8fca7178afdcacb31cfcdfea9429779d084a1:
chameleonv3: Convert CONFIG_SPL_MAX_SIZE to Kconfig (2023-02-22
00:28:39 +0100)
----------------------------------------------------------------
Paweł Anikiel (6):
socfpga: chameleonv3: Enable ext4 in SPL
socfpga: chameleonv3: Move environment to a text file
arm: dts: chameleonv3: Override chameleonv3 bitstream names
arm: dts: chameleonv3: Rename chameleonv3.dts to .dtsi
arm: dts: chameleonv3: Add 270-2 variant
chameleonv3: Convert CONFIG_SPL_MAX_SIZE to Kconfig
arch/arm/dts/Makefile
| 1 +
arch/arm/dts/{socfpga_arria10_chameleonv3.dts =>
socfpga_arria10_chameleonv3.dtsi} | 0
arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
| 12 ++++++++++++
arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
| 5 +++++
arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
| 4 ++++
arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
| 2 +-
arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
| 4 ++++
arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts
| 2 +-
board/google/chameleonv3/environment.txt
| 13 +++++++++++++
configs/socfpga_chameleonv3_defconfig
| 2 ++
include/configs/socfpga_chameleonv3.h
| 9 ++++-----
11 files changed, 47 insertions(+), 7 deletions(-)
rename arch/arm/dts/{socfpga_arria10_chameleonv3.dts =>
socfpga_arria10_chameleonv3.dtsi} (100%)
create mode 100644
arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
create mode 100644 board/google/chameleonv3/environment.txt
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PULL] u-boot-socfpga/master
2022-05-23 21:50 Marek Vasut
@ 2022-05-24 15:51 ` Tom Rini
0 siblings, 0 replies; 27+ messages in thread
From: Tom Rini @ 2022-05-24 15:51 UTC (permalink / raw)
To: Marek Vasut; +Cc: u-boot
[-- Attachment #1: Type: text/plain, Size: 539 bytes --]
On Mon, May 23, 2022 at 11:50:15PM +0200, Marek Vasut wrote:
> The following changes since commit c0a1409d21e7b342566dccb9cc1d38209aabc5ff:
>
> configs: Resync with savedefconfig (2022-05-23 13:56:21 -0400)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-socfpga.git master
>
> for you to fetch changes up to 1b05136a6ca8387175ca7bf1aa66a9c40a153cc2:
>
> arm: socfpga: Add the terasic de10-standard board (2022-05-23 21:28:07
> +0200)
>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL] u-boot-socfpga/master
@ 2022-05-23 21:50 Marek Vasut
2022-05-24 15:51 ` Tom Rini
0 siblings, 1 reply; 27+ messages in thread
From: Marek Vasut @ 2022-05-23 21:50 UTC (permalink / raw)
To: Tom Rini, u-boot
The following changes since commit c0a1409d21e7b342566dccb9cc1d38209aabc5ff:
configs: Resync with savedefconfig (2022-05-23 13:56:21 -0400)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to 1b05136a6ca8387175ca7bf1aa66a9c40a153cc2:
arm: socfpga: Add the terasic de10-standard board (2022-05-23
21:28:07 +0200)
----------------------------------------------------------------
Humberto Naves (1):
arm: socfpga: Add the terasic de10-standard board
arch/arm/dts/socfpga_cyclone5_de10_standard.dts | 86 +++++++++++
arch/arm/mach-socfpga/Kconfig | 7 +
board/terasic/de10-standard/MAINTAINERS | 5 +
board/terasic/de10-standard/Makefile | 6 +
board/terasic/de10-standard/qts/iocsr_config.h | 659
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
board/terasic/de10-standard/qts/pinmux_config.h | 218
++++++++++++++++++++++++++++
board/terasic/de10-standard/qts/pll_config.h | 84 +++++++++++
board/terasic/de10-standard/qts/sdram_config.h | 344
++++++++++++++++++++++++++++++++++++++++++++
board/terasic/de10-standard/socfpga.c | 5 +
configs/socfpga_de10_standard_defconfig | 66 +++++++++
include/configs/socfpga_de10_standard.h | 18 +++
11 files changed, 1498 insertions(+)
create mode 100644 arch/arm/dts/socfpga_cyclone5_de10_standard.dts
create mode 100644 board/terasic/de10-standard/MAINTAINERS
create mode 100644 board/terasic/de10-standard/Makefile
create mode 100644 board/terasic/de10-standard/qts/iocsr_config.h
create mode 100644 board/terasic/de10-standard/qts/pinmux_config.h
create mode 100644 board/terasic/de10-standard/qts/pll_config.h
create mode 100644 board/terasic/de10-standard/qts/sdram_config.h
create mode 100644 board/terasic/de10-standard/socfpga.c
create mode 100644 configs/socfpga_de10_standard_defconfig
create mode 100644 include/configs/socfpga_de10_standard.h
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PULL] u-boot-socfpga/master
2022-03-28 20:05 Marek Vasut
@ 2022-03-28 21:04 ` Tom Rini
0 siblings, 0 replies; 27+ messages in thread
From: Tom Rini @ 2022-03-28 21:04 UTC (permalink / raw)
To: Marek Vasut; +Cc: u-boot
[-- Attachment #1: Type: text/plain, Size: 567 bytes --]
On Mon, Mar 28, 2022 at 10:05:39PM +0200, Marek Vasut wrote:
> One-liner env fix below.
>
> The following changes since commit e893e8ea6a5d3af312747d00f93587559193a426:
>
> Prepare v2022.04-rc5 (2022-03-28 10:14:51 -0400)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-socfpga.git master
>
> for you to fetch changes up to 25cff0c1fa83e149e4693121f8b5e287659eed71:
>
> arm: socfpga: vining: Fix mtdparts for 2x256 MiB SF variant (2022-03-28
> 21:49:03 +0200)
>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL] u-boot-socfpga/master
@ 2022-03-28 20:05 Marek Vasut
2022-03-28 21:04 ` Tom Rini
0 siblings, 1 reply; 27+ messages in thread
From: Marek Vasut @ 2022-03-28 20:05 UTC (permalink / raw)
To: Tom Rini, u-boot
One-liner env fix below.
The following changes since commit e893e8ea6a5d3af312747d00f93587559193a426:
Prepare v2022.04-rc5 (2022-03-28 10:14:51 -0400)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to 25cff0c1fa83e149e4693121f8b5e287659eed71:
arm: socfpga: vining: Fix mtdparts for 2x256 MiB SF variant
(2022-03-28 21:49:03 +0200)
----------------------------------------------------------------
Marek Vasut (1):
arm: socfpga: vining: Fix mtdparts for 2x256 MiB SF variant
include/configs/socfpga_vining_fpga.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PULL] u-boot-socfpga/master
2021-09-22 22:36 Marek Vasut
@ 2021-09-23 21:20 ` Tom Rini
0 siblings, 0 replies; 27+ messages in thread
From: Tom Rini @ 2021-09-23 21:20 UTC (permalink / raw)
To: Marek Vasut; +Cc: u-boot
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On Thu, Sep 23, 2021 at 12:36:27AM +0200, Marek Vasut wrote:
> Bugfixes for this one socfpga platform, should go into 2021.10
>
> The following changes since commit a49930f4c6ed5dcbf5127f7bf6d189afa92bffb3:
>
> Merge https://source.denx.de/u-boot/custodians/u-boot-x86 (2021-09-22
> 11:43:12 -0400)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-socfpga.git master
>
> for you to fetch changes up to 532010da67329a1c3dbe92a167486df6e61d4f4a:
>
> ddr: altera: use KBUILD_BASENAME instead of __FILE__ (2021-09-22 21:31:05
> +0200)
>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL] u-boot-socfpga/master
@ 2021-09-22 22:36 Marek Vasut
2021-09-23 21:20 ` Tom Rini
0 siblings, 1 reply; 27+ messages in thread
From: Marek Vasut @ 2021-09-22 22:36 UTC (permalink / raw)
To: Tom Rini, u-boot
Bugfixes for this one socfpga platform, should go into 2021.10
The following changes since commit a49930f4c6ed5dcbf5127f7bf6d189afa92bffb3:
Merge https://source.denx.de/u-boot/custodians/u-boot-x86 (2021-09-22
11:43:12 -0400)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to 532010da67329a1c3dbe92a167486df6e61d4f4a:
ddr: altera: use KBUILD_BASENAME instead of __FILE__ (2021-09-22
21:31:05 +0200)
----------------------------------------------------------------
Marek Vasut (9):
arm: socfpga: vining: Drop meaningless comment
arm: socfpga: vining: Increase environment size
arm: socfpga: vining: Set USB gadget manufacturer to Softing with
capital S
arm: socfpga: vining: Set default SPI NOR mode and frequency
arm: socfpga: vining: Un-disable WDT in DT
arm: socfpga: vining: Fix UDC controller phandle in DT
arm: socfpga: vining: Enable DW I2C driver
arm: socfpga: vining: Let DWMAC configure PHY reset GPIO
ddr: altera: use KBUILD_BASENAME instead of __FILE__
arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 6 +-----
board/softing/vining_fpga/socfpga.c | 7 -------
configs/socfpga_vining_fpga_defconfig | 8 ++++++--
drivers/ddr/altera/sequencer.c | 8 ++++----
include/configs/socfpga_vining_fpga.h | 2 --
5 files changed, 11 insertions(+), 20 deletions(-)
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL] u-boot-socfpga/master
2020-06-14 15:28 Marek Vasut
@ 2020-06-15 13:33 ` Tom Rini
0 siblings, 0 replies; 27+ messages in thread
From: Tom Rini @ 2020-06-15 13:33 UTC (permalink / raw)
To: u-boot
On Sun, Jun 14, 2020 at 05:28:33PM +0200, Marek Vasut wrote:
> The following changes since commit be79009f3b9bbdbce283e67a865121e576d790ea:
>
> Merge tag 'u-boot-imx-20200609' of
> https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2020-06-09 09:17:24
> -0400)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-socfpga.git master
>
> for you to fetch changes up to a0bda1dd8382be57389833024ba40518ec098ac3:
>
> arm: dts: socfpga: cyclone5: Update i2c-scl-falling-time-ns
> (2020-06-14 13:37:31 +0200)
>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL] u-boot-socfpga/master
@ 2020-06-14 15:28 Marek Vasut
2020-06-15 13:33 ` Tom Rini
0 siblings, 1 reply; 27+ messages in thread
From: Marek Vasut @ 2020-06-14 15:28 UTC (permalink / raw)
To: u-boot
The following changes since commit be79009f3b9bbdbce283e67a865121e576d790ea:
Merge tag 'u-boot-imx-20200609' of
https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2020-06-09 09:17:24
-0400)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to a0bda1dd8382be57389833024ba40518ec098ac3:
arm: dts: socfpga: cyclone5: Update i2c-scl-falling-time-ns
(2020-06-14 13:37:31 +0200)
----------------------------------------------------------------
Ley Foon Tan (1):
arm: dts: socfpga: cyclone5: Update i2c-scl-falling-time-ns
arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi | 4 ++++
1 file changed, 4 insertions(+)
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL] u-boot-socfpga/master
2020-04-28 11:53 Marek Vasut
@ 2020-04-28 16:11 ` Tom Rini
0 siblings, 0 replies; 27+ messages in thread
From: Tom Rini @ 2020-04-28 16:11 UTC (permalink / raw)
To: u-boot
On Tue, Apr 28, 2020 at 01:53:51PM +0200, Marek Vasut wrote:
> The following changes since commit d202f67db0771247de562af5d6a5df778702857b:
>
> Merge branch '2020-04-25-master-imports' (2020-04-25 08:20:22 -0400)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-socfpga.git master
>
> for you to fetch changes up to b9d1671829b17f78c47f2d0d42a7f59767cdd84b:
>
> arm: socfpga: stratix10: Fix incorrect CLKMGR_S10_PERPLL_BYPASS offset
> (2020-04-27 09:14:52 +0200)
>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL] u-boot-socfpga/master
@ 2020-04-28 11:53 Marek Vasut
2020-04-28 16:11 ` Tom Rini
0 siblings, 1 reply; 27+ messages in thread
From: Marek Vasut @ 2020-04-28 11:53 UTC (permalink / raw)
To: u-boot
The following changes since commit d202f67db0771247de562af5d6a5df778702857b:
Merge branch '2020-04-25-master-imports' (2020-04-25 08:20:22 -0400)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to b9d1671829b17f78c47f2d0d42a7f59767cdd84b:
arm: socfpga: stratix10: Fix incorrect CLKMGR_S10_PERPLL_BYPASS offset
(2020-04-27 09:14:52 +0200)
----------------------------------------------------------------
Ley Foon Tan (2):
configs: socfpga: arria10: Enable USB support
arm: socfpga: stratix10: Fix incorrect CLKMGR_S10_PERPLL_BYPASS offset
arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 2 +-
configs/socfpga_arria10_defconfig | 4 ++++
2 files changed, 5 insertions(+), 1 deletion(-)
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL] u-boot-socfpga/master
2020-04-13 20:02 Marek Vasut
@ 2020-04-14 23:24 ` Tom Rini
0 siblings, 0 replies; 27+ messages in thread
From: Tom Rini @ 2020-04-14 23:24 UTC (permalink / raw)
To: u-boot
On Mon, Apr 13, 2020 at 10:02:53PM +0200, Marek Vasut wrote:
> The following changes since commit 995972ddbbcc5fccd324ab384bca9af90e710755:
>
> Merge tag 'dm-pull9apr20' of git://git.denx.de/u-boot-dm (2020-04-10
> 11:40:28 -0400)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-socfpga.git master
>
> for you to fetch changes up to 3958ef307e09a28ce649dd7d6e0cb398996dcaa5:
>
> arm: socfpga: arria10: Enable cache driver in SPL (2020-04-13 13:49:51
> +0200)
>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL] u-boot-socfpga/master
@ 2020-04-13 20:02 Marek Vasut
2020-04-14 23:24 ` Tom Rini
0 siblings, 1 reply; 27+ messages in thread
From: Marek Vasut @ 2020-04-13 20:02 UTC (permalink / raw)
To: u-boot
The following changes since commit 995972ddbbcc5fccd324ab384bca9af90e710755:
Merge tag 'dm-pull9apr20' of git://git.denx.de/u-boot-dm (2020-04-10
11:40:28 -0400)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to 3958ef307e09a28ce649dd7d6e0cb398996dcaa5:
arm: socfpga: arria10: Enable cache driver in SPL (2020-04-13 13:49:51
+0200)
----------------------------------------------------------------
Ley Foon Tan (3):
arm: dts: arria10: Move uboot specific properties to u-boot.dtsi
arm: dts: arria10: Update dtsi/dts from Linux
arm: socfpga: arria10: Enable cache driver in SPL
Marek Vasut (1):
ARM: socfpga: Enable DM RTC bootcount on ABB SECU1
arch/arm/dts/socfpga_arria10-u-boot.dtsi | 142
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
arch/arm/dts/socfpga_arria10.dtsi | 118
++++++++++++++++++++++++++++++++++--------------------------------
arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi | 17 ++++++++++
arch/arm/dts/socfpga_arria10_socdk.dtsi | 66
++++++++++++++++---------------------
arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi | 46
++++++++++++++++++++++++++
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 53
++----------------------------
arch/arm/dts/socfpga_arria5_secu1.dts | 6 ++++
arch/arm/mach-socfpga/Kconfig | 1 +
configs/socfpga_secu1_defconfig | 5 +++
9 files changed, 308 insertions(+), 146 deletions(-)
create mode 100644 arch/arm/dts/socfpga_arria10-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL] u-boot-socfpga/master
2020-03-31 3:24 Marek Vasut
@ 2020-03-31 19:09 ` Tom Rini
0 siblings, 0 replies; 27+ messages in thread
From: Tom Rini @ 2020-03-31 19:09 UTC (permalink / raw)
To: u-boot
On Tue, Mar 31, 2020 at 05:24:57AM +0200, Marek Vasut wrote:
> The following changes since commit 93330d4ce416208fe202e304e5a18166c57ac569:
>
> Prepare v2020.04-rc4 (2020-03-30 19:29:27 -0400)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-socfpga.git master
>
> for you to fetch changes up to df8e15af2bed62a5a93c5783ec9e32b9029bb010:
>
> arm: dts: agilex: Enable QSPI (2020-03-31 02:52:38 +0200)
>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL] u-boot-socfpga/master
@ 2020-03-31 3:24 Marek Vasut
2020-03-31 19:09 ` Tom Rini
0 siblings, 1 reply; 27+ messages in thread
From: Marek Vasut @ 2020-03-31 3:24 UTC (permalink / raw)
To: u-boot
The following changes since commit 93330d4ce416208fe202e304e5a18166c57ac569:
Prepare v2020.04-rc4 (2020-03-30 19:29:27 -0400)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to df8e15af2bed62a5a93c5783ec9e32b9029bb010:
arm: dts: agilex: Enable QSPI (2020-03-31 02:52:38 +0200)
----------------------------------------------------------------
Ley Foon Tan (4):
arm: socfpga: Add onchip RAM size macro
configs: socfpga: Change to use SOCFPGA_PHYS_OCRAM_SIZE macro
arm: socfpga: arria10: Add save_boot_params()
arm: dts: agilex: Enable QSPI
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 3 +++
arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 2 ++
arch/arm/mach-socfpga/include/mach/base_addr_ac5.h | 2 ++
arch/arm/mach-socfpga/spl_a10.c | 32
++++++++++++++++++++++++++++++++
include/configs/socfpga_common.h | 5 +++--
5 files changed, 42 insertions(+), 2 deletions(-)
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL] u-boot-socfpga/master
2020-03-04 12:23 Marek Vasut
@ 2020-03-04 23:51 ` Tom Rini
0 siblings, 0 replies; 27+ messages in thread
From: Tom Rini @ 2020-03-04 23:51 UTC (permalink / raw)
To: u-boot
On Wed, Mar 04, 2020 at 01:23:09PM +0100, Marek Vasut wrote:
> The following changes since commit 9e1d65f36b83c5422ece3c0ea28d07a2246cb07f:
>
> configs: Resync with savedefconfig (2020-02-28 13:28:38 -0500)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-socfpga.git master
>
> for you to fetch changes up to 468ba8d00b5af7828302e297736ae23d4873cfb0:
>
> ARM: socfpga: Add initial support for the ABB SECU board (2020-03-03
> 22:11:36 +0100)
>
Applied to u-boot/master, thanks!
--
Tom
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* [PULL] u-boot-socfpga/master
@ 2020-03-04 12:23 Marek Vasut
2020-03-04 23:51 ` Tom Rini
0 siblings, 1 reply; 27+ messages in thread
From: Marek Vasut @ 2020-03-04 12:23 UTC (permalink / raw)
To: u-boot
The following changes since commit 9e1d65f36b83c5422ece3c0ea28d07a2246cb07f:
configs: Resync with savedefconfig (2020-02-28 13:28:38 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to 468ba8d00b5af7828302e297736ae23d4873cfb0:
ARM: socfpga: Add initial support for the ABB SECU board (2020-03-03
22:11:36 +0100)
----------------------------------------------------------------
Holger Brunck (1):
ARM: socfpga: Add initial support for the ABB SECU board
Marek Vasut (3):
rtc: m41t62: add compatible for m41st87
ARM: socfpga: Permit overriding the default timer frequency
ARM: socfpga: Add missing Denali NAND config options
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_arria5_secu1.dts | 130 ++++++++++++++++++
arch/arm/mach-socfpga/Kconfig | 10 ++
board/keymile/Kconfig | 11 +-
board/keymile/common/ivm.c | 19 ++-
board/keymile/secu1/MAINTAINERS | 5 +
board/keymile/secu1/Makefile | 7 +
board/keymile/secu1/qts/iocsr_config.h | 694
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
board/keymile/secu1/qts/pinmux_config.h | 218 +++++++++++++++++++++++++++++
board/keymile/secu1/qts/pll_config.h | 83 ++++++++++++
board/keymile/secu1/qts/sdram_config.h | 327
++++++++++++++++++++++++++++++++++++++++++++
board/keymile/secu1/socfpga.c | 67 +++++++++
configs/socfpga_secu1_defconfig | 84 ++++++++++++
drivers/rtc/m41t62.c | 1 +
include/configs/socfpga_arria5_secu1.h | 131 ++++++++++++++++++
include/configs/socfpga_common.h | 4 +-
16 files changed, 1787 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/dts/socfpga_arria5_secu1.dts
create mode 100644 board/keymile/secu1/MAINTAINERS
create mode 100644 board/keymile/secu1/Makefile
create mode 100644 board/keymile/secu1/qts/iocsr_config.h
create mode 100644 board/keymile/secu1/qts/pinmux_config.h
create mode 100644 board/keymile/secu1/qts/pll_config.h
create mode 100644 board/keymile/secu1/qts/sdram_config.h
create mode 100644 board/keymile/secu1/socfpga.c
create mode 100644 configs/socfpga_secu1_defconfig
create mode 100644 include/configs/socfpga_arria5_secu1.h
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL] u-boot-socfpga/master
2020-01-08 15:31 Marek Vasut
@ 2020-01-08 23:55 ` Tom Rini
0 siblings, 0 replies; 27+ messages in thread
From: Tom Rini @ 2020-01-08 23:55 UTC (permalink / raw)
To: u-boot
On Wed, Jan 08, 2020 at 04:31:55PM +0100, Marek Vasut wrote:
> The following changes since commit 5a8fa095cb848c60c630a83edf30d4fc46101e90:
>
> Merge branch 'next' (2020-01-06 17:07:49 -0500)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-socfpga.git master
>
> for you to fetch changes up to 8097aee3abc3b773aceea01f756a38b34b274e1e:
>
> ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC Access (2020-01-07
> 14:38:34 +0100)
>
Applied to u-boot/master, thanks!
--
Tom
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* [PULL] u-boot-socfpga/master
@ 2020-01-08 15:31 Marek Vasut
2020-01-08 23:55 ` Tom Rini
0 siblings, 1 reply; 27+ messages in thread
From: Marek Vasut @ 2020-01-08 15:31 UTC (permalink / raw)
To: u-boot
The following changes since commit 5a8fa095cb848c60c630a83edf30d4fc46101e90:
Merge branch 'next' (2020-01-06 17:07:49 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to 8097aee3abc3b773aceea01f756a38b34b274e1e:
ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC Access (2020-01-07
14:38:34 +0100)
----------------------------------------------------------------
Ley Foon Tan (24):
spl: Allow cache drivers to be used in SPL
arm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr
nodes
arm: socfpga: Convert reset manager from struct to defines
arm: socfpga: Convert system manager from struct to defines
arm: socfpga: Convert clock manager from struct to defines
arm: socfpga: agilex: Add base address for Intel Agilex SoC
arm: socfpga: Move firewall code to firewall file
arm: socfpga: Move Stratix10 and Agilex reset manager common code
arm: socfpga: agilex: Add reset manager support
arm: socfpga: Move Stratix10 and Agilex system manager common code
arm: socfpga: agilex: Add system manager support
arm: socfpga: Move Stratix10 and Agilex clock manager common code
arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz
clk: agilex: Add clock driver for Agilex
arm: socfpga: agilex: Add clock wrapper functions
cache: Add Arteris Ncore cache coherent unit driver
arm: agilex: Add clock handoff offset for Agilex
ddr: altera: Restructure Stratix 10 SDRAM driver
ddr: altera: agilex: Add SDRAM driver for Agilex
board: intel: agilex: Add socdk board support for Intel Agilex SoC
arm: socfpga: agilex: Add SPL for Agilex SoC
arm: dts: agilex: Add base dtsi and devkit dts
configs: socfpga: Move Stratix10 and Agilex common CONFIGs
arm: socfpga: agilex: Enable Agilex SoC build
Simon Goldschmidt (1):
configs: socfpga: fix building Stratix10 and Agilex
Thor Thayer (2):
arm: socfpga: stratix10: Enable SMMU access
ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC Access
arch/arm/Kconfig | 4 +-
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga-common-u-boot.dtsi | 8 +
arch/arm/dts/socfpga.dtsi | 2 +-
arch/arm/dts/socfpga_agilex-u-boot.dtsi | 96
+++++++++++
arch/arm/dts/socfpga_agilex.dtsi | 622
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 39
+++++
arch/arm/dts/socfpga_agilex_socdk.dts | 141
+++++++++++++++
arch/arm/dts/socfpga_arria10.dtsi | 2 +-
arch/arm/dts/socfpga_arria10_socdk.dtsi | 8 +
arch/arm/dts/socfpga_stratix10.dtsi | 2 +-
arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 8 +
arch/arm/mach-socfpga/Kconfig | 16 ++
arch/arm/mach-socfpga/Makefile | 17 ++
arch/arm/mach-socfpga/clock_manager.c | 14 +-
arch/arm/mach-socfpga/clock_manager_agilex.c | 85
++++++++++
arch/arm/mach-socfpga/clock_manager_arria10.c | 155
+++++++++--------
arch/arm/mach-socfpga/clock_manager_gen5.c | 211
+++++++++++++----------
arch/arm/mach-socfpga/clock_manager_s10.c | 218
++++++++++++++----------
arch/arm/mach-socfpga/firewall.c | 107
++++++++++++
arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 4 +
arch/arm/mach-socfpga/include/mach/clock_manager.h | 4 +
arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h | 14 ++
arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h | 133
++++++---------
arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h | 112
+++++-------
arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 131
++++++--------
arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h | 21 +++
arch/arm/mach-socfpga/include/mach/{firewall_s10.h => firewall.h} | 17 +-
arch/arm/mach-socfpga/include/mach/handoff_s10.h | 9 +-
arch/arm/mach-socfpga/include/mach/misc.h | 1 +
arch/arm/mach-socfpga/include/mach/reset_manager.h | 7 +-
arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h | 43
+----
arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h | 22 +--
arch/arm/mach-socfpga/include/mach/reset_manager_s10.h | 118
-------------
arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h | 38
+++++
arch/arm/mach-socfpga/include/mach/system_manager.h | 7 +-
arch/arm/mach-socfpga/include/mach/system_manager_arria10.h | 94
+++-------
arch/arm/mach-socfpga/include/mach/system_manager_gen5.h | 123
+++-----------
arch/arm/mach-socfpga/include/mach/system_manager_s10.h | 176
-------------------
arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | 123
++++++++++++++
arch/arm/mach-socfpga/mailbox_s10.c | 6 +-
arch/arm/mach-socfpga/misc.c | 66
++++++++
arch/arm/mach-socfpga/misc_arria10.c | 11 +-
arch/arm/mach-socfpga/misc_gen5.c | 38
+++--
arch/arm/mach-socfpga/misc_s10.c | 9 +-
arch/arm/mach-socfpga/reset_manager_arria10.c | 73
++++----
arch/arm/mach-socfpga/reset_manager_gen5.c | 37
++--
arch/arm/mach-socfpga/reset_manager_s10.c | 56
+++---
arch/arm/mach-socfpga/scan_manager.c | 6 +-
arch/arm/mach-socfpga/spl_a10.c | 12 +-
arch/arm/mach-socfpga/spl_agilex.c | 98
+++++++++++
arch/arm/mach-socfpga/spl_gen5.c | 26 ++-
arch/arm/mach-socfpga/spl_s10.c | 109
++----------
arch/arm/mach-socfpga/system_manager_gen5.c | 42
+++--
arch/arm/mach-socfpga/system_manager_s10.c | 42
+++--
arch/arm/mach-socfpga/wrap_pll_config_s10.c | 20 ++-
board/intel/agilex-socdk/MAINTAINERS | 7 +
board/intel/agilex-socdk/Makefile | 7 +
board/intel/agilex-socdk/socfpga.c | 7 +
common/spl/Kconfig | 6 +
configs/socfpga_agilex_defconfig | 60
+++++++
drivers/Makefile | 1 +
drivers/cache/Kconfig | 8 +
drivers/cache/Makefile | 3 +-
drivers/cache/cache-ncore.c | 164
++++++++++++++++++
drivers/clk/altera/Makefile | 1 +
drivers/clk/altera/clk-agilex.c | 579
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
drivers/clk/altera/clk-agilex.h | 237
++++++++++++++++++++++++++
drivers/ddr/altera/Kconfig | 6 +-
drivers/ddr/altera/Makefile | 3 +-
drivers/ddr/altera/sdram_agilex.c | 168
++++++++++++++++++
drivers/ddr/altera/sdram_gen5.c | 12 +-
drivers/ddr/altera/sdram_s10.c | 320
+++-------------------------------
drivers/ddr/altera/sdram_s10.h | 148
+---------------
drivers/ddr/altera/sdram_soc64.c | 305
+++++++++++++++++++++++++++++++++
drivers/ddr/altera/sdram_soc64.h | 187
++++++++++++++++++++
drivers/fpga/socfpga_arria10.c | 7 +-
drivers/fpga/socfpga_gen5.c | 4 +-
drivers/mmc/socfpga_dw_mmc.c | 17 +-
drivers/sysreset/sysreset_socfpga.c | 6 +-
include/configs/socfpga_agilex_socdk.h | 12 ++
include/configs/socfpga_soc64_common.h | 202
++++++++++++++++++++++
include/configs/socfpga_stratix10_socdk.h | 192
+--------------------
include/dt-bindings/clock/agilex-clock.h | 71
++++++++
84 files changed, 4392 insertions(+), 1952 deletions(-)
create mode 100644 arch/arm/dts/socfpga_agilex-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_agilex.dtsi
create mode 100644 arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_agilex_socdk.dts
create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex.c
create mode 100644 arch/arm/mach-socfpga/firewall.c
create mode 100644
arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
rename arch/arm/mach-socfpga/include/mach/{firewall_s10.h =>
firewall.h} (85%)
delete mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
delete mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10.h
create mode 100644
arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
create mode 100644 arch/arm/mach-socfpga/spl_agilex.c
create mode 100644 board/intel/agilex-socdk/MAINTAINERS
create mode 100644 board/intel/agilex-socdk/Makefile
create mode 100644 board/intel/agilex-socdk/socfpga.c
create mode 100644 configs/socfpga_agilex_defconfig
create mode 100644 drivers/cache/cache-ncore.c
create mode 100644 drivers/clk/altera/clk-agilex.c
create mode 100644 drivers/clk/altera/clk-agilex.h
create mode 100644 drivers/ddr/altera/sdram_agilex.c
create mode 100644 drivers/ddr/altera/sdram_soc64.c
create mode 100644 drivers/ddr/altera/sdram_soc64.h
create mode 100644 include/configs/socfpga_agilex_socdk.h
create mode 100644 include/configs/socfpga_soc64_common.h
create mode 100644 include/dt-bindings/clock/agilex-clock.h
^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2023-02-22 22:51 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-02 17:18 [PULL] u-boot-socfpga/master Marek Vasut
2020-02-02 20:26 ` Tom Rini
2020-02-03 8:24 ` Marek Vasut
2020-02-03 8:47 ` Marek Vasut
2020-02-04 4:13 ` Tom Rini
2020-02-05 6:58 ` Marek Vasut
2020-02-07 18:51 ` Tom Rini
-- strict thread matches above, loose matches on Subject: below --
2023-02-22 1:04 Marek Vasut
2023-02-22 22:51 ` Tom Rini
2022-05-23 21:50 Marek Vasut
2022-05-24 15:51 ` Tom Rini
2022-03-28 20:05 Marek Vasut
2022-03-28 21:04 ` Tom Rini
2021-09-22 22:36 Marek Vasut
2021-09-23 21:20 ` Tom Rini
2020-06-14 15:28 Marek Vasut
2020-06-15 13:33 ` Tom Rini
2020-04-28 11:53 Marek Vasut
2020-04-28 16:11 ` Tom Rini
2020-04-13 20:02 Marek Vasut
2020-04-14 23:24 ` Tom Rini
2020-03-31 3:24 Marek Vasut
2020-03-31 19:09 ` Tom Rini
2020-03-04 12:23 Marek Vasut
2020-03-04 23:51 ` Tom Rini
2020-01-08 15:31 Marek Vasut
2020-01-08 23:55 ` Tom Rini
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