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From: Geert Uytterhoeven <geert+renesas@glider.be>
To: Magnus Damm <magnus.damm@gmail.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
	Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>,
	linux-renesas-soc@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Geert Uytterhoeven <geert+renesas@glider.be>
Subject: [PATCH v2 4/4] arm64: dts: renesas: rzg2: Add reset control properties for display
Date: Tue, 18 Feb 2020 14:30:19 +0100	[thread overview]
Message-ID: <20200218133019.22299-5-geert+renesas@glider.be> (raw)
In-Reply-To: <20200218133019.22299-1-geert+renesas@glider.be>

Add reset control properties to the device nodes for the Display Units
on all supported RZ/G2 SoCs.  Note that on these SoCs, there is only a
single reset for each pair of DU channels.

Join the clocks lines while at it, to increase uniformity.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2:
  - New.
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 5 +++--
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 5 +++--
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 5 +++--
 3 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 507e78ebaab52330..79023433a740b7ca 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -2634,10 +2634,11 @@
 			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 724>,
-				 <&cpg CPG_MOD 723>,
+			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
 				 <&cpg CPG_MOD 722>;
 			clock-names = "du.0", "du.1", "du.2";
+			resets = <&cpg 724>, <&cpg 722>;
+			reset-names = "du.0", "du.2";
 			status = "disabled";
 
 			renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 93dd10b5d6d05712..3137f735974be165 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -2480,10 +2480,11 @@
 			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 724>,
-				 <&cpg CPG_MOD 723>,
+			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
 				 <&cpg CPG_MOD 721>;
 			clock-names = "du.0", "du.1", "du.3";
+			resets = <&cpg 724>, <&cpg 722>;
+			reset-names = "du.0", "du.3";
 			status = "disabled";
 
 			renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index d4eee8fef35da74e..22785cbddff5d08c 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -1810,9 +1810,10 @@
 			reg = <0 0xfeb00000 0 0x40000>;
 			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 724>,
-				 <&cpg CPG_MOD 723>;
+			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
 			clock-names = "du.0", "du.1";
+			resets = <&cpg 724>;
+			reset-names = "du.0";
 			renesas,vsps = <&vspd0 0>, <&vspd1 0>;
 
 			status = "disabled";
-- 
2.17.1


WARNING: multiple messages have this Message-ID
From: Geert Uytterhoeven <geert+renesas@glider.be>
To: Magnus Damm <magnus.damm@gmail.com>
Cc: linux-renesas-soc@vger.kernel.org,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>,
	Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 4/4] arm64: dts: renesas: rzg2: Add reset control properties for display
Date: Tue, 18 Feb 2020 14:30:19 +0100	[thread overview]
Message-ID: <20200218133019.22299-5-geert+renesas@glider.be> (raw)
In-Reply-To: <20200218133019.22299-1-geert+renesas@glider.be>

Add reset control properties to the device nodes for the Display Units
on all supported RZ/G2 SoCs.  Note that on these SoCs, there is only a
single reset for each pair of DU channels.

Join the clocks lines while at it, to increase uniformity.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2:
  - New.
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 5 +++--
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 5 +++--
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 5 +++--
 3 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 507e78ebaab52330..79023433a740b7ca 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -2634,10 +2634,11 @@
 			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 724>,
-				 <&cpg CPG_MOD 723>,
+			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
 				 <&cpg CPG_MOD 722>;
 			clock-names = "du.0", "du.1", "du.2";
+			resets = <&cpg 724>, <&cpg 722>;
+			reset-names = "du.0", "du.2";
 			status = "disabled";
 
 			renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 93dd10b5d6d05712..3137f735974be165 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -2480,10 +2480,11 @@
 			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 724>,
-				 <&cpg CPG_MOD 723>,
+			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
 				 <&cpg CPG_MOD 721>;
 			clock-names = "du.0", "du.1", "du.3";
+			resets = <&cpg 724>, <&cpg 722>;
+			reset-names = "du.0", "du.3";
 			status = "disabled";
 
 			renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index d4eee8fef35da74e..22785cbddff5d08c 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -1810,9 +1810,10 @@
 			reg = <0 0xfeb00000 0 0x40000>;
 			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 724>,
-				 <&cpg CPG_MOD 723>;
+			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
 			clock-names = "du.0", "du.1";
+			resets = <&cpg 724>;
+			reset-names = "du.0";
 			renesas,vsps = <&vspd0 0>, <&vspd1 0>;
 
 			status = "disabled";
-- 
2.17.1


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  parent reply	other threads:[~2020-02-18 13:30 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-18 13:30 [PATCH v2 0/4] arm: dts: renesas: " Geert Uytterhoeven
2020-02-18 13:30 ` Geert Uytterhoeven
2020-02-18 13:30 ` [PATCH v2 1/4] ARM: dts: rcar-gen2: " Geert Uytterhoeven
2020-02-18 13:30   ` Geert Uytterhoeven
2020-02-19 10:59   ` Ulrich Hecht
2020-02-19 10:59     ` Ulrich Hecht
2020-02-19 15:27   ` Laurent Pinchart
2020-02-19 15:27     ` Laurent Pinchart
2020-02-19 15:30     ` Geert Uytterhoeven
2020-02-19 15:30       ` Geert Uytterhoeven
2020-02-18 13:30 ` [PATCH v2 2/4] ARM: dts: rzg1: " Geert Uytterhoeven
2020-02-18 13:30   ` Geert Uytterhoeven
2020-02-19 10:59   ` Ulrich Hecht
2020-02-19 10:59     ` Ulrich Hecht
2020-02-19 15:28   ` Laurent Pinchart
2020-02-19 15:28     ` Laurent Pinchart
2020-02-18 13:30 ` [PATCH v2 3/4] arm64: dts: renesas: rcar-gen3: " Geert Uytterhoeven
2020-02-18 13:30   ` Geert Uytterhoeven
2020-02-19 11:00   ` Ulrich Hecht
2020-02-19 11:00     ` Ulrich Hecht
2020-02-19 15:33   ` Laurent Pinchart
2020-02-19 15:33     ` Laurent Pinchart
2020-02-19 15:55     ` Geert Uytterhoeven
2020-02-19 15:55       ` Geert Uytterhoeven
2020-02-19 16:06       ` Laurent Pinchart
2020-02-19 16:06         ` Laurent Pinchart
2020-02-18 13:30 ` Geert Uytterhoeven [this message]
2020-02-18 13:30   ` [PATCH v2 4/4] arm64: dts: renesas: rzg2: " Geert Uytterhoeven
2020-02-19 11:01   ` Ulrich Hecht
2020-02-19 11:01     ` Ulrich Hecht
2020-02-19 15:40   ` Laurent Pinchart
2020-02-19 15:40     ` Laurent Pinchart

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