* [PATCH v3 0/4] mmc: mediatek: add mmc cqhci support @ 2020-02-17 6:56 ` Chun-Hung Wu 0 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-02-17 6:56 UTC (permalink / raw) To: Chaotian Jing, Ulf Hansson, Rob Herring, Mark Rutland, Matthias Brugger, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang Cc: kernel-team, linux-kernel, linux-mmc, linux-mediatek, devicetree, wsd_upstream, linux-arm-kernel, Chun-Hung Wu This series provides MediaTek cqhci implementations as below: - Add expose MMC_CAP2_CQE* to dt - Refine msdc timeout api to reduce redundant code - MediaTek command queue support - dt-bindings for mt6779 v1 -> v2: - Add more patch details in commit message - Separate msdc timeout api refine to individual patch v2 -> v3: - Remove CR-Id, Change-Id and Feature in patches - Add Signed-off-by in patches Chun-Hung Wu (4): [1/4] mmc: core: expose MMC_CAP2_CQE* to dt [2/4] mmc: mediatek: refine msdc timeout api [3/4] mmc: mediatek: command queue support [4/4] dt-bindings: mmc: mediatek: Add document for mt6779 Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 + drivers/mmc/core/host.c | 8 ++ drivers/mmc/host/mtk-sd.c | 151 +++++++++++++++++++++-- 3 files changed, 150 insertions(+), 10 deletions(-) -- 1.9.1 ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v3 0/4] mmc: mediatek: add mmc cqhci support @ 2020-02-17 6:56 ` Chun-Hung Wu 0 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-02-17 6:56 UTC (permalink / raw) To: Chaotian Jing, Ulf Hansson, Rob Herring, Mark Rutland, Matthias Brugger, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang Cc: devicetree, wsd_upstream, Chun-Hung Wu, linux-mmc, linux-kernel, linux-mediatek, kernel-team, linux-arm-kernel This series provides MediaTek cqhci implementations as below: - Add expose MMC_CAP2_CQE* to dt - Refine msdc timeout api to reduce redundant code - MediaTek command queue support - dt-bindings for mt6779 v1 -> v2: - Add more patch details in commit message - Separate msdc timeout api refine to individual patch v2 -> v3: - Remove CR-Id, Change-Id and Feature in patches - Add Signed-off-by in patches Chun-Hung Wu (4): [1/4] mmc: core: expose MMC_CAP2_CQE* to dt [2/4] mmc: mediatek: refine msdc timeout api [3/4] mmc: mediatek: command queue support [4/4] dt-bindings: mmc: mediatek: Add document for mt6779 Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 + drivers/mmc/core/host.c | 8 ++ drivers/mmc/host/mtk-sd.c | 151 +++++++++++++++++++++-- 3 files changed, 150 insertions(+), 10 deletions(-) -- 1.9.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v3 0/4] mmc: mediatek: add mmc cqhci support @ 2020-02-17 6:56 ` Chun-Hung Wu 0 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-02-17 6:56 UTC (permalink / raw) To: Chaotian Jing, Ulf Hansson, Rob Herring, Mark Rutland, Matthias Brugger, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang Cc: devicetree, wsd_upstream, Chun-Hung Wu, linux-mmc, linux-kernel, linux-mediatek, kernel-team, linux-arm-kernel This series provides MediaTek cqhci implementations as below: - Add expose MMC_CAP2_CQE* to dt - Refine msdc timeout api to reduce redundant code - MediaTek command queue support - dt-bindings for mt6779 v1 -> v2: - Add more patch details in commit message - Separate msdc timeout api refine to individual patch v2 -> v3: - Remove CR-Id, Change-Id and Feature in patches - Add Signed-off-by in patches Chun-Hung Wu (4): [1/4] mmc: core: expose MMC_CAP2_CQE* to dt [2/4] mmc: mediatek: refine msdc timeout api [3/4] mmc: mediatek: command queue support [4/4] dt-bindings: mmc: mediatek: Add document for mt6779 Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 + drivers/mmc/core/host.c | 8 ++ drivers/mmc/host/mtk-sd.c | 151 +++++++++++++++++++++-- 3 files changed, 150 insertions(+), 10 deletions(-) -- 1.9.1 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v3 1/4] mmc: core: expose MMC_CAP2_CQE* to dt 2020-02-17 6:56 ` Chun-Hung Wu (?) @ 2020-02-17 6:56 ` Chun-Hung Wu -1 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-02-17 6:56 UTC (permalink / raw) To: Chaotian Jing, Ulf Hansson, Rob Herring, Mark Rutland, Matthias Brugger, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang Cc: kernel-team, linux-kernel, linux-mmc, linux-mediatek, devicetree, wsd_upstream, linux-arm-kernel, Chun-Hung Wu Expose MMC_CAP2_CQE and MMC_CAP2_CQE_DCMD to host->caps2 if 1. "supports-cqe" is defined in dt and 2. "disable-cqe-dcmd" is not defined in dt. Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> --- drivers/mmc/core/host.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c index 105b7a7..efb0dbe 100644 --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c @@ -319,6 +319,14 @@ int mmc_of_parse(struct mmc_host *host) host->caps2 |= MMC_CAP2_NO_SD; if (device_property_read_bool(dev, "no-mmc")) host->caps2 |= MMC_CAP2_NO_MMC; + if (device_property_read_bool(dev, "supports-cqe")) + host->caps2 |= MMC_CAP2_CQE; + + /* Must be after "supports-cqe" check */ + if (!device_property_read_bool(dev, "disable-cqe-dcmd")) { + if (host->caps2 & MMC_CAP2_CQE) + host->caps2 |= MMC_CAP2_CQE_DCMD; + } /* Must be after "non-removable" check */ if (device_property_read_u32(dev, "fixed-emmc-driver-type", &drv_type) == 0) { -- 1.9.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v3 1/4] mmc: core: expose MMC_CAP2_CQE* to dt @ 2020-02-17 6:56 ` Chun-Hung Wu 0 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-02-17 6:56 UTC (permalink / raw) To: Chaotian Jing, Ulf Hansson, Rob Herring, Mark Rutland, Matthias Brugger, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang Cc: devicetree, wsd_upstream, Chun-Hung Wu, linux-mmc, linux-kernel, linux-mediatek, kernel-team, linux-arm-kernel Expose MMC_CAP2_CQE and MMC_CAP2_CQE_DCMD to host->caps2 if 1. "supports-cqe" is defined in dt and 2. "disable-cqe-dcmd" is not defined in dt. Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> --- drivers/mmc/core/host.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c index 105b7a7..efb0dbe 100644 --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c @@ -319,6 +319,14 @@ int mmc_of_parse(struct mmc_host *host) host->caps2 |= MMC_CAP2_NO_SD; if (device_property_read_bool(dev, "no-mmc")) host->caps2 |= MMC_CAP2_NO_MMC; + if (device_property_read_bool(dev, "supports-cqe")) + host->caps2 |= MMC_CAP2_CQE; + + /* Must be after "supports-cqe" check */ + if (!device_property_read_bool(dev, "disable-cqe-dcmd")) { + if (host->caps2 & MMC_CAP2_CQE) + host->caps2 |= MMC_CAP2_CQE_DCMD; + } /* Must be after "non-removable" check */ if (device_property_read_u32(dev, "fixed-emmc-driver-type", &drv_type) == 0) { -- 1.9.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v3 1/4] mmc: core: expose MMC_CAP2_CQE* to dt @ 2020-02-17 6:56 ` Chun-Hung Wu 0 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-02-17 6:56 UTC (permalink / raw) To: Chaotian Jing, Ulf Hansson, Rob Herring, Mark Rutland, Matthias Brugger, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang Cc: devicetree, wsd_upstream, Chun-Hung Wu, linux-mmc, linux-kernel, linux-mediatek, kernel-team, linux-arm-kernel Expose MMC_CAP2_CQE and MMC_CAP2_CQE_DCMD to host->caps2 if 1. "supports-cqe" is defined in dt and 2. "disable-cqe-dcmd" is not defined in dt. Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> --- drivers/mmc/core/host.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c index 105b7a7..efb0dbe 100644 --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c @@ -319,6 +319,14 @@ int mmc_of_parse(struct mmc_host *host) host->caps2 |= MMC_CAP2_NO_SD; if (device_property_read_bool(dev, "no-mmc")) host->caps2 |= MMC_CAP2_NO_MMC; + if (device_property_read_bool(dev, "supports-cqe")) + host->caps2 |= MMC_CAP2_CQE; + + /* Must be after "supports-cqe" check */ + if (!device_property_read_bool(dev, "disable-cqe-dcmd")) { + if (host->caps2 & MMC_CAP2_CQE) + host->caps2 |= MMC_CAP2_CQE_DCMD; + } /* Must be after "non-removable" check */ if (device_property_read_u32(dev, "fixed-emmc-driver-type", &drv_type) == 0) { -- 1.9.1 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH v3 1/4] mmc: core: expose MMC_CAP2_CQE* to dt 2020-02-17 6:56 ` Chun-Hung Wu (?) @ 2020-03-04 13:04 ` Ulf Hansson -1 siblings, 0 replies; 33+ messages in thread From: Ulf Hansson @ 2020-03-04 13:04 UTC (permalink / raw) To: Chun-Hung Wu Cc: Chaotian Jing, Rob Herring, Mark Rutland, Matthias Brugger, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang, Android Kernel Team, Linux Kernel Mailing List, linux-mmc, moderated list:ARM/Mediatek SoC support, DTML, wsd_upstream, Linux ARM On Mon, 17 Feb 2020 at 07:56, Chun-Hung Wu <chun-hung.wu@mediatek.com> wrote: > > Expose MMC_CAP2_CQE and MMC_CAP2_CQE_DCMD > to host->caps2 if > 1. "supports-cqe" is defined in dt and > 2. "disable-cqe-dcmd" is not defined in dt. Both of these DT properties are defined as common mmc DT properties, so the above isn't really correct. Please clarify this. Moreover, I suggest to update commit message header into "mmc: core: Extend mmc_of_parse() to parse CQE bindings", as I think it better describes the change. > > Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> > --- > drivers/mmc/core/host.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c > index 105b7a7..efb0dbe 100644 > --- a/drivers/mmc/core/host.c > +++ b/drivers/mmc/core/host.c > @@ -319,6 +319,14 @@ int mmc_of_parse(struct mmc_host *host) > host->caps2 |= MMC_CAP2_NO_SD; > if (device_property_read_bool(dev, "no-mmc")) > host->caps2 |= MMC_CAP2_NO_MMC; > + if (device_property_read_bool(dev, "supports-cqe")) > + host->caps2 |= MMC_CAP2_CQE; > + > + /* Must be after "supports-cqe" check */ > + if (!device_property_read_bool(dev, "disable-cqe-dcmd")) { > + if (host->caps2 & MMC_CAP2_CQE) Does it really doesn't matter if we set this cap, even if MMC_CAP2_CQE isn't set? You can probably skip the check above. > + host->caps2 |= MMC_CAP2_CQE_DCMD; > + } > > /* Must be after "non-removable" check */ > if (device_property_read_u32(dev, "fixed-emmc-driver-type", &drv_type) == 0) { > -- > 1.9.1 Kind regards Uffe ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 1/4] mmc: core: expose MMC_CAP2_CQE* to dt @ 2020-03-04 13:04 ` Ulf Hansson 0 siblings, 0 replies; 33+ messages in thread From: Ulf Hansson @ 2020-03-04 13:04 UTC (permalink / raw) To: Chun-Hung Wu Cc: Mark Rutland, Kate Stewart, wsd_upstream, linux-mmc, Linus Walleij, Pavel Machek, Chaotian Jing, Android Kernel Team, Pan Bian, DTML, Martin Blumenstingl, Rob Herring, moderated list:ARM/Mediatek SoC support, Matthias Brugger, Thomas Gleixner, Stanley Chu, Allison Randal, Linux ARM, Mathieu Malaterre, Greg Kroah-Hartman, Kuohong Wang, Linux Kernel Mailing List On Mon, 17 Feb 2020 at 07:56, Chun-Hung Wu <chun-hung.wu@mediatek.com> wrote: > > Expose MMC_CAP2_CQE and MMC_CAP2_CQE_DCMD > to host->caps2 if > 1. "supports-cqe" is defined in dt and > 2. "disable-cqe-dcmd" is not defined in dt. Both of these DT properties are defined as common mmc DT properties, so the above isn't really correct. Please clarify this. Moreover, I suggest to update commit message header into "mmc: core: Extend mmc_of_parse() to parse CQE bindings", as I think it better describes the change. > > Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> > --- > drivers/mmc/core/host.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c > index 105b7a7..efb0dbe 100644 > --- a/drivers/mmc/core/host.c > +++ b/drivers/mmc/core/host.c > @@ -319,6 +319,14 @@ int mmc_of_parse(struct mmc_host *host) > host->caps2 |= MMC_CAP2_NO_SD; > if (device_property_read_bool(dev, "no-mmc")) > host->caps2 |= MMC_CAP2_NO_MMC; > + if (device_property_read_bool(dev, "supports-cqe")) > + host->caps2 |= MMC_CAP2_CQE; > + > + /* Must be after "supports-cqe" check */ > + if (!device_property_read_bool(dev, "disable-cqe-dcmd")) { > + if (host->caps2 & MMC_CAP2_CQE) Does it really doesn't matter if we set this cap, even if MMC_CAP2_CQE isn't set? You can probably skip the check above. > + host->caps2 |= MMC_CAP2_CQE_DCMD; > + } > > /* Must be after "non-removable" check */ > if (device_property_read_u32(dev, "fixed-emmc-driver-type", &drv_type) == 0) { > -- > 1.9.1 Kind regards Uffe _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 1/4] mmc: core: expose MMC_CAP2_CQE* to dt @ 2020-03-04 13:04 ` Ulf Hansson 0 siblings, 0 replies; 33+ messages in thread From: Ulf Hansson @ 2020-03-04 13:04 UTC (permalink / raw) To: Chun-Hung Wu Cc: Mark Rutland, Kate Stewart, wsd_upstream, linux-mmc, Linus Walleij, Pavel Machek, Chaotian Jing, Android Kernel Team, Pan Bian, DTML, Martin Blumenstingl, Rob Herring, moderated list:ARM/Mediatek SoC support, Matthias Brugger, Thomas Gleixner, Stanley Chu, Allison Randal, Linux ARM, Mathieu Malaterre, Greg Kroah-Hartman, Kuohong Wang, Linux Kernel Mailing List On Mon, 17 Feb 2020 at 07:56, Chun-Hung Wu <chun-hung.wu@mediatek.com> wrote: > > Expose MMC_CAP2_CQE and MMC_CAP2_CQE_DCMD > to host->caps2 if > 1. "supports-cqe" is defined in dt and > 2. "disable-cqe-dcmd" is not defined in dt. Both of these DT properties are defined as common mmc DT properties, so the above isn't really correct. Please clarify this. Moreover, I suggest to update commit message header into "mmc: core: Extend mmc_of_parse() to parse CQE bindings", as I think it better describes the change. > > Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> > --- > drivers/mmc/core/host.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c > index 105b7a7..efb0dbe 100644 > --- a/drivers/mmc/core/host.c > +++ b/drivers/mmc/core/host.c > @@ -319,6 +319,14 @@ int mmc_of_parse(struct mmc_host *host) > host->caps2 |= MMC_CAP2_NO_SD; > if (device_property_read_bool(dev, "no-mmc")) > host->caps2 |= MMC_CAP2_NO_MMC; > + if (device_property_read_bool(dev, "supports-cqe")) > + host->caps2 |= MMC_CAP2_CQE; > + > + /* Must be after "supports-cqe" check */ > + if (!device_property_read_bool(dev, "disable-cqe-dcmd")) { > + if (host->caps2 & MMC_CAP2_CQE) Does it really doesn't matter if we set this cap, even if MMC_CAP2_CQE isn't set? You can probably skip the check above. > + host->caps2 |= MMC_CAP2_CQE_DCMD; > + } > > /* Must be after "non-removable" check */ > if (device_property_read_u32(dev, "fixed-emmc-driver-type", &drv_type) == 0) { > -- > 1.9.1 Kind regards Uffe _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 1/4] mmc: core: expose MMC_CAP2_CQE* to dt 2020-03-04 13:04 ` Ulf Hansson (?) @ 2020-03-09 23:13 ` Chun-Hung Wu -1 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-03-09 23:13 UTC (permalink / raw) To: Ulf Hansson Cc: Chaotian Jing, Rob Herring, Mark Rutland, Matthias Brugger, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang, Android Kernel Team, Linux Kernel Mailing List, linux-mmc, moderated list:ARM/Mediatek SoC support, DTML, wsd_upstream, Linux ARM On Wed, 2020-03-04 at 14:04 +0100, Ulf Hansson wrote: > On Mon, 17 Feb 2020 at 07:56, Chun-Hung Wu <chun-hung.wu@mediatek.com> wrote: > > > > Expose MMC_CAP2_CQE and MMC_CAP2_CQE_DCMD > > to host->caps2 if > > 1. "supports-cqe" is defined in dt and > > 2. "disable-cqe-dcmd" is not defined in dt. > > Both of these DT properties are defined as common mmc DT properties, > so the above isn't really correct. Please clarify this. Yes, the properties is common. But I think the "supports-cqe" or "disable-cqe-dcmd" is defined in vendor's mmc dt, not common mmc dt? Don't know what's wrong with the above description, any suggestion? > > Moreover, I suggest to update commit message header into "mmc: core: > Extend mmc_of_parse() to parse CQE bindings", as I think it better > describes the change. Thanks, I think the commit message you provide is better, will change it in v4. > > > > > Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> > > --- > > drivers/mmc/core/host.c | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c > > index 105b7a7..efb0dbe 100644 > > --- a/drivers/mmc/core/host.c > > +++ b/drivers/mmc/core/host.c > > @@ -319,6 +319,14 @@ int mmc_of_parse(struct mmc_host *host) > > host->caps2 |= MMC_CAP2_NO_SD; > > if (device_property_read_bool(dev, "no-mmc")) > > host->caps2 |= MMC_CAP2_NO_MMC; > > + if (device_property_read_bool(dev, "supports-cqe")) > > + host->caps2 |= MMC_CAP2_CQE; > > + > > + /* Must be after "supports-cqe" check */ > > + if (!device_property_read_bool(dev, "disable-cqe-dcmd")) { > > + if (host->caps2 & MMC_CAP2_CQE) > > Does it really doesn't matter if we set this cap, even if MMC_CAP2_CQE > isn't set? You can probably skip the check above. Will remove MMC_CAP2_CQE check here. > > > + host->caps2 |= MMC_CAP2_CQE_DCMD; > > + } > > > > /* Must be after "non-removable" check */ > > if (device_property_read_u32(dev, "fixed-emmc-driver-type", &drv_type) == 0) { > > -- > > 1.9.1 > > Kind regards > Uffe ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 1/4] mmc: core: expose MMC_CAP2_CQE* to dt @ 2020-03-09 23:13 ` Chun-Hung Wu 0 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-03-09 23:13 UTC (permalink / raw) To: Ulf Hansson Cc: Mark Rutland, Kate Stewart, wsd_upstream, linux-mmc, Linus Walleij, Pavel Machek, Chaotian Jing, Android Kernel Team, Pan Bian, DTML, Martin Blumenstingl, Rob Herring, moderated list:ARM/Mediatek SoC support, Matthias Brugger, Thomas Gleixner, Stanley Chu, Allison Randal, Linux ARM, Mathieu Malaterre, Greg Kroah-Hartman, Kuohong Wang, Linux Kernel Mailing List On Wed, 2020-03-04 at 14:04 +0100, Ulf Hansson wrote: > On Mon, 17 Feb 2020 at 07:56, Chun-Hung Wu <chun-hung.wu@mediatek.com> wrote: > > > > Expose MMC_CAP2_CQE and MMC_CAP2_CQE_DCMD > > to host->caps2 if > > 1. "supports-cqe" is defined in dt and > > 2. "disable-cqe-dcmd" is not defined in dt. > > Both of these DT properties are defined as common mmc DT properties, > so the above isn't really correct. Please clarify this. Yes, the properties is common. But I think the "supports-cqe" or "disable-cqe-dcmd" is defined in vendor's mmc dt, not common mmc dt? Don't know what's wrong with the above description, any suggestion? > > Moreover, I suggest to update commit message header into "mmc: core: > Extend mmc_of_parse() to parse CQE bindings", as I think it better > describes the change. Thanks, I think the commit message you provide is better, will change it in v4. > > > > > Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> > > --- > > drivers/mmc/core/host.c | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c > > index 105b7a7..efb0dbe 100644 > > --- a/drivers/mmc/core/host.c > > +++ b/drivers/mmc/core/host.c > > @@ -319,6 +319,14 @@ int mmc_of_parse(struct mmc_host *host) > > host->caps2 |= MMC_CAP2_NO_SD; > > if (device_property_read_bool(dev, "no-mmc")) > > host->caps2 |= MMC_CAP2_NO_MMC; > > + if (device_property_read_bool(dev, "supports-cqe")) > > + host->caps2 |= MMC_CAP2_CQE; > > + > > + /* Must be after "supports-cqe" check */ > > + if (!device_property_read_bool(dev, "disable-cqe-dcmd")) { > > + if (host->caps2 & MMC_CAP2_CQE) > > Does it really doesn't matter if we set this cap, even if MMC_CAP2_CQE > isn't set? You can probably skip the check above. Will remove MMC_CAP2_CQE check here. > > > + host->caps2 |= MMC_CAP2_CQE_DCMD; > > + } > > > > /* Must be after "non-removable" check */ > > if (device_property_read_u32(dev, "fixed-emmc-driver-type", &drv_type) == 0) { > > -- > > 1.9.1 > > Kind regards > Uffe _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 1/4] mmc: core: expose MMC_CAP2_CQE* to dt @ 2020-03-09 23:13 ` Chun-Hung Wu 0 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-03-09 23:13 UTC (permalink / raw) To: Ulf Hansson Cc: Mark Rutland, Kate Stewart, wsd_upstream, linux-mmc, Linus Walleij, Pavel Machek, Chaotian Jing, Android Kernel Team, Pan Bian, DTML, Martin Blumenstingl, Rob Herring, moderated list:ARM/Mediatek SoC support, Matthias Brugger, Thomas Gleixner, Stanley Chu, Allison Randal, Linux ARM, Mathieu Malaterre, Greg Kroah-Hartman, Kuohong Wang, Linux Kernel Mailing List On Wed, 2020-03-04 at 14:04 +0100, Ulf Hansson wrote: > On Mon, 17 Feb 2020 at 07:56, Chun-Hung Wu <chun-hung.wu@mediatek.com> wrote: > > > > Expose MMC_CAP2_CQE and MMC_CAP2_CQE_DCMD > > to host->caps2 if > > 1. "supports-cqe" is defined in dt and > > 2. "disable-cqe-dcmd" is not defined in dt. > > Both of these DT properties are defined as common mmc DT properties, > so the above isn't really correct. Please clarify this. Yes, the properties is common. But I think the "supports-cqe" or "disable-cqe-dcmd" is defined in vendor's mmc dt, not common mmc dt? Don't know what's wrong with the above description, any suggestion? > > Moreover, I suggest to update commit message header into "mmc: core: > Extend mmc_of_parse() to parse CQE bindings", as I think it better > describes the change. Thanks, I think the commit message you provide is better, will change it in v4. > > > > > Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> > > --- > > drivers/mmc/core/host.c | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c > > index 105b7a7..efb0dbe 100644 > > --- a/drivers/mmc/core/host.c > > +++ b/drivers/mmc/core/host.c > > @@ -319,6 +319,14 @@ int mmc_of_parse(struct mmc_host *host) > > host->caps2 |= MMC_CAP2_NO_SD; > > if (device_property_read_bool(dev, "no-mmc")) > > host->caps2 |= MMC_CAP2_NO_MMC; > > + if (device_property_read_bool(dev, "supports-cqe")) > > + host->caps2 |= MMC_CAP2_CQE; > > + > > + /* Must be after "supports-cqe" check */ > > + if (!device_property_read_bool(dev, "disable-cqe-dcmd")) { > > + if (host->caps2 & MMC_CAP2_CQE) > > Does it really doesn't matter if we set this cap, even if MMC_CAP2_CQE > isn't set? You can probably skip the check above. Will remove MMC_CAP2_CQE check here. > > > + host->caps2 |= MMC_CAP2_CQE_DCMD; > > + } > > > > /* Must be after "non-removable" check */ > > if (device_property_read_u32(dev, "fixed-emmc-driver-type", &drv_type) == 0) { > > -- > > 1.9.1 > > Kind regards > Uffe _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v3 2/4] mmc: mediatek: refine msdc timeout api 2020-02-17 6:56 ` Chun-Hung Wu (?) @ 2020-02-17 6:56 ` Chun-Hung Wu -1 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-02-17 6:56 UTC (permalink / raw) To: Chaotian Jing, Ulf Hansson, Rob Herring, Mark Rutland, Matthias Brugger, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang Cc: kernel-team, linux-kernel, linux-mmc, linux-mediatek, devicetree, wsd_upstream, linux-arm-kernel, Chun-Hung Wu Extract msdc timeout api common part to have better code architecture and avoid redundent code. Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> --- drivers/mmc/host/mtk-sd.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 189e426..127b0cf 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -698,21 +698,21 @@ static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) } } -/* clock control primitives */ -static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) +static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) { - u32 timeout, clk_ns; + u64 timeout, clk_ns; u32 mode = 0; - host->timeout_ns = ns; - host->timeout_clks = clks; if (host->mmc->actual_clock == 0) { timeout = 0; } else { - clk_ns = 1000000000UL / host->mmc->actual_clock; - timeout = (ns + clk_ns - 1) / clk_ns + clks; + clk_ns = 1000000000ULL; + do_div(clk_ns, host->mmc->actual_clock); + timeout = ns + clk_ns - 1; + do_div(timeout, clk_ns); + timeout += clks; /* in 1048576 sclk cycle unit */ - timeout = (timeout + (0x1 << 20) - 1) >> 20; + timeout = DIV_ROUND_UP(timeout, (0x1 << 20)); if (host->dev_comp->clk_div_bits == 8) sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode); @@ -722,9 +722,21 @@ static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) /*DDR mode will double the clk cycles for data timeout */ timeout = mode >= 2 ? timeout * 2 : timeout; timeout = timeout > 1 ? timeout - 1 : 0; - timeout = timeout > 255 ? 255 : timeout; } - sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); + return timeout; +} + +/* clock control primitives */ +static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) +{ + u64 timeout; + + host->timeout_ns = ns; + host->timeout_clks = clks; + + timeout = msdc_timeout_cal(host, ns, clks); + sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, + (u32)(timeout > 255 ? 255 : timeout)); } static void msdc_gate_clock(struct msdc_host *host) -- 1.9.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v3 2/4] mmc: mediatek: refine msdc timeout api @ 2020-02-17 6:56 ` Chun-Hung Wu 0 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-02-17 6:56 UTC (permalink / raw) To: Chaotian Jing, Ulf Hansson, Rob Herring, Mark Rutland, Matthias Brugger, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang Cc: devicetree, wsd_upstream, Chun-Hung Wu, linux-mmc, linux-kernel, linux-mediatek, kernel-team, linux-arm-kernel Extract msdc timeout api common part to have better code architecture and avoid redundent code. Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> --- drivers/mmc/host/mtk-sd.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 189e426..127b0cf 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -698,21 +698,21 @@ static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) } } -/* clock control primitives */ -static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) +static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) { - u32 timeout, clk_ns; + u64 timeout, clk_ns; u32 mode = 0; - host->timeout_ns = ns; - host->timeout_clks = clks; if (host->mmc->actual_clock == 0) { timeout = 0; } else { - clk_ns = 1000000000UL / host->mmc->actual_clock; - timeout = (ns + clk_ns - 1) / clk_ns + clks; + clk_ns = 1000000000ULL; + do_div(clk_ns, host->mmc->actual_clock); + timeout = ns + clk_ns - 1; + do_div(timeout, clk_ns); + timeout += clks; /* in 1048576 sclk cycle unit */ - timeout = (timeout + (0x1 << 20) - 1) >> 20; + timeout = DIV_ROUND_UP(timeout, (0x1 << 20)); if (host->dev_comp->clk_div_bits == 8) sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode); @@ -722,9 +722,21 @@ static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) /*DDR mode will double the clk cycles for data timeout */ timeout = mode >= 2 ? timeout * 2 : timeout; timeout = timeout > 1 ? timeout - 1 : 0; - timeout = timeout > 255 ? 255 : timeout; } - sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); + return timeout; +} + +/* clock control primitives */ +static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) +{ + u64 timeout; + + host->timeout_ns = ns; + host->timeout_clks = clks; + + timeout = msdc_timeout_cal(host, ns, clks); + sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, + (u32)(timeout > 255 ? 255 : timeout)); } static void msdc_gate_clock(struct msdc_host *host) -- 1.9.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v3 2/4] mmc: mediatek: refine msdc timeout api @ 2020-02-17 6:56 ` Chun-Hung Wu 0 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-02-17 6:56 UTC (permalink / raw) To: Chaotian Jing, Ulf Hansson, Rob Herring, Mark Rutland, Matthias Brugger, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang Cc: devicetree, wsd_upstream, Chun-Hung Wu, linux-mmc, linux-kernel, linux-mediatek, kernel-team, linux-arm-kernel Extract msdc timeout api common part to have better code architecture and avoid redundent code. Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> --- drivers/mmc/host/mtk-sd.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 189e426..127b0cf 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -698,21 +698,21 @@ static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) } } -/* clock control primitives */ -static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) +static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) { - u32 timeout, clk_ns; + u64 timeout, clk_ns; u32 mode = 0; - host->timeout_ns = ns; - host->timeout_clks = clks; if (host->mmc->actual_clock == 0) { timeout = 0; } else { - clk_ns = 1000000000UL / host->mmc->actual_clock; - timeout = (ns + clk_ns - 1) / clk_ns + clks; + clk_ns = 1000000000ULL; + do_div(clk_ns, host->mmc->actual_clock); + timeout = ns + clk_ns - 1; + do_div(timeout, clk_ns); + timeout += clks; /* in 1048576 sclk cycle unit */ - timeout = (timeout + (0x1 << 20) - 1) >> 20; + timeout = DIV_ROUND_UP(timeout, (0x1 << 20)); if (host->dev_comp->clk_div_bits == 8) sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode); @@ -722,9 +722,21 @@ static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) /*DDR mode will double the clk cycles for data timeout */ timeout = mode >= 2 ? timeout * 2 : timeout; timeout = timeout > 1 ? timeout - 1 : 0; - timeout = timeout > 255 ? 255 : timeout; } - sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); + return timeout; +} + +/* clock control primitives */ +static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) +{ + u64 timeout; + + host->timeout_ns = ns; + host->timeout_clks = clks; + + timeout = msdc_timeout_cal(host, ns, clks); + sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, + (u32)(timeout > 255 ? 255 : timeout)); } static void msdc_gate_clock(struct msdc_host *host) -- 1.9.1 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v3 3/4] mmc: mediatek: command queue support 2020-02-17 6:56 ` Chun-Hung Wu (?) @ 2020-02-17 6:56 ` Chun-Hung Wu -1 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-02-17 6:56 UTC (permalink / raw) To: Chaotian Jing, Ulf Hansson, Rob Herring, Mark Rutland, Matthias Brugger, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang Cc: kernel-team, linux-kernel, linux-mmc, linux-mediatek, devicetree, wsd_upstream, linux-arm-kernel, Chun-Hung Wu Support command queue for mt6779 platform. a. Add msdc_set_busy_timeout() to calculate emmc write timeout b. Connect mtk msdc driver to cqhci driver through host->cq_host->ops = &msdc_cmdq_ops; c. msdc_cmdq_irq() will link up with cqchi_irq(). Besides, it provides more irq error messages like RSPCRCERR/CMDTO/DATACRCERR/DATTMO. d. Use the options below to separate support for CQHCI or not, because some of our platform does not support CQHCI hence no kernel option: CONFIG_MMC_CQHCI. #if IS_ENABLED(CONFIG_MMC_CQHCI) XXX //Support CQHCI #else XXX //Not support CQHCI #endif Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> --- drivers/mmc/host/mtk-sd.c | 119 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 127b0cf..b132397 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -31,6 +31,8 @@ #include <linux/mmc/sdio.h> #include <linux/mmc/slot-gpio.h> +#include "cqhci.h" + #define MAX_BD_NUM 1024 /*--------------------------------------------------------------------------*/ @@ -151,6 +153,7 @@ #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ +#define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ /* MSDC_INTEN mask */ #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ @@ -181,6 +184,7 @@ /* SDC_CFG mask */ #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ +#define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ #define SDC_CFG_SDIO (0x1 << 19) /* RW */ #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ @@ -228,6 +232,7 @@ #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ +#define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ @@ -431,6 +436,7 @@ struct msdc_host { struct msdc_save_para save_para; /* used when gate HCLK */ struct msdc_tune_para def_tune_para; /* default tune setting */ struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ + struct cqhci_host *cq_host; }; static const struct mtk_mmc_compatible mt8135_compat = { @@ -527,6 +533,18 @@ struct msdc_host { .use_internal_cd = true, }; +static const struct mtk_mmc_compatible mt6779_compat = { + .clk_div_bits = 12, + .hs400_tune = false, + .pad_tune_reg = MSDC_PAD_TUNE0, + .async_fifo = true, + .data_tune = true, + .busy_check = true, + .stop_clk_fix = true, + .enhance_rx = true, + .support_64g = true, +}; + static const struct of_device_id msdc_of_ids[] = { { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, @@ -536,6 +554,7 @@ struct msdc_host { { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, + { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, {} }; MODULE_DEVICE_TABLE(of, msdc_of_ids); @@ -739,6 +758,15 @@ static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) (u32)(timeout > 255 ? 255 : timeout)); } +static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) +{ + u64 timeout; + + timeout = msdc_timeout_cal(host, ns, clks); + sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, + (u32)(timeout > 8191 ? 8191 : timeout)); +} + static void msdc_gate_clock(struct msdc_host *host) { clk_disable_unprepare(host->src_clk_cg); @@ -1425,6 +1453,36 @@ static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) pm_runtime_put_noidle(host->dev); } +#if IS_ENABLED(CONFIG_MMC_CQHCI) +static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) +{ + int cmd_err = 0, dat_err = 0; + + if (intsts & MSDC_INT_RSPCRCERR) { + cmd_err = (unsigned int)-EILSEQ; + dev_err(host->dev, "%s: CMD CRC ERR", __func__); + } else if (intsts & MSDC_INT_CMDTMO) { + cmd_err = (unsigned int)-ETIMEDOUT; + dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); + } + + if (intsts & MSDC_INT_DATCRCERR) { + dat_err = (unsigned int)-EILSEQ; + dev_err(host->dev, "%s: DATA CRC ERR", __func__); + } else if (intsts & MSDC_INT_DATTMO) { + dat_err = (unsigned int)-ETIMEDOUT; + dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); + } + + if (cmd_err || dat_err) { + dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", + cmd_err, dat_err, intsts); + } + + return cqhci_irq(host->mmc, 0, cmd_err, dat_err); +} +#endif + static irqreturn_t msdc_irq(int irq, void *dev_id) { struct msdc_host *host = (struct msdc_host *) dev_id; @@ -1461,6 +1519,16 @@ static irqreturn_t msdc_irq(int irq, void *dev_id) if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) break; +#if IS_ENABLED(CONFIG_MMC_CQHCI) + if ((host->mmc->caps2 & MMC_CAP2_CQE) && + (events & MSDC_INT_CMDQ)) { + msdc_cmdq_irq(host, events); + /* clear interrupts */ + writel(events, host->base + MSDC_INT); + return IRQ_HANDLED; + } +#endif + if (!mrq) { dev_err(host->dev, "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", @@ -2144,6 +2212,36 @@ static int msdc_get_cd(struct mmc_host *mmc) return !val; } +static void msdc_cqe_enable(struct mmc_host *mmc) +{ + struct msdc_host *host = mmc_priv(mmc); + + /* enable cmdq irq */ + writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); + /* enable busy check */ + sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); + /* default write data / busy timeout 20s */ + msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); + /* default read data timeout 1s */ + msdc_set_timeout(host, 1000000000ULL, 0); +} + +void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) +{ + struct msdc_host *host = mmc_priv(mmc); + + /* disable cmdq irq */ + sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); + /* disable busy check */ + sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); + + if (recovery) { + sdr_set_field(host->base + MSDC_DMA_CTRL, + MSDC_DMA_CTRL_STOP, 1); + msdc_reset_hw(host); + } +} + static const struct mmc_host_ops mt_msdc_ops = { .post_req = msdc_post_req, .pre_req = msdc_pre_req, @@ -2160,6 +2258,11 @@ static int msdc_get_cd(struct mmc_host *mmc) .hw_reset = msdc_hw_reset, }; +static const struct cqhci_host_ops msdc_cmdq_ops = { + .enable = msdc_cqe_enable, + .disable = msdc_cqe_disable, +}; + static void msdc_of_property_parse(struct platform_device *pdev, struct msdc_host *host) { @@ -2311,6 +2414,22 @@ static int msdc_drv_probe(struct platform_device *pdev) host->dma_mask = DMA_BIT_MASK(32); mmc_dev(mmc)->dma_mask = &host->dma_mask; +#if IS_ENABLED(CONFIG_MMC_CQHCI) + if (mmc->caps2 & MMC_CAP2_CQE) { + host->cq_host = devm_kzalloc(host->mmc->parent, + sizeof(*host->cq_host), + GFP_KERNEL); + host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; + host->cq_host->mmio = host->base + 0x800; + host->cq_host->ops = &msdc_cmdq_ops; + cqhci_init(host->cq_host, mmc, true); + mmc->max_segs = 128; + /* cqhci 16bit length */ + /* 0 size, means 65536 so we don't have to -1 here */ + mmc->max_seg_size = 64 * 1024; + } +#endif + host->timeout_clks = 3 * 1048576; host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2 * sizeof(struct mt_gpdma_desc), -- 1.9.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v3 3/4] mmc: mediatek: command queue support @ 2020-02-17 6:56 ` Chun-Hung Wu 0 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-02-17 6:56 UTC (permalink / raw) To: Chaotian Jing, Ulf Hansson, Rob Herring, Mark Rutland, Matthias Brugger, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang Cc: devicetree, wsd_upstream, Chun-Hung Wu, linux-mmc, linux-kernel, linux-mediatek, kernel-team, linux-arm-kernel Support command queue for mt6779 platform. a. Add msdc_set_busy_timeout() to calculate emmc write timeout b. Connect mtk msdc driver to cqhci driver through host->cq_host->ops = &msdc_cmdq_ops; c. msdc_cmdq_irq() will link up with cqchi_irq(). Besides, it provides more irq error messages like RSPCRCERR/CMDTO/DATACRCERR/DATTMO. d. Use the options below to separate support for CQHCI or not, because some of our platform does not support CQHCI hence no kernel option: CONFIG_MMC_CQHCI. #if IS_ENABLED(CONFIG_MMC_CQHCI) XXX //Support CQHCI #else XXX //Not support CQHCI #endif Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> --- drivers/mmc/host/mtk-sd.c | 119 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 127b0cf..b132397 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -31,6 +31,8 @@ #include <linux/mmc/sdio.h> #include <linux/mmc/slot-gpio.h> +#include "cqhci.h" + #define MAX_BD_NUM 1024 /*--------------------------------------------------------------------------*/ @@ -151,6 +153,7 @@ #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ +#define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ /* MSDC_INTEN mask */ #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ @@ -181,6 +184,7 @@ /* SDC_CFG mask */ #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ +#define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ #define SDC_CFG_SDIO (0x1 << 19) /* RW */ #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ @@ -228,6 +232,7 @@ #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ +#define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ @@ -431,6 +436,7 @@ struct msdc_host { struct msdc_save_para save_para; /* used when gate HCLK */ struct msdc_tune_para def_tune_para; /* default tune setting */ struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ + struct cqhci_host *cq_host; }; static const struct mtk_mmc_compatible mt8135_compat = { @@ -527,6 +533,18 @@ struct msdc_host { .use_internal_cd = true, }; +static const struct mtk_mmc_compatible mt6779_compat = { + .clk_div_bits = 12, + .hs400_tune = false, + .pad_tune_reg = MSDC_PAD_TUNE0, + .async_fifo = true, + .data_tune = true, + .busy_check = true, + .stop_clk_fix = true, + .enhance_rx = true, + .support_64g = true, +}; + static const struct of_device_id msdc_of_ids[] = { { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, @@ -536,6 +554,7 @@ struct msdc_host { { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, + { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, {} }; MODULE_DEVICE_TABLE(of, msdc_of_ids); @@ -739,6 +758,15 @@ static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) (u32)(timeout > 255 ? 255 : timeout)); } +static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) +{ + u64 timeout; + + timeout = msdc_timeout_cal(host, ns, clks); + sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, + (u32)(timeout > 8191 ? 8191 : timeout)); +} + static void msdc_gate_clock(struct msdc_host *host) { clk_disable_unprepare(host->src_clk_cg); @@ -1425,6 +1453,36 @@ static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) pm_runtime_put_noidle(host->dev); } +#if IS_ENABLED(CONFIG_MMC_CQHCI) +static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) +{ + int cmd_err = 0, dat_err = 0; + + if (intsts & MSDC_INT_RSPCRCERR) { + cmd_err = (unsigned int)-EILSEQ; + dev_err(host->dev, "%s: CMD CRC ERR", __func__); + } else if (intsts & MSDC_INT_CMDTMO) { + cmd_err = (unsigned int)-ETIMEDOUT; + dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); + } + + if (intsts & MSDC_INT_DATCRCERR) { + dat_err = (unsigned int)-EILSEQ; + dev_err(host->dev, "%s: DATA CRC ERR", __func__); + } else if (intsts & MSDC_INT_DATTMO) { + dat_err = (unsigned int)-ETIMEDOUT; + dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); + } + + if (cmd_err || dat_err) { + dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", + cmd_err, dat_err, intsts); + } + + return cqhci_irq(host->mmc, 0, cmd_err, dat_err); +} +#endif + static irqreturn_t msdc_irq(int irq, void *dev_id) { struct msdc_host *host = (struct msdc_host *) dev_id; @@ -1461,6 +1519,16 @@ static irqreturn_t msdc_irq(int irq, void *dev_id) if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) break; +#if IS_ENABLED(CONFIG_MMC_CQHCI) + if ((host->mmc->caps2 & MMC_CAP2_CQE) && + (events & MSDC_INT_CMDQ)) { + msdc_cmdq_irq(host, events); + /* clear interrupts */ + writel(events, host->base + MSDC_INT); + return IRQ_HANDLED; + } +#endif + if (!mrq) { dev_err(host->dev, "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", @@ -2144,6 +2212,36 @@ static int msdc_get_cd(struct mmc_host *mmc) return !val; } +static void msdc_cqe_enable(struct mmc_host *mmc) +{ + struct msdc_host *host = mmc_priv(mmc); + + /* enable cmdq irq */ + writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); + /* enable busy check */ + sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); + /* default write data / busy timeout 20s */ + msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); + /* default read data timeout 1s */ + msdc_set_timeout(host, 1000000000ULL, 0); +} + +void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) +{ + struct msdc_host *host = mmc_priv(mmc); + + /* disable cmdq irq */ + sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); + /* disable busy check */ + sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); + + if (recovery) { + sdr_set_field(host->base + MSDC_DMA_CTRL, + MSDC_DMA_CTRL_STOP, 1); + msdc_reset_hw(host); + } +} + static const struct mmc_host_ops mt_msdc_ops = { .post_req = msdc_post_req, .pre_req = msdc_pre_req, @@ -2160,6 +2258,11 @@ static int msdc_get_cd(struct mmc_host *mmc) .hw_reset = msdc_hw_reset, }; +static const struct cqhci_host_ops msdc_cmdq_ops = { + .enable = msdc_cqe_enable, + .disable = msdc_cqe_disable, +}; + static void msdc_of_property_parse(struct platform_device *pdev, struct msdc_host *host) { @@ -2311,6 +2414,22 @@ static int msdc_drv_probe(struct platform_device *pdev) host->dma_mask = DMA_BIT_MASK(32); mmc_dev(mmc)->dma_mask = &host->dma_mask; +#if IS_ENABLED(CONFIG_MMC_CQHCI) + if (mmc->caps2 & MMC_CAP2_CQE) { + host->cq_host = devm_kzalloc(host->mmc->parent, + sizeof(*host->cq_host), + GFP_KERNEL); + host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; + host->cq_host->mmio = host->base + 0x800; + host->cq_host->ops = &msdc_cmdq_ops; + cqhci_init(host->cq_host, mmc, true); + mmc->max_segs = 128; + /* cqhci 16bit length */ + /* 0 size, means 65536 so we don't have to -1 here */ + mmc->max_seg_size = 64 * 1024; + } +#endif + host->timeout_clks = 3 * 1048576; host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2 * sizeof(struct mt_gpdma_desc), -- 1.9.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v3 3/4] mmc: mediatek: command queue support @ 2020-02-17 6:56 ` Chun-Hung Wu 0 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-02-17 6:56 UTC (permalink / raw) To: Chaotian Jing, Ulf Hansson, Rob Herring, Mark Rutland, Matthias Brugger, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang Cc: devicetree, wsd_upstream, Chun-Hung Wu, linux-mmc, linux-kernel, linux-mediatek, kernel-team, linux-arm-kernel Support command queue for mt6779 platform. a. Add msdc_set_busy_timeout() to calculate emmc write timeout b. Connect mtk msdc driver to cqhci driver through host->cq_host->ops = &msdc_cmdq_ops; c. msdc_cmdq_irq() will link up with cqchi_irq(). Besides, it provides more irq error messages like RSPCRCERR/CMDTO/DATACRCERR/DATTMO. d. Use the options below to separate support for CQHCI or not, because some of our platform does not support CQHCI hence no kernel option: CONFIG_MMC_CQHCI. #if IS_ENABLED(CONFIG_MMC_CQHCI) XXX //Support CQHCI #else XXX //Not support CQHCI #endif Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> --- drivers/mmc/host/mtk-sd.c | 119 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 127b0cf..b132397 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -31,6 +31,8 @@ #include <linux/mmc/sdio.h> #include <linux/mmc/slot-gpio.h> +#include "cqhci.h" + #define MAX_BD_NUM 1024 /*--------------------------------------------------------------------------*/ @@ -151,6 +153,7 @@ #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ +#define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ /* MSDC_INTEN mask */ #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ @@ -181,6 +184,7 @@ /* SDC_CFG mask */ #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ +#define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ #define SDC_CFG_SDIO (0x1 << 19) /* RW */ #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ @@ -228,6 +232,7 @@ #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ +#define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ @@ -431,6 +436,7 @@ struct msdc_host { struct msdc_save_para save_para; /* used when gate HCLK */ struct msdc_tune_para def_tune_para; /* default tune setting */ struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ + struct cqhci_host *cq_host; }; static const struct mtk_mmc_compatible mt8135_compat = { @@ -527,6 +533,18 @@ struct msdc_host { .use_internal_cd = true, }; +static const struct mtk_mmc_compatible mt6779_compat = { + .clk_div_bits = 12, + .hs400_tune = false, + .pad_tune_reg = MSDC_PAD_TUNE0, + .async_fifo = true, + .data_tune = true, + .busy_check = true, + .stop_clk_fix = true, + .enhance_rx = true, + .support_64g = true, +}; + static const struct of_device_id msdc_of_ids[] = { { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, @@ -536,6 +554,7 @@ struct msdc_host { { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, + { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, {} }; MODULE_DEVICE_TABLE(of, msdc_of_ids); @@ -739,6 +758,15 @@ static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) (u32)(timeout > 255 ? 255 : timeout)); } +static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) +{ + u64 timeout; + + timeout = msdc_timeout_cal(host, ns, clks); + sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, + (u32)(timeout > 8191 ? 8191 : timeout)); +} + static void msdc_gate_clock(struct msdc_host *host) { clk_disable_unprepare(host->src_clk_cg); @@ -1425,6 +1453,36 @@ static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) pm_runtime_put_noidle(host->dev); } +#if IS_ENABLED(CONFIG_MMC_CQHCI) +static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) +{ + int cmd_err = 0, dat_err = 0; + + if (intsts & MSDC_INT_RSPCRCERR) { + cmd_err = (unsigned int)-EILSEQ; + dev_err(host->dev, "%s: CMD CRC ERR", __func__); + } else if (intsts & MSDC_INT_CMDTMO) { + cmd_err = (unsigned int)-ETIMEDOUT; + dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); + } + + if (intsts & MSDC_INT_DATCRCERR) { + dat_err = (unsigned int)-EILSEQ; + dev_err(host->dev, "%s: DATA CRC ERR", __func__); + } else if (intsts & MSDC_INT_DATTMO) { + dat_err = (unsigned int)-ETIMEDOUT; + dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); + } + + if (cmd_err || dat_err) { + dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", + cmd_err, dat_err, intsts); + } + + return cqhci_irq(host->mmc, 0, cmd_err, dat_err); +} +#endif + static irqreturn_t msdc_irq(int irq, void *dev_id) { struct msdc_host *host = (struct msdc_host *) dev_id; @@ -1461,6 +1519,16 @@ static irqreturn_t msdc_irq(int irq, void *dev_id) if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) break; +#if IS_ENABLED(CONFIG_MMC_CQHCI) + if ((host->mmc->caps2 & MMC_CAP2_CQE) && + (events & MSDC_INT_CMDQ)) { + msdc_cmdq_irq(host, events); + /* clear interrupts */ + writel(events, host->base + MSDC_INT); + return IRQ_HANDLED; + } +#endif + if (!mrq) { dev_err(host->dev, "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", @@ -2144,6 +2212,36 @@ static int msdc_get_cd(struct mmc_host *mmc) return !val; } +static void msdc_cqe_enable(struct mmc_host *mmc) +{ + struct msdc_host *host = mmc_priv(mmc); + + /* enable cmdq irq */ + writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); + /* enable busy check */ + sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); + /* default write data / busy timeout 20s */ + msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); + /* default read data timeout 1s */ + msdc_set_timeout(host, 1000000000ULL, 0); +} + +void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) +{ + struct msdc_host *host = mmc_priv(mmc); + + /* disable cmdq irq */ + sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); + /* disable busy check */ + sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); + + if (recovery) { + sdr_set_field(host->base + MSDC_DMA_CTRL, + MSDC_DMA_CTRL_STOP, 1); + msdc_reset_hw(host); + } +} + static const struct mmc_host_ops mt_msdc_ops = { .post_req = msdc_post_req, .pre_req = msdc_pre_req, @@ -2160,6 +2258,11 @@ static int msdc_get_cd(struct mmc_host *mmc) .hw_reset = msdc_hw_reset, }; +static const struct cqhci_host_ops msdc_cmdq_ops = { + .enable = msdc_cqe_enable, + .disable = msdc_cqe_disable, +}; + static void msdc_of_property_parse(struct platform_device *pdev, struct msdc_host *host) { @@ -2311,6 +2414,22 @@ static int msdc_drv_probe(struct platform_device *pdev) host->dma_mask = DMA_BIT_MASK(32); mmc_dev(mmc)->dma_mask = &host->dma_mask; +#if IS_ENABLED(CONFIG_MMC_CQHCI) + if (mmc->caps2 & MMC_CAP2_CQE) { + host->cq_host = devm_kzalloc(host->mmc->parent, + sizeof(*host->cq_host), + GFP_KERNEL); + host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; + host->cq_host->mmio = host->base + 0x800; + host->cq_host->ops = &msdc_cmdq_ops; + cqhci_init(host->cq_host, mmc, true); + mmc->max_segs = 128; + /* cqhci 16bit length */ + /* 0 size, means 65536 so we don't have to -1 here */ + mmc->max_seg_size = 64 * 1024; + } +#endif + host->timeout_clks = 3 * 1048576; host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2 * sizeof(struct mt_gpdma_desc), -- 1.9.1 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH v3 3/4] mmc: mediatek: command queue support 2020-02-17 6:56 ` Chun-Hung Wu (?) @ 2020-02-17 9:47 ` Matthias Brugger -1 siblings, 0 replies; 33+ messages in thread From: Matthias Brugger @ 2020-02-17 9:47 UTC (permalink / raw) To: Chun-Hung Wu, Chaotian Jing, Ulf Hansson, Rob Herring, Mark Rutland, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang Cc: kernel-team, linux-kernel, linux-mmc, linux-mediatek, devicetree, wsd_upstream, linux-arm-kernel On 17/02/2020 07:56, Chun-Hung Wu wrote: > Support command queue for mt6779 platform. > a. Add msdc_set_busy_timeout() to calculate emmc write timeout > b. Connect mtk msdc driver to cqhci driver through > host->cq_host->ops = &msdc_cmdq_ops; > c. msdc_cmdq_irq() will link up with cqchi_irq(). Besides, it provides > more irq error messages like RSPCRCERR/CMDTO/DATACRCERR/DATTMO. > d. Use the options below to separate support for CQHCI or not, because > some of our platform does not support CQHCI hence no kernel option: > CONFIG_MMC_CQHCI. > #if IS_ENABLED(CONFIG_MMC_CQHCI) > XXX //Support CQHCI > #else > XXX //Not support CQHCI > #endif > > Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> > --- > drivers/mmc/host/mtk-sd.c | 119 ++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 119 insertions(+) > > diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c > index 127b0cf..b132397 100644 > --- a/drivers/mmc/host/mtk-sd.c > +++ b/drivers/mmc/host/mtk-sd.c > @@ -31,6 +31,8 @@ > #include <linux/mmc/sdio.h> > #include <linux/mmc/slot-gpio.h> > > +#include "cqhci.h" > + > #define MAX_BD_NUM 1024 > > /*--------------------------------------------------------------------------*/ > @@ -151,6 +153,7 @@ > #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ > #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ > #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ > +#define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ > > /* MSDC_INTEN mask */ > #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ > @@ -181,6 +184,7 @@ > /* SDC_CFG mask */ > #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ > #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ > +#define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ > #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ > #define SDC_CFG_SDIO (0x1 << 19) /* RW */ > #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ > @@ -228,6 +232,7 @@ > #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ > #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ > > +#define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ > #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ > > #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ > @@ -431,6 +436,7 @@ struct msdc_host { > struct msdc_save_para save_para; /* used when gate HCLK */ > struct msdc_tune_para def_tune_para; /* default tune setting */ > struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ > + struct cqhci_host *cq_host; > }; > > static const struct mtk_mmc_compatible mt8135_compat = { > @@ -527,6 +533,18 @@ struct msdc_host { > .use_internal_cd = true, > }; > > +static const struct mtk_mmc_compatible mt6779_compat = { > + .clk_div_bits = 12, I suppose .hs400_tune = false, and with this the driver is basically the same as mt8183. So you should put in the binding description: "mediatek,mt6779-mmc" "mediatek,mt8183-mmc": for mmc host ip compatible with mt6779 > + .hs400_tune = false, > + .pad_tune_reg = MSDC_PAD_TUNE0, > + .async_fifo = true, > + .data_tune = true, > + .busy_check = true, > + .stop_clk_fix = true, > + .enhance_rx = true, > + .support_64g = true, > +}; > + > static const struct of_device_id msdc_of_ids[] = { > { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, > { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, > @@ -536,6 +554,7 @@ struct msdc_host { > { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, > { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, > { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, > + { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, With the above mentioned, not needed. The driver will use the fallback compatible mt8183-mmc. If in the future we find anything special with mt6779-mmc we can still add an entry here. Regards, Matthias > {} > }; > MODULE_DEVICE_TABLE(of, msdc_of_ids); > @@ -739,6 +758,15 @@ static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) > (u32)(timeout > 255 ? 255 : timeout)); > } > > +static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) > +{ > + u64 timeout; > + > + timeout = msdc_timeout_cal(host, ns, clks); > + sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, > + (u32)(timeout > 8191 ? 8191 : timeout)); > +} > + > static void msdc_gate_clock(struct msdc_host *host) > { > clk_disable_unprepare(host->src_clk_cg); > @@ -1425,6 +1453,36 @@ static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) > pm_runtime_put_noidle(host->dev); > } > > +#if IS_ENABLED(CONFIG_MMC_CQHCI) > +static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) > +{ > + int cmd_err = 0, dat_err = 0; > + > + if (intsts & MSDC_INT_RSPCRCERR) { > + cmd_err = (unsigned int)-EILSEQ; > + dev_err(host->dev, "%s: CMD CRC ERR", __func__); > + } else if (intsts & MSDC_INT_CMDTMO) { > + cmd_err = (unsigned int)-ETIMEDOUT; > + dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); > + } > + > + if (intsts & MSDC_INT_DATCRCERR) { > + dat_err = (unsigned int)-EILSEQ; > + dev_err(host->dev, "%s: DATA CRC ERR", __func__); > + } else if (intsts & MSDC_INT_DATTMO) { > + dat_err = (unsigned int)-ETIMEDOUT; > + dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); > + } > + > + if (cmd_err || dat_err) { > + dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", > + cmd_err, dat_err, intsts); > + } > + > + return cqhci_irq(host->mmc, 0, cmd_err, dat_err); > +} > +#endif > + > static irqreturn_t msdc_irq(int irq, void *dev_id) > { > struct msdc_host *host = (struct msdc_host *) dev_id; > @@ -1461,6 +1519,16 @@ static irqreturn_t msdc_irq(int irq, void *dev_id) > if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) > break; > > +#if IS_ENABLED(CONFIG_MMC_CQHCI) > + if ((host->mmc->caps2 & MMC_CAP2_CQE) && > + (events & MSDC_INT_CMDQ)) { > + msdc_cmdq_irq(host, events); > + /* clear interrupts */ > + writel(events, host->base + MSDC_INT); > + return IRQ_HANDLED; > + } > +#endif > + > if (!mrq) { > dev_err(host->dev, > "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", > @@ -2144,6 +2212,36 @@ static int msdc_get_cd(struct mmc_host *mmc) > return !val; > } > > +static void msdc_cqe_enable(struct mmc_host *mmc) > +{ > + struct msdc_host *host = mmc_priv(mmc); > + > + /* enable cmdq irq */ > + writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); > + /* enable busy check */ > + sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); > + /* default write data / busy timeout 20s */ > + msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); > + /* default read data timeout 1s */ > + msdc_set_timeout(host, 1000000000ULL, 0); > +} > + > +void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) > +{ > + struct msdc_host *host = mmc_priv(mmc); > + > + /* disable cmdq irq */ > + sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); > + /* disable busy check */ > + sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); > + > + if (recovery) { > + sdr_set_field(host->base + MSDC_DMA_CTRL, > + MSDC_DMA_CTRL_STOP, 1); > + msdc_reset_hw(host); > + } > +} > + > static const struct mmc_host_ops mt_msdc_ops = { > .post_req = msdc_post_req, > .pre_req = msdc_pre_req, > @@ -2160,6 +2258,11 @@ static int msdc_get_cd(struct mmc_host *mmc) > .hw_reset = msdc_hw_reset, > }; > > +static const struct cqhci_host_ops msdc_cmdq_ops = { > + .enable = msdc_cqe_enable, > + .disable = msdc_cqe_disable, > +}; > + > static void msdc_of_property_parse(struct platform_device *pdev, > struct msdc_host *host) > { > @@ -2311,6 +2414,22 @@ static int msdc_drv_probe(struct platform_device *pdev) > host->dma_mask = DMA_BIT_MASK(32); > mmc_dev(mmc)->dma_mask = &host->dma_mask; > > +#if IS_ENABLED(CONFIG_MMC_CQHCI) > + if (mmc->caps2 & MMC_CAP2_CQE) { > + host->cq_host = devm_kzalloc(host->mmc->parent, > + sizeof(*host->cq_host), > + GFP_KERNEL); > + host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; > + host->cq_host->mmio = host->base + 0x800; > + host->cq_host->ops = &msdc_cmdq_ops; > + cqhci_init(host->cq_host, mmc, true); > + mmc->max_segs = 128; > + /* cqhci 16bit length */ > + /* 0 size, means 65536 so we don't have to -1 here */ > + mmc->max_seg_size = 64 * 1024; > + } > +#endif > + > host->timeout_clks = 3 * 1048576; > host->dma.gpd = dma_alloc_coherent(&pdev->dev, > 2 * sizeof(struct mt_gpdma_desc), > ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 3/4] mmc: mediatek: command queue support @ 2020-02-17 9:47 ` Matthias Brugger 0 siblings, 0 replies; 33+ messages in thread From: Matthias Brugger @ 2020-02-17 9:47 UTC (permalink / raw) To: Chun-Hung Wu, Chaotian Jing, Ulf Hansson, Rob Herring, Mark Rutland, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang Cc: devicetree, wsd_upstream, linux-mmc, linux-kernel, linux-mediatek, kernel-team, linux-arm-kernel On 17/02/2020 07:56, Chun-Hung Wu wrote: > Support command queue for mt6779 platform. > a. Add msdc_set_busy_timeout() to calculate emmc write timeout > b. Connect mtk msdc driver to cqhci driver through > host->cq_host->ops = &msdc_cmdq_ops; > c. msdc_cmdq_irq() will link up with cqchi_irq(). Besides, it provides > more irq error messages like RSPCRCERR/CMDTO/DATACRCERR/DATTMO. > d. Use the options below to separate support for CQHCI or not, because > some of our platform does not support CQHCI hence no kernel option: > CONFIG_MMC_CQHCI. > #if IS_ENABLED(CONFIG_MMC_CQHCI) > XXX //Support CQHCI > #else > XXX //Not support CQHCI > #endif > > Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> > --- > drivers/mmc/host/mtk-sd.c | 119 ++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 119 insertions(+) > > diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c > index 127b0cf..b132397 100644 > --- a/drivers/mmc/host/mtk-sd.c > +++ b/drivers/mmc/host/mtk-sd.c > @@ -31,6 +31,8 @@ > #include <linux/mmc/sdio.h> > #include <linux/mmc/slot-gpio.h> > > +#include "cqhci.h" > + > #define MAX_BD_NUM 1024 > > /*--------------------------------------------------------------------------*/ > @@ -151,6 +153,7 @@ > #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ > #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ > #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ > +#define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ > > /* MSDC_INTEN mask */ > #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ > @@ -181,6 +184,7 @@ > /* SDC_CFG mask */ > #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ > #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ > +#define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ > #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ > #define SDC_CFG_SDIO (0x1 << 19) /* RW */ > #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ > @@ -228,6 +232,7 @@ > #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ > #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ > > +#define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ > #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ > > #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ > @@ -431,6 +436,7 @@ struct msdc_host { > struct msdc_save_para save_para; /* used when gate HCLK */ > struct msdc_tune_para def_tune_para; /* default tune setting */ > struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ > + struct cqhci_host *cq_host; > }; > > static const struct mtk_mmc_compatible mt8135_compat = { > @@ -527,6 +533,18 @@ struct msdc_host { > .use_internal_cd = true, > }; > > +static const struct mtk_mmc_compatible mt6779_compat = { > + .clk_div_bits = 12, I suppose .hs400_tune = false, and with this the driver is basically the same as mt8183. So you should put in the binding description: "mediatek,mt6779-mmc" "mediatek,mt8183-mmc": for mmc host ip compatible with mt6779 > + .hs400_tune = false, > + .pad_tune_reg = MSDC_PAD_TUNE0, > + .async_fifo = true, > + .data_tune = true, > + .busy_check = true, > + .stop_clk_fix = true, > + .enhance_rx = true, > + .support_64g = true, > +}; > + > static const struct of_device_id msdc_of_ids[] = { > { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, > { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, > @@ -536,6 +554,7 @@ struct msdc_host { > { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, > { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, > { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, > + { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, With the above mentioned, not needed. The driver will use the fallback compatible mt8183-mmc. If in the future we find anything special with mt6779-mmc we can still add an entry here. Regards, Matthias > {} > }; > MODULE_DEVICE_TABLE(of, msdc_of_ids); > @@ -739,6 +758,15 @@ static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) > (u32)(timeout > 255 ? 255 : timeout)); > } > > +static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) > +{ > + u64 timeout; > + > + timeout = msdc_timeout_cal(host, ns, clks); > + sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, > + (u32)(timeout > 8191 ? 8191 : timeout)); > +} > + > static void msdc_gate_clock(struct msdc_host *host) > { > clk_disable_unprepare(host->src_clk_cg); > @@ -1425,6 +1453,36 @@ static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) > pm_runtime_put_noidle(host->dev); > } > > +#if IS_ENABLED(CONFIG_MMC_CQHCI) > +static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) > +{ > + int cmd_err = 0, dat_err = 0; > + > + if (intsts & MSDC_INT_RSPCRCERR) { > + cmd_err = (unsigned int)-EILSEQ; > + dev_err(host->dev, "%s: CMD CRC ERR", __func__); > + } else if (intsts & MSDC_INT_CMDTMO) { > + cmd_err = (unsigned int)-ETIMEDOUT; > + dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); > + } > + > + if (intsts & MSDC_INT_DATCRCERR) { > + dat_err = (unsigned int)-EILSEQ; > + dev_err(host->dev, "%s: DATA CRC ERR", __func__); > + } else if (intsts & MSDC_INT_DATTMO) { > + dat_err = (unsigned int)-ETIMEDOUT; > + dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); > + } > + > + if (cmd_err || dat_err) { > + dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", > + cmd_err, dat_err, intsts); > + } > + > + return cqhci_irq(host->mmc, 0, cmd_err, dat_err); > +} > +#endif > + > static irqreturn_t msdc_irq(int irq, void *dev_id) > { > struct msdc_host *host = (struct msdc_host *) dev_id; > @@ -1461,6 +1519,16 @@ static irqreturn_t msdc_irq(int irq, void *dev_id) > if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) > break; > > +#if IS_ENABLED(CONFIG_MMC_CQHCI) > + if ((host->mmc->caps2 & MMC_CAP2_CQE) && > + (events & MSDC_INT_CMDQ)) { > + msdc_cmdq_irq(host, events); > + /* clear interrupts */ > + writel(events, host->base + MSDC_INT); > + return IRQ_HANDLED; > + } > +#endif > + > if (!mrq) { > dev_err(host->dev, > "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", > @@ -2144,6 +2212,36 @@ static int msdc_get_cd(struct mmc_host *mmc) > return !val; > } > > +static void msdc_cqe_enable(struct mmc_host *mmc) > +{ > + struct msdc_host *host = mmc_priv(mmc); > + > + /* enable cmdq irq */ > + writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); > + /* enable busy check */ > + sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); > + /* default write data / busy timeout 20s */ > + msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); > + /* default read data timeout 1s */ > + msdc_set_timeout(host, 1000000000ULL, 0); > +} > + > +void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) > +{ > + struct msdc_host *host = mmc_priv(mmc); > + > + /* disable cmdq irq */ > + sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); > + /* disable busy check */ > + sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); > + > + if (recovery) { > + sdr_set_field(host->base + MSDC_DMA_CTRL, > + MSDC_DMA_CTRL_STOP, 1); > + msdc_reset_hw(host); > + } > +} > + > static const struct mmc_host_ops mt_msdc_ops = { > .post_req = msdc_post_req, > .pre_req = msdc_pre_req, > @@ -2160,6 +2258,11 @@ static int msdc_get_cd(struct mmc_host *mmc) > .hw_reset = msdc_hw_reset, > }; > > +static const struct cqhci_host_ops msdc_cmdq_ops = { > + .enable = msdc_cqe_enable, > + .disable = msdc_cqe_disable, > +}; > + > static void msdc_of_property_parse(struct platform_device *pdev, > struct msdc_host *host) > { > @@ -2311,6 +2414,22 @@ static int msdc_drv_probe(struct platform_device *pdev) > host->dma_mask = DMA_BIT_MASK(32); > mmc_dev(mmc)->dma_mask = &host->dma_mask; > > +#if IS_ENABLED(CONFIG_MMC_CQHCI) > + if (mmc->caps2 & MMC_CAP2_CQE) { > + host->cq_host = devm_kzalloc(host->mmc->parent, > + sizeof(*host->cq_host), > + GFP_KERNEL); > + host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; > + host->cq_host->mmio = host->base + 0x800; > + host->cq_host->ops = &msdc_cmdq_ops; > + cqhci_init(host->cq_host, mmc, true); > + mmc->max_segs = 128; > + /* cqhci 16bit length */ > + /* 0 size, means 65536 so we don't have to -1 here */ > + mmc->max_seg_size = 64 * 1024; > + } > +#endif > + > host->timeout_clks = 3 * 1048576; > host->dma.gpd = dma_alloc_coherent(&pdev->dev, > 2 * sizeof(struct mt_gpdma_desc), > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 3/4] mmc: mediatek: command queue support @ 2020-02-17 9:47 ` Matthias Brugger 0 siblings, 0 replies; 33+ messages in thread From: Matthias Brugger @ 2020-02-17 9:47 UTC (permalink / raw) To: Chun-Hung Wu, Chaotian Jing, Ulf Hansson, Rob Herring, Mark Rutland, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang Cc: devicetree, wsd_upstream, linux-mmc, linux-kernel, linux-mediatek, kernel-team, linux-arm-kernel On 17/02/2020 07:56, Chun-Hung Wu wrote: > Support command queue for mt6779 platform. > a. Add msdc_set_busy_timeout() to calculate emmc write timeout > b. Connect mtk msdc driver to cqhci driver through > host->cq_host->ops = &msdc_cmdq_ops; > c. msdc_cmdq_irq() will link up with cqchi_irq(). Besides, it provides > more irq error messages like RSPCRCERR/CMDTO/DATACRCERR/DATTMO. > d. Use the options below to separate support for CQHCI or not, because > some of our platform does not support CQHCI hence no kernel option: > CONFIG_MMC_CQHCI. > #if IS_ENABLED(CONFIG_MMC_CQHCI) > XXX //Support CQHCI > #else > XXX //Not support CQHCI > #endif > > Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> > --- > drivers/mmc/host/mtk-sd.c | 119 ++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 119 insertions(+) > > diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c > index 127b0cf..b132397 100644 > --- a/drivers/mmc/host/mtk-sd.c > +++ b/drivers/mmc/host/mtk-sd.c > @@ -31,6 +31,8 @@ > #include <linux/mmc/sdio.h> > #include <linux/mmc/slot-gpio.h> > > +#include "cqhci.h" > + > #define MAX_BD_NUM 1024 > > /*--------------------------------------------------------------------------*/ > @@ -151,6 +153,7 @@ > #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ > #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ > #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ > +#define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ > > /* MSDC_INTEN mask */ > #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ > @@ -181,6 +184,7 @@ > /* SDC_CFG mask */ > #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ > #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ > +#define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ > #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ > #define SDC_CFG_SDIO (0x1 << 19) /* RW */ > #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ > @@ -228,6 +232,7 @@ > #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ > #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ > > +#define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ > #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ > > #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ > @@ -431,6 +436,7 @@ struct msdc_host { > struct msdc_save_para save_para; /* used when gate HCLK */ > struct msdc_tune_para def_tune_para; /* default tune setting */ > struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ > + struct cqhci_host *cq_host; > }; > > static const struct mtk_mmc_compatible mt8135_compat = { > @@ -527,6 +533,18 @@ struct msdc_host { > .use_internal_cd = true, > }; > > +static const struct mtk_mmc_compatible mt6779_compat = { > + .clk_div_bits = 12, I suppose .hs400_tune = false, and with this the driver is basically the same as mt8183. So you should put in the binding description: "mediatek,mt6779-mmc" "mediatek,mt8183-mmc": for mmc host ip compatible with mt6779 > + .hs400_tune = false, > + .pad_tune_reg = MSDC_PAD_TUNE0, > + .async_fifo = true, > + .data_tune = true, > + .busy_check = true, > + .stop_clk_fix = true, > + .enhance_rx = true, > + .support_64g = true, > +}; > + > static const struct of_device_id msdc_of_ids[] = { > { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, > { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, > @@ -536,6 +554,7 @@ struct msdc_host { > { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, > { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, > { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, > + { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, With the above mentioned, not needed. The driver will use the fallback compatible mt8183-mmc. If in the future we find anything special with mt6779-mmc we can still add an entry here. Regards, Matthias > {} > }; > MODULE_DEVICE_TABLE(of, msdc_of_ids); > @@ -739,6 +758,15 @@ static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) > (u32)(timeout > 255 ? 255 : timeout)); > } > > +static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) > +{ > + u64 timeout; > + > + timeout = msdc_timeout_cal(host, ns, clks); > + sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, > + (u32)(timeout > 8191 ? 8191 : timeout)); > +} > + > static void msdc_gate_clock(struct msdc_host *host) > { > clk_disable_unprepare(host->src_clk_cg); > @@ -1425,6 +1453,36 @@ static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) > pm_runtime_put_noidle(host->dev); > } > > +#if IS_ENABLED(CONFIG_MMC_CQHCI) > +static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) > +{ > + int cmd_err = 0, dat_err = 0; > + > + if (intsts & MSDC_INT_RSPCRCERR) { > + cmd_err = (unsigned int)-EILSEQ; > + dev_err(host->dev, "%s: CMD CRC ERR", __func__); > + } else if (intsts & MSDC_INT_CMDTMO) { > + cmd_err = (unsigned int)-ETIMEDOUT; > + dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); > + } > + > + if (intsts & MSDC_INT_DATCRCERR) { > + dat_err = (unsigned int)-EILSEQ; > + dev_err(host->dev, "%s: DATA CRC ERR", __func__); > + } else if (intsts & MSDC_INT_DATTMO) { > + dat_err = (unsigned int)-ETIMEDOUT; > + dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); > + } > + > + if (cmd_err || dat_err) { > + dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", > + cmd_err, dat_err, intsts); > + } > + > + return cqhci_irq(host->mmc, 0, cmd_err, dat_err); > +} > +#endif > + > static irqreturn_t msdc_irq(int irq, void *dev_id) > { > struct msdc_host *host = (struct msdc_host *) dev_id; > @@ -1461,6 +1519,16 @@ static irqreturn_t msdc_irq(int irq, void *dev_id) > if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) > break; > > +#if IS_ENABLED(CONFIG_MMC_CQHCI) > + if ((host->mmc->caps2 & MMC_CAP2_CQE) && > + (events & MSDC_INT_CMDQ)) { > + msdc_cmdq_irq(host, events); > + /* clear interrupts */ > + writel(events, host->base + MSDC_INT); > + return IRQ_HANDLED; > + } > +#endif > + > if (!mrq) { > dev_err(host->dev, > "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", > @@ -2144,6 +2212,36 @@ static int msdc_get_cd(struct mmc_host *mmc) > return !val; > } > > +static void msdc_cqe_enable(struct mmc_host *mmc) > +{ > + struct msdc_host *host = mmc_priv(mmc); > + > + /* enable cmdq irq */ > + writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); > + /* enable busy check */ > + sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); > + /* default write data / busy timeout 20s */ > + msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); > + /* default read data timeout 1s */ > + msdc_set_timeout(host, 1000000000ULL, 0); > +} > + > +void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) > +{ > + struct msdc_host *host = mmc_priv(mmc); > + > + /* disable cmdq irq */ > + sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); > + /* disable busy check */ > + sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); > + > + if (recovery) { > + sdr_set_field(host->base + MSDC_DMA_CTRL, > + MSDC_DMA_CTRL_STOP, 1); > + msdc_reset_hw(host); > + } > +} > + > static const struct mmc_host_ops mt_msdc_ops = { > .post_req = msdc_post_req, > .pre_req = msdc_pre_req, > @@ -2160,6 +2258,11 @@ static int msdc_get_cd(struct mmc_host *mmc) > .hw_reset = msdc_hw_reset, > }; > > +static const struct cqhci_host_ops msdc_cmdq_ops = { > + .enable = msdc_cqe_enable, > + .disable = msdc_cqe_disable, > +}; > + > static void msdc_of_property_parse(struct platform_device *pdev, > struct msdc_host *host) > { > @@ -2311,6 +2414,22 @@ static int msdc_drv_probe(struct platform_device *pdev) > host->dma_mask = DMA_BIT_MASK(32); > mmc_dev(mmc)->dma_mask = &host->dma_mask; > > +#if IS_ENABLED(CONFIG_MMC_CQHCI) > + if (mmc->caps2 & MMC_CAP2_CQE) { > + host->cq_host = devm_kzalloc(host->mmc->parent, > + sizeof(*host->cq_host), > + GFP_KERNEL); > + host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; > + host->cq_host->mmio = host->base + 0x800; > + host->cq_host->ops = &msdc_cmdq_ops; > + cqhci_init(host->cq_host, mmc, true); > + mmc->max_segs = 128; > + /* cqhci 16bit length */ > + /* 0 size, means 65536 so we don't have to -1 here */ > + mmc->max_seg_size = 64 * 1024; > + } > +#endif > + > host->timeout_clks = 3 * 1048576; > host->dma.gpd = dma_alloc_coherent(&pdev->dev, > 2 * sizeof(struct mt_gpdma_desc), > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v3 4/4] dt-bindings: mmc: mediatek: Add document for mt6779 2020-02-17 6:56 ` Chun-Hung Wu (?) @ 2020-02-17 6:56 ` Chun-Hung Wu -1 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-02-17 6:56 UTC (permalink / raw) To: Chaotian Jing, Ulf Hansson, Rob Herring, Mark Rutland, Matthias Brugger, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang Cc: kernel-team, linux-kernel, linux-mmc, linux-mediatek, devicetree, wsd_upstream, linux-arm-kernel, Chun-Hung Wu Add compatible node for mt6779 mmc Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> --- Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt index 8a532f4..0c9cf6a 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt @@ -12,6 +12,7 @@ Required properties: "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173 "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183 "mediatek,mt8516-mmc": for mmc host ip compatible with mt8516 + "mediatek,mt6779-mmc": for mmc host ip compatible with mt6779 "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701 "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712 "mediatek,mt7622-mmc": for MT7622 SoC -- 1.9.1 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v3 4/4] dt-bindings: mmc: mediatek: Add document for mt6779 @ 2020-02-17 6:56 ` Chun-Hung Wu 0 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-02-17 6:56 UTC (permalink / raw) To: Chaotian Jing, Ulf Hansson, Rob Herring, Mark Rutland, Matthias Brugger, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang Cc: devicetree, wsd_upstream, Chun-Hung Wu, linux-mmc, linux-kernel, linux-mediatek, kernel-team, linux-arm-kernel Add compatible node for mt6779 mmc Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> --- Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt index 8a532f4..0c9cf6a 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt @@ -12,6 +12,7 @@ Required properties: "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173 "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183 "mediatek,mt8516-mmc": for mmc host ip compatible with mt8516 + "mediatek,mt6779-mmc": for mmc host ip compatible with mt6779 "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701 "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712 "mediatek,mt7622-mmc": for MT7622 SoC -- 1.9.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v3 4/4] dt-bindings: mmc: mediatek: Add document for mt6779 @ 2020-02-17 6:56 ` Chun-Hung Wu 0 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-02-17 6:56 UTC (permalink / raw) To: Chaotian Jing, Ulf Hansson, Rob Herring, Mark Rutland, Matthias Brugger, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang Cc: devicetree, wsd_upstream, Chun-Hung Wu, linux-mmc, linux-kernel, linux-mediatek, kernel-team, linux-arm-kernel Add compatible node for mt6779 mmc Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> --- Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt index 8a532f4..0c9cf6a 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt @@ -12,6 +12,7 @@ Required properties: "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173 "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183 "mediatek,mt8516-mmc": for mmc host ip compatible with mt8516 + "mediatek,mt6779-mmc": for mmc host ip compatible with mt6779 "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701 "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712 "mediatek,mt7622-mmc": for MT7622 SoC -- 1.9.1 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH v3 4/4] dt-bindings: mmc: mediatek: Add document for mt6779 2020-02-17 6:56 ` Chun-Hung Wu (?) @ 2020-02-19 3:02 ` Rob Herring -1 siblings, 0 replies; 33+ messages in thread From: Rob Herring @ 2020-02-19 3:02 UTC (permalink / raw) To: Chun-Hung Wu Cc: Chaotian Jing, Ulf Hansson, Mark Rutland, Matthias Brugger, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang, kernel-team, linux-kernel, linux-mmc, linux-mediatek, devicetree, wsd_upstream, linux-arm-kernel, Chun-Hung Wu On Mon, 17 Feb 2020 14:56:04 +0800, Chun-Hung Wu wrote: > Add compatible node for mt6779 mmc > > Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> > --- > Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 4/4] dt-bindings: mmc: mediatek: Add document for mt6779 @ 2020-02-19 3:02 ` Rob Herring 0 siblings, 0 replies; 33+ messages in thread From: Rob Herring @ 2020-02-19 3:02 UTC (permalink / raw) To: Chun-Hung Wu Cc: Mark Rutland, Kate Stewart, Ulf Hansson, wsd_upstream, linux-mmc, Linus Walleij, Pavel Machek, Chaotian Jing, kernel-team, Pan Bian, devicetree, Martin Blumenstingl, Chun-Hung Wu, linux-mediatek, Matthias Brugger, Thomas Gleixner, Stanley Chu, Allison Randal, linux-arm-kernel, Mathieu Malaterre, Greg Kroah-Hartman, Kuohong Wang, linux-kernel On Mon, 17 Feb 2020 14:56:04 +0800, Chun-Hung Wu wrote: > Add compatible node for mt6779 mmc > > Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> > --- > Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 4/4] dt-bindings: mmc: mediatek: Add document for mt6779 @ 2020-02-19 3:02 ` Rob Herring 0 siblings, 0 replies; 33+ messages in thread From: Rob Herring @ 2020-02-19 3:02 UTC (permalink / raw) To: Chun-Hung Wu Cc: Mark Rutland, Kate Stewart, Ulf Hansson, wsd_upstream, linux-mmc, Linus Walleij, Pavel Machek, Chaotian Jing, kernel-team, Pan Bian, devicetree, Martin Blumenstingl, Chun-Hung Wu, linux-mediatek, Matthias Brugger, Thomas Gleixner, Stanley Chu, Allison Randal, linux-arm-kernel, Mathieu Malaterre, Greg Kroah-Hartman, Kuohong Wang, linux-kernel On Mon, 17 Feb 2020 14:56:04 +0800, Chun-Hung Wu wrote: > Add compatible node for mt6779 mmc > > Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> > --- > Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org> _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 4/4] dt-bindings: mmc: mediatek: Add document for mt6779 2020-02-19 3:02 ` Rob Herring (?) @ 2020-02-20 22:06 ` Matthias Brugger -1 siblings, 0 replies; 33+ messages in thread From: Matthias Brugger @ 2020-02-20 22:06 UTC (permalink / raw) To: Rob Herring, Chun-Hung Wu Cc: Chaotian Jing, Ulf Hansson, Mark Rutland, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang, kernel-team, linux-kernel, linux-mmc, linux-mediatek, devicetree, wsd_upstream, linux-arm-kernel On 19/02/2020 04:02, Rob Herring wrote: > On Mon, 17 Feb 2020 14:56:04 +0800, Chun-Hung Wu wrote: >> Add compatible node for mt6779 mmc >> >> Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> >> --- >> Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 + >> 1 file changed, 1 insertion(+) >> > > Acked-by: Rob Herring <robh@kernel.org> > With the commit from patch 3/4 the compatible should be: "mediatek,mt6779-mmc", "mediatek,mt8183-mmc": for mmc host ip compatible with mt6779 Regards, Matthias ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 4/4] dt-bindings: mmc: mediatek: Add document for mt6779 @ 2020-02-20 22:06 ` Matthias Brugger 0 siblings, 0 replies; 33+ messages in thread From: Matthias Brugger @ 2020-02-20 22:06 UTC (permalink / raw) To: Rob Herring, Chun-Hung Wu Cc: Mark Rutland, Kate Stewart, Ulf Hansson, wsd_upstream, devicetree, Martin Blumenstingl, Greg Kroah-Hartman, Linus Walleij, Kuohong Wang, linux-kernel, Mathieu Malaterre, linux-mediatek, Allison Randal, Pavel Machek, linux-mmc, Thomas Gleixner, Stanley Chu, kernel-team, Pan Bian, Chaotian Jing, linux-arm-kernel On 19/02/2020 04:02, Rob Herring wrote: > On Mon, 17 Feb 2020 14:56:04 +0800, Chun-Hung Wu wrote: >> Add compatible node for mt6779 mmc >> >> Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> >> --- >> Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 + >> 1 file changed, 1 insertion(+) >> > > Acked-by: Rob Herring <robh@kernel.org> > With the commit from patch 3/4 the compatible should be: "mediatek,mt6779-mmc", "mediatek,mt8183-mmc": for mmc host ip compatible with mt6779 Regards, Matthias _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 4/4] dt-bindings: mmc: mediatek: Add document for mt6779 @ 2020-02-20 22:06 ` Matthias Brugger 0 siblings, 0 replies; 33+ messages in thread From: Matthias Brugger @ 2020-02-20 22:06 UTC (permalink / raw) To: Rob Herring, Chun-Hung Wu Cc: Mark Rutland, Kate Stewart, Ulf Hansson, wsd_upstream, devicetree, Martin Blumenstingl, Greg Kroah-Hartman, Linus Walleij, Kuohong Wang, linux-kernel, Mathieu Malaterre, linux-mediatek, Allison Randal, Pavel Machek, linux-mmc, Thomas Gleixner, Stanley Chu, kernel-team, Pan Bian, Chaotian Jing, linux-arm-kernel On 19/02/2020 04:02, Rob Herring wrote: > On Mon, 17 Feb 2020 14:56:04 +0800, Chun-Hung Wu wrote: >> Add compatible node for mt6779 mmc >> >> Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> >> --- >> Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 + >> 1 file changed, 1 insertion(+) >> > > Acked-by: Rob Herring <robh@kernel.org> > With the commit from patch 3/4 the compatible should be: "mediatek,mt6779-mmc", "mediatek,mt8183-mmc": for mmc host ip compatible with mt6779 Regards, Matthias _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 4/4] dt-bindings: mmc: mediatek: Add document for mt6779 2020-02-20 22:06 ` Matthias Brugger (?) @ 2020-03-09 23:16 ` Chun-Hung Wu -1 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-03-09 23:16 UTC (permalink / raw) To: Matthias Brugger Cc: Rob Herring, Chaotian Jing, Ulf Hansson, Mark Rutland, Linus Walleij, Pavel Machek, Kate Stewart, Greg Kroah-Hartman, Martin Blumenstingl, Pan Bian, Thomas Gleixner, Allison Randal, Mathieu Malaterre, Stanley Chu, Kuohong Wang, kernel-team, linux-kernel, linux-mmc, linux-mediatek, devicetree, wsd_upstream, linux-arm-kernel On Thu, 2020-02-20 at 23:06 +0100, Matthias Brugger wrote: > > On 19/02/2020 04:02, Rob Herring wrote: > > On Mon, 17 Feb 2020 14:56:04 +0800, Chun-Hung Wu wrote: > >> Add compatible node for mt6779 mmc > >> > >> Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> > >> --- > >> Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 + > >> 1 file changed, 1 insertion(+) > >> > > > > Acked-by: Rob Herring <robh@kernel.org> > > > > With the commit from patch 3/4 the compatible should be: > "mediatek,mt6779-mmc", "mediatek,mt8183-mmc": for mmc host ip compatible with mt6779 As I know mt8183 is mt6771 platform not mt6779. mt6771 does not support CQHCI. > > Regards, > Matthias ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 4/4] dt-bindings: mmc: mediatek: Add document for mt6779 @ 2020-03-09 23:16 ` Chun-Hung Wu 0 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-03-09 23:16 UTC (permalink / raw) To: Matthias Brugger Cc: Mark Rutland, Kate Stewart, Ulf Hansson, wsd_upstream, linux-mmc, Linus Walleij, Pavel Machek, Rob Herring, Chaotian Jing, kernel-team, Pan Bian, devicetree, Martin Blumenstingl, linux-mediatek, Thomas Gleixner, Stanley Chu, Allison Randal, linux-arm-kernel, Mathieu Malaterre, Greg Kroah-Hartman, Kuohong Wang, linux-kernel On Thu, 2020-02-20 at 23:06 +0100, Matthias Brugger wrote: > > On 19/02/2020 04:02, Rob Herring wrote: > > On Mon, 17 Feb 2020 14:56:04 +0800, Chun-Hung Wu wrote: > >> Add compatible node for mt6779 mmc > >> > >> Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> > >> --- > >> Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 + > >> 1 file changed, 1 insertion(+) > >> > > > > Acked-by: Rob Herring <robh@kernel.org> > > > > With the commit from patch 3/4 the compatible should be: > "mediatek,mt6779-mmc", "mediatek,mt8183-mmc": for mmc host ip compatible with mt6779 As I know mt8183 is mt6771 platform not mt6779. mt6771 does not support CQHCI. > > Regards, > Matthias _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 4/4] dt-bindings: mmc: mediatek: Add document for mt6779 @ 2020-03-09 23:16 ` Chun-Hung Wu 0 siblings, 0 replies; 33+ messages in thread From: Chun-Hung Wu @ 2020-03-09 23:16 UTC (permalink / raw) To: Matthias Brugger Cc: Mark Rutland, Kate Stewart, Ulf Hansson, wsd_upstream, linux-mmc, Linus Walleij, Pavel Machek, Rob Herring, Chaotian Jing, kernel-team, Pan Bian, devicetree, Martin Blumenstingl, linux-mediatek, Thomas Gleixner, Stanley Chu, Allison Randal, linux-arm-kernel, Mathieu Malaterre, Greg Kroah-Hartman, Kuohong Wang, linux-kernel On Thu, 2020-02-20 at 23:06 +0100, Matthias Brugger wrote: > > On 19/02/2020 04:02, Rob Herring wrote: > > On Mon, 17 Feb 2020 14:56:04 +0800, Chun-Hung Wu wrote: > >> Add compatible node for mt6779 mmc > >> > >> Signed-off-by: Chun-Hung Wu <chun-hung.wu@mediatek.com> > >> --- > >> Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 + > >> 1 file changed, 1 insertion(+) > >> > > > > Acked-by: Rob Herring <robh@kernel.org> > > > > With the commit from patch 3/4 the compatible should be: > "mediatek,mt6779-mmc", "mediatek,mt8183-mmc": for mmc host ip compatible with mt6779 As I know mt8183 is mt6771 platform not mt6779. mt6771 does not support CQHCI. > > Regards, > Matthias _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 33+ messages in thread
end of thread, other threads:[~2020-03-09 23:16 UTC | newest] Thread overview: 33+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-02-17 6:56 [PATCH v3 0/4] mmc: mediatek: add mmc cqhci support Chun-Hung Wu 2020-02-17 6:56 ` Chun-Hung Wu 2020-02-17 6:56 ` Chun-Hung Wu 2020-02-17 6:56 ` [PATCH v3 1/4] mmc: core: expose MMC_CAP2_CQE* to dt Chun-Hung Wu 2020-02-17 6:56 ` Chun-Hung Wu 2020-02-17 6:56 ` Chun-Hung Wu 2020-03-04 13:04 ` Ulf Hansson 2020-03-04 13:04 ` Ulf Hansson 2020-03-04 13:04 ` Ulf Hansson 2020-03-09 23:13 ` Chun-Hung Wu 2020-03-09 23:13 ` Chun-Hung Wu 2020-03-09 23:13 ` Chun-Hung Wu 2020-02-17 6:56 ` [PATCH v3 2/4] mmc: mediatek: refine msdc timeout api Chun-Hung Wu 2020-02-17 6:56 ` Chun-Hung Wu 2020-02-17 6:56 ` Chun-Hung Wu 2020-02-17 6:56 ` [PATCH v3 3/4] mmc: mediatek: command queue support Chun-Hung Wu 2020-02-17 6:56 ` Chun-Hung Wu 2020-02-17 6:56 ` Chun-Hung Wu 2020-02-17 9:47 ` Matthias Brugger 2020-02-17 9:47 ` Matthias Brugger 2020-02-17 9:47 ` Matthias Brugger 2020-02-17 6:56 ` [PATCH v3 4/4] dt-bindings: mmc: mediatek: Add document for mt6779 Chun-Hung Wu 2020-02-17 6:56 ` Chun-Hung Wu 2020-02-17 6:56 ` Chun-Hung Wu 2020-02-19 3:02 ` Rob Herring 2020-02-19 3:02 ` Rob Herring 2020-02-19 3:02 ` Rob Herring 2020-02-20 22:06 ` Matthias Brugger 2020-02-20 22:06 ` Matthias Brugger 2020-02-20 22:06 ` Matthias Brugger 2020-03-09 23:16 ` Chun-Hung Wu 2020-03-09 23:16 ` Chun-Hung Wu 2020-03-09 23:16 ` Chun-Hung Wu
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