From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v5 0/4] target-riscv: support vector extension part 1 Date: Fri, 21 Feb 2020 17:45:27 +0800 [thread overview] Message-ID: <20200221094531.61894-1-zhiwei_liu@c-sky.com> (raw) This is the first part of v5 patchset. The changelog of v5 is only coverd the part1. Features: * support specification riscv-v-spec-0.7.1. * support basic vector extension. * support Zvlsseg. * support Zvamo. * not support Zvediv as it is changing. * SLEN always equals VLEN. * element width support 8bit, 16bit, 32bit, 64bit. Changelog: v5 * vector registers as direct fields in RISCVCPUState. * mov the properties to last patch. * check RVV in vs(). * check if rs1 is x0 in vsetvl/vsetvli. * check VILL, EDIV, RESERVED fileds in vsetvl. v4 * adjust max vlen to 512 bits. * check maximum on elen(64bits). * check minimum on vlen(128bits). * check if rs1 is x0 in vsetvl/vsetvli. * use gen_goto_tb in vsetvli instead of exit_tb. * fixup fetch vlmax from rs2, not env->vext.type. v3 * support VLEN configure from qemu command line. * support ELEN configure from qemu command line. * support vector specification version configure from qemu command line. * only default on for "any" cpu, others turn on from command line. * use a continous memory block for vector register description. V2 * use float16_compare{_quiet} * only use GETPC() in outer most helper * add ctx.ext_v Property LIU Zhiwei (4): target/riscv: add vector extension field in CPURISCVState target/riscv: implementation-defined constant parameters target/riscv: support vector extension csr target/riscv: add vector configure instruction MAINTAINERS | 1 + target/riscv/Makefile.objs | 2 +- target/riscv/cpu.c | 7 +++ target/riscv/cpu.h | 78 ++++++++++++++++++++++--- target/riscv/cpu_bits.h | 15 +++++ target/riscv/csr.c | 75 +++++++++++++++++++++++- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 5 ++ target/riscv/insn_trans/trans_rvv.inc.c | 69 ++++++++++++++++++++++ target/riscv/translate.c | 17 +++++- target/riscv/vector_helper.c | 53 +++++++++++++++++ 11 files changed, 312 insertions(+), 12 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c create mode 100644 target/riscv/vector_helper.c -- 2.23.0
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Cc: wenmeng_zhang@c-sky.com, wxy194768@alibaba-inc.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v5 0/4] target-riscv: support vector extension part 1 Date: Fri, 21 Feb 2020 17:45:27 +0800 [thread overview] Message-ID: <20200221094531.61894-1-zhiwei_liu@c-sky.com> (raw) This is the first part of v5 patchset. The changelog of v5 is only coverd the part1. Features: * support specification riscv-v-spec-0.7.1. * support basic vector extension. * support Zvlsseg. * support Zvamo. * not support Zvediv as it is changing. * SLEN always equals VLEN. * element width support 8bit, 16bit, 32bit, 64bit. Changelog: v5 * vector registers as direct fields in RISCVCPUState. * mov the properties to last patch. * check RVV in vs(). * check if rs1 is x0 in vsetvl/vsetvli. * check VILL, EDIV, RESERVED fileds in vsetvl. v4 * adjust max vlen to 512 bits. * check maximum on elen(64bits). * check minimum on vlen(128bits). * check if rs1 is x0 in vsetvl/vsetvli. * use gen_goto_tb in vsetvli instead of exit_tb. * fixup fetch vlmax from rs2, not env->vext.type. v3 * support VLEN configure from qemu command line. * support ELEN configure from qemu command line. * support vector specification version configure from qemu command line. * only default on for "any" cpu, others turn on from command line. * use a continous memory block for vector register description. V2 * use float16_compare{_quiet} * only use GETPC() in outer most helper * add ctx.ext_v Property LIU Zhiwei (4): target/riscv: add vector extension field in CPURISCVState target/riscv: implementation-defined constant parameters target/riscv: support vector extension csr target/riscv: add vector configure instruction MAINTAINERS | 1 + target/riscv/Makefile.objs | 2 +- target/riscv/cpu.c | 7 +++ target/riscv/cpu.h | 78 ++++++++++++++++++++++--- target/riscv/cpu_bits.h | 15 +++++ target/riscv/csr.c | 75 +++++++++++++++++++++++- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 5 ++ target/riscv/insn_trans/trans_rvv.inc.c | 69 ++++++++++++++++++++++ target/riscv/translate.c | 17 +++++- target/riscv/vector_helper.c | 53 +++++++++++++++++ 11 files changed, 312 insertions(+), 12 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c create mode 100644 target/riscv/vector_helper.c -- 2.23.0
next reply other threads:[~2020-02-21 9:47 UTC|newest] Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-02-21 9:45 LIU Zhiwei [this message] 2020-02-21 9:45 ` [PATCH v5 0/4] target-riscv: support vector extension part 1 LIU Zhiwei 2020-02-21 9:45 ` [PATCH v5 1/4] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei 2020-02-21 9:45 ` LIU Zhiwei 2020-02-26 18:03 ` Alistair Francis 2020-02-26 18:03 ` Alistair Francis 2020-02-27 20:32 ` Richard Henderson 2020-02-27 20:32 ` Richard Henderson 2020-02-21 9:45 ` [PATCH v5 2/4] target/riscv: implementation-defined constant parameters LIU Zhiwei 2020-02-21 9:45 ` LIU Zhiwei 2020-02-26 18:05 ` Alistair Francis 2020-02-26 18:05 ` Alistair Francis 2020-02-27 20:33 ` Richard Henderson 2020-02-27 20:33 ` Richard Henderson 2020-02-21 9:45 ` [PATCH v5 3/4] target/riscv: support vector extension csr LIU Zhiwei 2020-02-21 9:45 ` LIU Zhiwei 2020-02-26 18:42 ` Alistair Francis 2020-02-26 18:42 ` Alistair Francis 2020-02-27 0:41 ` LIU Zhiwei 2020-02-27 0:41 ` LIU Zhiwei 2020-02-26 20:16 ` Jim Wilson 2020-02-21 9:45 ` [PATCH v5 4/4] target/riscv: add vector configure instruction LIU Zhiwei 2020-02-21 9:45 ` LIU Zhiwei 2020-02-26 19:20 ` Alistair Francis 2020-02-26 19:20 ` Alistair Francis 2020-02-27 1:41 ` LIU Zhiwei 2020-02-27 1:41 ` LIU Zhiwei 2020-02-27 21:48 ` Alistair Francis 2020-02-27 21:48 ` Alistair Francis 2020-02-26 20:20 ` Jim Wilson 2020-02-26 20:09 ` [PATCH v5 0/4] target-riscv: support vector extension part 1 Jim Wilson 2020-02-26 22:28 ` Alistair Francis 2020-02-26 22:28 ` Alistair Francis 2020-02-26 23:39 ` Jim Wilson 2020-02-26 23:39 ` Jim Wilson 2020-02-26 23:46 ` Alistair Francis 2020-02-26 23:46 ` Alistair Francis
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