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From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
	alistair23@gmail.com, chihmin.chao@sifive.com,
	palmer@dabbelt.com
Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org,
	qemu-devel@nongnu.org, wxy194768@alibaba-inc.com
Subject: Re: [PATCH v5 1/4] target/riscv: add vector extension field in CPURISCVState
Date: Thu, 27 Feb 2020 12:32:45 -0800	[thread overview]
Message-ID: <229be418-8fe0-cb5a-3ba5-3ea85f2843f0@linaro.org> (raw)
In-Reply-To: <20200221094531.61894-2-zhiwei_liu@c-sky.com>

On 2/21/20 1:45 AM, LIU Zhiwei wrote:
> The 32 vector registers will be viewed as a continuous memory block.
> It avoids the convension between element index and (regno, offset).
> Thus elements can be directly accessed by offset from the first vector
> base address.
> 
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
>  target/riscv/cpu.h | 12 ++++++++++++
>  1 file changed, 12 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~


WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
	alistair23@gmail.com, chihmin.chao@sifive.com,
	palmer@dabbelt.com
Cc: wenmeng_zhang@c-sky.com, wxy194768@alibaba-inc.com,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: Re: [PATCH v5 1/4] target/riscv: add vector extension field in CPURISCVState
Date: Thu, 27 Feb 2020 12:32:45 -0800	[thread overview]
Message-ID: <229be418-8fe0-cb5a-3ba5-3ea85f2843f0@linaro.org> (raw)
In-Reply-To: <20200221094531.61894-2-zhiwei_liu@c-sky.com>

On 2/21/20 1:45 AM, LIU Zhiwei wrote:
> The 32 vector registers will be viewed as a continuous memory block.
> It avoids the convension between element index and (regno, offset).
> Thus elements can be directly accessed by offset from the first vector
> base address.
> 
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
>  target/riscv/cpu.h | 12 ++++++++++++
>  1 file changed, 12 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~


  parent reply	other threads:[~2020-02-27 20:33 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-21  9:45 [PATCH v5 0/4] target-riscv: support vector extension part 1 LIU Zhiwei
2020-02-21  9:45 ` LIU Zhiwei
2020-02-21  9:45 ` [PATCH v5 1/4] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-02-21  9:45   ` LIU Zhiwei
2020-02-26 18:03   ` Alistair Francis
2020-02-26 18:03     ` Alistair Francis
2020-02-27 20:32   ` Richard Henderson [this message]
2020-02-27 20:32     ` Richard Henderson
2020-02-21  9:45 ` [PATCH v5 2/4] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-02-21  9:45   ` LIU Zhiwei
2020-02-26 18:05   ` Alistair Francis
2020-02-26 18:05     ` Alistair Francis
2020-02-27 20:33   ` Richard Henderson
2020-02-27 20:33     ` Richard Henderson
2020-02-21  9:45 ` [PATCH v5 3/4] target/riscv: support vector extension csr LIU Zhiwei
2020-02-21  9:45   ` LIU Zhiwei
2020-02-26 18:42   ` Alistair Francis
2020-02-26 18:42     ` Alistair Francis
2020-02-27  0:41     ` LIU Zhiwei
2020-02-27  0:41       ` LIU Zhiwei
2020-02-26 20:16   ` Jim Wilson
2020-02-21  9:45 ` [PATCH v5 4/4] target/riscv: add vector configure instruction LIU Zhiwei
2020-02-21  9:45   ` LIU Zhiwei
2020-02-26 19:20   ` Alistair Francis
2020-02-26 19:20     ` Alistair Francis
2020-02-27  1:41     ` LIU Zhiwei
2020-02-27  1:41       ` LIU Zhiwei
2020-02-27 21:48       ` Alistair Francis
2020-02-27 21:48         ` Alistair Francis
2020-02-26 20:20   ` Jim Wilson
2020-02-26 20:09 ` [PATCH v5 0/4] target-riscv: support vector extension part 1 Jim Wilson
2020-02-26 22:28   ` Alistair Francis
2020-02-26 22:28     ` Alistair Francis
2020-02-26 23:39     ` Jim Wilson
2020-02-26 23:39       ` Jim Wilson
2020-02-26 23:46       ` Alistair Francis
2020-02-26 23:46         ` Alistair Francis

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