* [Intel-gfx] [PATCH] drm/i915/tgl: Add Wa_1608008084 @ 2020-02-24 19:12 Lucas De Marchi 2020-02-24 21:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Add Wa_1608008084 (rev2) Patchwork 2020-02-26 8:56 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 0 siblings, 2 replies; 8+ messages in thread From: Lucas De Marchi @ 2020-02-24 19:12 UTC (permalink / raw) To: intel-gfx; +Cc: Lucas De Marchi, ramlingam.c Wa_1608008084 is an additional WA that applies to writes on FF_MODE2 register. We can't read it back either from CPU or GPU. Since the other bits should be 0, recommendation to handle Wa_1604555607 is to actually just write the timer value. Do a write only and don't try to read it, neither before or after the WA is applied. Fixes: ff690b2111ba ("drm/i915/tgl: Implement Wa_1604555607") Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 887e0dc701f7..06cef3c18f26 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -580,24 +580,19 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) { - u32 val; - /* Wa_1409142259:tgl */ WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); - /* Wa_1604555607:tgl */ - val = intel_uncore_read(engine->uncore, FF_MODE2); - val &= ~FF_MODE2_TDS_TIMER_MASK; - val |= FF_MODE2_TDS_TIMER_128; /* - * FIXME: FF_MODE2 register is not readable till TGL B0. We can - * enable verification of WA from the later steppings, which enables - * the read of FF_MODE2. + * Wa_1604555607:gen12 and Wa_1608008084:gen12 + * FF_MODE2 register will return the wrong value when read. The default + * value for this register is zero for all fields and there are no bit + * masks. So instead of doing a RMW we should just write the TDS timer + * value for Wa_1604555607. */ - wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, - IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 : - FF_MODE2_TDS_TIMER_MASK); + wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, + FF_MODE2_TDS_TIMER_128, 0); } static void -- 2.24.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Add Wa_1608008084 (rev2) 2020-02-24 19:12 [Intel-gfx] [PATCH] drm/i915/tgl: Add Wa_1608008084 Lucas De Marchi @ 2020-02-24 21:06 ` Patchwork 2020-02-26 8:56 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 1 sibling, 0 replies; 8+ messages in thread From: Patchwork @ 2020-02-24 21:06 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx == Series Details == Series: drm/i915/tgl: Add Wa_1608008084 (rev2) URL : https://patchwork.freedesktop.org/series/73801/ State : success == Summary == CI Bug Log - changes from CI_DRM_7999 -> Patchwork_16694 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/index.html Known issues ------------ Here are the changes found in Patchwork_16694 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_suspend@basic-s4-devices: - fi-tgl-y: [PASS][1] -> [FAIL][2] ([CI#94]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html * igt@gem_mmap@basic: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([CI#94] / [i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/fi-tgl-y/igt@gem_mmap@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/fi-tgl-y/igt@gem_mmap@basic.html * igt@i915_selftest@live_gem_contexts: - fi-hsw-peppy: [PASS][5] -> [DMESG-FAIL][6] ([i915#722]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html - fi-hsw-4770r: [PASS][7] -> [DMESG-FAIL][8] ([i915#722]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/fi-hsw-4770r/igt@i915_selftest@live_gem_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/fi-hsw-4770r/igt@i915_selftest@live_gem_contexts.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][9] -> [FAIL][10] ([fdo#111407]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html #### Possible fixes #### * igt@kms_addfb_basic@addfb25-yf-tiled: - fi-tgl-y: [DMESG-WARN][11] ([CI#94] / [i915#402]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/fi-tgl-y/igt@kms_addfb_basic@addfb25-yf-tiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/fi-tgl-y/igt@kms_addfb_basic@addfb25-yf-tiled.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722 Participating hosts (52 -> 42) ------------------------------ Missing (10): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ilk-650 fi-ctg-p8600 fi-byt-n2820 fi-byt-clapper fi-bsw-nick fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7999 -> Patchwork_16694 CI-20190529: 20190529 CI_DRM_7999: e853e3d470d1bb4ac87042094b99adbdbaa87944 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5463: d519c80219ebe558cd2fa378f26f9d73f9e35310 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16694: f7e443d7006eb83427b962f2ed0043822856ea3f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f7e443d7006e drm/i915/tgl: Add Wa_1608008084 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl: Add Wa_1608008084 (rev2) 2020-02-24 19:12 [Intel-gfx] [PATCH] drm/i915/tgl: Add Wa_1608008084 Lucas De Marchi 2020-02-24 21:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Add Wa_1608008084 (rev2) Patchwork @ 2020-02-26 8:56 ` Patchwork 1 sibling, 0 replies; 8+ messages in thread From: Patchwork @ 2020-02-26 8:56 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx == Series Details == Series: drm/i915/tgl: Add Wa_1608008084 (rev2) URL : https://patchwork.freedesktop.org/series/73801/ State : success == Summary == CI Bug Log - changes from CI_DRM_7999_full -> Patchwork_16694_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_16694_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_busy@busy-vcs1: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +23 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-iclb4/igt@gem_busy@busy-vcs1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-iclb8/igt@gem_busy@busy-vcs1.html * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-kbl1/igt@gem_ctx_isolation@rcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-kbl2/igt@gem_ctx_isolation@rcs0-s3.html * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110841]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-iclb5/igt@gem_ctx_shared@exec-single-timeline-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html * igt@gem_exec_schedule@pi-common-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([i915#677]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-iclb3/igt@gem_exec_schedule@pi-common-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-iclb1/igt@gem_exec_schedule@pi-common-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +21 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-iclb7/igt@gem_exec_schedule@preempt-queue-bsd1.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +5 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-iclb5/igt@gem_exec_schedule@preemptive-hang-bsd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-iclb4/igt@gem_exec_schedule@preemptive-hang-bsd.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-apl: [PASS][13] -> [FAIL][14] ([i915#644]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-apl7/igt@gem_ppgtt@flink-and-close-vma-leak.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-apl1/igt@gem_ppgtt@flink-and-close-vma-leak.html * igt@kms_cursor_crc@pipe-c-cursor-128x128-onscreen: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#54]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-128x128-onscreen.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-128x128-onscreen.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt: - shard-glk: [PASS][17] -> [FAIL][18] ([i915#49]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-glk5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-glk3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt.html * igt@kms_pipe_crc_basic@hang-read-crc-pipe-b: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#53]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-skl5/igt@kms_pipe_crc_basic@hang-read-crc-pipe-b.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-skl7/igt@kms_pipe_crc_basic@hang-read-crc-pipe-b.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-glk: [PASS][25] -> [FAIL][26] ([i915#899]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-glk6/igt@kms_plane_lowres@pipe-a-tiling-y.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-glk5/igt@kms_plane_lowres@pipe-a-tiling-y.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-iclb7/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_setmode@basic: - shard-kbl: [PASS][29] -> [FAIL][30] ([i915#31]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-kbl7/igt@kms_setmode@basic.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-kbl1/igt@kms_setmode@basic.html * igt@sw_sync@sync_multi_producer_single_consumer: - shard-iclb: [PASS][31] -> [TIMEOUT][32] ([fdo#112271]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-iclb7/igt@sw_sync@sync_multi_producer_single_consumer.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-iclb2/igt@sw_sync@sync_multi_producer_single_consumer.html #### Possible fixes #### * igt@gem_ctx_isolation@vcs1-s3: - shard-kbl: [DMESG-WARN][33] ([i915#56]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-kbl7/igt@gem_ctx_isolation@vcs1-s3.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-kbl3/igt@gem_ctx_isolation@vcs1-s3.html * igt@gem_exec_balancer@smoke: - shard-iclb: [SKIP][35] ([fdo#110854]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-iclb6/igt@gem_exec_balancer@smoke.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-iclb1/igt@gem_exec_balancer@smoke.html * {igt@gem_exec_schedule@implicit-write-read-bsd1}: - shard-iclb: [SKIP][37] ([fdo#109276] / [i915#677]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-iclb5/igt@gem_exec_schedule@implicit-write-read-bsd1.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-iclb4/igt@gem_exec_schedule@implicit-write-read-bsd1.html * igt@gem_exec_schedule@pi-userfault-bsd: - shard-iclb: [SKIP][39] ([i915#677]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-iclb4/igt@gem_exec_schedule@pi-userfault-bsd.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-iclb8/igt@gem_exec_schedule@pi-userfault-bsd.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [SKIP][41] ([fdo#112146]) -> [PASS][42] +7 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-iclb7/igt@gem_exec_schedule@reorder-wide-bsd.html * igt@i915_pm_rpm@system-suspend-execbuf: - shard-skl: [INCOMPLETE][43] ([i915#151] / [i915#69]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-skl1/igt@i915_pm_rpm@system-suspend-execbuf.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-skl8/igt@i915_pm_rpm@system-suspend-execbuf.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-apl: [DMESG-WARN][45] ([i915#180]) -> [PASS][46] +3 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html * {igt@kms_hdr@bpc-switch-dpms}: - shard-skl: [FAIL][47] ([i915#1188]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html * {igt@kms_hdr@bpc-switch-suspend}: - shard-kbl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +3 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-kbl3/igt@kms_hdr@bpc-switch-suspend.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-kbl4/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_psr@psr2_primary_render: - shard-iclb: [SKIP][51] ([fdo#109441]) -> [PASS][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-iclb7/igt@kms_psr@psr2_primary_render.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-iclb2/igt@kms_psr@psr2_primary_render.html * igt@kms_setmode@basic: - shard-skl: [FAIL][53] ([i915#31]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-skl6/igt@kms_setmode@basic.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-skl3/igt@kms_setmode@basic.html - shard-glk: [FAIL][55] ([i915#31]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-glk2/igt@kms_setmode@basic.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-glk4/igt@kms_setmode@basic.html * igt@perf_pmu@busy-no-semaphores-vcs1: - shard-iclb: [SKIP][57] ([fdo#112080]) -> [PASS][58] +10 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-iclb5/igt@perf_pmu@busy-no-semaphores-vcs1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html * igt@prime_busy@hang-bsd2: - shard-iclb: [SKIP][59] ([fdo#109276]) -> [PASS][60] +29 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-iclb6/igt@prime_busy@hang-bsd2.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-iclb1/igt@prime_busy@hang-bsd2.html #### Warnings #### * igt@gem_ctx_isolation@vcs1-nonpriv-switch: - shard-iclb: [SKIP][61] ([fdo#112080]) -> [FAIL][62] ([IGT#28]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html * igt@i915_pm_rpm@legacy-planes-dpms: - shard-snb: [INCOMPLETE][63] ([i915#82]) -> [SKIP][64] ([fdo#109271]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-snb5/igt@i915_pm_rpm@legacy-planes-dpms.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-snb6/igt@i915_pm_rpm@legacy-planes-dpms.html * igt@kms_content_protection@atomic: - shard-kbl: [TIMEOUT][65] ([fdo#112271]) -> [TIMEOUT][66] ([fdo#112271] / [i915#727]) +2 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-kbl6/igt@kms_content_protection@atomic.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-kbl6/igt@kms_content_protection@atomic.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [DMESG-WARN][67] ([i915#1226]) -> [SKIP][68] ([fdo#109349]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7999/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/shard-iclb7/igt@kms_dp_dsc@basic-dsc-enable-edp.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841 [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854 [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080 [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226 [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#56]: https://gitlab.freedesktop.org/drm/intel/issues/56 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644 [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#727]: https://gitlab.freedesktop.org/drm/intel/issues/727 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (10 -> 10) ------------------------------ No changes in participating hosts Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7999 -> Patchwork_16694 CI-20190529: 20190529 CI_DRM_7999: e853e3d470d1bb4ac87042094b99adbdbaa87944 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5463: d519c80219ebe558cd2fa378f26f9d73f9e35310 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16694: f7e443d7006eb83427b962f2ed0043822856ea3f @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16694/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/tgl: Add Wa_1608008084 @ 2020-02-22 0:28 Lucas De Marchi 2020-02-22 0:36 ` Souza, Jose 0 siblings, 1 reply; 8+ messages in thread From: Lucas De Marchi @ 2020-02-22 0:28 UTC (permalink / raw) To: intel-gfx; +Cc: Lucas De Marchi Wa_1608008084 is an additional WA that applies to writes on FF_MODE2 register. We can't read it back either from CPU or GPU. Since the other bits should be 0, recommendation to handle Wa_1604555607 is to actually just write the timer value. Do a write only and don't try to read it, neither before or after the WA is applied. Fixes: ff690b2111ba ("drm/i915/tgl: Implement Wa_1604555607") Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 ++++++++++----------- 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 887e0dc701f7..0d76e1d6ec87 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -580,24 +580,22 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) { - u32 val; - /* Wa_1409142259:tgl */ WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); - /* Wa_1604555607:tgl */ - val = intel_uncore_read(engine->uncore, FF_MODE2); - val &= ~FF_MODE2_TDS_TIMER_MASK; - val |= FF_MODE2_TDS_TIMER_128; /* - * FIXME: FF_MODE2 register is not readable till TGL B0. We can - * enable verification of WA from the later steppings, which enables - * the read of FF_MODE2. + * Wa_1604555607:gen12 + * FF_MODE2 register is not readable till TGL B0, either by CPU or GPU. + * + * Wa_1608008084:gen12 + * FF_MODE2 register will return the wrong value when read. The default + * value for this register is zero for all fields and there are no bit + * masks. So instead of doing a RMW we should just write the TDS timer + * value for Wa_1604555607. */ - wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, - IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 : - FF_MODE2_TDS_TIMER_MASK); + wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, + FF_MODE2_TDS_TIMER_128, 0); } static void -- 2.24.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: Add Wa_1608008084 2020-02-22 0:28 [Intel-gfx] [PATCH] drm/i915/tgl: Add Wa_1608008084 Lucas De Marchi @ 2020-02-22 0:36 ` Souza, Jose 2020-02-22 1:39 ` Lucas De Marchi 2020-02-24 21:10 ` Chris Wilson 0 siblings, 2 replies; 8+ messages in thread From: Souza, Jose @ 2020-02-22 0:36 UTC (permalink / raw) To: intel-gfx, De Marchi, Lucas; +Cc: michel.thierry, ramlingam.c + CCing people involved in the patch fixed. On Fri, 2020-02-21 at 16:28 -0800, Lucas De Marchi wrote: > Wa_1608008084 is an additional WA that applies to writes on FF_MODE2 > register. We can't read it back either from CPU or GPU. Since the > other > bits should be 0, recommendation to handle Wa_1604555607 is to > actually > just write the timer value. > > Do a write only and don't try to read it, neither before or after > the WA is applied. > > Fixes: ff690b2111ba ("drm/i915/tgl: Implement Wa_1604555607") > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 ++++++++++--------- > -- > 1 file changed, 10 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 887e0dc701f7..0d76e1d6ec87 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -580,24 +580,22 @@ static void icl_ctx_workarounds_init(struct > intel_engine_cs *engine, > static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, > struct i915_wa_list *wal) > { > - u32 val; > - > /* Wa_1409142259:tgl */ > WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, > GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); > > - /* Wa_1604555607:tgl */ > - val = intel_uncore_read(engine->uncore, FF_MODE2); > - val &= ~FF_MODE2_TDS_TIMER_MASK; > - val |= FF_MODE2_TDS_TIMER_128; > /* > - * FIXME: FF_MODE2 register is not readable till TGL B0. We can > - * enable verification of WA from the later steppings, which > enables > - * the read of FF_MODE2. > + * Wa_1604555607:gen12 > + * FF_MODE2 register is not readable till TGL B0, either by CPU > or GPU. The line above could be removed as the comments above explain it better, also BSpec don't say that it will be fixed in B0. With that: Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > + * > + * Wa_1608008084:gen12 > + * FF_MODE2 register will return the wrong value when read. The > default > + * value for this register is zero for all fields and there are > no bit > + * masks. So instead of doing a RMW we should just write the > TDS timer > + * value for Wa_1604555607. > */ > - wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, > - IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? > 0 : > - FF_MODE2_TDS_TIMER_MASK); > + wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, > + FF_MODE2_TDS_TIMER_128, 0); > } > > static void _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: Add Wa_1608008084 2020-02-22 0:36 ` Souza, Jose @ 2020-02-22 1:39 ` Lucas De Marchi 2020-02-24 21:10 ` Chris Wilson 1 sibling, 0 replies; 8+ messages in thread From: Lucas De Marchi @ 2020-02-22 1:39 UTC (permalink / raw) To: Souza, Jose; +Cc: intel-gfx, michel.thierry, ramlingam.c On Fri, Feb 21, 2020 at 04:36:53PM -0800, Jose Souza wrote: >+ CCing people involved in the patch fixed. > >On Fri, 2020-02-21 at 16:28 -0800, Lucas De Marchi wrote: >> Wa_1608008084 is an additional WA that applies to writes on FF_MODE2 >> register. We can't read it back either from CPU or GPU. Since the >> other >> bits should be 0, recommendation to handle Wa_1604555607 is to >> actually >> just write the timer value. >> >> Do a write only and don't try to read it, neither before or after >> the WA is applied. >> >> Fixes: ff690b2111ba ("drm/i915/tgl: Implement Wa_1604555607") >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> >> --- >> drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 ++++++++++--------- >> -- >> 1 file changed, 10 insertions(+), 12 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c >> b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> index 887e0dc701f7..0d76e1d6ec87 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> @@ -580,24 +580,22 @@ static void icl_ctx_workarounds_init(struct >> intel_engine_cs *engine, >> static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, >> struct i915_wa_list *wal) >> { >> - u32 val; >> - >> /* Wa_1409142259:tgl */ >> WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, >> GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); >> >> - /* Wa_1604555607:tgl */ >> - val = intel_uncore_read(engine->uncore, FF_MODE2); >> - val &= ~FF_MODE2_TDS_TIMER_MASK; >> - val |= FF_MODE2_TDS_TIMER_128; >> /* >> - * FIXME: FF_MODE2 register is not readable till TGL B0. We can >> - * enable verification of WA from the later steppings, which >> enables >> - * the read of FF_MODE2. >> + * Wa_1604555607:gen12 >> + * FF_MODE2 register is not readable till TGL B0, either by CPU >> or GPU. > >The line above could be removed as the comments above explain it >better, also BSpec don't say that it will be fixed in B0. 1604555607 was documented to be fixed in B0. Just saw it's not anymore. > >With that: >Reviewed-by: José Roberto de Souza <jose.souza@intel.com> thanks Lucas De Marchi > >> + * >> + * Wa_1608008084:gen12 >> + * FF_MODE2 register will return the wrong value when read. The >> default >> + * value for this register is zero for all fields and there are >> no bit >> + * masks. So instead of doing a RMW we should just write the >> TDS timer >> + * value for Wa_1604555607. >> */ >> - wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, >> - IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? >> 0 : >> - FF_MODE2_TDS_TIMER_MASK); >> + wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, >> + FF_MODE2_TDS_TIMER_128, 0); >> } >> >> static void _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: Add Wa_1608008084 2020-02-22 0:36 ` Souza, Jose 2020-02-22 1:39 ` Lucas De Marchi @ 2020-02-24 21:10 ` Chris Wilson 2020-02-24 21:54 ` Lucas De Marchi 1 sibling, 1 reply; 8+ messages in thread From: Chris Wilson @ 2020-02-24 21:10 UTC (permalink / raw) To: De Marchi, Lucas, Souza, Jose, intel-gfx; +Cc: michel.thierry, ramlingam.c Quoting Souza, Jose (2020-02-22 00:36:53) > + CCing people involved in the patch fixed. > > On Fri, 2020-02-21 at 16:28 -0800, Lucas De Marchi wrote: > > Wa_1608008084 is an additional WA that applies to writes on FF_MODE2 > > register. We can't read it back either from CPU or GPU. Since the > > other > > bits should be 0, recommendation to handle Wa_1604555607 is to > > actually > > just write the timer value. > > > > Do a write only and don't try to read it, neither before or after > > the WA is applied. > > > > Fixes: ff690b2111ba ("drm/i915/tgl: Implement Wa_1604555607") > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > > --- > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 ++++++++++--------- > > -- > > 1 file changed, 10 insertions(+), 12 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > index 887e0dc701f7..0d76e1d6ec87 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > @@ -580,24 +580,22 @@ static void icl_ctx_workarounds_init(struct > > intel_engine_cs *engine, > > static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, > > struct i915_wa_list *wal) > > { > > - u32 val; > > - > > /* Wa_1409142259:tgl */ > > WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, > > GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); > > > > - /* Wa_1604555607:tgl */ > > - val = intel_uncore_read(engine->uncore, FF_MODE2); > > - val &= ~FF_MODE2_TDS_TIMER_MASK; > > - val |= FF_MODE2_TDS_TIMER_128; > > /* > > - * FIXME: FF_MODE2 register is not readable till TGL B0. We can > > - * enable verification of WA from the later steppings, which > > enables > > - * the read of FF_MODE2. > > + * Wa_1604555607:gen12 > > + * FF_MODE2 register is not readable till TGL B0, either by CPU > > or GPU. > > The line above could be removed as the comments above explain it > better, also BSpec don't say that it will be fixed in B0. The HW guys on discovering the bug promised it would be fixed for B0. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: Add Wa_1608008084 2020-02-24 21:10 ` Chris Wilson @ 2020-02-24 21:54 ` Lucas De Marchi 0 siblings, 0 replies; 8+ messages in thread From: Lucas De Marchi @ 2020-02-24 21:54 UTC (permalink / raw) To: Chris Wilson; +Cc: michel.thierry, intel-gfx, ramlingam.c On Mon, Feb 24, 2020 at 09:10:34PM +0000, Chris Wilson wrote: >Quoting Souza, Jose (2020-02-22 00:36:53) >> + CCing people involved in the patch fixed. >> >> On Fri, 2020-02-21 at 16:28 -0800, Lucas De Marchi wrote: >> > Wa_1608008084 is an additional WA that applies to writes on FF_MODE2 >> > register. We can't read it back either from CPU or GPU. Since the >> > other >> > bits should be 0, recommendation to handle Wa_1604555607 is to >> > actually >> > just write the timer value. >> > >> > Do a write only and don't try to read it, neither before or after >> > the WA is applied. >> > >> > Fixes: ff690b2111ba ("drm/i915/tgl: Implement Wa_1604555607") >> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> >> > --- >> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 ++++++++++--------- >> > -- >> > 1 file changed, 10 insertions(+), 12 deletions(-) >> > >> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c >> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> > index 887e0dc701f7..0d76e1d6ec87 100644 >> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> > @@ -580,24 +580,22 @@ static void icl_ctx_workarounds_init(struct >> > intel_engine_cs *engine, >> > static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, >> > struct i915_wa_list *wal) >> > { >> > - u32 val; >> > - >> > /* Wa_1409142259:tgl */ >> > WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, >> > GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); >> > >> > - /* Wa_1604555607:tgl */ >> > - val = intel_uncore_read(engine->uncore, FF_MODE2); >> > - val &= ~FF_MODE2_TDS_TIMER_MASK; >> > - val |= FF_MODE2_TDS_TIMER_128; >> > /* >> > - * FIXME: FF_MODE2 register is not readable till TGL B0. We can >> > - * enable verification of WA from the later steppings, which >> > enables >> > - * the read of FF_MODE2. >> > + * Wa_1604555607:gen12 >> > + * FF_MODE2 register is not readable till TGL B0, either by CPU >> > or GPU. >> >> The line above could be removed as the comments above explain it >> better, also BSpec don't say that it will be fixed in B0. > >The HW guys on discovering the bug promised it would be fixed for B0. >-Chris So... we have 2 different things here: setting the timer in FF_MODE2 is the Wa_1604555607. According to the comments on the spec it could even be treated as a general "gen12 programming mode" rather that a WA. The fact that we can't read the register since it's tied to another clock is the Wa_1608008084. I don't see it documented anywhere that it is fixed in B0. Not even as a comment to the issue. And it's in fact even marked as permanent. Lucas De Marchi _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-02-26 8:57 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-02-24 19:12 [Intel-gfx] [PATCH] drm/i915/tgl: Add Wa_1608008084 Lucas De Marchi 2020-02-24 21:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Add Wa_1608008084 (rev2) Patchwork 2020-02-26 8:56 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork -- strict thread matches above, loose matches on Subject: below -- 2020-02-22 0:28 [Intel-gfx] [PATCH] drm/i915/tgl: Add Wa_1608008084 Lucas De Marchi 2020-02-22 0:36 ` Souza, Jose 2020-02-22 1:39 ` Lucas De Marchi 2020-02-24 21:10 ` Chris Wilson 2020-02-24 21:54 ` Lucas De Marchi
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