* [PATCH] ARM: dts: uniphier: rename cache controller nodes to follow json-schema
@ 2020-02-27 12:37 ` Masahiro Yamada
0 siblings, 0 replies; 4+ messages in thread
From: Masahiro Yamada @ 2020-02-27 12:37 UTC (permalink / raw)
To: linux-arm-kernel
Cc: devicetree, Rob Herring, Frank Rowand, Masahiro Yamada,
Mark Rutland, linux-kernel
Follow the standard nodename pattern
"^(cache-controller|cpu)(@[0-9a-f,]+)*$" defined in
schemas/cache-controller.yaml of dt-schema.
Otherwise, after the dt-binding is converted to json-schema,
'make ARCH=arm dtbs_check' will show a warning like this:
l2-cache@500c0000: $nodename:0: 'l2-cache@500c0000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/boot/dts/uniphier-ld4.dtsi | 2 +-
arch/arm/boot/dts/uniphier-pro4.dtsi | 2 +-
arch/arm/boot/dts/uniphier-pro5.dtsi | 4 ++--
arch/arm/boot/dts/uniphier-pxs2.dtsi | 2 +-
arch/arm/boot/dts/uniphier-sld8.dtsi | 2 +-
5 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
index 197bee7d8b7f..06e7400d2940 100644
--- a/arch/arm/boot/dts/uniphier-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
@@ -51,7 +51,7 @@
ranges;
interrupt-parent = <&intc>;
- l2: l2-cache@500c0000 {
+ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
index b02bc8a6346b..1c866f0306fc 100644
--- a/arch/arm/boot/dts/uniphier-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
@@ -59,7 +59,7 @@
ranges;
interrupt-parent = <&intc>;
- l2: l2-cache@500c0000 {
+ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index f84a43a10f38..da772429b55a 100644
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -131,7 +131,7 @@
ranges;
interrupt-parent = <&intc>;
- l2: l2-cache@500c0000 {
+ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
@@ -144,7 +144,7 @@
next-level-cache = <&l3>;
};
- l3: l3-cache@500c8000 {
+ l3: cache-controller@500c8000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
<0x506c8000 0x400>;
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index 989b2a241822..7044f8700cb2 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -157,7 +157,7 @@
ranges;
interrupt-parent = <&intc>;
- l2: l2-cache@500c0000 {
+ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
index fbfd25050a04..09992163e1f4 100644
--- a/arch/arm/boot/dts/uniphier-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
@@ -51,7 +51,7 @@
ranges;
interrupt-parent = <&intc>;
- l2: l2-cache@500c0000 {
+ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH] ARM: dts: uniphier: rename cache controller nodes to follow json-schema
@ 2020-02-27 12:37 ` Masahiro Yamada
0 siblings, 0 replies; 4+ messages in thread
From: Masahiro Yamada @ 2020-02-27 12:37 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Mark Rutland, devicetree, linux-kernel, Masahiro Yamada,
Rob Herring, Frank Rowand
Follow the standard nodename pattern
"^(cache-controller|cpu)(@[0-9a-f,]+)*$" defined in
schemas/cache-controller.yaml of dt-schema.
Otherwise, after the dt-binding is converted to json-schema,
'make ARCH=arm dtbs_check' will show a warning like this:
l2-cache@500c0000: $nodename:0: 'l2-cache@500c0000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/boot/dts/uniphier-ld4.dtsi | 2 +-
arch/arm/boot/dts/uniphier-pro4.dtsi | 2 +-
arch/arm/boot/dts/uniphier-pro5.dtsi | 4 ++--
arch/arm/boot/dts/uniphier-pxs2.dtsi | 2 +-
arch/arm/boot/dts/uniphier-sld8.dtsi | 2 +-
5 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
index 197bee7d8b7f..06e7400d2940 100644
--- a/arch/arm/boot/dts/uniphier-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
@@ -51,7 +51,7 @@
ranges;
interrupt-parent = <&intc>;
- l2: l2-cache@500c0000 {
+ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
index b02bc8a6346b..1c866f0306fc 100644
--- a/arch/arm/boot/dts/uniphier-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
@@ -59,7 +59,7 @@
ranges;
interrupt-parent = <&intc>;
- l2: l2-cache@500c0000 {
+ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index f84a43a10f38..da772429b55a 100644
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -131,7 +131,7 @@
ranges;
interrupt-parent = <&intc>;
- l2: l2-cache@500c0000 {
+ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
@@ -144,7 +144,7 @@
next-level-cache = <&l3>;
};
- l3: l3-cache@500c8000 {
+ l3: cache-controller@500c8000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
<0x506c8000 0x400>;
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index 989b2a241822..7044f8700cb2 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -157,7 +157,7 @@
ranges;
interrupt-parent = <&intc>;
- l2: l2-cache@500c0000 {
+ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
index fbfd25050a04..09992163e1f4 100644
--- a/arch/arm/boot/dts/uniphier-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
@@ -51,7 +51,7 @@
ranges;
interrupt-parent = <&intc>;
- l2: l2-cache@500c0000 {
+ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] ARM: dts: uniphier: rename cache controller nodes to follow json-schema
2020-02-27 12:37 ` Masahiro Yamada
@ 2020-02-29 6:07 ` Masahiro Yamada
-1 siblings, 0 replies; 4+ messages in thread
From: Masahiro Yamada @ 2020-02-29 6:07 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Mark Rutland, DTML, Linux Kernel Mailing List, Rob Herring, Frank Rowand
On Thu, Feb 27, 2020 at 9:38 PM Masahiro Yamada
<yamada.masahiro@socionext.com> wrote:
>
> Follow the standard nodename pattern
> "^(cache-controller|cpu)(@[0-9a-f,]+)*$" defined in
> schemas/cache-controller.yaml of dt-schema.
>
> Otherwise, after the dt-binding is converted to json-schema,
> 'make ARCH=arm dtbs_check' will show a warning like this:
>
> l2-cache@500c0000: $nodename:0: 'l2-cache@500c0000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> ---
Applied to linux-uniphier.
>
> arch/arm/boot/dts/uniphier-ld4.dtsi | 2 +-
> arch/arm/boot/dts/uniphier-pro4.dtsi | 2 +-
> arch/arm/boot/dts/uniphier-pro5.dtsi | 4 ++--
> arch/arm/boot/dts/uniphier-pxs2.dtsi | 2 +-
> arch/arm/boot/dts/uniphier-sld8.dtsi | 2 +-
> 5 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
> index 197bee7d8b7f..06e7400d2940 100644
> --- a/arch/arm/boot/dts/uniphier-ld4.dtsi
> +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
> @@ -51,7 +51,7 @@
> ranges;
> interrupt-parent = <&intc>;
>
> - l2: l2-cache@500c0000 {
> + l2: cache-controller@500c0000 {
> compatible = "socionext,uniphier-system-cache";
> reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
> <0x506c0000 0x400>;
> diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
> index b02bc8a6346b..1c866f0306fc 100644
> --- a/arch/arm/boot/dts/uniphier-pro4.dtsi
> +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
> @@ -59,7 +59,7 @@
> ranges;
> interrupt-parent = <&intc>;
>
> - l2: l2-cache@500c0000 {
> + l2: cache-controller@500c0000 {
> compatible = "socionext,uniphier-system-cache";
> reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
> <0x506c0000 0x400>;
> diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
> index f84a43a10f38..da772429b55a 100644
> --- a/arch/arm/boot/dts/uniphier-pro5.dtsi
> +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
> @@ -131,7 +131,7 @@
> ranges;
> interrupt-parent = <&intc>;
>
> - l2: l2-cache@500c0000 {
> + l2: cache-controller@500c0000 {
> compatible = "socionext,uniphier-system-cache";
> reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
> <0x506c0000 0x400>;
> @@ -144,7 +144,7 @@
> next-level-cache = <&l3>;
> };
>
> - l3: l3-cache@500c8000 {
> + l3: cache-controller@500c8000 {
> compatible = "socionext,uniphier-system-cache";
> reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
> <0x506c8000 0x400>;
> diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
> index 989b2a241822..7044f8700cb2 100644
> --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
> +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
> @@ -157,7 +157,7 @@
> ranges;
> interrupt-parent = <&intc>;
>
> - l2: l2-cache@500c0000 {
> + l2: cache-controller@500c0000 {
> compatible = "socionext,uniphier-system-cache";
> reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
> <0x506c0000 0x400>;
> diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
> index fbfd25050a04..09992163e1f4 100644
> --- a/arch/arm/boot/dts/uniphier-sld8.dtsi
> +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
> @@ -51,7 +51,7 @@
> ranges;
> interrupt-parent = <&intc>;
>
> - l2: l2-cache@500c0000 {
> + l2: cache-controller@500c0000 {
> compatible = "socionext,uniphier-system-cache";
> reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
> <0x506c0000 0x400>;
> --
> 2.17.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] ARM: dts: uniphier: rename cache controller nodes to follow json-schema
@ 2020-02-29 6:07 ` Masahiro Yamada
0 siblings, 0 replies; 4+ messages in thread
From: Masahiro Yamada @ 2020-02-29 6:07 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Mark Rutland, DTML, Rob Herring, Frank Rowand, Linux Kernel Mailing List
On Thu, Feb 27, 2020 at 9:38 PM Masahiro Yamada
<yamada.masahiro@socionext.com> wrote:
>
> Follow the standard nodename pattern
> "^(cache-controller|cpu)(@[0-9a-f,]+)*$" defined in
> schemas/cache-controller.yaml of dt-schema.
>
> Otherwise, after the dt-binding is converted to json-schema,
> 'make ARCH=arm dtbs_check' will show a warning like this:
>
> l2-cache@500c0000: $nodename:0: 'l2-cache@500c0000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> ---
Applied to linux-uniphier.
>
> arch/arm/boot/dts/uniphier-ld4.dtsi | 2 +-
> arch/arm/boot/dts/uniphier-pro4.dtsi | 2 +-
> arch/arm/boot/dts/uniphier-pro5.dtsi | 4 ++--
> arch/arm/boot/dts/uniphier-pxs2.dtsi | 2 +-
> arch/arm/boot/dts/uniphier-sld8.dtsi | 2 +-
> 5 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
> index 197bee7d8b7f..06e7400d2940 100644
> --- a/arch/arm/boot/dts/uniphier-ld4.dtsi
> +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
> @@ -51,7 +51,7 @@
> ranges;
> interrupt-parent = <&intc>;
>
> - l2: l2-cache@500c0000 {
> + l2: cache-controller@500c0000 {
> compatible = "socionext,uniphier-system-cache";
> reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
> <0x506c0000 0x400>;
> diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
> index b02bc8a6346b..1c866f0306fc 100644
> --- a/arch/arm/boot/dts/uniphier-pro4.dtsi
> +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
> @@ -59,7 +59,7 @@
> ranges;
> interrupt-parent = <&intc>;
>
> - l2: l2-cache@500c0000 {
> + l2: cache-controller@500c0000 {
> compatible = "socionext,uniphier-system-cache";
> reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
> <0x506c0000 0x400>;
> diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
> index f84a43a10f38..da772429b55a 100644
> --- a/arch/arm/boot/dts/uniphier-pro5.dtsi
> +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
> @@ -131,7 +131,7 @@
> ranges;
> interrupt-parent = <&intc>;
>
> - l2: l2-cache@500c0000 {
> + l2: cache-controller@500c0000 {
> compatible = "socionext,uniphier-system-cache";
> reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
> <0x506c0000 0x400>;
> @@ -144,7 +144,7 @@
> next-level-cache = <&l3>;
> };
>
> - l3: l3-cache@500c8000 {
> + l3: cache-controller@500c8000 {
> compatible = "socionext,uniphier-system-cache";
> reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
> <0x506c8000 0x400>;
> diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
> index 989b2a241822..7044f8700cb2 100644
> --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
> +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
> @@ -157,7 +157,7 @@
> ranges;
> interrupt-parent = <&intc>;
>
> - l2: l2-cache@500c0000 {
> + l2: cache-controller@500c0000 {
> compatible = "socionext,uniphier-system-cache";
> reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
> <0x506c0000 0x400>;
> diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
> index fbfd25050a04..09992163e1f4 100644
> --- a/arch/arm/boot/dts/uniphier-sld8.dtsi
> +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
> @@ -51,7 +51,7 @@
> ranges;
> interrupt-parent = <&intc>;
>
> - l2: l2-cache@500c0000 {
> + l2: cache-controller@500c0000 {
> compatible = "socionext,uniphier-system-cache";
> reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
> <0x506c0000 0x400>;
> --
> 2.17.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Best Regards
Masahiro Yamada
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-02-29 6:08 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2020-02-27 12:37 [PATCH] ARM: dts: uniphier: rename cache controller nodes to follow json-schema Masahiro Yamada
2020-02-27 12:37 ` Masahiro Yamada
2020-02-29 6:07 ` Masahiro Yamada
2020-02-29 6:07 ` Masahiro Yamada
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