[PATCH 01/27] rtc: ds1337: Add driver model support

[PATCH 01/27] rtc: ds1337: Add driver model support

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

Add support of driver model of ds1337

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 drivers/rtc/ds1337.c | 127 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 127 insertions(+)

diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c
index 9b31048e97..e12d368675 100644
--- a/drivers/rtc/ds1337.c
+++ b/drivers/rtc/ds1337.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2001-2008
+ * Copyright 2020 NXP
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
  * Keith Outwater, keith_outwater at mvis.com`
  */
@@ -12,6 +13,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <dm.h>
 #include <rtc.h>
 #include <i2c.h>
 
@@ -60,6 +62,7 @@
 #define RTC_STAT_BIT_OSF	0x80	/* Oscillator stop flag		*/
 
 
+#if !CONFIG_IS_ENABLED(DM_RTC)
 static uchar rtc_read (uchar reg);
 static void rtc_write (uchar reg, uchar val);
 
@@ -188,3 +191,127 @@ static void rtc_write (uchar reg, uchar val)
 {
 	i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
 }
+#else
+static uchar rtc_read (struct udevice *dev, uchar reg)
+{
+	return (dm_i2c_reg_read (dev, reg));
+}
+
+static void rtc_write (struct udevice *dev, uchar reg, uchar val)
+{
+	dm_i2c_reg_write (dev, reg, val);
+}
+
+static int ds1337_rtc_get (struct udevice *dev, struct rtc_time *tmp)
+{
+	int rel = 0;
+	uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
+
+	control = rtc_read (dev, RTC_CTL_REG_ADDR);
+	status = rtc_read (dev, RTC_STAT_REG_ADDR);
+	sec = rtc_read (dev, RTC_SEC_REG_ADDR);
+	min = rtc_read (dev, RTC_MIN_REG_ADDR);
+	hour = rtc_read (dev, RTC_HR_REG_ADDR);
+	wday = rtc_read (dev, RTC_DAY_REG_ADDR);
+	mday = rtc_read (dev, RTC_DATE_REG_ADDR);
+	mon_cent = rtc_read (dev, RTC_MON_REG_ADDR);
+	year = rtc_read (dev, RTC_YR_REG_ADDR);
+
+	/* No century bit, assume year 2000 */
+#ifdef CONFIG_RTC_DS1388
+	mon_cent |= 0x80;
+#endif
+
+	debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
+		"hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
+		year, mon_cent, mday, wday, hour, min, sec, control, status);
+
+	if (status & RTC_STAT_BIT_OSF) {
+		printf ("### Warning: RTC oscillator has stopped\n");
+		/* clear the OSF flag */
+		rtc_write (dev, RTC_STAT_REG_ADDR,
+			   rtc_read (dev, RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
+		rel = -1;
+	}
+
+	tmp->tm_sec  = bcd2bin (sec & 0x7F);
+	tmp->tm_min  = bcd2bin (min & 0x7F);
+	tmp->tm_hour = bcd2bin (hour & 0x3F);
+	tmp->tm_mday = bcd2bin (mday & 0x3F);
+	tmp->tm_mon  = bcd2bin (mon_cent & 0x1F);
+	tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
+	tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
+	tmp->tm_yday = 0;
+	tmp->tm_isdst= 0;
+
+	debug("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+	return rel;
+}
+
+static int ds1337_rtc_set (struct udevice *dev, const struct rtc_time *tmp)
+{
+	uchar century;
+
+	debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+	rtc_write (dev, RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
+
+	century = (tmp->tm_year >= 2000) ? 0x80 : 0;
+	rtc_write (dev, RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century);
+
+	rtc_write (dev, RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
+	rtc_write (dev, RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
+	rtc_write (dev, RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
+	rtc_write (dev, RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
+	rtc_write (dev, RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
+
+	return 0;
+}
+
+#ifdef CONFIG_RTC_DS1337_NOOSC
+ #define RTC_DS1337_RESET_VAL \
+	(RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
+#else
+ #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
+#endif
+static int ds1337_rtc_reset (struct udevice *dev)
+{
+#ifdef CONFIG_RTC_DS1337
+	rtc_write (dev, RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
+#elif defined CONFIG_RTC_DS1388
+	rtc_write(dev, RTC_CTL_REG_ADDR, 0x0); /* hw default */
+#endif
+#ifdef CONFIG_RTC_DS1339_TCR_VAL
+	rtc_write (dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL);
+#endif
+#ifdef CONFIG_RTC_DS1388_TCR_VAL
+	rtc_write(dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL);
+#endif
+	return 0;
+}
+
+static const struct rtc_ops ds1337_rtc_ops = {
+	.get = ds1337_rtc_get,
+	.set = ds1337_rtc_set,
+	.reset = ds1337_rtc_reset,
+};
+
+static const struct udevice_id ds1337_rtc_ids[] = {
+	{ .compatible = "ds1337" },
+	{ .compatible = "ds1338" },
+	{ .compatible = "ds1338" },
+	{ }
+};
+
+U_BOOT_DRIVER(rtc_ds1337) = {
+	.name   = "rtc-ds1337",
+	.id     = UCLASS_RTC,
+	.of_match = ds1337_rtc_ids,
+	.ops    = &ds1337_rtc_ops,
+};
+#endif
-- 
2.17.1

[PATCH 02/27] rtc: pt7c4338: Add driver model support

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

Add support of driver model of pt7c4338

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 drivers/rtc/pt7c4338.c | 98 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 98 insertions(+)

diff --git a/drivers/rtc/pt7c4338.c b/drivers/rtc/pt7c4338.c
index 6a19fe1d23..8f69bb00e3 100644
--- a/drivers/rtc/pt7c4338.c
+++ b/drivers/rtc/pt7c4338.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2010 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  *
  * Author:	Priyanka Jain <Priyanka.Jain@freescale.com>
  */
@@ -19,6 +20,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <dm.h>
 #include <rtc.h>
 #include <i2c.h>
 
@@ -46,6 +48,7 @@
 #define RTC_PT7C4338_RESET_VAL \
 	(RTC_CTL_STAT_BIT_RS0 | RTC_CTL_STAT_BIT_RS1 | RTC_CTL_STAT_BIT_OUT)
 
+#if !CONFIG_IS_ENABLED(DM_RTC)
 /****** Helper functions ****************************************/
 static u8 rtc_read(u8 reg)
 {
@@ -125,3 +128,98 @@ void rtc_reset(void)
 	rtc_write(RTC_SEC_REG_ADDR, 0x00);	/* clearing Clock Halt	*/
 	rtc_write(RTC_CTL_STAT_REG_ADDR, RTC_PT7C4338_RESET_VAL);
 }
+#else
+static u8 rtc_read(struct udevice *dev, u8 reg)
+{
+	return dm_i2c_reg_read(dev, reg);
+}
+
+static void rtc_write(struct udevice *dev, u8 reg, u8 val)
+{
+	dm_i2c_reg_write(dev, reg, val);
+}
+
+static int pt7c4338_rtc_get(struct udevice *dev, struct rtc_time *tmp)
+{
+	int ret = 0;
+	u8 sec, min, hour, mday, wday, mon, year, ctl_stat;
+
+	ctl_stat = rtc_read(dev, RTC_CTL_STAT_REG_ADDR);
+	sec = rtc_read(dev, RTC_SEC_REG_ADDR);
+	min = rtc_read(dev, RTC_MIN_REG_ADDR);
+	hour = rtc_read(dev, RTC_HR_REG_ADDR);
+	wday = rtc_read(dev, RTC_DAY_REG_ADDR);
+	mday = rtc_read(dev, RTC_DATE_REG_ADDR);
+	mon = rtc_read(dev, RTC_MON_REG_ADDR);
+	year = rtc_read(dev, RTC_YR_REG_ADDR);
+	debug("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
+		"hr: %02x min: %02x sec: %02x control_status: %02x\n",
+		year, mon, mday, wday, hour, min, sec, ctl_stat);
+
+	if (ctl_stat & RTC_CTL_STAT_BIT_OSF) {
+		printf("### Warning: RTC oscillator has stopped\n");
+		/* clear the OSF flag */
+		rtc_write(dev, RTC_CTL_STAT_REG_ADDR,
+			rtc_read(dev, RTC_CTL_STAT_REG_ADDR)\
+			& ~RTC_CTL_STAT_BIT_OSF);
+		ret = -1;
+	}
+
+	tmp->tm_sec = bcd2bin(sec & 0x7F);
+	tmp->tm_min = bcd2bin(min & 0x7F);
+	tmp->tm_hour = bcd2bin(hour & 0x3F);
+	tmp->tm_mday = bcd2bin(mday & 0x3F);
+	tmp->tm_mon = bcd2bin(mon & 0x1F);
+	tmp->tm_year = bcd2bin(year) + 2000;
+	tmp->tm_wday = bcd2bin((wday - 1) & 0x07);
+	tmp->tm_yday = 0;
+	tmp->tm_isdst = 0;
+	debug("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+	return ret;
+}
+
+static int pt7c4338_rtc_set(struct udevice *dev, const struct rtc_time *tmp)
+{
+	debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+	rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100));
+	rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon));
+	rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday + 1));
+	rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday));
+	rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour));
+	rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min));
+	rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec));
+
+	return 0;
+}
+
+static int pt7c4338_rtc_reset(struct udevice *dev)
+{
+	rtc_write(dev, RTC_SEC_REG_ADDR, 0x00);	/* clearing Clock Halt	*/
+	rtc_write(dev, RTC_CTL_STAT_REG_ADDR, RTC_PT7C4338_RESET_VAL);
+	return 0;
+}
+
+static const struct rtc_ops pt7c4338_rtc_ops = {
+	.get = pt7c4338_rtc_get,
+	.set = pt7c4338_rtc_set,
+	.reset = pt7c4338_rtc_reset,
+};
+
+static const struct udevice_id pt7c4338_rtc_ids[] = {
+	{ .compatible = "pericom,pt7c4338" },
+	{ }
+};
+
+U_BOOT_DRIVER(rtc_pt7c4338) = {
+	.name   = "rtc-pt7c4338",
+	.id     = UCLASS_RTC,
+	.of_match = pt7c4338_rtc_ids,
+	.ops    = &pt7c4338_rtc_ops,
+};
+#endif
-- 
2.17.1

[PATCH 02/27] rtc: pt7c4338: Add driver model support

[Priyanka Jain]

>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Biwen Li
>Sent: Sunday, April 12, 2020 2:24 PM
>To: Jagdish Gediya <jagdish.gediya@nxp.com>; Priyanka Jain
><priyanka.jain@nxp.com>; hs at denx.de; jagan at amarulasolutions.com;
>aford173 at gmail.com; Alison Wang <alison.wang@nxp.com>;
>jh80.chung at samsung.com; Pramod Kumar <pramod.kumar_1@nxp.com>;
>Rajesh Bhagat <rajesh.bhagat@nxp.com>; Ruchika Gupta
><ruchika.gupta@nxp.com>; olteanv at gmail.com
>Cc: Xiaobo Xie <xiaobo.xie@nxp.com>; Jiafei Pan <jiafei.pan@nxp.com>; u-
>boot at lists.denx.de; Z.q. Hou <zhiqiang.hou@nxp.com>; Biwen Li
><biwen.li@nxp.com>
>Subject: [PATCH 02/27] rtc: pt7c4338: Add driver model support
>
>From: Biwen Li <biwen.li@nxp.com>
>
>Add support of driver model of pt7c4338
>
>Signed-off-by: Biwen Li <biwen.li@nxp.com>
>---
> drivers/rtc/pt7c4338.c | 98
>++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 98 insertions(+)
>
>diff --git a/drivers/rtc/pt7c4338.c b/drivers/rtc/pt7c4338.c index
>6a19fe1d23..8f69bb00e3 100644
>--- a/drivers/rtc/pt7c4338.c
>+++ b/drivers/rtc/pt7c4338.c
>@@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
>  * Copyright 2010 Freescale Semiconductor, Inc.
>+ * Copyright 2020 NXP
>  *
>  * Author:	Priyanka Jain <Priyanka.Jain@freescale.com>
>  */
>@@ -19,6 +20,7 @@
>
> #include <common.h>
> #include <command.h>
>+#include <dm.h>
> #include <rtc.h>
> #include <i2c.h>
>
>@@ -46,6 +48,7 @@
> #define RTC_PT7C4338_RESET_VAL \
> 	(RTC_CTL_STAT_BIT_RS0 | RTC_CTL_STAT_BIT_RS1 |
>RTC_CTL_STAT_BIT_OUT)
>
>+#if !CONFIG_IS_ENABLED(DM_RTC)
> /****** Helper functions ****************************************/
> static u8 rtc_read(u8 reg)
> {
>@@ -125,3 +128,98 @@ void rtc_reset(void)
> 	rtc_write(RTC_SEC_REG_ADDR, 0x00);	/* clearing Clock Halt	*/
> 	rtc_write(RTC_CTL_STAT_REG_ADDR, RTC_PT7C4338_RESET_VAL);  }
>+#else
>+static u8 rtc_read(struct udevice *dev, u8 reg) {
>+	return dm_i2c_reg_read(dev, reg);
>+}
>+
>+static void rtc_write(struct udevice *dev, u8 reg, u8 val) {
>+	dm_i2c_reg_write(dev, reg, val);
>+}
>+
>+static int pt7c4338_rtc_get(struct udevice *dev, struct rtc_time *tmp)
>+{
>+	int ret = 0;
>+	u8 sec, min, hour, mday, wday, mon, year, ctl_stat;
>+
>+	ctl_stat = rtc_read(dev, RTC_CTL_STAT_REG_ADDR);
>+	sec = rtc_read(dev, RTC_SEC_REG_ADDR);
>+	min = rtc_read(dev, RTC_MIN_REG_ADDR);
>+	hour = rtc_read(dev, RTC_HR_REG_ADDR);
>+	wday = rtc_read(dev, RTC_DAY_REG_ADDR);
>+	mday = rtc_read(dev, RTC_DATE_REG_ADDR);
>+	mon = rtc_read(dev, RTC_MON_REG_ADDR);
>+	year = rtc_read(dev, RTC_YR_REG_ADDR);
>+	debug("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
>+		"hr: %02x min: %02x sec: %02x control_status: %02x\n",
>+		year, mon, mday, wday, hour, min, sec, ctl_stat);
>+
>+	if (ctl_stat & RTC_CTL_STAT_BIT_OSF) {
>+		printf("### Warning: RTC oscillator has stopped\n");
>+		/* clear the OSF flag */
>+		rtc_write(dev, RTC_CTL_STAT_REG_ADDR,
>+			rtc_read(dev, RTC_CTL_STAT_REG_ADDR)\
>+			& ~RTC_CTL_STAT_BIT_OSF);
>+		ret = -1;
>+	}
>+
>+	tmp->tm_sec = bcd2bin(sec & 0x7F);
>+	tmp->tm_min = bcd2bin(min & 0x7F);
>+	tmp->tm_hour = bcd2bin(hour & 0x3F);
>+	tmp->tm_mday = bcd2bin(mday & 0x3F);
>+	tmp->tm_mon = bcd2bin(mon & 0x1F);
>+	tmp->tm_year = bcd2bin(year) + 2000;
>+	tmp->tm_wday = bcd2bin((wday - 1) & 0x07);
>+	tmp->tm_yday = 0;
>+	tmp->tm_isdst = 0;
>+	debug("Get DATE: %4d-%02d-%02d (wday=%d)  TIME:
>%2d:%02d:%02d\n",
>+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp-
>>tm_wday,
>+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
>+
>+	return ret;
>+}
>+
>+static int pt7c4338_rtc_set(struct udevice *dev, const struct rtc_time
>+*tmp) {
>+	debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME:
>%2d:%02d:%02d\n",
>+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp-
>>tm_wday,
>+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
>+
>+	rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100));
>+	rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon));
>+	rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday + 1));
>+	rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday));
>+	rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour));
>+	rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min));
>+	rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec));
>+
>+	return 0;
>+}
>+
>+static int pt7c4338_rtc_reset(struct udevice *dev) {
>+	rtc_write(dev, RTC_SEC_REG_ADDR, 0x00);	/* clearing Clock Halt
>	*/
>+	rtc_write(dev, RTC_CTL_STAT_REG_ADDR,
>RTC_PT7C4338_RESET_VAL);
>+	return 0;
>+}
>+
>+static const struct rtc_ops pt7c4338_rtc_ops = {
>+	.get = pt7c4338_rtc_get,
>+	.set = pt7c4338_rtc_set,
>+	.reset = pt7c4338_rtc_reset,
>+};
>+
>+static const struct udevice_id pt7c4338_rtc_ids[] = {
>+	{ .compatible = "pericom,pt7c4338" },
>+	{ }
>+};
>+
>+U_BOOT_DRIVER(rtc_pt7c4338) = {
>+	.name   = "rtc-pt7c4338",
>+	.id     = UCLASS_RTC,
>+	.of_match = pt7c4338_rtc_ids,
>+	.ops    = &pt7c4338_rtc_ops,
>+};
>+#endif
>--
>2.17.1
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

[PATCH 03/27] powerpc: create dts component of i2c to build up an SoC

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

Provide a common i2c components that we can utilize to
build up the various device tree.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 arch/powerpc/dts/pq3-i2c-0.dtsi   | 15 +++++++++++++++
 arch/powerpc/dts/pq3-i2c-1.dtsi   | 15 +++++++++++++++
 arch/powerpc/dts/qoriq-i2c-0.dtsi | 26 ++++++++++++++++++++++++++
 arch/powerpc/dts/qoriq-i2c-1.dtsi | 26 ++++++++++++++++++++++++++
 4 files changed, 82 insertions(+)
 create mode 100644 arch/powerpc/dts/pq3-i2c-0.dtsi
 create mode 100644 arch/powerpc/dts/pq3-i2c-1.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-i2c-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-i2c-1.dtsi

diff --git a/arch/powerpc/dts/pq3-i2c-0.dtsi b/arch/powerpc/dts/pq3-i2c-0.dtsi
new file mode 100644
index 0000000000..86a91e6336
--- /dev/null
+++ b/arch/powerpc/dts/pq3-i2c-0.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 I2C Device Tree stub
+ *
+ * Copyright 2020 NXP
+ */
+i2c at 3000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	cell-index = <0>;
+	compatible = "fsl-i2c";
+	u-boot,dm-pre-reloc;
+	reg = <0x3000 0x100>;
+	interrupts = <43 2 0 0>;
+};
diff --git a/arch/powerpc/dts/pq3-i2c-1.dtsi b/arch/powerpc/dts/pq3-i2c-1.dtsi
new file mode 100644
index 0000000000..5d79b1fb4c
--- /dev/null
+++ b/arch/powerpc/dts/pq3-i2c-1.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 I2C Device Tree stub
+ *
+ * Copyright 2020 NXP
+ */
+i2c at 3100 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	cell-index = <1>;
+	compatible = "fsl-i2c";
+	u-boot,dm-pre-reloc;
+	reg = <0x3100 0x100>;
+	interrupts = <43 2 0 0>;
+};
diff --git a/arch/powerpc/dts/qoriq-i2c-0.dtsi b/arch/powerpc/dts/qoriq-i2c-0.dtsi
new file mode 100644
index 0000000000..f9f979e041
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-i2c-0.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * QorIQ I2C Device Tree stub
+ *
+ * Copyright 2020 NXP
+ */
+i2c0: i2c at 118000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	cell-index = <0>;
+	compatible = "fsl-i2c";
+	u-boot,dm-pre-reloc;
+	reg = <0x118000 0x100>;
+	interrupts = <38 2 0 0>;
+};
+
+i2c1: i2c at 118100 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	cell-index = <1>;
+	compatible = "fsl-i2c";
+	u-boot,dm-pre-reloc;
+	reg = <0x118100 0x100>;
+	interrupts = <38 2 0 0>;
+};
+
diff --git a/arch/powerpc/dts/qoriq-i2c-1.dtsi b/arch/powerpc/dts/qoriq-i2c-1.dtsi
new file mode 100644
index 0000000000..e065ddd472
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-i2c-1.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * QorIQ I2C Device Tree stub
+ *
+ * Copyright 2020 NXP
+ */
+i2c2: i2c at 119000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	cell-index = <2>;
+	compatible = "fsl-i2c";
+	u-boot,dm-pre-reloc;
+	reg = <0x119000 0x100>;
+	interrupts = <39 2 0 0>;
+};
+
+i2c3: i2c at 119100 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	cell-index = <3>;
+	compatible = "fsl-i2c";
+	u-boot,dm-pre-reloc;
+	reg = <0x119100 0x100>;
+	interrupts = <39 2 0 0>;
+};
+
-- 
2.17.1

[PATCH 04/27] dm: powerpc: P5040DS: add i2c DM support

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This supports i2c DM for board P5040DS

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 arch/powerpc/dts/p5040.dtsi  | 5 ++++-
 include/configs/corenet_ds.h | 8 +++++++-
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi
index 67a62a7725..45988574a2 100644
--- a/arch/powerpc/dts/p5040.dtsi
+++ b/arch/powerpc/dts/p5040.dtsi
@@ -3,7 +3,7 @@
  * P5040 Silicon/SoC Device Tree Source (pre include)
  *
  * Copyright 2012 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
  */
 
 /dts-v1/;
@@ -85,6 +85,9 @@
 			reg = <0x114000 0x1000>;
 			clock-frequency = <0>;
 		};
+
+		/include/ "qoriq-i2c-0.dtsi"
+		/include/ "qoriq-i2c-1.dtsi"
 	};
 
 	pcie at ffe200000 {
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index bafedcb0d2..d8402e493d 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2009-2012 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 /*
@@ -276,14 +277,19 @@
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 
 /* I2C */
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
+#else
+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
+#endif
+#define CONFIG_SYS_I2C_FSL
 
 /*
  * RapidIO
-- 
2.17.1

[PATCH 04/27] dm: powerpc: P5040DS: add i2c DM support

[Priyanka Jain]

>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Biwen Li
>Sent: Sunday, April 12, 2020 2:24 PM
>To: Jagdish Gediya <jagdish.gediya@nxp.com>; Priyanka Jain
><priyanka.jain@nxp.com>; hs at denx.de; jagan at amarulasolutions.com;
>aford173 at gmail.com; Alison Wang <alison.wang@nxp.com>;
>jh80.chung at samsung.com; Pramod Kumar <pramod.kumar_1@nxp.com>;
>Rajesh Bhagat <rajesh.bhagat@nxp.com>; Ruchika Gupta
><ruchika.gupta@nxp.com>; olteanv at gmail.com
>Cc: Xiaobo Xie <xiaobo.xie@nxp.com>; Jiafei Pan <jiafei.pan@nxp.com>; u-
>boot at lists.denx.de; Z.q. Hou <zhiqiang.hou@nxp.com>; Biwen Li
><biwen.li@nxp.com>
>Subject: [PATCH 04/27] dm: powerpc: P5040DS: add i2c DM support
>
>From: Biwen Li <biwen.li@nxp.com>
>
>This supports i2c DM for board P5040DS
>
>Signed-off-by: Biwen Li <biwen.li@nxp.com>
>---
> arch/powerpc/dts/p5040.dtsi  | 5 ++++-
> include/configs/corenet_ds.h | 8 +++++++-
> 2 files changed, 11 insertions(+), 2 deletions(-)
>
>diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi
>index 67a62a7725..45988574a2 100644
>--- a/arch/powerpc/dts/p5040.dtsi
>+++ b/arch/powerpc/dts/p5040.dtsi
>@@ -3,7 +3,7 @@
>  * P5040 Silicon/SoC Device Tree Source (pre include)
>  *
>  * Copyright 2012 - 2015 Freescale Semiconductor Inc.
>- * Copyright 2019 NXP
>+ * Copyright 2019-2020 NXP
>  */
>
> /dts-v1/;
>@@ -85,6 +85,9 @@
> 			reg = <0x114000 0x1000>;
> 			clock-frequency = <0>;
> 		};
>+
>+		/include/ "qoriq-i2c-0.dtsi"
>+		/include/ "qoriq-i2c-1.dtsi"
> 	};
>
> 	pcie at ffe200000 {
>diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index
>bafedcb0d2..d8402e493d 100644
>--- a/include/configs/corenet_ds.h
>+++ b/include/configs/corenet_ds.h
Biwen,

Please confirm that P5040DS is the only board using corenet_ds.h file

Regards
Priyanka
>@@ -1,6 +1,7 @@
> /* SPDX-License-Identifier: GPL-2.0+ */
> /*
>  * Copyright 2009-2012 Freescale Semiconductor, Inc.
>+ * Copyright 2020 NXP
>  */
>
> /*
>@@ -276,14 +277,19 @@
> #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
>
> /* I2C */
>+#ifndef CONFIG_DM_I2C
> #define CONFIG_SYS_I2C
>-#define CONFIG_SYS_I2C_FSL
> #define CONFIG_SYS_FSL_I2C_SPEED	400000
> #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
> #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
> #define CONFIG_SYS_FSL_I2C2_SPEED	400000
> #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
> #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
>+#else
>+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
>+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
>+#endif
>+#define CONFIG_SYS_I2C_FSL
>
> /*
>  * RapidIO
>--
>2.17.1

[PATCH 04/27] dm: powerpc: P5040DS: add i2c DM support

[Biwen Li]

> >---
> > arch/powerpc/dts/p5040.dtsi  | 5 ++++-  include/configs/corenet_ds.h |
> >8 +++++++-
> > 2 files changed, 11 insertions(+), 2 deletions(-)
> >
> >diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi
> >index 67a62a7725..45988574a2 100644
> >--- a/arch/powerpc/dts/p5040.dtsi
> >+++ b/arch/powerpc/dts/p5040.dtsi
> >@@ -3,7 +3,7 @@
> >  * P5040 Silicon/SoC Device Tree Source (pre include)
> >  *
> >  * Copyright 2012 - 2015 Freescale Semiconductor Inc.
> >- * Copyright 2019 NXP
> >+ * Copyright 2019-2020 NXP
> >  */
> >
> > /dts-v1/;
> >@@ -85,6 +85,9 @@
> > 			reg = <0x114000 0x1000>;
> > 			clock-frequency = <0>;
> > 		};
> >+
> >+		/include/ "qoriq-i2c-0.dtsi"
> >+		/include/ "qoriq-i2c-1.dtsi"
> > 	};
> >
> > 	pcie at ffe200000 {
> >diff --git a/include/configs/corenet_ds.h
> >b/include/configs/corenet_ds.h index bafedcb0d2..d8402e493d 100644
> >--- a/include/configs/corenet_ds.h
> >+++ b/include/configs/corenet_ds.h
> Biwen,
> 
> Please confirm that P5040DS is the only board using corenet_ds.h file
No, P3041DS, P4080DS also nned the header file.
> 
> Regards
> Priyanka
> >@@ -1,6 +1,7 @@
> > /* SPDX-License-Identifier: GPL-2.0+ */
> > /*
> >  * Copyright 2009-2012 Freescale Semiconductor, Inc.
> >+ * Copyright 2020 NXP
> >  */
> >
> > /*
> >@@ -276,14 +277,19 @@
> > #define CONFIG_SYS_NS16550_COM4
> 	(CONFIG_SYS_CCSRBAR+0x11D600)
> >
> > /* I2C */
> >+#ifndef CONFIG_DM_I2C
> > #define CONFIG_SYS_I2C
> >-#define CONFIG_SYS_I2C_FSL
> > #define CONFIG_SYS_FSL_I2C_SPEED	400000
> > #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
> > #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
> > #define CONFIG_SYS_FSL_I2C2_SPEED	400000
> > #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
> > #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
> >+#else
> >+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
> >+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
> >+#endif
> >+#define CONFIG_SYS_I2C_FSL
> >
> > /*
> >  * RapidIO
> >--
> >2.17.1

[PATCH 05/27] configs: P5040DS: enable DM_I2C

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This enable DM_I2C in P5040DS defconfigs,
except P5040DS SECURE_BOOT defconfigs

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 configs/P5040DS_NAND_defconfig     | 1 +
 configs/P5040DS_SDCARD_defconfig   | 1 +
 configs/P5040DS_SPIFLASH_defconfig | 1 +
 configs/P5040DS_defconfig          | 1 +
 4 files changed, 4 insertions(+)

diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index 4c3f705238..6f6f672762 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -59,3 +59,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index 3874e06f31..2b9ac1cb19 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -57,3 +57,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index 09c13fecd6..612121d490 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -58,3 +58,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index d531401796..9c26705bf9 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -56,3 +56,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
-- 
2.17.1

[PATCH 05/27] configs: P5040DS: enable DM_I2C

[Priyanka Jain]

>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Biwen Li
>Sent: Sunday, April 12, 2020 2:24 PM
>To: Jagdish Gediya <jagdish.gediya@nxp.com>; Priyanka Jain
><priyanka.jain@nxp.com>; hs at denx.de; jagan at amarulasolutions.com;
>aford173 at gmail.com; Alison Wang <alison.wang@nxp.com>;
>jh80.chung at samsung.com; Pramod Kumar <pramod.kumar_1@nxp.com>;
>Rajesh Bhagat <rajesh.bhagat@nxp.com>; Ruchika Gupta
><ruchika.gupta@nxp.com>; olteanv at gmail.com
>Cc: Xiaobo Xie <xiaobo.xie@nxp.com>; Jiafei Pan <jiafei.pan@nxp.com>; u-
>boot at lists.denx.de; Z.q. Hou <zhiqiang.hou@nxp.com>; Biwen Li
><biwen.li@nxp.com>
>Subject: [PATCH 05/27] configs: P5040DS: enable DM_I2C
>
>From: Biwen Li <biwen.li@nxp.com>
>
>This enable DM_I2C in P5040DS defconfigs, except P5040DS SECURE_BOOT
>defconfigs
Why P5040DS_SECURE_BOOT is not covered? Any particular reason?

Regards
Priyanka
>
>Signed-off-by: Biwen Li <biwen.li@nxp.com>
>---
> configs/P5040DS_NAND_defconfig     | 1 +
> configs/P5040DS_SDCARD_defconfig   | 1 +
> configs/P5040DS_SPIFLASH_defconfig | 1 +
> configs/P5040DS_defconfig          | 1 +
> 4 files changed, 4 insertions(+)
>
>diff --git a/configs/P5040DS_NAND_defconfig
>b/configs/P5040DS_NAND_defconfig index 4c3f705238..6f6f672762 100644
>--- a/configs/P5040DS_NAND_defconfig
>+++ b/configs/P5040DS_NAND_defconfig
>@@ -59,3 +59,4 @@ CONFIG_SPI=y
> CONFIG_FSL_ESPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
>+CONFIG_DM_I2C=y
>diff --git a/configs/P5040DS_SDCARD_defconfig
>b/configs/P5040DS_SDCARD_defconfig
>index 3874e06f31..2b9ac1cb19 100644
>--- a/configs/P5040DS_SDCARD_defconfig
>+++ b/configs/P5040DS_SDCARD_defconfig
>@@ -57,3 +57,4 @@ CONFIG_SPI=y
> CONFIG_FSL_ESPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
>+CONFIG_DM_I2C=y
>diff --git a/configs/P5040DS_SPIFLASH_defconfig
>b/configs/P5040DS_SPIFLASH_defconfig
>index 09c13fecd6..612121d490 100644
>--- a/configs/P5040DS_SPIFLASH_defconfig
>+++ b/configs/P5040DS_SPIFLASH_defconfig
>@@ -58,3 +58,4 @@ CONFIG_SPI=y
> CONFIG_FSL_ESPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
>+CONFIG_DM_I2C=y
>diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index
>d531401796..9c26705bf9 100644
>--- a/configs/P5040DS_defconfig
>+++ b/configs/P5040DS_defconfig
>@@ -56,3 +56,4 @@ CONFIG_SPI=y
> CONFIG_FSL_ESPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
>+CONFIG_DM_I2C=y
>--
>2.17.1

[PATCH 05/27] configs: P5040DS: enable DM_I2C

[Biwen Li]

> 
> >-----Original Message-----
> >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Biwen Li
> >Sent: Sunday, April 12, 2020 2:24 PM
> >To: Jagdish Gediya <jagdish.gediya@nxp.com>; Priyanka Jain
> ><priyanka.jain@nxp.com>; hs at denx.de; jagan at amarulasolutions.com;
> >aford173 at gmail.com; Alison Wang <alison.wang@nxp.com>;
> >jh80.chung at samsung.com; Pramod Kumar <pramod.kumar_1@nxp.com>;
> Rajesh
> >Bhagat <rajesh.bhagat@nxp.com>; Ruchika Gupta
> <ruchika.gupta@nxp.com>;
> >olteanv at gmail.com
> >Cc: Xiaobo Xie <xiaobo.xie@nxp.com>; Jiafei Pan <jiafei.pan@nxp.com>;
> >u- boot at lists.denx.de; Z.q. Hou <zhiqiang.hou@nxp.com>; Biwen Li
> ><biwen.li@nxp.com>
> >Subject: [PATCH 05/27] configs: P5040DS: enable DM_I2C
> >
> >From: Biwen Li <biwen.li@nxp.com>
> >
> >This enable DM_I2C in P5040DS defconfigs, except P5040DS SECURE_BOOT
> >defconfigs
> Why P5040DS_SECURE_BOOT is not covered? Any particular reason?
Currently doesn't support dm in SECURE BOOT for powerpc architecture.
It needs some efforts to test SECURE BOOT.(My patch also depend on other patches when enable DM_I2C for SECURE BOOT ) 
> 
> Regards
> Priyanka
> >
> >Signed-off-by: Biwen Li <biwen.li@nxp.com>
> >---
> > configs/P5040DS_NAND_defconfig     | 1 +
> > configs/P5040DS_SDCARD_defconfig   | 1 +
> > configs/P5040DS_SPIFLASH_defconfig | 1 +
> > configs/P5040DS_defconfig          | 1 +
> > 4 files changed, 4 insertions(+)
> >
> >diff --git a/configs/P5040DS_NAND_defconfig
> >b/configs/P5040DS_NAND_defconfig index 4c3f705238..6f6f672762 100644
> >--- a/configs/P5040DS_NAND_defconfig
> >+++ b/configs/P5040DS_NAND_defconfig
> >@@ -59,3 +59,4 @@ CONFIG_SPI=y
> > CONFIG_FSL_ESPI=y
> > CONFIG_USB=y
> > CONFIG_DM_USB=y
> >+CONFIG_DM_I2C=y
> >diff --git a/configs/P5040DS_SDCARD_defconfig
> >b/configs/P5040DS_SDCARD_defconfig
> >index 3874e06f31..2b9ac1cb19 100644
> >--- a/configs/P5040DS_SDCARD_defconfig
> >+++ b/configs/P5040DS_SDCARD_defconfig
> >@@ -57,3 +57,4 @@ CONFIG_SPI=y
> > CONFIG_FSL_ESPI=y
> > CONFIG_USB=y
> > CONFIG_DM_USB=y
> >+CONFIG_DM_I2C=y
> >diff --git a/configs/P5040DS_SPIFLASH_defconfig
> >b/configs/P5040DS_SPIFLASH_defconfig
> >index 09c13fecd6..612121d490 100644
> >--- a/configs/P5040DS_SPIFLASH_defconfig
> >+++ b/configs/P5040DS_SPIFLASH_defconfig
> >@@ -58,3 +58,4 @@ CONFIG_SPI=y
> > CONFIG_FSL_ESPI=y
> > CONFIG_USB=y
> > CONFIG_DM_USB=y
> >+CONFIG_DM_I2C=y
> >diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
> >index
> >d531401796..9c26705bf9 100644
> >--- a/configs/P5040DS_defconfig
> >+++ b/configs/P5040DS_defconfig
> >@@ -56,3 +56,4 @@ CONFIG_SPI=y
> > CONFIG_FSL_ESPI=y
> > CONFIG_USB=y
> > CONFIG_DM_USB=y
> >+CONFIG_DM_I2C=y
> >--
> >2.17.1

[PATCH 06/27] dm: powerpc: P1020: add i2c DM support

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This supports i2c DM for SoC P1020

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 arch/powerpc/dts/p1020-post.dtsi            |  2 ++
 arch/powerpc/dts/p1020.dtsi                 |  2 +-
 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 24 ++++++++++++++++++++-
 include/configs/P1022DS.h                   |  5 ++++-
 include/configs/p1_p2_rdb_pc.h              |  7 ++++++
 5 files changed, 37 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi
index 1c77702f01..1dce8e86e9 100644
--- a/arch/powerpc/dts/p1020-post.dtsi
+++ b/arch/powerpc/dts/p1020-post.dtsi
@@ -44,6 +44,8 @@
 		clock-frequency = <0>;
 	};
 
+	/include/ "pq3-i2c-0.dtsi"
+	/include/ "pq3-i2c-1.dtsi"
 };
 
 /* PCIe controller base address 0x9000 */
diff --git a/arch/powerpc/dts/p1020.dtsi b/arch/powerpc/dts/p1020.dtsi
index ee2b6f4945..facc251953 100644
--- a/arch/powerpc/dts/p1020.dtsi
+++ b/arch/powerpc/dts/p1020.dtsi
@@ -3,7 +3,7 @@
  * P1020 Silicon/SoC Device Tree Source (pre include)
  *
  * Copyright 2013 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
  */
 
 /dts-v1/;
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 71fca8ca1e..f668d7efb1 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 #include <common.h>
@@ -227,6 +228,7 @@ int checkboard(void)
 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	u8 in, out, io_config, val;
+	int bus_num = CONFIG_SYS_SPD_BUS_NUM;
 
 	printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
 		in_8(&cpld_data->cpld_rev_major) & 0x0F,
@@ -234,7 +236,26 @@ int checkboard(void)
 		in_8(&cpld_data->pcba_rev) & 0x0F);
 
 	/* Initialize i2c early for rom_loc and flash bank information */
-	i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
+	#if defined(CONFIG_DM_I2C)
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_PCA9557_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return -ENXIO;
+	}
+
+	if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
+	    dm_i2c_read(dev, 1, &out, 1) < 0 ||
+	    dm_i2c_read(dev, 3, &io_config, 1) < 0) {
+		printf("Error reading i2c boot information!\n");
+		return 0; /* Don't want to hang() on this error */
+	}
+	#else /* Non DM I2C support - will be removed */
+	i2c_set_bus_num(bus_num);
 
 	if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
 	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
@@ -242,6 +263,7 @@ int checkboard(void)
 		printf("Error reading i2c boot information!\n");
 		return 0; /* Don't want to hang() on this error */
 	}
+	#endif
 
 	val = (in & io_config) | (out & (~io_config));
 
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 5cc2e06979..f1d77c8e1c 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -359,16 +359,19 @@
 #endif
 
 /* I2C */
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#endif
+
 #define CONFIG_SYS_I2C_NOPROBES		{{0, 0x29}}
 
+#define CONFIG_SYS_I2C_FSL
 /*
  * I2C2 EEPROM
  */
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index c42f1a9fce..7089b69bf3 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 /*
@@ -546,6 +547,12 @@
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
+#else
+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
+#endif
+
+#define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
 #define CONFIG_SYS_SPD_BUS_NUM		1 /* For rom_loc and flash bank */
 
-- 
2.17.1

[PATCH 06/27] dm: powerpc: P1020: add i2c DM support

[Priyanka Jain]

>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Biwen Li
>Sent: Sunday, April 12, 2020 2:24 PM
>To: Jagdish Gediya <jagdish.gediya@nxp.com>; Priyanka Jain
><priyanka.jain@nxp.com>; hs at denx.de; jagan at amarulasolutions.com;
>aford173 at gmail.com; Alison Wang <alison.wang@nxp.com>;
>jh80.chung at samsung.com; Pramod Kumar <pramod.kumar_1@nxp.com>;
>Rajesh Bhagat <rajesh.bhagat@nxp.com>; Ruchika Gupta
><ruchika.gupta@nxp.com>; olteanv at gmail.com
>Cc: Xiaobo Xie <xiaobo.xie@nxp.com>; Jiafei Pan <jiafei.pan@nxp.com>; u-
>boot at lists.denx.de; Z.q. Hou <zhiqiang.hou@nxp.com>; Biwen Li
><biwen.li@nxp.com>
>Subject: [PATCH 06/27] dm: powerpc: P1020: add i2c DM support
>
>From: Biwen Li <biwen.li@nxp.com>
>
>This supports i2c DM for SoC P1020
>
>Signed-off-by: Biwen Li <biwen.li@nxp.com>
>---
> arch/powerpc/dts/p1020-post.dtsi            |  2 ++
> arch/powerpc/dts/p1020.dtsi                 |  2 +-
> board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 24
>++++++++++++++++++++-
> include/configs/P1022DS.h                   |  5 ++++-
> include/configs/p1_p2_rdb_pc.h              |  7 ++++++
> 5 files changed, 37 insertions(+), 3 deletions(-)
>
>diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-
>post.dtsi
>index 1c77702f01..1dce8e86e9 100644
>--- a/arch/powerpc/dts/p1020-post.dtsi
>+++ b/arch/powerpc/dts/p1020-post.dtsi
>@@ -44,6 +44,8 @@
> 		clock-frequency = <0>;
> 	};
>
>+	/include/ "pq3-i2c-0.dtsi"
>+	/include/ "pq3-i2c-1.dtsi"
> };
>
> /* PCIe controller base address 0x9000 */ diff --git
>a/arch/powerpc/dts/p1020.dtsi b/arch/powerpc/dts/p1020.dtsi index
>ee2b6f4945..facc251953 100644
>--- a/arch/powerpc/dts/p1020.dtsi
>+++ b/arch/powerpc/dts/p1020.dtsi
>@@ -3,7 +3,7 @@
>  * P1020 Silicon/SoC Device Tree Source (pre include)
>  *
>  * Copyright 2013 Freescale Semiconductor Inc.
>- * Copyright 2019 NXP
>+ * Copyright 2019-2020 NXP
>  */
>
> /dts-v1/;
>diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
>b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
>index 71fca8ca1e..f668d7efb1 100644
>--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
>+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
>@@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
>  * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
>+ * Copyright 2020 NXP
>  */
>
> #include <common.h>
>@@ -227,6 +228,7 @@ int checkboard(void)
> 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
> 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> 	u8 in, out, io_config, val;
>+	int bus_num = CONFIG_SYS_SPD_BUS_NUM;
>
> 	printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n",
>CONFIG_BOARDNAME,
> 		in_8(&cpld_data->cpld_rev_major) & 0x0F, @@ -234,7
>+236,26 @@ int checkboard(void)
> 		in_8(&cpld_data->pcba_rev) & 0x0F);
>
> 	/* Initialize i2c early for rom_loc and flash bank information */
>-	i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
>+	#if defined(CONFIG_DM_I2C)
>+	struct udevice *dev;
>+	int ret;
>+
>+	ret = i2c_get_chip_for_busnum(bus_num,
>CONFIG_SYS_I2C_PCA9557_ADDR,
>+				      1, &dev);
>+	if (ret) {
>+		printf("%s: Cannot find udev for a bus %d\n", __func__,
>+		       bus_num);
>+		return -ENXIO;
>+	}
>+
>+	if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
>+	    dm_i2c_read(dev, 1, &out, 1) < 0 ||
>+	    dm_i2c_read(dev, 3, &io_config, 1) < 0) {
>+		printf("Error reading i2c boot information!\n");
>+		return 0; /* Don't want to hang() on this error */
>+	}
>+	#else /* Non DM I2C support - will be removed */
>+	i2c_set_bus_num(bus_num);
>
> 	if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
> 	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
>@@ -242,6 +263,7 @@ int checkboard(void)
> 		printf("Error reading i2c boot information!\n");
> 		return 0; /* Don't want to hang() on this error */
> 	}
>+	#endif
>
> 	val = (in & io_config) | (out & (~io_config));
>
>diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index
>5cc2e06979..f1d77c8e1c 100644
>--- a/include/configs/P1022DS.h
>+++ b/include/configs/P1022DS.h
>@@ -359,16 +359,19 @@
> #endif
>
> /* I2C */
>+#ifndef CONFIG_DM_I2C
> #define CONFIG_SYS_I2C
>-#define CONFIG_SYS_I2C_FSL
> #define CONFIG_SYS_FSL_I2C_SPEED	400000
> #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
> #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
> #define CONFIG_SYS_FSL_I2C2_SPEED	400000
> #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
> #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
>+#endif
>+
> #define CONFIG_SYS_I2C_NOPROBES		{{0, 0x29}}
>
>+#define CONFIG_SYS_I2C_FSL
> /*
>  * I2C2 EEPROM
>  */
>diff --git a/include/configs/p1_p2_rdb_pc.h
>b/include/configs/p1_p2_rdb_pc.h index c42f1a9fce..7089b69bf3 100644
>--- a/include/configs/p1_p2_rdb_pc.h
>+++ b/include/configs/p1_p2_rdb_pc.h
>@@ -1,6 +1,7 @@
> /* SPDX-License-Identifier: GPL-2.0+ */
> /*
>  * Copyright 2010-2011 Freescale Semiconductor, Inc.
>+ * Copyright 2020 NXP
>  */
>
> /*
>@@ -546,6 +547,12 @@
> #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
> #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
> #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
>+#else
>+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
>+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
>+#endif
>+
>+#define CONFIG_SYS_I2C_FSL
> #define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
> #define CONFIG_SYS_SPD_BUS_NUM		1 /* For rom_loc and flash
>bank */
>
>--
>2.17.1
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

[PATCH 06/27] dm: powerpc: P1020: add i2c DM support

[Priyanka Jain]

>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Biwen Li
>Sent: Sunday, April 12, 2020 2:24 PM
>To: Jagdish Gediya <jagdish.gediya@nxp.com>; Priyanka Jain
><priyanka.jain@nxp.com>; hs at denx.de; jagan at amarulasolutions.com;
>aford173 at gmail.com; Alison Wang <alison.wang@nxp.com>;
>jh80.chung at samsung.com; Pramod Kumar <pramod.kumar_1@nxp.com>;
>Rajesh Bhagat <rajesh.bhagat@nxp.com>; Ruchika Gupta
><ruchika.gupta@nxp.com>; olteanv at gmail.com
>Cc: Xiaobo Xie <xiaobo.xie@nxp.com>; Jiafei Pan <jiafei.pan@nxp.com>; u-
>boot at lists.denx.de; Z.q. Hou <zhiqiang.hou@nxp.com>; Biwen Li
><biwen.li@nxp.com>
>Subject: [PATCH 06/27] dm: powerpc: P1020: add i2c DM support
>
>From: Biwen Li <biwen.li@nxp.com>
>
>This supports i2c DM for SoC P1020
>
>Signed-off-by: Biwen Li <biwen.li@nxp.com>
>---
> arch/powerpc/dts/p1020-post.dtsi            |  2 ++
> arch/powerpc/dts/p1020.dtsi                 |  2 +-
> board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 24
>++++++++++++++++++++-
> include/configs/P1022DS.h                   |  5 ++++-
> include/configs/p1_p2_rdb_pc.h              |  7 ++++++
> 5 files changed, 37 insertions(+), 3 deletions(-)
>
>diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-
>post.dtsi
>index 1c77702f01..1dce8e86e9 100644
>--- a/arch/powerpc/dts/p1020-post.dtsi
>+++ b/arch/powerpc/dts/p1020-post.dtsi
>@@ -44,6 +44,8 @@
> 		clock-frequency = <0>;
> 	};
>
>+	/include/ "pq3-i2c-0.dtsi"
>+	/include/ "pq3-i2c-1.dtsi"
> };
>
> /* PCIe controller base address 0x9000 */ diff --git
>a/arch/powerpc/dts/p1020.dtsi b/arch/powerpc/dts/p1020.dtsi index
>ee2b6f4945..facc251953 100644
>--- a/arch/powerpc/dts/p1020.dtsi
>+++ b/arch/powerpc/dts/p1020.dtsi
>@@ -3,7 +3,7 @@
>  * P1020 Silicon/SoC Device Tree Source (pre include)
>  *
>  * Copyright 2013 Freescale Semiconductor Inc.
>- * Copyright 2019 NXP
>+ * Copyright 2019-2020 NXP
>  */
>
> /dts-v1/;
>diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
>b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
>index 71fca8ca1e..f668d7efb1 100644
>--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
>+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
>@@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
>  * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
>+ * Copyright 2020 NXP
>  */
>
> #include <common.h>
>@@ -227,6 +228,7 @@ int checkboard(void)
> 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
> 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> 	u8 in, out, io_config, val;
>+	int bus_num = CONFIG_SYS_SPD_BUS_NUM;
>
> 	printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n",
>CONFIG_BOARDNAME,
> 		in_8(&cpld_data->cpld_rev_major) & 0x0F, @@ -234,7
>+236,26 @@ int checkboard(void)
> 		in_8(&cpld_data->pcba_rev) & 0x0F);
>
> 	/* Initialize i2c early for rom_loc and flash bank information */
>-	i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
>+	#if defined(CONFIG_DM_I2C)
>+	struct udevice *dev;
>+	int ret;
>+
>+	ret = i2c_get_chip_for_busnum(bus_num,
>CONFIG_SYS_I2C_PCA9557_ADDR,
>+				      1, &dev);
>+	if (ret) {
>+		printf("%s: Cannot find udev for a bus %d\n", __func__,
>+		       bus_num);
>+		return -ENXIO;
>+	}
>+
>+	if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
>+	    dm_i2c_read(dev, 1, &out, 1) < 0 ||
>+	    dm_i2c_read(dev, 3, &io_config, 1) < 0) {
>+		printf("Error reading i2c boot information!\n");
>+		return 0; /* Don't want to hang() on this error */
>+	}
>+	#else /* Non DM I2C support - will be removed */
>+	i2c_set_bus_num(bus_num);
>
> 	if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
> 	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
>@@ -242,6 +263,7 @@ int checkboard(void)
> 		printf("Error reading i2c boot information!\n");
> 		return 0; /* Don't want to hang() on this error */
> 	}
>+	#endif
>
> 	val = (in & io_config) | (out & (~io_config));
>
>diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index
>5cc2e06979..f1d77c8e1c 100644
>--- a/include/configs/P1022DS.h
>+++ b/include/configs/P1022DS.h
>@@ -359,16 +359,19 @@
> #endif
>
> /* I2C */
>+#ifndef CONFIG_DM_I2C
> #define CONFIG_SYS_I2C
>-#define CONFIG_SYS_I2C_FSL
> #define CONFIG_SYS_FSL_I2C_SPEED	400000
> #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
> #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
> #define CONFIG_SYS_FSL_I2C2_SPEED	400000
> #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
> #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
>+#endif
>+
> #define CONFIG_SYS_I2C_NOPROBES		{{0, 0x29}}
>
>+#define CONFIG_SYS_I2C_FSL
> /*
>  * I2C2 EEPROM
>  */
>diff --git a/include/configs/p1_p2_rdb_pc.h
>b/include/configs/p1_p2_rdb_pc.h index c42f1a9fce..7089b69bf3 100644
>--- a/include/configs/p1_p2_rdb_pc.h
>+++ b/include/configs/p1_p2_rdb_pc.h
>@@ -1,6 +1,7 @@
> /* SPDX-License-Identifier: GPL-2.0+ */
> /*
>  * Copyright 2010-2011 Freescale Semiconductor, Inc.
>+ * Copyright 2020 NXP
>  */
>
> /*
>@@ -546,6 +547,12 @@
> #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
> #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
> #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
>+#else
>+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
>+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
>+#endif
Biwen,

One thing I missed earlier, where is corresponding #ifdef

Regards
Priyanka
>+
>+#define CONFIG_SYS_I2C_FSL
> #define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
> #define CONFIG_SYS_SPD_BUS_NUM		1 /* For rom_loc and flash
>bank */
>
>--
>2.17.1

[PATCH 06/27] dm: powerpc: P1020: add i2c DM support

[Biwen Li]

> >--- a/include/configs/p1_p2_rdb_pc.h
> >+++ b/include/configs/p1_p2_rdb_pc.h
> >@@ -1,6 +1,7 @@
> > /* SPDX-License-Identifier: GPL-2.0+ */
> > /*
> >  * Copyright 2010-2011 Freescale Semiconductor, Inc.
> >+ * Copyright 2020 NXP
> >  */
> >
> > /*
> >@@ -546,6 +547,12 @@
> > #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
> > #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
> > #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
> >+#else
> >+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
> >+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
> >+#endif
> Biwen,
> 
> One thing I missed earlier, where is corresponding #ifdef
Yeah, I missed #ifndef,
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
#else
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
#endif

#define CONFIG_SYS_I2C_FSL
> 
> Regards
> Priyanka
> >+
> >+#define CONFIG_SYS_I2C_FSL
> > #define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
> > #define CONFIG_SYS_SPD_BUS_NUM		1 /* For rom_loc and flash
> >bank */
> >
> >--
> >2.17.1

[PATCH 07/27] configs: P1020RDB: enable DM_I2C and DM_RTC

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This enables DM_I2C and DM_RTC in P1020RDB defconfigs

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 configs/P1020RDB-PC_36BIT_NAND_defconfig     | 2 ++
 configs/P1020RDB-PC_36BIT_SDCARD_defconfig   | 2 ++
 configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 2 ++
 configs/P1020RDB-PC_36BIT_defconfig          | 2 ++
 configs/P1020RDB-PC_NAND_defconfig           | 2 ++
 configs/P1020RDB-PC_SDCARD_defconfig         | 2 ++
 configs/P1020RDB-PC_SPIFLASH_defconfig       | 2 ++
 configs/P1020RDB-PC_defconfig                | 2 ++
 configs/P1020RDB-PD_NAND_defconfig           | 2 ++
 configs/P1020RDB-PD_SDCARD_defconfig         | 2 ++
 configs/P1020RDB-PD_SPIFLASH_defconfig       | 2 ++
 configs/P1020RDB-PD_defconfig                | 2 ++
 12 files changed, 24 insertions(+)

diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index fadb4461ef..68e556fa07 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -74,3 +74,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index f79176e5c4..63f1b36c4c 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -69,3 +69,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index f9f5ab4254..9ff0b27c03 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -71,3 +71,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index 6cab654759..58d7041be3 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -58,3 +58,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index 723d150ef1..bdea18ec1d 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -73,3 +73,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index 0829adec7c..44b2154e08 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -68,3 +68,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index 8d1e989b87..042118b92b 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -70,3 +70,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index e337cebea4..0ec4dfef20 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -57,3 +57,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index e5ee950acf..b0c5cfa129 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -77,3 +77,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index ba9bea5eee..94f1e8a504 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -72,3 +72,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index d3a54f71f7..49b336c4b1 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -74,3 +74,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index fffdcc852a..79f2cca15b 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -61,3 +61,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
-- 
2.17.1

[PATCH 07/27] configs: P1020RDB: enable DM_I2C and DM_RTC

[Priyanka Jain]

>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Biwen Li
>Sent: Sunday, April 12, 2020 2:24 PM
>To: Jagdish Gediya <jagdish.gediya@nxp.com>; Priyanka Jain
><priyanka.jain@nxp.com>; hs at denx.de; jagan at amarulasolutions.com;
>aford173 at gmail.com; Alison Wang <alison.wang@nxp.com>;
>jh80.chung at samsung.com; Pramod Kumar <pramod.kumar_1@nxp.com>;
>Rajesh Bhagat <rajesh.bhagat@nxp.com>; Ruchika Gupta
><ruchika.gupta@nxp.com>; olteanv at gmail.com
>Cc: Xiaobo Xie <xiaobo.xie@nxp.com>; Jiafei Pan <jiafei.pan@nxp.com>; u-
>boot at lists.denx.de; Z.q. Hou <zhiqiang.hou@nxp.com>; Biwen Li
><biwen.li@nxp.com>
>Subject: [PATCH 07/27] configs: P1020RDB: enable DM_I2C and DM_RTC
>
>From: Biwen Li <biwen.li@nxp.com>
>
>This enables DM_I2C and DM_RTC in P1020RDB defconfigs
>
>Signed-off-by: Biwen Li <biwen.li@nxp.com>
>---
> configs/P1020RDB-PC_36BIT_NAND_defconfig     | 2 ++
> configs/P1020RDB-PC_36BIT_SDCARD_defconfig   | 2 ++
> configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 2 ++
> configs/P1020RDB-PC_36BIT_defconfig          | 2 ++
> configs/P1020RDB-PC_NAND_defconfig           | 2 ++
> configs/P1020RDB-PC_SDCARD_defconfig         | 2 ++
> configs/P1020RDB-PC_SPIFLASH_defconfig       | 2 ++
> configs/P1020RDB-PC_defconfig                | 2 ++
> configs/P1020RDB-PD_NAND_defconfig           | 2 ++
> configs/P1020RDB-PD_SDCARD_defconfig         | 2 ++
> configs/P1020RDB-PD_SPIFLASH_defconfig       | 2 ++
> configs/P1020RDB-PD_defconfig                | 2 ++
> 12 files changed, 24 insertions(+)
>
>diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig
>b/configs/P1020RDB-PC_36BIT_NAND_defconfig
>index fadb4461ef..68e556fa07 100644
>--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
>+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
>@@ -74,3 +74,5 @@ CONFIG_SPI=y
> CONFIG_FSL_ESPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
>+CONFIG_DM_I2C=y
>+CONFIG_DM_RTC=y
>diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
>b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
>index f79176e5c4..63f1b36c4c 100644
>--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
>+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
>@@ -69,3 +69,5 @@ CONFIG_SPI=y
> CONFIG_FSL_ESPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
>+CONFIG_DM_I2C=y
>+CONFIG_DM_RTC=y
>diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
>b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
>index f9f5ab4254..9ff0b27c03 100644
>--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
>+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
>@@ -71,3 +71,5 @@ CONFIG_SPI=y
> CONFIG_FSL_ESPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
>+CONFIG_DM_I2C=y
>+CONFIG_DM_RTC=y
>diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-
>PC_36BIT_defconfig
>index 6cab654759..58d7041be3 100644
>--- a/configs/P1020RDB-PC_36BIT_defconfig
>+++ b/configs/P1020RDB-PC_36BIT_defconfig
>@@ -58,3 +58,5 @@ CONFIG_SPI=y
> CONFIG_FSL_ESPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
>+CONFIG_DM_I2C=y
>+CONFIG_DM_RTC=y
>diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-
>PC_NAND_defconfig
>index 723d150ef1..bdea18ec1d 100644
>--- a/configs/P1020RDB-PC_NAND_defconfig
>+++ b/configs/P1020RDB-PC_NAND_defconfig
>@@ -73,3 +73,5 @@ CONFIG_SPI=y
> CONFIG_FSL_ESPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
>+CONFIG_DM_I2C=y
>+CONFIG_DM_RTC=y
>diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-
>PC_SDCARD_defconfig
>index 0829adec7c..44b2154e08 100644
>--- a/configs/P1020RDB-PC_SDCARD_defconfig
>+++ b/configs/P1020RDB-PC_SDCARD_defconfig
>@@ -68,3 +68,5 @@ CONFIG_SPI=y
> CONFIG_FSL_ESPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
>+CONFIG_DM_I2C=y
>+CONFIG_DM_RTC=y
>diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-
>PC_SPIFLASH_defconfig
>index 8d1e989b87..042118b92b 100644
>--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
>+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
>@@ -70,3 +70,5 @@ CONFIG_SPI=y
> CONFIG_FSL_ESPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
>+CONFIG_DM_I2C=y
>+CONFIG_DM_RTC=y
>diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
>index e337cebea4..0ec4dfef20 100644
>--- a/configs/P1020RDB-PC_defconfig
>+++ b/configs/P1020RDB-PC_defconfig
>@@ -57,3 +57,5 @@ CONFIG_SPI=y
> CONFIG_FSL_ESPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
>+CONFIG_DM_I2C=y
>+CONFIG_DM_RTC=y
>diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-
>PD_NAND_defconfig
>index e5ee950acf..b0c5cfa129 100644
>--- a/configs/P1020RDB-PD_NAND_defconfig
>+++ b/configs/P1020RDB-PD_NAND_defconfig
>@@ -77,3 +77,5 @@ CONFIG_SPI=y
> CONFIG_FSL_ESPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
>+CONFIG_DM_I2C=y
>+CONFIG_DM_RTC=y
>diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-
>PD_SDCARD_defconfig
>index ba9bea5eee..94f1e8a504 100644
>--- a/configs/P1020RDB-PD_SDCARD_defconfig
>+++ b/configs/P1020RDB-PD_SDCARD_defconfig
>@@ -72,3 +72,5 @@ CONFIG_SPI=y
> CONFIG_FSL_ESPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
>+CONFIG_DM_I2C=y
>+CONFIG_DM_RTC=y
>diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-
>PD_SPIFLASH_defconfig
>index d3a54f71f7..49b336c4b1 100644
>--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
>+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
In the 6/27th patch , you have made some changes in p1_p2_rdb_pc.c. 
Please confirm that  P1020RDB-PD defconfigs also use the above file only?

Regards
Priyanka
>@@ -74,3 +74,5 @@ CONFIG_SPI=y
> CONFIG_FSL_ESPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
>+CONFIG_DM_I2C=y
>+CONFIG_DM_RTC=y
>diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
>index fffdcc852a..79f2cca15b 100644
>--- a/configs/P1020RDB-PD_defconfig
>+++ b/configs/P1020RDB-PD_defconfig
>@@ -61,3 +61,5 @@ CONFIG_SPI=y
> CONFIG_FSL_ESPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
>+CONFIG_DM_I2C=y
>+CONFIG_DM_RTC=y
>--
>2.17.1

[PATCH 07/27] configs: P1020RDB: enable DM_I2C and DM_RTC

[Biwen Li]

> 
> >-----Original Message-----
> >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Biwen Li
> >Sent: Sunday, April 12, 2020 2:24 PM
> >To: Jagdish Gediya <jagdish.gediya@nxp.com>; Priyanka Jain
> ><priyanka.jain@nxp.com>; hs at denx.de; jagan at amarulasolutions.com;
> >aford173 at gmail.com; Alison Wang <alison.wang@nxp.com>;
> >jh80.chung at samsung.com; Pramod Kumar <pramod.kumar_1@nxp.com>;
> Rajesh
> >Bhagat <rajesh.bhagat@nxp.com>; Ruchika Gupta
> <ruchika.gupta@nxp.com>;
> >olteanv at gmail.com
> >Cc: Xiaobo Xie <xiaobo.xie@nxp.com>; Jiafei Pan <jiafei.pan@nxp.com>;
> >u- boot at lists.denx.de; Z.q. Hou <zhiqiang.hou@nxp.com>; Biwen Li
> ><biwen.li@nxp.com>
> >Subject: [PATCH 07/27] configs: P1020RDB: enable DM_I2C and DM_RTC
> >
> >From: Biwen Li <biwen.li@nxp.com>
> >
> >This enables DM_I2C and DM_RTC in P1020RDB defconfigs
> >
> >Signed-off-by: Biwen Li <biwen.li@nxp.com>
> >---
> > configs/P1020RDB-PC_36BIT_NAND_defconfig     | 2 ++
> > configs/P1020RDB-PC_36BIT_SDCARD_defconfig   | 2 ++
> > configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 2 ++
> > configs/P1020RDB-PC_36BIT_defconfig          | 2 ++
> > configs/P1020RDB-PC_NAND_defconfig           | 2 ++
> > configs/P1020RDB-PC_SDCARD_defconfig         | 2 ++
> > configs/P1020RDB-PC_SPIFLASH_defconfig       | 2 ++
> > configs/P1020RDB-PC_defconfig                | 2 ++
> > configs/P1020RDB-PD_NAND_defconfig           | 2 ++
> > configs/P1020RDB-PD_SDCARD_defconfig         | 2 ++
> > configs/P1020RDB-PD_SPIFLASH_defconfig       | 2 ++
> > configs/P1020RDB-PD_defconfig                | 2 ++
> > 12 files changed, 24 insertions(+)
> >
> >diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig
> >b/configs/P1020RDB-PC_36BIT_NAND_defconfig
> >index fadb4461ef..68e556fa07 100644
> >--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
> >+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
> >@@ -74,3 +74,5 @@ CONFIG_SPI=y
> > CONFIG_FSL_ESPI=y
> > CONFIG_USB=y
> > CONFIG_DM_USB=y
> >+CONFIG_DM_I2C=y
> >+CONFIG_DM_RTC=y
> >diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
> >b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
> >index f79176e5c4..63f1b36c4c 100644
> >--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
> >+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
> >@@ -69,3 +69,5 @@ CONFIG_SPI=y
> > CONFIG_FSL_ESPI=y
> > CONFIG_USB=y
> > CONFIG_DM_USB=y
> >+CONFIG_DM_I2C=y
> >+CONFIG_DM_RTC=y
> >diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
> >b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
> >index f9f5ab4254..9ff0b27c03 100644
> >--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
> >+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
> >@@ -71,3 +71,5 @@ CONFIG_SPI=y
> > CONFIG_FSL_ESPI=y
> > CONFIG_USB=y
> > CONFIG_DM_USB=y
> >+CONFIG_DM_I2C=y
> >+CONFIG_DM_RTC=y
> >diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-
> >PC_36BIT_defconfig index 6cab654759..58d7041be3 100644
> >--- a/configs/P1020RDB-PC_36BIT_defconfig
> >+++ b/configs/P1020RDB-PC_36BIT_defconfig
> >@@ -58,3 +58,5 @@ CONFIG_SPI=y
> > CONFIG_FSL_ESPI=y
> > CONFIG_USB=y
> > CONFIG_DM_USB=y
> >+CONFIG_DM_I2C=y
> >+CONFIG_DM_RTC=y
> >diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-
> >PC_NAND_defconfig index 723d150ef1..bdea18ec1d 100644
> >--- a/configs/P1020RDB-PC_NAND_defconfig
> >+++ b/configs/P1020RDB-PC_NAND_defconfig
> >@@ -73,3 +73,5 @@ CONFIG_SPI=y
> > CONFIG_FSL_ESPI=y
> > CONFIG_USB=y
> > CONFIG_DM_USB=y
> >+CONFIG_DM_I2C=y
> >+CONFIG_DM_RTC=y
> >diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-
> >PC_SDCARD_defconfig index 0829adec7c..44b2154e08 100644
> >--- a/configs/P1020RDB-PC_SDCARD_defconfig
> >+++ b/configs/P1020RDB-PC_SDCARD_defconfig
> >@@ -68,3 +68,5 @@ CONFIG_SPI=y
> > CONFIG_FSL_ESPI=y
> > CONFIG_USB=y
> > CONFIG_DM_USB=y
> >+CONFIG_DM_I2C=y
> >+CONFIG_DM_RTC=y
> >diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-
> >PC_SPIFLASH_defconfig index 8d1e989b87..042118b92b 100644
> >--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
> >+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
> >@@ -70,3 +70,5 @@ CONFIG_SPI=y
> > CONFIG_FSL_ESPI=y
> > CONFIG_USB=y
> > CONFIG_DM_USB=y
> >+CONFIG_DM_I2C=y
> >+CONFIG_DM_RTC=y
> >diff --git a/configs/P1020RDB-PC_defconfig
> >b/configs/P1020RDB-PC_defconfig index e337cebea4..0ec4dfef20 100644
> >--- a/configs/P1020RDB-PC_defconfig
> >+++ b/configs/P1020RDB-PC_defconfig
> >@@ -57,3 +57,5 @@ CONFIG_SPI=y
> > CONFIG_FSL_ESPI=y
> > CONFIG_USB=y
> > CONFIG_DM_USB=y
> >+CONFIG_DM_I2C=y
> >+CONFIG_DM_RTC=y
> >diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-
> >PD_NAND_defconfig index e5ee950acf..b0c5cfa129 100644
> >--- a/configs/P1020RDB-PD_NAND_defconfig
> >+++ b/configs/P1020RDB-PD_NAND_defconfig
> >@@ -77,3 +77,5 @@ CONFIG_SPI=y
> > CONFIG_FSL_ESPI=y
> > CONFIG_USB=y
> > CONFIG_DM_USB=y
> >+CONFIG_DM_I2C=y
> >+CONFIG_DM_RTC=y
> >diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-
> >PD_SDCARD_defconfig index ba9bea5eee..94f1e8a504 100644
> >--- a/configs/P1020RDB-PD_SDCARD_defconfig
> >+++ b/configs/P1020RDB-PD_SDCARD_defconfig
> >@@ -72,3 +72,5 @@ CONFIG_SPI=y
> > CONFIG_FSL_ESPI=y
> > CONFIG_USB=y
> > CONFIG_DM_USB=y
> >+CONFIG_DM_I2C=y
> >+CONFIG_DM_RTC=y
> >diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-
> >PD_SPIFLASH_defconfig index d3a54f71f7..49b336c4b1 100644
> >--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
> >+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
> In the 6/27th patch , you have made some changes in p1_p2_rdb_pc.c.
> Please confirm that  P1020RDB-PD defconfigs also use the above file only?
No, P2020RDB also need use it.
> 
> Regards
> Priyanka
> >@@ -74,3 +74,5 @@ CONFIG_SPI=y
> > CONFIG_FSL_ESPI=y
> > CONFIG_USB=y
> > CONFIG_DM_USB=y
> >+CONFIG_DM_I2C=y
> >+CONFIG_DM_RTC=y
> >diff --git a/configs/P1020RDB-PD_defconfig
> >b/configs/P1020RDB-PD_defconfig index fffdcc852a..79f2cca15b 100644
> >--- a/configs/P1020RDB-PD_defconfig
> >+++ b/configs/P1020RDB-PD_defconfig
> >@@ -61,3 +61,5 @@ CONFIG_SPI=y
> > CONFIG_FSL_ESPI=y
> > CONFIG_USB=y
> > CONFIG_DM_USB=y
> >+CONFIG_DM_I2C=y
> >+CONFIG_DM_RTC=y
> >--
> >2.17.1

[PATCH 08/27] dm: powerpc: P2020RDB: add i2c DM support

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This supports i2c DM for board P2020RDB

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 arch/powerpc/dts/p2020-post.dtsi | 3 +++
 arch/powerpc/dts/p2020.dtsi      | 2 +-
 include/configs/p1_p2_rdb_pc.h   | 2 +-
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index 5bbd5c5468..4ed093dad4 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -37,6 +37,9 @@
 		/* Filled in by U-Boot */
 		clock-frequency = <0>;
 	};
+
+	/include/ "pq3-i2c-0.dtsi"
+	/include/ "pq3-i2c-1.dtsi"
 };
 
 /* PCIe controller base address 0x8000 */
diff --git a/arch/powerpc/dts/p2020.dtsi b/arch/powerpc/dts/p2020.dtsi
index 7c4c2061d4..13a4a51526 100644
--- a/arch/powerpc/dts/p2020.dtsi
+++ b/arch/powerpc/dts/p2020.dtsi
@@ -3,7 +3,7 @@
  * P2020 Silicon/SoC Device Tree Source (pre include)
  *
  * Copyright 2013 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
  */
 
 /dts-v1/;
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 7089b69bf3..d59fd033bd 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -538,8 +538,8 @@
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
 /* I2C */
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-- 
2.17.1

[PATCH 08/27] dm: powerpc: P2020RDB: add i2c DM support

[Priyanka Jain]

>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Biwen Li
>Sent: Sunday, April 12, 2020 2:24 PM
>To: Jagdish Gediya <jagdish.gediya@nxp.com>; Priyanka Jain
><priyanka.jain@nxp.com>; hs at denx.de; jagan at amarulasolutions.com;
>aford173 at gmail.com; Alison Wang <alison.wang@nxp.com>;
>jh80.chung at samsung.com; Pramod Kumar <pramod.kumar_1@nxp.com>;
>Rajesh Bhagat <rajesh.bhagat@nxp.com>; Ruchika Gupta
><ruchika.gupta@nxp.com>; olteanv at gmail.com
>Cc: Xiaobo Xie <xiaobo.xie@nxp.com>; Jiafei Pan <jiafei.pan@nxp.com>; u-
>boot at lists.denx.de; Z.q. Hou <zhiqiang.hou@nxp.com>; Biwen Li
><biwen.li@nxp.com>
>Subject: [PATCH 08/27] dm: powerpc: P2020RDB: add i2c DM support
>
>From: Biwen Li <biwen.li@nxp.com>
>
>This supports i2c DM for board P2020RDB
>
>Signed-off-by: Biwen Li <biwen.li@nxp.com>
>---
> arch/powerpc/dts/p2020-post.dtsi | 3 +++
> arch/powerpc/dts/p2020.dtsi      | 2 +-
> include/configs/p1_p2_rdb_pc.h   | 2 +-
> 3 files changed, 5 insertions(+), 2 deletions(-)
>
>diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-
>post.dtsi
>index 5bbd5c5468..4ed093dad4 100644
>--- a/arch/powerpc/dts/p2020-post.dtsi
>+++ b/arch/powerpc/dts/p2020-post.dtsi
>@@ -37,6 +37,9 @@
> 		/* Filled in by U-Boot */
> 		clock-frequency = <0>;
> 	};
>+
>+	/include/ "pq3-i2c-0.dtsi"
>+	/include/ "pq3-i2c-1.dtsi"
> };
>
> /* PCIe controller base address 0x8000 */ diff --git
>a/arch/powerpc/dts/p2020.dtsi b/arch/powerpc/dts/p2020.dtsi index
>7c4c2061d4..13a4a51526 100644
>--- a/arch/powerpc/dts/p2020.dtsi
>+++ b/arch/powerpc/dts/p2020.dtsi
>@@ -3,7 +3,7 @@
>  * P2020 Silicon/SoC Device Tree Source (pre include)
>  *
>  * Copyright 2013 Freescale Semiconductor Inc.
>- * Copyright 2019 NXP
>+ * Copyright 2019-2020 NXP
>  */
>
> /dts-v1/;
>diff --git a/include/configs/p1_p2_rdb_pc.h
>b/include/configs/p1_p2_rdb_pc.h index 7089b69bf3..d59fd033bd 100644
>--- a/include/configs/p1_p2_rdb_pc.h
>+++ b/include/configs/p1_p2_rdb_pc.h
>@@ -538,8 +538,8 @@
> #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
>
> /* I2C */
>+#ifndef CONFIG_DM_I2C
> #define CONFIG_SYS_I2C
>-#define CONFIG_SYS_I2C_FSL
> #define CONFIG_SYS_FSL_I2C_SPEED	400000
> #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
> #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
>--
>2.17.1
This changes were supposed to be merged with a previous patch.
We need to ensure that all patches are compiling independently successfully.

Do run buildman test before submitting the next version of this patch set.

Regards
Priyanka

[PATCH 09/27] configs: P2020RDB: enable DM_I2C and DM_RTC

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This enables DM_I2C and DM_RTC in P2020RDB defconfigs

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 configs/P2020RDB-PC_36BIT_NAND_defconfig     | 2 ++
 configs/P2020RDB-PC_36BIT_SDCARD_defconfig   | 2 ++
 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 2 ++
 configs/P2020RDB-PC_36BIT_defconfig          | 2 ++
 configs/P2020RDB-PC_NAND_defconfig           | 2 ++
 configs/P2020RDB-PC_SDCARD_defconfig         | 2 ++
 configs/P2020RDB-PC_SPIFLASH_defconfig       | 2 ++
 configs/P2020RDB-PC_defconfig                | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index e2c647dbdf..85f1ca6f97 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -79,3 +79,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index 04f2fc9c91..0de353b1c9 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -74,3 +74,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index 03e5c7e211..4be2941ea0 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -76,3 +76,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index 8655b15b91..6d50449fd1 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -63,3 +63,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index 4e2b4e21a7..f37a792374 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -78,3 +78,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index d1f3197774..d5b9bbcb3a 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -73,3 +73,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index b38940dd0b..bb8b88d7ce 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -75,3 +75,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index d681e59732..1e62502289 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -62,3 +62,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
-- 
2.17.1

[PATCH 10/27] dm: powerpc: P2041RDB: add i2c DM support

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This supports i2c DM for board P2041RDB

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 arch/powerpc/dts/p2041.dtsi | 5 ++++-
 include/configs/P2041RDB.h  | 9 ++++++++-
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi
index 0f5e7dbdc8..95931e299d 100644
--- a/arch/powerpc/dts/p2041.dtsi
+++ b/arch/powerpc/dts/p2041.dtsi
@@ -3,7 +3,7 @@
  * P2041 Silicon/SoC Device Tree Source (pre include)
  *
  * Copyright 2011 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
  */
 
 /dts-v1/;
@@ -86,6 +86,9 @@
 			reg = <0x114000 0x1000>;
 			clock-frequency = <0>;
 		};
+
+		/include/ "qoriq-i2c-0.dtsi"
+		/include/ "qoriq-i2c-1.dtsi"
 	};
 
 	pcie at ffe200000 {
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index f6472b9e11..f1eb6d7100 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 /*
@@ -267,14 +268,20 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 
 /* I2C */
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
+#else
+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
+#endif
+#define CONFIG_SYS_I2C_FSL
+
 
 /*
  * RapidIO
-- 
2.17.1

[PATCH 11/27] config: P2041RDB: enable DM_I2C

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This enables DM_I2C in P2041RDB defconfig,
except P2041RDB SRIO_PCIE_BOOT and SECURE_BOOT defconfigs

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 configs/P2041RDB_NAND_defconfig     | 1 +
 configs/P2041RDB_SDCARD_defconfig   | 1 +
 configs/P2041RDB_SPIFLASH_defconfig | 1 +
 configs/P2041RDB_defconfig          | 1 +
 4 files changed, 4 insertions(+)

diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 110e50bfd9..fef533e357 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -58,3 +58,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index c47c60158d..5364d7cee7 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -57,3 +57,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 40eafa7162..9818a6eb74 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -58,3 +58,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 3a79fc62b6..7a4e62582a 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -56,3 +56,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
-- 
2.17.1

[PATCH 11/27] config: P2041RDB: enable DM_I2C

[Priyanka Jain]

>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Biwen Li
>Sent: Sunday, April 12, 2020 2:24 PM
>To: Jagdish Gediya <jagdish.gediya@nxp.com>; Priyanka Jain
><priyanka.jain@nxp.com>; hs at denx.de; jagan at amarulasolutions.com;
>aford173 at gmail.com; Alison Wang <alison.wang@nxp.com>;
>jh80.chung at samsung.com; Pramod Kumar <pramod.kumar_1@nxp.com>;
>Rajesh Bhagat <rajesh.bhagat@nxp.com>; Ruchika Gupta
><ruchika.gupta@nxp.com>; olteanv at gmail.com
>Cc: Xiaobo Xie <xiaobo.xie@nxp.com>; Jiafei Pan <jiafei.pan@nxp.com>; u-
>boot at lists.denx.de; Z.q. Hou <zhiqiang.hou@nxp.com>; Biwen Li
><biwen.li@nxp.com>
>Subject: [PATCH 11/27] config: P2041RDB: enable DM_I2C
>
>From: Biwen Li <biwen.li@nxp.com>
>
>This enables DM_I2C in P2041RDB defconfig, except P2041RDB
>SRIO_PCIE_BOOT and SECURE_BOOT defconfigs
>
Why are we not doing changes for all defconfigs.

Regards
Priyanka
>Signed-off-by: Biwen Li <biwen.li@nxp.com>
>---
> configs/P2041RDB_NAND_defconfig     | 1 +
> configs/P2041RDB_SDCARD_defconfig   | 1 +
> configs/P2041RDB_SPIFLASH_defconfig | 1 +
> configs/P2041RDB_defconfig          | 1 +
> 4 files changed, 4 insertions(+)
>
>diff --git a/configs/P2041RDB_NAND_defconfig
>b/configs/P2041RDB_NAND_defconfig index 110e50bfd9..fef533e357 100644
>--- a/configs/P2041RDB_NAND_defconfig
>+++ b/configs/P2041RDB_NAND_defconfig
>@@ -58,3 +58,4 @@ CONFIG_SPI=y
> CONFIG_FSL_ESPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
>+CONFIG_DM_I2C=y
>diff --git a/configs/P2041RDB_SDCARD_defconfig
>b/configs/P2041RDB_SDCARD_defconfig
>index c47c60158d..5364d7cee7 100644
>--- a/configs/P2041RDB_SDCARD_defconfig
>+++ b/configs/P2041RDB_SDCARD_defconfig
>@@ -57,3 +57,4 @@ CONFIG_SPI=y
> CONFIG_FSL_ESPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
>+CONFIG_DM_I2C=y
>diff --git a/configs/P2041RDB_SPIFLASH_defconfig
>b/configs/P2041RDB_SPIFLASH_defconfig
>index 40eafa7162..9818a6eb74 100644
>--- a/configs/P2041RDB_SPIFLASH_defconfig
>+++ b/configs/P2041RDB_SPIFLASH_defconfig
>@@ -58,3 +58,4 @@ CONFIG_SPI=y
> CONFIG_FSL_ESPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
>+CONFIG_DM_I2C=y
>diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index
>3a79fc62b6..7a4e62582a 100644
>--- a/configs/P2041RDB_defconfig
>+++ b/configs/P2041RDB_defconfig
>@@ -56,3 +56,4 @@ CONFIG_SPI=y
> CONFIG_FSL_ESPI=y
> CONFIG_USB=y
> CONFIG_DM_USB=y
>+CONFIG_DM_I2C=y
>--
>2.17.1

[PATCH 11/27] config: P2041RDB: enable DM_I2C

[Biwen Li]

> 
> >-----Original Message-----
> >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Biwen Li
> >Sent: Sunday, April 12, 2020 2:24 PM
> >To: Jagdish Gediya <jagdish.gediya@nxp.com>; Priyanka Jain
> ><priyanka.jain@nxp.com>; hs at denx.de; jagan at amarulasolutions.com;
> >aford173 at gmail.com; Alison Wang <alison.wang@nxp.com>;
> >jh80.chung at samsung.com; Pramod Kumar <pramod.kumar_1@nxp.com>;
> Rajesh
> >Bhagat <rajesh.bhagat@nxp.com>; Ruchika Gupta
> <ruchika.gupta@nxp.com>;
> >olteanv at gmail.com
> >Cc: Xiaobo Xie <xiaobo.xie@nxp.com>; Jiafei Pan <jiafei.pan@nxp.com>;
> >u- boot at lists.denx.de; Z.q. Hou <zhiqiang.hou@nxp.com>; Biwen Li
> ><biwen.li@nxp.com>
> >Subject: [PATCH 11/27] config: P2041RDB: enable DM_I2C
> >
> >From: Biwen Li <biwen.li@nxp.com>
> >
> >This enables DM_I2C in P2041RDB defconfig, except P2041RDB
> >SRIO_PCIE_BOOT and SECURE_BOOT defconfigs
> >
> Why are we not doing changes for all defconfigs.
Currently not support dm for these defconfigs.(It needs other patches from other ip, such as pci)

> 
> Regards
> Priyanka
> >Signed-off-by: Biwen Li <biwen.li@nxp.com>
> >---
> > configs/P2041RDB_NAND_defconfig     | 1 +
> > configs/P2041RDB_SDCARD_defconfig   | 1 +
> > configs/P2041RDB_SPIFLASH_defconfig | 1 +
> > configs/P2041RDB_defconfig          | 1 +
> > 4 files changed, 4 insertions(+)
> >
> >diff --git a/configs/P2041RDB_NAND_defconfig
> >b/configs/P2041RDB_NAND_defconfig index 110e50bfd9..fef533e357
> 100644
> >--- a/configs/P2041RDB_NAND_defconfig
> >+++ b/configs/P2041RDB_NAND_defconfig
> >@@ -58,3 +58,4 @@ CONFIG_SPI=y
> > CONFIG_FSL_ESPI=y
> > CONFIG_USB=y
> > CONFIG_DM_USB=y
> >+CONFIG_DM_I2C=y
> >diff --git a/configs/P2041RDB_SDCARD_defconfig
> >b/configs/P2041RDB_SDCARD_defconfig
> >index c47c60158d..5364d7cee7 100644
> >--- a/configs/P2041RDB_SDCARD_defconfig
> >+++ b/configs/P2041RDB_SDCARD_defconfig
> >@@ -57,3 +57,4 @@ CONFIG_SPI=y
> > CONFIG_FSL_ESPI=y
> > CONFIG_USB=y
> > CONFIG_DM_USB=y
> >+CONFIG_DM_I2C=y
> >diff --git a/configs/P2041RDB_SPIFLASH_defconfig
> >b/configs/P2041RDB_SPIFLASH_defconfig
> >index 40eafa7162..9818a6eb74 100644
> >--- a/configs/P2041RDB_SPIFLASH_defconfig
> >+++ b/configs/P2041RDB_SPIFLASH_defconfig
> >@@ -58,3 +58,4 @@ CONFIG_SPI=y
> > CONFIG_FSL_ESPI=y
> > CONFIG_USB=y
> > CONFIG_DM_USB=y
> >+CONFIG_DM_I2C=y
> >diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
> >index 3a79fc62b6..7a4e62582a 100644
> >--- a/configs/P2041RDB_defconfig
> >+++ b/configs/P2041RDB_defconfig
> >@@ -56,3 +56,4 @@ CONFIG_SPI=y
> > CONFIG_FSL_ESPI=y
> > CONFIG_USB=y
> > CONFIG_DM_USB=y
> >+CONFIG_DM_I2C=y
> >--
> >2.17.1

[PATCH 12/27] powerpc: dts: P3041: add i2c node

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This adds i2c node for SoC P3041

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 arch/powerpc/dts/p3041.dtsi | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi
index 6736d00035..3152683b84 100644
--- a/arch/powerpc/dts/p3041.dtsi
+++ b/arch/powerpc/dts/p3041.dtsi
@@ -3,7 +3,7 @@
  * P3041 Silicon/SoC Device Tree Source (pre include)
  *
  * Copyright 2010 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
  */
 
 /dts-v1/;
@@ -86,6 +86,8 @@
 			reg = <0x114000 0x1000>;
 			clock-frequency = <0>;
 		};
+		/include/ "qoriq-i2c-0.dtsi"
+		/include/ "qoriq-i2c-1.dtsi"
 	};
 
 	pcie at ffe200000 {
-- 
2.17.1

[PATCH 13/27] configs: P3041DS: enable DM_I2C

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This enables DM_I2C in P3041DS defconfigs,
except P3041DS SECURE_BOOT and SRIO_PCIE_BOOT defconfig

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 configs/P3041DS_NAND_defconfig     | 1 +
 configs/P3041DS_SDCARD_defconfig   | 1 +
 configs/P3041DS_SPIFLASH_defconfig | 1 +
 configs/P3041DS_defconfig          | 1 +
 4 files changed, 4 insertions(+)

diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index 473ad5b055..a0ab1500d3 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -58,3 +58,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index 806653e748..3e5bbf35fa 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -57,3 +57,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index cbafc9c8a0..6793a44aff 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -58,3 +58,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index e00958566a..d79cf65728 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -56,3 +56,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
-- 
2.17.1

[PATCH 14/27] powerpc: dts: P4080: add i2c node

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This adds i2c node for SoC P4080

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 arch/powerpc/dts/p4080.dtsi | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi
index 02f39fbfcb..4a80561e18 100644
--- a/arch/powerpc/dts/p4080.dtsi
+++ b/arch/powerpc/dts/p4080.dtsi
@@ -3,7 +3,7 @@
  * P4080/P4040 Silicon/SoC Device Tree Source (pre include)
  *
  * Copyright 2011 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
  */
 
 /dts-v1/;
@@ -97,6 +97,8 @@
 			reg = <0x211000 0x1000>;
 			phy_type = "ulpi";
 		};
+		/include/ "qoriq-i2c-0.dtsi"
+		/include/ "qoriq-i2c-1.dtsi"
 	};
 
 	pcie at ffe200000 {
-- 
2.17.1

[PATCH 15/27] configs: P4080DS: enable DM_I2C

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This enables DM_I2C in P4080DS defconfigs,
except P4080DS SRIO_PCIE_BOOT and SECURE_BOOT defconfigs

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 configs/P4080DS_SDCARD_defconfig   | 1 +
 configs/P4080DS_SPIFLASH_defconfig | 1 +
 configs/P4080DS_defconfig          | 1 +
 3 files changed, 3 insertions(+)

diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index da929598f6..591f9a9e9c 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -56,3 +56,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index 9ed25c10ba..fcd054b4ed 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -57,3 +57,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index fcefd8d1e7..f9e87c739c 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -55,3 +55,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
-- 
2.17.1

[PATCH 16/27] dm: powerpc: T1023/T1024: add i2c DM support

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

Thiss supports i2c DM for SoC T1023/T1024

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 arch/powerpc/dts/t102x.dtsi         |  4 +-
 board/freescale/t102xqds/t102xqds.c | 94 ++++++++++++++++++++++++++++-
 board/freescale/t102xqds/t102xqds.h |  3 +-
 board/freescale/t102xrdb/t102xrdb.c | 70 +++++++++++++++++++--
 include/configs/T102xQDS.h          | 10 ++-
 include/configs/T102xRDB.h          |  8 ++-
 6 files changed, 179 insertions(+), 10 deletions(-)

diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi
index a6b821a76a..521825d85a 100644
--- a/arch/powerpc/dts/t102x.dtsi
+++ b/arch/powerpc/dts/t102x.dtsi
@@ -3,7 +3,7 @@
  * T102X Silicon/SoC Device Tree Source (pre include)
  *
  * Copyright 2013 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
  */
 
 /dts-v1/;
@@ -75,6 +75,8 @@
 			reg = <0x114000 0x1000>;
 			clock-frequency = <0>;
 		};
+		/include/ "qoriq-i2c-0.dtsi"
+		/include/ "qoriq-i2c-1.dtsi"
 	};
 
 	pcie at ffe240000 {
diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c
index e42337e47a..0bff011ff8 100644
--- a/board/freescale/t102xqds/t102xqds.c
+++ b/board/freescale/t102xqds/t102xqds.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 #include <common.h>
@@ -75,11 +76,23 @@ int checkboard(void)
 	return 0;
 }
 
-int select_i2c_ch_pca9547(u8 ch)
+int select_i2c_ch_pca9547(u8 ch, int bus_num)
 {
 	int ret;
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
 
+	ret = dm_i2c_write(dev, 0, &ch, 1);
+#else
 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
 	if (ret) {
 		puts("PCA: failed to select proper channel\n");
 		return ret;
@@ -191,6 +204,82 @@ void board_retimer_ds125df111_init(void)
 {
 	u8 reg;
 
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+	int ret, bus_num = 0;
+
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
+				      1, &dev);
+	if (ret)
+		goto failed;
+
+	/* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
+	reg = I2C_MUX_CH7;
+	dm_i2c_write(dev, 0, &reg, 1);
+
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
+				      1, &dev);
+	if (ret)
+		goto failed;
+
+	reg = I2C_MUX_CH5;
+	dm_i2c_write(dev, 0, &reg, 1);
+
+	/* Access to Control/Shared register */
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
+				      1, &dev);
+	if (ret)
+		goto failed;
+	reg = 0x0;
+	dm_i2c_write(dev, 0xff, &reg, 1);
+
+	/* Read device revision and ID */
+	dm_i2c_read(dev, 1, &reg, 1);
+	debug("Retimer version id = 0x%x\n", reg);
+
+	/* Enable Broadcast */
+	reg = 0x0c;
+	dm_i2c_write(dev, 0xff, &reg, 1);
+
+	/* Reset Channel Registers */
+	dm_i2c_read(dev, 0, &reg, 1);
+	reg |= 0x4;
+	dm_i2c_write(dev, 0, &reg, 1);
+
+	/* Enable override divider select and Enable Override Output Mux */
+	dm_i2c_read(dev, 9, &reg, 1);
+	reg |= 0x24;
+	dm_i2c_write(dev, 9, &reg, 1);
+
+	/* Select VCO Divider to full rate (000) */
+	dm_i2c_read(dev, 0x18, &reg, 1);
+	reg &= 0x8f;
+	dm_i2c_write(dev, 0x18, &reg, 1);
+
+	/* Select active PFD MUX input as re-timed data (001) */
+	dm_i2c_read(dev, 0x1e, &reg, 1);
+	reg &= 0x3f;
+	reg |= 0x20;
+	dm_i2c_write(dev, 0x1e, &reg, 1);
+
+	/* Set data rate as 10.3125 Gbps */
+	reg = 0x0;
+	dm_i2c_write(dev, 0x60, &reg, 1);
+	reg = 0xb2;
+	dm_i2c_write(dev, 0x61, &reg, 1);
+	reg = 0x90;
+	dm_i2c_write(dev, 0x62, &reg, 1);
+	reg = 0xb3;
+	dm_i2c_write(dev, 0x63, &reg, 1);
+	reg = 0xcd;
+	dm_i2c_write(dev, 0x64, &reg, 1);
+	return;
+
+failed:
+	printf("%s: Cannot find udev for a bus %d\n", __func__,
+	       bus_num);
+	return;
+#else
 	/* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
 	reg = I2C_MUX_CH7;
 	i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
@@ -241,6 +330,7 @@ void board_retimer_ds125df111_init(void)
 	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 	reg = 0xcd;
 	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
+#endif
 }
 
 int board_early_init_f(void)
@@ -281,7 +371,7 @@ int board_early_init_r(void)
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
 #endif
-	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 	board_mux_lane_to_slot();
 	board_retimer_ds125df111_init();
 
diff --git a/board/freescale/t102xqds/t102xqds.h b/board/freescale/t102xqds/t102xqds.h
index 15de132598..d327b5edb9 100644
--- a/board/freescale/t102xqds/t102xqds.h
+++ b/board/freescale/t102xqds/t102xqds.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 #ifndef __T102x_QDS_H__
@@ -8,6 +9,6 @@
 
 void fdt_fixup_board_enet(void *blob);
 void pci_of_setup(void *blob, bd_t *bd);
-int select_i2c_ch_pca9547(u8 ch);
+int select_i2c_ch_pca9547(u8 ch, int bus_num);
 
 #endif
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index eee09a5701..71ca9a5361 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 #include <common.h>
@@ -250,8 +251,68 @@ static u32 t1023rdb_ctrl(u32 ctrl_type)
 {
 	ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 	ccsr_gur_t __iomem  *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 val, orig_bus = i2c_get_bus_num();
+	u32 val;
 	u8 tmp;
+	int bus_num = I2C_PCA6408_BUS_NUM;
+
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA6408_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+	switch (ctrl_type) {
+	case GPIO1_SD_SEL:
+		val = in_be32(&pgpio->gpdat);
+		val |= GPIO1_SD_SEL;
+		out_be32(&pgpio->gpdat, val);
+		setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
+		break;
+	case GPIO1_EMMC_SEL:
+		val = in_be32(&pgpio->gpdat);
+		val &= ~GPIO1_SD_SEL;
+		out_be32(&pgpio->gpdat, val);
+		setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
+		break;
+	case GPIO3_GET_VERSION:
+		pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
+			 + GPIO3_OFFSET);
+		val = in_be32(&pgpio->gpdat);
+		val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
+		if (val == 0x3) /* GPIO3_4/5 not used on RevB */
+			val = 0;
+		return val;
+	case I2C_GET_BANK:
+		dm_i2c_read(dev, 0, &tmp, 1);
+		tmp &= 0x7;
+		tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
+		return tmp;
+	case I2C_SET_BANK0:
+		tmp = 0x0;
+		dm_i2c_write(dev, 1, &tmp, 1);
+		tmp = 0xf8;
+		dm_i2c_write(dev, 3, &tmp, 1);
+		/* asserting HRESET_REQ */
+		out_be32(&gur->rstcr, 0x2);
+		break;
+	case I2C_SET_BANK4:
+		tmp = 0x1;
+		dm_i2c_write(dev, 1, &tmp, 1);
+		tmp = 0xf8;
+		dm_i2c_write(dev, 3, &tmp, 1);
+		out_be32(&gur->rstcr, 0x2);
+		break;
+	default:
+		break;
+	}
+#else
+	u32 orig_bus;
+	orig_bus = i2c_get_bus_num();
 
 	switch (ctrl_type) {
 	case GPIO1_SD_SEL:
@@ -275,14 +336,14 @@ static u32 t1023rdb_ctrl(u32 ctrl_type)
 			val = 0;
 		return val;
 	case I2C_GET_BANK:
-		i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
+		i2c_set_bus_num(bus_num);
 		i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
 		tmp &= 0x7;
 		tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
 		i2c_set_bus_num(orig_bus);
 		return tmp;
 	case I2C_SET_BANK0:
-		i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
+		i2c_set_bus_num(bus_num);
 		tmp = 0x0;
 		i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
 		tmp = 0xf8;
@@ -291,7 +352,7 @@ static u32 t1023rdb_ctrl(u32 ctrl_type)
 		out_be32(&gur->rstcr, 0x2);
 		break;
 	case I2C_SET_BANK4:
-		i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
+		i2c_set_bus_num(bus_num);
 		tmp = 0x1;
 		i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
 		tmp = 0xf8;
@@ -301,6 +362,7 @@ static u32 t1023rdb_ctrl(u32 ctrl_type)
 	default:
 		break;
 	}
+#endif
 	return 0;
 }
 
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index 8ac260c2bc..2b61fa56e5 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 /*
@@ -437,14 +438,20 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 /* I2C */
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
 #define CONFIG_SYS_FSL_I2C_SPEED	50000	/* I2C speed in Hz */
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_SPEED	50000	/* I2C speed in Hz */
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
+#else
+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
+#endif
+
+#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
 
 #define I2C_MUX_PCA_ADDR		0x77
 #define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
@@ -460,6 +467,7 @@ unsigned long get_board_ddr_clk(void);
 /* LDI/DVI Encoder for display */
 #define CONFIG_SYS_I2C_LDI_ADDR	 0x38
 #define CONFIG_SYS_I2C_DVI_ADDR	 0x75
+#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
 
 /*
  * RTC configuration
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 43897a711a..b9dbc01f08 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 /*
@@ -434,15 +435,20 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 /* I2C */
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
 #define CONFIG_SYS_FSL_I2C_SPEED	50000	/* I2C speed in Hz */
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_SPEED	50000	/* I2C speed in Hz */
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
+#else
+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
+#endif
 
+#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
 #define I2C_PCA6408_BUS_NUM		1
 #define I2C_PCA6408_ADDR		0x20
 
-- 
2.17.1

[PATCH 16/27] dm: powerpc: T1023/T1024: add i2c DM support

[Priyanka Jain]

>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Biwen Li
>Sent: Sunday, April 12, 2020 2:24 PM
>To: Jagdish Gediya <jagdish.gediya@nxp.com>; Priyanka Jain
><priyanka.jain@nxp.com>; hs at denx.de; jagan at amarulasolutions.com;
>aford173 at gmail.com; Alison Wang <alison.wang@nxp.com>;
>jh80.chung at samsung.com; Pramod Kumar <pramod.kumar_1@nxp.com>;
>Rajesh Bhagat <rajesh.bhagat@nxp.com>; Ruchika Gupta
><ruchika.gupta@nxp.com>; olteanv at gmail.com
>Cc: Xiaobo Xie <xiaobo.xie@nxp.com>; Jiafei Pan <jiafei.pan@nxp.com>; u-
>boot at lists.denx.de; Z.q. Hou <zhiqiang.hou@nxp.com>; Biwen Li
><biwen.li@nxp.com>
>Subject: [PATCH 16/27] dm: powerpc: T1023/T1024: add i2c DM support
>
>From: Biwen Li <biwen.li@nxp.com>
>
>Thiss supports i2c DM for SoC T1023/T1024
Typo error in This
>
>Signed-off-by: Biwen Li <biwen.li@nxp.com>
>---
Priyanka
<snip>

[PATCH 17/27] configs: T1024RDB: enable DM_I2C and DM_RTC

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This enables DM_I2C and DM_RTC in T1024RDB defconfigs,
except T1024RDB SECURE_BOOT defconfig

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 configs/T1024RDB_NAND_defconfig     | 2 ++
 configs/T1024RDB_SDCARD_defconfig   | 2 ++
 configs/T1024RDB_SPIFLASH_defconfig | 2 ++
 configs/T1024RDB_defconfig          | 2 ++
 4 files changed, 8 insertions(+)

diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index d75e5ec38a..6ce69954cd 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -80,3 +80,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index 95d30f1017..f6787ceb83 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -77,3 +77,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 4068b6ca5a..b4fe080afc 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -80,3 +80,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index ad4ba96a2e..4adfd1155f 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -65,3 +65,5 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
-- 
2.17.1

[PATCH 18/27] dm: ppc: p1010: add i2c DM support

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This supports i2c DM for SoC P1010

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 board/freescale/p1010rdb/p1010rdb.c | 159 +++++++++++++++++++++++++++-
 include/configs/P1010RDB.h          |   8 +-
 2 files changed, 164 insertions(+), 3 deletions(-)

diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index a086692683..f49e679d01 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 #include <common.h>
@@ -136,6 +137,125 @@ int config_board_mux(int ctrl_type)
 	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	u8 tmp;
 
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+	int ret;
+#if defined(CONFIG_TARGET_P1010RDB_PA)
+	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+	ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR1,
+			1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+				I2C_PCA9557_BUS_NUM);
+		return ret;
+	}
+	switch (ctrl_type) {
+	case MUX_TYPE_IFC:
+		tmp = 0xf0;
+		dm_i2c_write(dev, 3, &tmp, 1);
+		tmp = 0x01;
+		dm_i2c_write(dev, 1, &tmp, 1);
+		sd_ifc_mux = MUX_TYPE_IFC;
+		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
+		break;
+	case MUX_TYPE_SDHC:
+		tmp = 0xf0;
+		dm_i2c_write(dev, 3, &tmp, 1);
+		tmp = 0x05;
+		dm_i2c_write(dev, 1, &tmp, 1);
+		sd_ifc_mux = MUX_TYPE_SDHC;
+		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
+				PMUXCR1_SDHC_ENABLE);
+		break;
+	case MUX_TYPE_SPIFLASH:
+		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
+		break;
+	case MUX_TYPE_TDM:
+		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
+		out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
+		break;
+	case MUX_TYPE_CAN:
+		out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
+		break;
+	default:
+		break;
+	}
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
+	ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2,
+			1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+				I2C_PCA9557_BUS_NUM);
+		return ret;
+	}
+	switch (ctrl_type) {
+	case MUX_TYPE_IFC:
+		dm_i2c_read(dev, 0, &tmp, 1);
+		clrbits_8(&tmp, 0x04);
+		dm_i2c_write(dev, 1, &tmp, 1);
+		dm_i2c_read(dev, 3, &tmp, 1);
+		clrbits_8(&tmp, 0x04);
+		dm_i2c_write(dev, 3, &tmp, 1);
+		sd_ifc_mux = MUX_TYPE_IFC;
+		clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
+		break;
+	case MUX_TYPE_SDHC:
+		dm_i2c_read(dev, 0, &tmp, 1);
+		setbits_8(&tmp, 0x04);
+		dm_i2c_write(dev, 1, &tmp, 1);
+		dm_i2c_read(dev, 3, &tmp, 1);
+		clrbits_8(&tmp, 0x04);
+		dm_i2c_write(dev, 3, &tmp, 1);
+		sd_ifc_mux = MUX_TYPE_SDHC;
+		clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
+				PMUXCR1_SDHC_ENABLE);
+		break;
+	case MUX_TYPE_SPIFLASH:
+		dm_i2c_read(dev, 0, &tmp, 1);
+		clrbits_8(&tmp, 0x80);
+		dm_i2c_write(dev, 1, &tmp, 1);
+		dm_i2c_read(dev, 3, &tmp, 1);
+		clrbits_8(&tmp, 0x80);
+		dm_i2c_write(dev, 3, &tmp, 1);
+		break;
+	case MUX_TYPE_TDM:
+		dm_i2c_read(dev, 0, &tmp, 1);
+		setbits_8(&tmp, 0x82);
+		dm_i2c_write(dev, 1, &tmp, 1);
+		dm_i2c_read(dev, 3, &tmp, 1);
+		clrbits_8(&tmp, 0x82);
+		dm_i2c_write(dev, 3, &tmp, 1);
+		break;
+	case MUX_TYPE_CAN:
+		dm_i2c_read(dev, 0, &tmp, 1);
+		clrbits_8(&tmp, 0x02);
+		dm_i2c_write(dev, 1, &tmp, 1);
+		dm_i2c_read(dev, 3, &tmp, 1);
+		clrbits_8(&tmp, 0x02);
+		dm_i2c_write(dev, 3, &tmp, 1);
+		break;
+	case MUX_TYPE_CS0_NOR:
+		dm_i2c_read(dev, 0, &tmp, 1);
+		clrbits_8(&tmp, 0x08);
+		dm_i2c_write(dev, 1, &tmp, 1);
+		dm_i2c_read(dev, 3, &tmp, 1);
+		clrbits_8(&tmp, 0x08);
+		dm_i2c_write(dev, 3, &tmp, 1);
+		break;
+	case MUX_TYPE_CS0_NAND:
+		dm_i2c_read(dev, 0, &tmp, 1);
+		setbits_8(&tmp, 0x08);
+		dm_i2c_write(dev, 1, &tmp, 1);
+		dm_i2c_read(dev, 3, &tmp, 1);
+		clrbits_8(&tmp, 0x08);
+		dm_i2c_write(dev, 3, &tmp, 1);
+		break;
+	default:
+		break;
+	}
+#endif
+#else
 #if defined(CONFIG_TARGET_P1010RDB_PA)
 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 
@@ -242,6 +362,7 @@ int config_board_mux(int ctrl_type)
 		break;
 	}
 	i2c_set_bus_num(orig_bus);
+#endif
 #endif
 	return 0;
 }
@@ -250,9 +371,24 @@ int config_board_mux(int ctrl_type)
 int i2c_pca9557_read(int type)
 {
 	u8 val;
-
-	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+	int bus_num = I2C_PCA9557_BUS_NUM;
+
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2,
+			1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+				bus_num);
+		return ret;
+	}
+	dm_i2c_read(dev, 0, &val, 1);
+#else
+	i2c_set_bus_num(bus_num);
 	i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
+#endif
 
 	switch (type) {
 	case I2C_READ_BANK:
@@ -280,11 +416,26 @@ int checkboard(void)
 	printf("Board: %sRDB-PA, ", cpu->name);
 #elif defined(CONFIG_TARGET_P1010RDB_PB)
 	printf("Board: %sRDB-PB, ", cpu->name);
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       I2C_PCA9557_BUS_NUM);
+		return ret;
+	}
+	val = 0x0;  /* no polarity inversion */
+	dm_i2c_write(dev, 2, &val, 1);
+#else
 	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 	i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
 	val = 0x0;  /* no polarity inversion */
 	i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
 #endif
+#endif
 
 #ifdef CONFIG_SDCARD
 	/* switch to IFC to read info from CPLD */
@@ -308,7 +459,11 @@ int checkboard(void)
 	case 0xe:
 		puts("SDHC\n");
 		val = 0x60; /* set pca9557 pin input/output */
+#ifdef CONFIG_DM_I2C
+		dm_i2c_write(dev, 3, &val, 1);
+#else
 		i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
+#endif
 		break;
 	case 0x5:
 		config_board_mux(MUX_TYPE_IFC);
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 60e8904d42..41dbbedecc 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 /*
@@ -522,17 +523,22 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
 
 /* I2C */
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#else
+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
+#endif
 #define I2C_PCA9557_ADDR1		0x18
 #define I2C_PCA9557_ADDR2		0x19
 #define I2C_PCA9557_BUS_NUM		0
+#define CONFIG_SYS_I2C_FSL
 
 /* I2C EEPROM */
 #if defined(CONFIG_TARGET_P1010RDB_PB)
-- 
2.17.1

[PATCH 19/27] configs: P1010: Enable DM_I2C and DM_RTC

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

Enable DM_I2C and DM_RTC in P1010RDB defconfigs,
except P1010RDB SECBOOT defconfigs.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 configs/P1010RDB-PA_36BIT_NAND_defconfig     | 2 ++
 configs/P1010RDB-PA_36BIT_NOR_defconfig      | 2 ++
 configs/P1010RDB-PA_36BIT_SDCARD_defconfig   | 2 ++
 configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 ++
 configs/P1010RDB-PA_NAND_defconfig           | 2 ++
 configs/P1010RDB-PA_NOR_defconfig            | 2 ++
 configs/P1010RDB-PA_SDCARD_defconfig         | 2 ++
 configs/P1010RDB-PA_SPIFLASH_defconfig       | 2 ++
 configs/P1010RDB-PB_36BIT_NAND_defconfig     | 2 ++
 configs/P1010RDB-PB_36BIT_NOR_defconfig      | 2 ++
 configs/P1010RDB-PB_36BIT_SDCARD_defconfig   | 2 ++
 configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 ++
 configs/P1010RDB-PB_NAND_defconfig           | 2 ++
 configs/P1010RDB-PB_NOR_defconfig            | 2 ++
 configs/P1010RDB-PB_SDCARD_defconfig         | 2 ++
 configs/P1010RDB-PB_SPIFLASH_defconfig       | 2 ++
 16 files changed, 32 insertions(+)

diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index 4b2b8c4628..824dec0d68 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -69,3 +69,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index 6f328a5745..deda02cb5e 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -50,3 +50,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index 83ad24aea8..5fa07b2f72 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -63,3 +63,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index 08d8864653..a9803fc1d6 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -65,3 +65,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index 796e112732..37a84ebef6 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -68,3 +68,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index 73dbb867e2..24fe95c19f 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -49,3 +49,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index 947bd22657..5b49862a72 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -62,3 +62,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index bd6d1ea702..db2fd29ccf 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -64,3 +64,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 1461b89f24..7e87d41e97 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -69,3 +69,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index c857c8d728..be33af3b88 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -50,3 +50,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index f79796a480..d54f9b5ca1 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -63,3 +63,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index c4c3c4486c..c0568f15a5 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -65,3 +65,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index 8378eede02..dd46b1df0f 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -68,3 +68,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index 764017a907..558c799ba2 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -49,3 +49,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index 437858b800..510dde4f5b 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -62,3 +62,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index 7f222db0ab..dfc0a1d9a7 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -64,3 +64,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
-- 
2.17.1

[PATCH 20/27] dm: ppc: MPC8548CDS: add i2c DM support

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This supports i2c DM for board MPC8548CDS

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 board/freescale/common/sys_eeprom.c | 3 ++-
 include/configs/MPC8548CDS.h        | 9 ++++++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index 6f151b0f71..c52af7060e 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -589,6 +589,7 @@ unsigned int get_cpu_board_revision(void)
 		u8 major;         /* 0x04        Board revision, major */
 		u8 minor;         /* 0x05        Board revision, minor */
 	} be;
+	int ret;
 
 #ifndef CONFIG_DM_I2C
 	i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
@@ -603,7 +604,7 @@ unsigned int get_cpu_board_revision(void)
 #else
 	ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
 				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
-				      &dev)
+				      &dev);
 #endif
 	if (!ret)
 		dm_i2c_read(dev, 0, (void *)&be, sizeof(be));
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index a68d190f6a..d185926cab 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
+ * Copyright 2020 NXP
  */
 
 /*
@@ -304,12 +305,18 @@ extern unsigned long get_clock_freq(void);
 /*
  * I2C
  */
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+#else
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
+#endif
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	400000
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
 
 /* EEPROM */
 #define CONFIG_ID_EEPROM
-- 
2.17.1

[PATCH 20/27] dm: ppc: MPC8548CDS: add i2c DM support

[Priyanka Jain]

>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Biwen Li
>Sent: Sunday, April 12, 2020 2:24 PM
>To: Jagdish Gediya <jagdish.gediya@nxp.com>; Priyanka Jain
><priyanka.jain@nxp.com>; hs at denx.de; jagan at amarulasolutions.com;
>aford173 at gmail.com; Alison Wang <alison.wang@nxp.com>;
>jh80.chung at samsung.com; Pramod Kumar <pramod.kumar_1@nxp.com>;
>Rajesh Bhagat <rajesh.bhagat@nxp.com>; Ruchika Gupta
><ruchika.gupta@nxp.com>; olteanv at gmail.com
>Cc: Xiaobo Xie <xiaobo.xie@nxp.com>; Jiafei Pan <jiafei.pan@nxp.com>; u-
>boot at lists.denx.de; Z.q. Hou <zhiqiang.hou@nxp.com>; Biwen Li
><biwen.li@nxp.com>
>Subject: [PATCH 20/27] dm: ppc: MPC8548CDS: add i2c DM support
>
>From: Biwen Li <biwen.li@nxp.com>
>
>This supports i2c DM for board MPC8548CDS
>
>Signed-off-by: Biwen Li <biwen.li@nxp.com>
>---
> board/freescale/common/sys_eeprom.c | 3 ++-
> include/configs/MPC8548CDS.h        | 9 ++++++++-
> 2 files changed, 10 insertions(+), 2 deletions(-)
>
>diff --git a/board/freescale/common/sys_eeprom.c
>b/board/freescale/common/sys_eeprom.c
>index 6f151b0f71..c52af7060e 100644
>--- a/board/freescale/common/sys_eeprom.c
>+++ b/board/freescale/common/sys_eeprom.c
>@@ -589,6 +589,7 @@ unsigned int get_cpu_board_revision(void)
> 		u8 major;         /* 0x04        Board revision, major */
> 		u8 minor;         /* 0x05        Board revision, minor */
> 	} be;
>+	int ret;
>
> #ifndef CONFIG_DM_I2C
> 	i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
>CONFIG_SYS_I2C_EEPROM_ADDR_LEN, @@ -603,7 +604,7 @@ unsigned int
>get_cpu_board_revision(void)  #else
> 	ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
> 				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
>-				      &dev)
>+				      &dev);
Was this compilation error exist before this patch series as well?

> #endif
> 	if (!ret)
> 		dm_i2c_read(dev, 0, (void *)&be, sizeof(be)); diff --git
>a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index
>a68d190f6a..d185926cab 100644
>--- a/include/configs/MPC8548CDS.h
>+++ b/include/configs/MPC8548CDS.h
>@@ -1,6 +1,7 @@
> /* SPDX-License-Identifier: GPL-2.0+ */
> /*
>  * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
>+ * Copyright 2020 NXP
>  */
>
> /*
>@@ -304,12 +305,18 @@ extern unsigned long get_clock_freq(void);
> /*
>  * I2C
>  */
>+#ifndef CONFIG_DM_I2C
> #define CONFIG_SYS_I2C
>+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
>+#else
>+#define CONFIG_SYS_SPD_BUS_NUM 0
>+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
>+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
>+#endif
> #define CONFIG_SYS_I2C_FSL
> #define CONFIG_SYS_FSL_I2C_SPEED	400000
In other similar patches, you were adding this kind of defines under #ifndef CONFIG_DM_I2C
Why it is different for this patch?

Priyanka
> #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
> #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
>-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
>
> /* EEPROM */
> #define CONFIG_ID_EEPROM
>--
>2.17.1

[PATCH 20/27] dm: ppc: MPC8548CDS: add i2c DM support

[Biwen Li]

> >
> >From: Biwen Li <biwen.li@nxp.com>
> >
> >This supports i2c DM for board MPC8548CDS
> >
> >Signed-off-by: Biwen Li <biwen.li@nxp.com>
> >---
> > board/freescale/common/sys_eeprom.c | 3 ++-
> > include/configs/MPC8548CDS.h        | 9 ++++++++-
> > 2 files changed, 10 insertions(+), 2 deletions(-)
> >
> >diff --git a/board/freescale/common/sys_eeprom.c
> >b/board/freescale/common/sys_eeprom.c
> >index 6f151b0f71..c52af7060e 100644
> >--- a/board/freescale/common/sys_eeprom.c
> >+++ b/board/freescale/common/sys_eeprom.c
> >@@ -589,6 +589,7 @@ unsigned int get_cpu_board_revision(void)
> > 		u8 major;         /* 0x04        Board revision, major */
> > 		u8 minor;         /* 0x05        Board revision, minor */
> > 	} be;
> >+	int ret;
> >
> > #ifndef CONFIG_DM_I2C
> > 	i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
> >CONFIG_SYS_I2C_EEPROM_ADDR_LEN, @@ -603,7 +604,7 @@ unsigned int
> >get_cpu_board_revision(void)  #else
> > 	ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
> > 				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
> >-				      &dev)
> >+				      &dev);
> Was this compilation error exist before this patch series as well?
Yes, it is.
> 
> > #endif
> > 	if (!ret)
> > 		dm_i2c_read(dev, 0, (void *)&be, sizeof(be)); diff --git
> >a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index
> >a68d190f6a..d185926cab 100644
> >--- a/include/configs/MPC8548CDS.h
> >+++ b/include/configs/MPC8548CDS.h
> >@@ -1,6 +1,7 @@
> > /* SPDX-License-Identifier: GPL-2.0+ */
> > /*
> >  * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
> >+ * Copyright 2020 NXP
> >  */
> >
> > /*
> >@@ -304,12 +305,18 @@ extern unsigned long get_clock_freq(void);
> > /*
> >  * I2C
> >  */
> >+#ifndef CONFIG_DM_I2C
> > #define CONFIG_SYS_I2C
> >+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
> >+#else
> >+#define CONFIG_SYS_SPD_BUS_NUM 0
> >+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
> >+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
> >+#endif
> > #define CONFIG_SYS_I2C_FSL
> > #define CONFIG_SYS_FSL_I2C_SPEED	400000
> In other similar patches, you were adding this kind of defines under #ifndef
> CONFIG_DM_I2C Why it is different for this patch?
> 
> Priyanka
> > #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
> > #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
> >-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
> >
> > /* EEPROM */
> > #define CONFIG_ID_EEPROM
> >--
> >2.17.1

[PATCH 20/27] dm: ppc: MPC8548CDS: add i2c DM support

[Biwen Li]

> Subject: RE: [PATCH 20/27] dm: ppc: MPC8548CDS: add i2c DM support
> 
> >-----Original Message-----
> >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Biwen Li
> >Sent: Sunday, April 12, 2020 2:24 PM
> >To: Jagdish Gediya <jagdish.gediya@nxp.com>; Priyanka Jain
> ><priyanka.jain@nxp.com>; hs at denx.de; jagan at amarulasolutions.com;
> >aford173 at gmail.com; Alison Wang <alison.wang@nxp.com>;
> >jh80.chung at samsung.com; Pramod Kumar <pramod.kumar_1@nxp.com>;
> Rajesh
> >Bhagat <rajesh.bhagat@nxp.com>; Ruchika Gupta
> <ruchika.gupta@nxp.com>;
> >olteanv at gmail.com
> >Cc: Xiaobo Xie <xiaobo.xie@nxp.com>; Jiafei Pan <jiafei.pan@nxp.com>;
> >u- boot at lists.denx.de; Z.q. Hou <zhiqiang.hou@nxp.com>; Biwen Li
> ><biwen.li@nxp.com>
> >Subject: [PATCH 20/27] dm: ppc: MPC8548CDS: add i2c DM support
> >
> >From: Biwen Li <biwen.li@nxp.com>
> >
> >This supports i2c DM for board MPC8548CDS
> >
> >Signed-off-by: Biwen Li <biwen.li@nxp.com>
> >---
> > board/freescale/common/sys_eeprom.c | 3 ++-
> > include/configs/MPC8548CDS.h        | 9 ++++++++-
> > 2 files changed, 10 insertions(+), 2 deletions(-)
> >
> >diff --git a/board/freescale/common/sys_eeprom.c
> >b/board/freescale/common/sys_eeprom.c
> >index 6f151b0f71..c52af7060e 100644
> >--- a/board/freescale/common/sys_eeprom.c
> >+++ b/board/freescale/common/sys_eeprom.c
> >@@ -589,6 +589,7 @@ unsigned int get_cpu_board_revision(void)
> > 		u8 major;         /* 0x04        Board revision, major */
> > 		u8 minor;         /* 0x05        Board revision, minor */
> > 	} be;
> >+	int ret;
> >
> > #ifndef CONFIG_DM_I2C
> > 	i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
> >CONFIG_SYS_I2C_EEPROM_ADDR_LEN, @@ -603,7 +604,7 @@ unsigned int
> >get_cpu_board_revision(void)  #else
> > 	ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
> > 				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
> >-				      &dev)
> >+				      &dev);
> Was this compilation error exist before this patch series as well?
> 
> > #endif
> > 	if (!ret)
> > 		dm_i2c_read(dev, 0, (void *)&be, sizeof(be)); diff --git
> >a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index
> >a68d190f6a..d185926cab 100644
> >--- a/include/configs/MPC8548CDS.h
> >+++ b/include/configs/MPC8548CDS.h
> >@@ -1,6 +1,7 @@
> > /* SPDX-License-Identifier: GPL-2.0+ */
> > /*
> >  * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
> >+ * Copyright 2020 NXP
> >  */
> >
> > /*
> >@@ -304,12 +305,18 @@ extern unsigned long get_clock_freq(void);
> > /*
> >  * I2C
> >  */
> >+#ifndef CONFIG_DM_I2C
> > #define CONFIG_SYS_I2C
> >+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
> >+#else
> >+#define CONFIG_SYS_SPD_BUS_NUM 0
> >+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
> >+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
> >+#endif
> > #define CONFIG_SYS_I2C_FSL
> > #define CONFIG_SYS_FSL_I2C_SPEED	400000
> In other similar patches, you were adding this kind of defines under #ifndef
> CONFIG_DM_I2C Why it is different for this patch?
I will move it to #ifndef CONFIG_DM_I2C, and below configs in v2.
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
 
> Priyanka
> > #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
> > #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
> >-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
> >
> > /* EEPROM */
> > #define CONFIG_ID_EEPROM
> >--
> >2.17.1

[PATCH 21/27] configs: MPC8548CDS: enable DM_I2C

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This enables DM_I2C in MPC8548CDS defconfigs

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 configs/MPC8548CDS_36BIT_defconfig  | 1 +
 configs/MPC8548CDS_defconfig        | 1 +
 configs/MPC8548CDS_legacy_defconfig | 1 +
 3 files changed, 3 insertions(+)

diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index a8700100e1..f5680ccaaa 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -37,3 +37,4 @@ CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_CONS_INDEX=2
 CONFIG_SYS_NS16550=y
+CONFIG_DM_I2C=y
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index 42c31d4237..c8dd29c08c 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig
@@ -36,3 +36,4 @@ CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_CONS_INDEX=2
 CONFIG_SYS_NS16550=y
+CONFIG_DM_I2C=y
diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig
index 263f24c179..e82749b808 100644
--- a/configs/MPC8548CDS_legacy_defconfig
+++ b/configs/MPC8548CDS_legacy_defconfig
@@ -36,3 +36,4 @@ CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_CONS_INDEX=2
 CONFIG_SYS_NS16550=y
+CONFIG_DM_I2C=y
-- 
2.17.1

[PATCH 22/27] dm: ppc: T4240: add i2c DM support

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This supports i2c DM for SoC T4240

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 arch/powerpc/dts/t4240.dtsi           |   4 +-
 board/freescale/common/vsc3316_3308.c | 255 +++++++++++++++++++++++++-
 board/freescale/t4qds/t4240qds.c      |  43 ++++-
 include/configs/T4240QDS.h            |  13 ++
 include/configs/T4240RDB.h            |   9 +-
 5 files changed, 314 insertions(+), 10 deletions(-)

diff --git a/arch/powerpc/dts/t4240.dtsi b/arch/powerpc/dts/t4240.dtsi
index 43f98cd9e1..56bec0346e 100644
--- a/arch/powerpc/dts/t4240.dtsi
+++ b/arch/powerpc/dts/t4240.dtsi
@@ -3,7 +3,7 @@
  * T4240 Silicon/SoC Device Tree Source (pre include)
  *
  * Copyright 2013 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
  */
 
 /dts-v1/;
@@ -174,4 +174,6 @@
 		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000   /* downstream I/O */
 			  0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */
 	};
+	/include/ "qoriq-i2c-0.dtsi"
+	/include/ "qoriq-i2c-1.dtsi"
 };
diff --git a/board/freescale/common/vsc3316_3308.c b/board/freescale/common/vsc3316_3308.c
index 033fae020f..3fb702aba1 100644
--- a/board/freescale/common/vsc3316_3308.c
+++ b/board/freescale/common/vsc3316_3308.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 #include "vsc3316_3308.h"
@@ -32,7 +33,22 @@ int vsc_if_enable(unsigned int vsc_addr)
 
 	/* enable 2-wire Serial InterFace (I2C) */
 	data = 0x02;
+#ifdef CONFIG_DM_I2C
+	int ret, bus_num = 0;
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, vsc_addr,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+
+	return dm_i2c_write(dev, INTERFACE_MODE_REG, &data, 1);
+#else
 	return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, &data, 1);
+#endif
 }
 
 int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
@@ -45,6 +61,65 @@ int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
 	debug("VSC:Initializing VSC3316 at I2C address 0x%2x"
 		" for Tx\n", vsc_addr);
 
+#ifdef CONFIG_DM_I2C
+	int bus_num = 0;
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, vsc_addr,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+
+	ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1);
+	if (ret < 0) {
+		printf("VSC:0x%x could not read REV_ID from device.\n",
+			vsc_addr);
+		return ret;
+	}
+
+	if (rev_id != 0xab) {
+		printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
+			vsc_addr);
+		return -ENODEV;
+	}
+
+	ret = vsc_if_enable(vsc_addr);
+	if (ret) {
+		printf("VSC:0x%x could not configured for 2-wire I/F.\n",
+			vsc_addr);
+		return ret;
+	}
+
+	/* config connections - page 0x00 */
+	dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
+
+	/* Making crosspoint connections, by connecting required
+	 * input to output */
+	for (i = 0; i < num_con ; i++)
+		dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]);
+
+	/* input state - page 0x13 */
+	dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
+	/* Configuring the required input of the switch */
+	for (i = 0; i < num_con ; i++)
+		dm_i2c_reg_write(dev, con_arr[i][0], 0x80);
+
+	/* Setting Global Input LOS threshold value */
+	dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0x60);
+
+	/* config output mode - page 0x23 */
+	dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
+	/* Turn ON the Output driver correspond to required output*/
+	for (i = 0; i < num_con ; i++)
+		dm_i2c_reg_write(dev,  con_arr[i][1], 0);
+
+	/* configure global core control register, Turn on Global core power */
+	dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0);
+
+#else
 	ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
 	if (ret < 0) {
 		printf("VSC:0x%x could not read REV_ID from device.\n",
@@ -90,6 +165,7 @@ int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
 
 	/* configure global core control register, Turn on Global core power */
 	i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
+#endif
 
 	vsc_wp_config(vsc_addr);
 
@@ -107,6 +183,104 @@ int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2],
 	debug("VSC:Initializing VSC3308 at I2C address 0x%x for Tx\n",
 	      vsc_addr);
 
+#ifdef CONFIG_DM_I2C
+	int bus_num = 0;
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, vsc_addr,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+
+	ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1);
+	if (ret < 0) {
+		printf("VSC:0x%x could not read REV_ID from device.\n",
+		       vsc_addr);
+		return ret;
+	}
+
+	if (rev_id != 0xab) {
+		printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
+		       vsc_addr);
+		return -ENODEV;
+	}
+
+	ret = vsc_if_enable(vsc_addr);
+	if (ret) {
+		printf("VSC:0x%x could not configured for 2-wire I/F.\n",
+		       vsc_addr);
+		return ret;
+	}
+
+	/* config connections - page 0x00 */
+	dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
+
+	/* Configure Global Input ISE */
+	dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE1, 0);
+	dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE2, 0);
+
+	/* Configure Tx/Rx Global Output PE1 */
+	dm_i2c_reg_write(dev, GLOBAL_OUTPUT_PE1, 0);
+
+	/* Configure Tx/Rx Global Output PE2 */
+	dm_i2c_reg_write(dev, GLOBAL_OUTPUT_PE2, 0);
+
+	/* Configure Tx/Rx Global Input GAIN */
+	dm_i2c_reg_write(dev, GLOBAL_INPUT_GAIN, 0x3F);
+
+	/* Setting Global Input LOS threshold value */
+	dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0xE0);
+
+	/* Setting Global output termination */
+	dm_i2c_reg_write(dev, GLOBAL_OUTPUT_TERMINATION, 0);
+
+	/* Configure Tx/Rx Global Output level */
+	if (vsc_addr == VSC3308_TX_ADDRESS)
+		dm_i2c_reg_write(dev, GLOBAL_OUTPUT_LEVEL, 4);
+	else
+		dm_i2c_reg_write(dev, GLOBAL_OUTPUT_LEVEL, 2);
+
+	/* Making crosspoint connections, by connecting required
+	 * input to output */
+	for (i = 0; i < num_con ; i++)
+		dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]);
+
+	/* input state - page 0x13 */
+	dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
+	/* Turning off all the required input of the switch */
+	for (i = 0; i < num_con; i++)
+		dm_i2c_reg_write(dev, con_arr[i][0], 1);
+
+	/* only turn on specific Tx/Rx requested by the XFI erratum */
+	if (vsc_addr == VSC3308_TX_ADDRESS) {
+		dm_i2c_reg_write(dev, 2, 0);
+		dm_i2c_reg_write(dev, 3, 0);
+	} else {
+		dm_i2c_reg_write(dev, 0, 0);
+		dm_i2c_reg_write(dev, 1, 0);
+	}
+
+	/* config output mode - page 0x23 */
+	dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
+	/* Turn off the Output driver correspond to required output*/
+	for (i = 0; i < num_con ; i++)
+		dm_i2c_reg_write(dev,  con_arr[i][1], 1);
+
+	/* only turn on specific Tx/Rx requested by the XFI erratum */
+	if (vsc_addr == VSC3308_TX_ADDRESS) {
+		dm_i2c_reg_write(dev, 0, 0);
+		dm_i2c_reg_write(dev, 1, 0);
+	} else {
+		dm_i2c_reg_write(dev, 3, 0);
+		dm_i2c_reg_write(dev, 4, 0);
+	}
+
+	/* configure global core control register, Turn on Global core power */
+	dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0);
+#else
 	ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
 	if (ret < 0) {
 		printf("VSC:0x%x could not read REV_ID from device.\n",
@@ -192,7 +366,7 @@ int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2],
 
 	/* configure global core control register, Turn on Global core power */
 	i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
-
+#endif
 	vsc_wp_config(vsc_addr);
 
 	return 0;
@@ -208,7 +382,68 @@ int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
 
 	debug("VSC:Initializing VSC3308 at I2C address 0x%x"
 		" for Tx\n", vsc_addr);
+#ifdef CONFIG_DM_I2C
+	int bus_num = 0;
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, vsc_addr,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+
+	ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1);
+	if (ret < 0) {
+		printf("VSC:0x%x could not read REV_ID from device.\n",
+			vsc_addr);
+		return ret;
+	}
+
+	if (rev_id != 0xab) {
+		printf("VSC: device@address 0x%x is not VSC3316/3308.\n",
+			vsc_addr);
+		return -ENODEV;
+	}
+
+	ret = vsc_if_enable(vsc_addr);
+	if (ret) {
+		printf("VSC:0x%x could not configured for 2-wire I/F.\n",
+			vsc_addr);
+		return ret;
+	}
+
+	/* config connections - page 0x00 */
+	dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
+
+	/* Making crosspoint connections, by connecting required
+	 * input to output */
+	for (i = 0; i < num_con ; i++)
+		dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]);
 
+	/*Configure Global Input ISE and gain */
+	dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE1, 0x12);
+	dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE2, 0x12);
+
+	/* input state - page 0x13 */
+	dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
+	/* Turning ON the required input of the switch */
+	for (i = 0; i < num_con ; i++)
+		dm_i2c_reg_write(dev, con_arr[i][0], 0);
+
+	/* Setting Global Input LOS threshold value */
+	dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0x60);
+
+	/* config output mode - page 0x23 */
+	dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
+	/* Turn ON the Output driver correspond to required output*/
+	for (i = 0; i < num_con ; i++)
+		dm_i2c_reg_write(dev,  con_arr[i][1], 0);
+
+	/* configure global core control register, Turn on Global core power */
+	dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0);
+#else
 	ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
 	if (ret < 0) {
 		printf("VSC:0x%x could not read REV_ID from device.\n",
@@ -258,7 +493,7 @@ int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
 
 	/* configure global core control register, Turn on Global core power */
 	i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
-
+#endif
 	vsc_wp_config(vsc_addr);
 
 	return 0;
@@ -270,6 +505,22 @@ void vsc_wp_config(unsigned int vsc_addr)
 
 	/* For new crosspoint configuration to occur, WP bit of
 	 * CORE_CONFIG_REG should be set 1 and then reset to 0 */
+#ifdef CONFIG_DM_I2C
+	int ret, bus_num = 0;
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, vsc_addr,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return;
+	}
+
+	dm_i2c_reg_write(dev, CORE_CONFIG_REG, 0x01);
+	dm_i2c_reg_write(dev, CORE_CONFIG_REG, 0x0);
+#else
 	i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x01);
 	i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x0);
+#endif
 }
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index 5608774afd..5656e9c048 100644
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2009-2012 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 #include <common.h>
@@ -91,11 +92,25 @@ int checkboard(void)
 	return 0;
 }
 
-int select_i2c_ch_pca9547(u8 ch)
+int select_i2c_ch_pca9547(u8 ch, int bus_num)
 {
 	int ret;
 
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+
+	ret = dm_i2c_write(dev, 0, &ch, 1);
+#else
 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
 	if (ret) {
 		puts("PCA: failed to select proper channel\n");
 		return ret;
@@ -115,10 +130,26 @@ static inline int read_voltage(void)
 {
 	int i, ret, voltage_read = 0;
 	u16 vol_mon;
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+	int bus_num = 0;
+#endif
 
 	for (i = 0; i < NUM_READINGS; i++) {
+#ifdef CONFIG_DM_I2C
+		ret = i2c_get_chip_for_busnum(bus_num, I2C_VOL_MONITOR_ADDR,
+					      1, &dev);
+		if (ret) {
+			printf("%s: Cannot find udev for a bus %d\n", __func__,
+			       bus_num);
+			return ret;
+		}
+
+		ret = dm_i2c_read(dev, I2C_VOL_MONITOR_BUS_V_OFFSET, (void *)&vol_mon, 2);
+#else
 		ret = i2c_read(I2C_VOL_MONITOR_ADDR,
 			I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
+#endif
 		if (ret) {
 			printf("VID: failed to read core voltage\n");
 			return ret;
@@ -250,7 +281,7 @@ static int adjust_vdd(ulong vdd_override)
 		unsigned voltage;
 	};
 
-	ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR);
+	ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0);
 	if (ret) {
 		debug("VID: I2c failed to switch channel\n");
 		ret = -1;
@@ -348,7 +379,7 @@ int config_frontside_crossbar_vsc3316(void)
 	u32 srds_prtcl_s1, srds_prtcl_s2;
 	int ret;
 
-	ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS);
+	ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS, 0);
 	if (ret)
 		return ret;
 
@@ -567,7 +598,7 @@ int board_early_init_r(void)
 	/* Configure board SERDES ports crossbar */
 	config_frontside_crossbar_vsc3316();
 	config_backside_crossbar_mux();
-	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 
 	return 0;
 }
@@ -732,11 +763,11 @@ void board_detail(void)
 	}
 
 	/* Voltage secion */
-	if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) {
+	if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0)) {
 		vdd = read_voltage();
 		if (vdd > 0)
 			printf("Core voltage= %d mV\n", vdd);
-		select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+		select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 	}
 
 	printf("XVDD        = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 94e0ddbd88..f89d43c3a3 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -280,6 +280,19 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 /* I2C */
+#ifndef CONFIG_DM_I2C
+#define CONFIG_SYS_I2C
+#else
+#undef CONFIG_SYS_I2C
+#undef CONFIG_SYS_FSL_I2C2_OFFSET
+#undef CONFIG_SYS_FSL_I2C2_SLAVE
+#undef CONFIG_SYS_FSL_I2C2_SPEED
+#undef CONFIG_SYS_FSL_I2C_SLAVE
+#undef CONFIG_SYS_FSL_I2C_SPEED
+#undef CONFIG_SYS_FSL_I2C_OFFSET
+#endif
+
+#define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SPEED	100000	/* I2C speed */
 #define CONFIG_SYS_FSL_I2C2_SPEED	100000	/* I2C2 speed */
 #define I2C_MUX_PCA_ADDR_PRI		0x77 /* I2C bus multiplexer,primary */
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 042757c20e..4c0b9ada62 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 /*
@@ -159,12 +160,18 @@
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 
 /* I2C */
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
+#else
+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
+#endif
+
+#define CONFIG_SYS_I2C_FSL
 
 /*
  * General PCI
-- 
2.17.1

[PATCH 23/27] configs: T4240RDB: enable DM_I2C

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This enable DM_I2C in T4240RDB defconfigs

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 configs/T4240RDB_SDCARD_defconfig | 1 +
 configs/T4240RDB_defconfig        | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index 17be2e78ae..20d9afc7dc 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -68,3 +68,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index 426ddef391..9949ae74a0 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -56,3 +56,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
-- 
2.17.1

[PATCH 24/27] dm: powerpc: T2080/T2081: add i2c DM support

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This supports i2c DM for SoC T2080/T2081

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 arch/powerpc/dts/t2080.dtsi         |  4 +++-
 board/freescale/t208xqds/t208xqds.c | 19 ++++++++++++++++---
 include/configs/T208xQDS.h          |  7 ++++++-
 include/configs/T208xRDB.h          | 10 +++++++++-
 4 files changed, 34 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/dts/t2080.dtsi b/arch/powerpc/dts/t2080.dtsi
index 458019ae92..a9e9b404f6 100644
--- a/arch/powerpc/dts/t2080.dtsi
+++ b/arch/powerpc/dts/t2080.dtsi
@@ -3,7 +3,7 @@
  * T2080/T2081 Silicon/SoC Device Tree Source (pre include)
  *
  * Copyright 2013 Freescale Semiconductor Inc.
- * Copyright 2018 NXP
+ * Copyright 2018,2020 NXP
  */
 
 /dts-v1/;
@@ -96,6 +96,8 @@
 			sata-number = <2>;
 			sata-fpdma = <0>;
 		};
+		/include/ "qoriq-i2c-0.dtsi"
+		/include/ "qoriq-i2c-1.dtsi"
 	};
 
 	pcie at ffe240000 {
diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
index 79cc1543f9..9100401022 100644
--- a/board/freescale/t208xqds/t208xqds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2009-2013 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 #include <common.h>
@@ -75,11 +76,23 @@ int checkboard(void)
 	return 0;
 }
 
-int select_i2c_ch_pca9547(u8 ch)
+int select_i2c_ch_pca9547(u8 ch, int bus_num)
 {
 	int ret;
 
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+	ret = dm_i2c_write(dev, 0, &ch, 1);
+#else
 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
 	if (ret) {
 		puts("PCA: failed to select proper channel\n");
 		return ret;
@@ -90,7 +103,7 @@ int select_i2c_ch_pca9547(u8 ch)
 
 int i2c_multiplexer_select_vid_channel(u8 channel)
 {
-	return select_i2c_ch_pca9547(channel);
+	return select_i2c_ch_pca9547(channel, 0);
 }
 
 int brd_mux_lane_to_slot(void)
@@ -368,7 +381,7 @@ int board_early_init_r(void)
 		printf("Warning: Adjusting core voltage failed.\n");
 
 	brd_mux_lane_to_slot();
-	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 
 	return 0;
 }
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index be5a658d7e..fb44ae9a4c 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2011-2013 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 /*
@@ -385,8 +386,8 @@ unsigned long get_board_ddr_clk(void);
 /*
  * I2C
  */
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
@@ -399,6 +400,10 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
+#endif
+
+#define CONFIG_SYS_I2C_FSL
+
 #define I2C_MUX_PCA_ADDR_PRI	0x77 /* I2C bus multiplexer,primary */
 #define I2C_MUX_PCA_ADDR_SEC1	0x75 /* I2C bus multiplexer,secondary 1 */
 #define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 68de90fbbb..71dd9e79c7 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 /*
@@ -333,8 +334,8 @@ unsigned long get_board_ddr_clk(void);
 /*
  * I2C
  */
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
@@ -347,6 +348,13 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
+#else
+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
+#endif
+
+#define CONFIG_SYS_I2C_FSL
+
 #define I2C_MUX_PCA_ADDR_PRI	0x77 /* I2C bus multiplexer,primary */
 #define I2C_MUX_PCA_ADDR_SEC1	0x75 /* I2C bus multiplexer,secondary 1 */
 #define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
-- 
2.17.1

[PATCH 25/27] configs: T2080: enable DM_I2C

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This enables DM_I2C in T2080 defconfigs

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 configs/T2080QDS_NAND_defconfig           | 1 +
 configs/T2080QDS_SDCARD_defconfig         | 1 +
 configs/T2080QDS_SECURE_BOOT_defconfig    | 1 +
 configs/T2080QDS_SPIFLASH_defconfig       | 1 +
 configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 1 +
 configs/T2080QDS_defconfig                | 1 +
 configs/T2080RDB_NAND_defconfig           | 1 +
 configs/T2080RDB_SDCARD_defconfig         | 1 +
 configs/T2080RDB_SPIFLASH_defconfig       | 1 +
 configs/T2080RDB_defconfig                | 1 +
 10 files changed, 10 insertions(+)

diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 2c3a2edde8..fbfb0d6ccd 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -77,3 +77,4 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_DM_I2C=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index a7c2fa8121..69e33bc83b 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -74,3 +74,4 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_DM_I2C=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index ef5aa483f8..4fcf117ad3 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -64,3 +64,4 @@ CONFIG_USB_STORAGE=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_DM_I2C=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 1848a790ee..9e41df99ad 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -77,3 +77,4 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_DM_I2C=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index a6c3215c78..0bb1e7393a 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -54,3 +54,4 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_DM_I2C=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index 18d0a50ee0..c57e1ccb61 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -62,3 +62,4 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_DM_I2C=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index ca96fb8d3b..9c1da1bd9c 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -78,3 +78,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index 1c21dc69a9..ad5c6a2995 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -75,3 +75,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 8c45787bce..cebccc68d9 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -78,3 +78,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index ea43eb5d17..26934fe3f3 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -62,3 +62,4 @@ CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_I2C=y
-- 
2.17.1

[PATCH 26/27] dm: powerpc: T1040/T1042: add i2c DM support

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This supports i2c DM for SoC T1040/T1042

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 arch/powerpc/dts/t104x.dtsi         |  4 +++-
 board/freescale/t1040qds/diu.c      |  5 +++--
 board/freescale/t1040qds/t1040qds.c | 18 ++++++++++++++++--
 board/freescale/t1040qds/t1040qds.h |  3 ++-
 include/configs/T1040QDS.h          |  7 +++++++
 include/configs/T104xRDB.h          | 10 +++++++++-
 6 files changed, 40 insertions(+), 7 deletions(-)

diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi
index 093aaab834..0a08a69f31 100644
--- a/arch/powerpc/dts/t104x.dtsi
+++ b/arch/powerpc/dts/t104x.dtsi
@@ -3,7 +3,7 @@
  * T104X Silicon/SoC Device Tree Source (pre include)
  *
  * Copyright 2013 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
  */
 
 /dts-v1/;
@@ -85,6 +85,8 @@
 			reg = <0x114000 0x1000>;
 			clock-frequency = <0>;
 		};
+		/include/ "qoriq-i2c-0.dtsi"
+		/include/ "qoriq-i2c-1.dtsi"
 	};
 
 	pcie at ffe240000 {
diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c
index ab9e922a92..0b1aeed69e 100644
--- a/board/freescale/t1040qds/diu.c
+++ b/board/freescale/t1040qds/diu.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
  */
 
@@ -48,7 +49,7 @@ void diu_set_pixel_clock(unsigned int pixclock)
 
 	/* Program HDMI encoder */
 	/* Switch channel to DIU */
-	select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
+	select_i2c_ch_pca9547(I2C_MUX_CH_DIU, 0);
 
 	/* Set dispaly encoder */
 	ret = diu_set_dvi_encoder(temp);
@@ -58,7 +59,7 @@ void diu_set_pixel_clock(unsigned int pixclock)
 	}
 
 	/* Switch channel to default */
-	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 
 	/* Program pixel clock */
 	out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
index 92dd9237ec..90c5d15ab2 100644
--- a/board/freescale/t1040qds/t1040qds.c
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 #include <common.h>
@@ -79,11 +80,24 @@ int checkboard(void)
 	return 0;
 }
 
-int select_i2c_ch_pca9547(u8 ch)
+int select_i2c_ch_pca9547(u8 ch, int bus_num)
 {
 	int ret;
 
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+
+	ret = dm_i2c_write(dev, 0, &ch, 1);
+#else
 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
 	if (ret) {
 		puts("PCA: failed to select proper channel\n");
 		return ret;
@@ -154,7 +168,7 @@ int board_early_init_r(void)
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
 #endif
-	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 
 	return 0;
 }
diff --git a/board/freescale/t1040qds/t1040qds.h b/board/freescale/t1040qds/t1040qds.h
index d2f0203f17..781bcdefc9 100644
--- a/board/freescale/t1040qds/t1040qds.h
+++ b/board/freescale/t1040qds/t1040qds.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 #ifndef __T1040_QDS_H__
@@ -8,6 +9,6 @@
 
 void fdt_fixup_board_enet(void *blob);
 void pci_of_setup(void *blob, bd_t *bd);
-int select_i2c_ch_pca9547(u8 ch);
+int select_i2c_ch_pca9547(u8 ch, int bus_bum);
 
 #endif
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index aa2a8b00de..f7e6376587 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -1,5 +1,6 @@
 /*
  * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -360,6 +361,8 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 /* I2C */
+
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
 #define CONFIG_SYS_FSL_I2C_SPEED	50000	/* I2C speed in Hz */
@@ -374,6 +377,9 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
 #define CONFIG_SYS_FSL_I2C3_OFFSET	0x119000
 #define CONFIG_SYS_FSL_I2C4_OFFSET	0x119100
+#endif
+
+#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
 
 #define I2C_MUX_PCA_ADDR		0x77
 #define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
@@ -385,6 +391,7 @@ unsigned long get_board_ddr_clk(void);
 /* LDI/DVI Encoder for display */
 #define CONFIG_SYS_I2C_LDI_ADDR         0x38
 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
+#define CONFIG_SYS_I2C_DVI_BUS_NUM	0
 
 /*
  * RTC configuration
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 50b37acf05..1c8fc6c3dd 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 #ifndef __CONFIG_H
@@ -27,6 +28,7 @@
 #define CONFIG_SPL_SKIP_RELOCATE
 #define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#undef CONFIG_DM_I2C
 #endif
 #define RESET_VECTOR_OFFSET		0x27FFC
 #define BOOT_PAGE_OFFSET		0x27000
@@ -459,8 +461,8 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 #endif
 
 /* I2C */
+#ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
 #define CONFIG_SYS_FSL_I2C_SPEED	400000	/* I2C speed in Hz */
 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
 #define CONFIG_SYS_FSL_I2C3_SPEED	400000
@@ -473,7 +475,12 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
 #define CONFIG_SYS_FSL_I2C3_OFFSET	0x119000
 #define CONFIG_SYS_FSL_I2C4_OFFSET	0x119100
+#else
+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
+#define CONFIG_I2C_DEFAULT_BUS_NUMBER	0
+#endif
 
+#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
 /* I2C bus multiplexer */
 #define I2C_MUX_PCA_ADDR                0x70
 #define I2C_MUX_CH_DEFAULT      0x8
@@ -484,6 +491,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 /* LDI/DVI Encoder for display */
 #define CONFIG_SYS_I2C_LDI_ADDR		0x38
 #define CONFIG_SYS_I2C_DVI_ADDR		0x75
+#define CONFIG_SYS_I2C_DVI_BUS_NUM	0
 
 /*
  * RTC configuration
-- 
2.17.1

[PATCH 27/27] configs: T1042D4RDB: enable DM_I2C and DM_RTC

[Biwen Li]

From: Biwen Li <biwen.li@nxp.com>

This enables DM_I2C and DM_RTC in T1042D4RDB defconfigs,
except T1042D4RDB SECURE_BOOT defconfig

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 configs/T1042D4RDB_NAND_defconfig     | 2 ++
 configs/T1042D4RDB_SDCARD_defconfig   | 2 ++
 configs/T1042D4RDB_SPIFLASH_defconfig | 2 ++
 configs/T1042D4RDB_defconfig          | 2 ++
 4 files changed, 8 insertions(+)

diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 05544f04a1..c57369597e 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -80,3 +80,5 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index f8f5998571..571530fecb 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -77,3 +77,5 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index ebb62df96b..beacb58283 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -80,3 +80,5 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 4e66073ef4..9ae110a178 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -65,3 +65,5 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_DM_I2C=y
+CONFIG_DM_RTC=y
-- 
2.17.1

[PATCH 01/27] rtc: ds1337: Add driver model support

[Priyanka Jain]

>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Biwen Li
>Sent: Sunday, April 12, 2020 2:24 PM
>To: Jagdish Gediya <jagdish.gediya@nxp.com>; Priyanka Jain
><priyanka.jain@nxp.com>; hs at denx.de; jagan at amarulasolutions.com;
>aford173 at gmail.com; Alison Wang <alison.wang@nxp.com>;
>jh80.chung at samsung.com; Pramod Kumar <pramod.kumar_1@nxp.com>;
>Rajesh Bhagat <rajesh.bhagat@nxp.com>; Ruchika Gupta
><ruchika.gupta@nxp.com>; olteanv at gmail.com
>Cc: Xiaobo Xie <xiaobo.xie@nxp.com>; Jiafei Pan <jiafei.pan@nxp.com>; u-
>boot at lists.denx.de; Z.q. Hou <zhiqiang.hou@nxp.com>; Biwen Li
><biwen.li@nxp.com>
>Subject: [PATCH 01/27] rtc: ds1337: Add driver model support
>
>From: Biwen Li <biwen.li@nxp.com>
>
>Add support of driver model of ds1337
>
>Signed-off-by: Biwen Li <biwen.li@nxp.com>
>---
> drivers/rtc/ds1337.c | 127
>+++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 127 insertions(+)
>
>diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c index
>9b31048e97..e12d368675 100644
>--- a/drivers/rtc/ds1337.c
>+++ b/drivers/rtc/ds1337.c
>@@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
>  * (C) Copyright 2001-2008
>+ * Copyright 2020 NXP
>  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
>  * Keith Outwater, keith_outwater at mvis.com`
>  */
>@@ -12,6 +13,7 @@
>
> #include <common.h>
> #include <command.h>
>+#include <dm.h>
> #include <rtc.h>
> #include <i2c.h>
>
>@@ -60,6 +62,7 @@
> #define RTC_STAT_BIT_OSF	0x80	/* Oscillator stop flag		*/
>
>
>+#if !CONFIG_IS_ENABLED(DM_RTC)
> static uchar rtc_read (uchar reg);
> static void rtc_write (uchar reg, uchar val);
>
>@@ -188,3 +191,127 @@ static void rtc_write (uchar reg, uchar val)  {
> 	i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);  }
>+#else
>+static uchar rtc_read (struct udevice *dev, uchar reg) {
>+	return (dm_i2c_reg_read (dev, reg));
>+}
>+
>+static void rtc_write (struct udevice *dev, uchar reg, uchar val) {
>+	dm_i2c_reg_write (dev, reg, val);
>+}
>+
>+static int ds1337_rtc_get (struct udevice *dev, struct rtc_time *tmp) {
>+	int rel = 0;
>+	uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
>+
>+	control = rtc_read (dev, RTC_CTL_REG_ADDR);
>+	status = rtc_read (dev, RTC_STAT_REG_ADDR);
>+	sec = rtc_read (dev, RTC_SEC_REG_ADDR);
>+	min = rtc_read (dev, RTC_MIN_REG_ADDR);
>+	hour = rtc_read (dev, RTC_HR_REG_ADDR);
>+	wday = rtc_read (dev, RTC_DAY_REG_ADDR);
>+	mday = rtc_read (dev, RTC_DATE_REG_ADDR);
>+	mon_cent = rtc_read (dev, RTC_MON_REG_ADDR);
>+	year = rtc_read (dev, RTC_YR_REG_ADDR);
>+
>+	/* No century bit, assume year 2000 */ #ifdef CONFIG_RTC_DS1388
>+	mon_cent |= 0x80;
>+#endif
>+
>+	debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x
>"
>+		"hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
>+		year, mon_cent, mday, wday, hour, min, sec, control, status);
>+
>+	if (status & RTC_STAT_BIT_OSF) {
>+		printf ("### Warning: RTC oscillator has stopped\n");
>+		/* clear the OSF flag */
>+		rtc_write (dev, RTC_STAT_REG_ADDR,
>+			   rtc_read (dev, RTC_STAT_REG_ADDR) &
>~RTC_STAT_BIT_OSF);
>+		rel = -1;
>+	}
>+
>+	tmp->tm_sec  = bcd2bin (sec & 0x7F);
>+	tmp->tm_min  = bcd2bin (min & 0x7F);
>+	tmp->tm_hour = bcd2bin (hour & 0x3F);
>+	tmp->tm_mday = bcd2bin (mday & 0x3F);
>+	tmp->tm_mon  = bcd2bin (mon_cent & 0x1F);
>+	tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
>+	tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
>+	tmp->tm_yday = 0;
>+	tmp->tm_isdst= 0;
>+
>+	debug("Get DATE: %4d-%02d-%02d (wday=%d)  TIME:
>%2d:%02d:%02d\n",
>+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp-
>>tm_wday,
>+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
>+
>+	return rel;
>+}
>+
>+static int ds1337_rtc_set (struct udevice *dev, const struct rtc_time
>+*tmp) {
>+	uchar century;
>+
>+	debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME:
>%2d:%02d:%02d\n",
>+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp-
>>tm_wday,
>+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
>+
>+	rtc_write (dev, RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
>+
>+	century = (tmp->tm_year >= 2000) ? 0x80 : 0;
>+	rtc_write (dev, RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) |
>century);
>+
>+	rtc_write (dev, RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
>+	rtc_write (dev, RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
>+	rtc_write (dev, RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
>+	rtc_write (dev, RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
>+	rtc_write (dev, RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
>+
>+	return 0;
>+}
>+
>+#ifdef CONFIG_RTC_DS1337_NOOSC
>+ #define RTC_DS1337_RESET_VAL \
>+	(RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) #else
>#define
>+RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) #endif
>static
>+int ds1337_rtc_reset (struct udevice *dev) { #ifdef CONFIG_RTC_DS1337
>+	rtc_write (dev, RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL); #elif
>defined
>+CONFIG_RTC_DS1388
>+	rtc_write(dev, RTC_CTL_REG_ADDR, 0x0); /* hw default */ #endif
>#ifdef
>+CONFIG_RTC_DS1339_TCR_VAL
>+	rtc_write (dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL);
>#endif
>+#ifdef CONFIG_RTC_DS1388_TCR_VAL
>+	rtc_write(dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL);
>#endif
>+	return 0;
>+}
>+
>+static const struct rtc_ops ds1337_rtc_ops = {
>+	.get = ds1337_rtc_get,
>+	.set = ds1337_rtc_set,
>+	.reset = ds1337_rtc_reset,
>+};
>+
>+static const struct udevice_id ds1337_rtc_ids[] = {
>+	{ .compatible = "ds1337" },
>+	{ .compatible = "ds1338" },
>+	{ .compatible = "ds1338" },
>+	{ }
>+};
>+
>+U_BOOT_DRIVER(rtc_ds1337) = {
>+	.name   = "rtc-ds1337",
>+	.id     = UCLASS_RTC,
>+	.of_match = ds1337_rtc_ids,
>+	.ops    = &ds1337_rtc_ops,
>+};
>+#endif
>--
>2.17.1
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>