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From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Subject: [Intel-gfx] [PATCH 2/9] drm/i915/gt: Fix up clock frequency
Date: Mon, 27 Apr 2020 09:54:01 +0100	[thread overview]
Message-ID: <20200427085408.13879-2-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <20200427085408.13879-1-chris@chris-wilson.co.uk>

The bspec lists both the clock frequency and the effective interval. The
interval corresponds to observed behaviour, so adjust the frequency to
match.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index 852a7d731b3b..999079686846 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -7,9 +7,9 @@
 #include "intel_gt.h"
 #include "intel_gt_clock_utils.h"
 
+#define MHZ_12   12000000 /* 12MHz (24MHz/2), 83.333ns */
+#define MHZ_12_5 12500000 /* 12.5MHz (25MHz/2), 80ns */
 #define MHZ_19_2 19200000 /* 19.2MHz, 52.083ns */
-#define MHZ_24 24000000 /* 24MHz, 83.333ns */
-#define MHZ_25 25000000 /* 25MHz, 80ns */
 
 static u32 read_clock_frequency(const struct intel_gt *gt)
 {
@@ -21,19 +21,19 @@ static u32 read_clock_frequency(const struct intel_gt *gt)
 		config >>= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
 
 		switch (config) {
-		case 0: return MHZ_24;
+		case 0: return MHZ_12;
 		case 1:
 		case 2: return MHZ_19_2;
 		default:
-		case 3: return MHZ_25;
+		case 3: return MHZ_12_5;
 		}
 	} else if (INTEL_GEN(gt->i915) >= 9) {
 		if (IS_GEN9_LP(gt->i915))
 			return MHZ_19_2;
 		else
-			return MHZ_24;
+			return MHZ_12;
 	} else {
-		return MHZ_25;
+		return MHZ_12_5;
 	}
 }
 
-- 
2.20.1

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  reply	other threads:[~2020-04-27  8:54 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-27  8:54 [Intel-gfx] [PATCH 1/9] drm/i915/gt: Sanitize GT first Chris Wilson
2020-04-27  8:54 ` Chris Wilson [this message]
2020-04-27 19:52   ` [Intel-gfx] [PATCH 2/9] drm/i915/gt: Fix up clock frequency Andi Shyti
2020-04-27 20:03     ` Chris Wilson
2020-04-27  8:54 ` [Intel-gfx] [PATCH 3/9] drm/i915/execlists: Check preempt-timeout target before submit_ports Chris Wilson
2020-04-27  8:54 ` [Intel-gfx] [PATCH 4/9] drm/i915/gt: Always enable busy-stats for execlists Chris Wilson
2020-04-27  8:54 ` [Intel-gfx] [PATCH 5/9] drm/i915/gt: Move rps.enabled/active to flags Chris Wilson
2020-04-27 19:53   ` Andi Shyti
2020-04-27  8:54 ` [Intel-gfx] [PATCH 6/9] drm/i915/gt: Track use of RPS interrupts in flags Chris Wilson
2020-04-27  8:54 ` [Intel-gfx] [PATCH 7/9] drm/i915/gt: Switch to manual evaluation of RPS Chris Wilson
2020-04-27 16:39   ` Andi Shyti
2020-04-27  8:54 ` [Intel-gfx] [PATCH 8/9] drm/i915/gt: Apply the aggressive downclocking to parking Chris Wilson
2020-04-27 20:38   ` Andi Shyti
2020-04-27  8:54 ` [Intel-gfx] [PATCH 9/9] drm/i915/gt: Restore aggressive post-boost downclocking Chris Wilson
2020-04-27 12:40   ` Chris Wilson
2020-04-27 17:06     ` Chris Wilson
2020-04-27 20:42       ` Andi Shyti
2020-04-27  9:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/9] drm/i915/gt: Sanitize GT first Patchwork
2020-04-27  9:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-04-27 10:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-27 11:10 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-04-27 19:51 ` [Intel-gfx] [PATCH 1/9] " Andi Shyti

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