* [PATCH 1/3] drm/amdgpu: disable MGCG/MGLS also on gfx CG ungate
@ 2020-04-30 6:43 Evan Quan
2020-04-30 6:43 ` [PATCH 2/3] drm/amdgpu: drop unnecessary cancel_delayed_work_sync on PG ungate Evan Quan
2020-04-30 6:43 ` [PATCH 3/3] drm/amd/powerplay: perform PG ungate prior to CG ungate Evan Quan
0 siblings, 2 replies; 4+ messages in thread
From: Evan Quan @ 2020-04-30 6:43 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Evan Quan
Otherwise, MGCG/MGLS will be left enabled.
Change-Id: I620c5a58b814ae4a0f6005bbc467d7cc2b6d0d66
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index f059c1c546ec..5519f31b2c00 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7027,7 +7027,7 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
/* === CGCG /CGLS for GFX 3D Only === */
gfx_v10_0_update_3d_clock_gating(adev, enable);
/* === MGCG + MGLS === */
- /* gfx_v10_0_update_medium_grain_clock_gating(adev, enable); */
+ gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
}
if (adev->cg_flags &
--
2.26.2
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/3] drm/amdgpu: drop unnecessary cancel_delayed_work_sync on PG ungate
2020-04-30 6:43 [PATCH 1/3] drm/amdgpu: disable MGCG/MGLS also on gfx CG ungate Evan Quan
@ 2020-04-30 6:43 ` Evan Quan
2020-04-30 6:43 ` [PATCH 3/3] drm/amd/powerplay: perform PG ungate prior to CG ungate Evan Quan
1 sibling, 0 replies; 4+ messages in thread
From: Evan Quan @ 2020-04-30 6:43 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Evan Quan
As this is already properly handled in amdgpu_gfx_off_ctrl(). In fact,
this unnecessary cancel_delayed_work_sync may leave a small time window
for race condition and is dangerous.
Change-Id: I601b7b86850db3ed4f4990fd796de663401451ca
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +-----
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 +++---------
2 files changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 5519f31b2c00..53c47353c7ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7108,11 +7108,7 @@ static int gfx_v10_0_set_powergating_state(void *handle,
case CHIP_NAVI10:
case CHIP_NAVI12:
case CHIP_NAVI14:
- if (!enable) {
- amdgpu_gfx_off_ctrl(adev, false);
- cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
- } else
- amdgpu_gfx_off_ctrl(adev, true);
+ amdgpu_gfx_off_ctrl(adev, enable);
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index d89359485997..384ebabf8605 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -5031,10 +5031,9 @@ static int gfx_v9_0_set_powergating_state(void *handle,
switch (adev->asic_type) {
case CHIP_RAVEN:
case CHIP_RENOIR:
- if (!enable) {
+ if (!enable)
amdgpu_gfx_off_ctrl(adev, false);
- cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
- }
+
if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
@@ -5058,12 +5057,7 @@ static int gfx_v9_0_set_powergating_state(void *handle,
amdgpu_gfx_off_ctrl(adev, true);
break;
case CHIP_VEGA12:
- if (!enable) {
- amdgpu_gfx_off_ctrl(adev, false);
- cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
- } else {
- amdgpu_gfx_off_ctrl(adev, true);
- }
+ amdgpu_gfx_off_ctrl(adev, enable);
break;
default:
break;
--
2.26.2
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 3/3] drm/amd/powerplay: perform PG ungate prior to CG ungate
2020-04-30 6:43 [PATCH 1/3] drm/amdgpu: disable MGCG/MGLS also on gfx CG ungate Evan Quan
2020-04-30 6:43 ` [PATCH 2/3] drm/amdgpu: drop unnecessary cancel_delayed_work_sync on PG ungate Evan Quan
@ 2020-04-30 6:43 ` Evan Quan
2020-04-30 13:24 ` Alex Deucher
1 sibling, 1 reply; 4+ messages in thread
From: Evan Quan @ 2020-04-30 6:43 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Evan Quan
Since gfxoff should be disabled first before trying to access those
GC registers.
Change-Id: I5bf0fbe01fa05c89bbb392ef40e11c07edfee039
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 6 +++---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index fdff3e1c5e95..96c91bb70df5 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -322,12 +322,12 @@ static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr,
if (*level & profile_mode_mask) {
hwmgr->saved_dpm_level = hwmgr->dpm_level;
hwmgr->en_umd_pstate = true;
- amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
- AMD_IP_BLOCK_TYPE_GFX,
- AMD_CG_STATE_UNGATE);
amdgpu_device_ip_set_powergating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_GFX,
AMD_PG_STATE_UNGATE);
+ amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
+ AMD_IP_BLOCK_TYPE_GFX,
+ AMD_CG_STATE_UNGATE);
}
} else {
/* exit umd pstate, restore level, enable gfx cg*/
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 12810fd81d5d..e6252bcaa641 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1780,12 +1780,12 @@ static int smu_enable_umd_pstate(void *handle,
if (*level & profile_mode_mask) {
smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
smu_dpm_ctx->enable_umd_pstate = true;
- amdgpu_device_ip_set_clockgating_state(smu->adev,
- AMD_IP_BLOCK_TYPE_GFX,
- AMD_CG_STATE_UNGATE);
amdgpu_device_ip_set_powergating_state(smu->adev,
AMD_IP_BLOCK_TYPE_GFX,
AMD_PG_STATE_UNGATE);
+ amdgpu_device_ip_set_clockgating_state(smu->adev,
+ AMD_IP_BLOCK_TYPE_GFX,
+ AMD_CG_STATE_UNGATE);
}
} else {
/* exit umd pstate, restore level, enable gfx cg*/
--
2.26.2
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 3/3] drm/amd/powerplay: perform PG ungate prior to CG ungate
2020-04-30 6:43 ` [PATCH 3/3] drm/amd/powerplay: perform PG ungate prior to CG ungate Evan Quan
@ 2020-04-30 13:24 ` Alex Deucher
0 siblings, 0 replies; 4+ messages in thread
From: Alex Deucher @ 2020-04-30 13:24 UTC (permalink / raw)
To: Evan Quan; +Cc: Deucher, Alexander, amd-gfx list
On Thu, Apr 30, 2020 at 2:44 AM Evan Quan <evan.quan@amd.com> wrote:
>
> Since gfxoff should be disabled first before trying to access those
> GC registers.
>
> Change-Id: I5bf0fbe01fa05c89bbb392ef40e11c07edfee039
> Signed-off-by: Evan Quan <evan.quan@amd.com>
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 6 +++---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 6 +++---
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index fdff3e1c5e95..96c91bb70df5 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -322,12 +322,12 @@ static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr,
> if (*level & profile_mode_mask) {
> hwmgr->saved_dpm_level = hwmgr->dpm_level;
> hwmgr->en_umd_pstate = true;
> - amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> - AMD_IP_BLOCK_TYPE_GFX,
> - AMD_CG_STATE_UNGATE);
> amdgpu_device_ip_set_powergating_state(hwmgr->adev,
> AMD_IP_BLOCK_TYPE_GFX,
> AMD_PG_STATE_UNGATE);
> + amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
> + AMD_IP_BLOCK_TYPE_GFX,
> + AMD_CG_STATE_UNGATE);
> }
> } else {
> /* exit umd pstate, restore level, enable gfx cg*/
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 12810fd81d5d..e6252bcaa641 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1780,12 +1780,12 @@ static int smu_enable_umd_pstate(void *handle,
> if (*level & profile_mode_mask) {
> smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
> smu_dpm_ctx->enable_umd_pstate = true;
> - amdgpu_device_ip_set_clockgating_state(smu->adev,
> - AMD_IP_BLOCK_TYPE_GFX,
> - AMD_CG_STATE_UNGATE);
> amdgpu_device_ip_set_powergating_state(smu->adev,
> AMD_IP_BLOCK_TYPE_GFX,
> AMD_PG_STATE_UNGATE);
> + amdgpu_device_ip_set_clockgating_state(smu->adev,
> + AMD_IP_BLOCK_TYPE_GFX,
> + AMD_CG_STATE_UNGATE);
> }
> } else {
> /* exit umd pstate, restore level, enable gfx cg*/
> --
> 2.26.2
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-04-30 13:24 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2020-04-30 6:43 [PATCH 1/3] drm/amdgpu: disable MGCG/MGLS also on gfx CG ungate Evan Quan
2020-04-30 6:43 ` [PATCH 2/3] drm/amdgpu: drop unnecessary cancel_delayed_work_sync on PG ungate Evan Quan
2020-04-30 6:43 ` [PATCH 3/3] drm/amd/powerplay: perform PG ungate prior to CG ungate Evan Quan
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