From: Bjorn Helgaas <helgaas@kernel.org> To: Jim Quinlan <james.quinlan@broadcom.com> Cc: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Rob Herring <robh@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>, Florian Fainelli <f.fainelli@gmail.com>, "maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE" <bcm-kernel-feedback-list@broadcom.com>, "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" <linux-rpi-kernel@lists.infradead.org>, "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" <linux-arm-kernel@lists.infradead.org>, "open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS" <linux-pci@vger.kernel.org>, open list <linux-kernel@vger.kernel.org> Subject: Re: [PATCH 3/5] PCI: brcmstb: enable CRS Date: Thu, 30 Apr 2020 15:32:52 -0500 [thread overview] Message-ID: <20200430203252.GA62266@bjorn-Precision-5520> (raw) In-Reply-To: <20200430185522.4116-3-james.quinlan@broadcom.com> On Thu, Apr 30, 2020 at 02:55:20PM -0400, Jim Quinlan wrote: > From: Jim Quinlan <jquinlan@broadcom.com> > > Configuration Retry Request Status is off by default on this > PCIe controller. Turn it on. Are you talking about CRS itself, i.e., the ability of a Root Port to deal with Completions with Configuration Retry Request Status? That really shouldn't be switchable in the hardware since it's a required feature for all PCIe devices. Or are you talking about CRS Software Visibility, which is controlled by a bit in the PCIe Root Control register? That *should* be managed by the PCI core in pci_enable_crs(). Does that generic method of controlling it not work for this device? It looks like maybe the latter, since the generic: #define PCI_EXP_RTCTL_CRSSVE 0x0010 matches your new PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_MASK. If pci_enable_crs() doesn't work on this device, it sounds like a hardware defect that we need to work around, but I'm not sure that just enabling it unconditionally here is the right thing. > Signed-off-by: Jim Quinlan <jquinlan@broadcom.com> > --- > drivers/pci/controller/pcie-brcmstb.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > index 5b0dec5971b8..2bc913c0262c 100644 > --- a/drivers/pci/controller/pcie-brcmstb.c > +++ b/drivers/pci/controller/pcie-brcmstb.c > @@ -34,6 +34,9 @@ > #define BRCM_PCIE_CAP_REGS 0x00ac > > /* Broadcom STB PCIe Register Offsets */ > +#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL 0x00c8 > +#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_MASK 0x10 > + > #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188 > #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc > #define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0 > @@ -827,6 +830,12 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) > pci_speed_string(pcie_link_speed[cls]), nlw, > ssc_good ? "(SSC)" : "(!SSC)"); > > + /* Enable configuration request retry (CRS) */ > + tmp = readl(base + PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL); > + u32p_replace_bits(&tmp, 1, > + PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_MASK); > + writel(tmp, base + PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL); > + > /* PCIe->SCB endian mode for BAR */ > tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); > u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN, > -- > 2.17.1 >
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Helgaas <helgaas@kernel.org> To: Jim Quinlan <james.quinlan@broadcom.com> Cc: "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" <linux-arm-kernel@lists.infradead.org>, Rob Herring <robh@kernel.org>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, "open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS" <linux-pci@vger.kernel.org>, open list <linux-kernel@vger.kernel.org>, Florian Fainelli <f.fainelli@gmail.com>, "maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE" <bcm-kernel-feedback-list@broadcom.com>, "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" <linux-rpi-kernel@lists.infradead.org>, Bjorn Helgaas <bhelgaas@google.com>, Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Subject: Re: [PATCH 3/5] PCI: brcmstb: enable CRS Date: Thu, 30 Apr 2020 15:32:52 -0500 [thread overview] Message-ID: <20200430203252.GA62266@bjorn-Precision-5520> (raw) In-Reply-To: <20200430185522.4116-3-james.quinlan@broadcom.com> On Thu, Apr 30, 2020 at 02:55:20PM -0400, Jim Quinlan wrote: > From: Jim Quinlan <jquinlan@broadcom.com> > > Configuration Retry Request Status is off by default on this > PCIe controller. Turn it on. Are you talking about CRS itself, i.e., the ability of a Root Port to deal with Completions with Configuration Retry Request Status? That really shouldn't be switchable in the hardware since it's a required feature for all PCIe devices. Or are you talking about CRS Software Visibility, which is controlled by a bit in the PCIe Root Control register? That *should* be managed by the PCI core in pci_enable_crs(). Does that generic method of controlling it not work for this device? It looks like maybe the latter, since the generic: #define PCI_EXP_RTCTL_CRSSVE 0x0010 matches your new PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_MASK. If pci_enable_crs() doesn't work on this device, it sounds like a hardware defect that we need to work around, but I'm not sure that just enabling it unconditionally here is the right thing. > Signed-off-by: Jim Quinlan <jquinlan@broadcom.com> > --- > drivers/pci/controller/pcie-brcmstb.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > index 5b0dec5971b8..2bc913c0262c 100644 > --- a/drivers/pci/controller/pcie-brcmstb.c > +++ b/drivers/pci/controller/pcie-brcmstb.c > @@ -34,6 +34,9 @@ > #define BRCM_PCIE_CAP_REGS 0x00ac > > /* Broadcom STB PCIe Register Offsets */ > +#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL 0x00c8 > +#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_MASK 0x10 > + > #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188 > #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc > #define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0 > @@ -827,6 +830,12 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) > pci_speed_string(pcie_link_speed[cls]), nlw, > ssc_good ? "(SSC)" : "(!SSC)"); > > + /* Enable configuration request retry (CRS) */ > + tmp = readl(base + PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL); > + u32p_replace_bits(&tmp, 1, > + PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_MASK); > + writel(tmp, base + PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL); > + > /* PCIe->SCB endian mode for BAR */ > tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); > u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN, > -- > 2.17.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-04-30 20:32 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-04-30 18:55 [PATCH 1/5] PCI: brcmstb: don't clk_put() a managed clock Jim Quinlan 2020-04-30 18:55 ` Jim Quinlan 2020-04-30 18:55 ` [PATCH 2/5] PCI: brcmstb: fix window register offset from 4 to 8 Jim Quinlan 2020-04-30 18:55 ` Jim Quinlan 2020-04-30 19:07 ` Florian Fainelli 2020-04-30 19:07 ` Florian Fainelli 2020-04-30 20:43 ` Bjorn Helgaas 2020-04-30 20:43 ` Bjorn Helgaas 2020-04-30 18:55 ` [PATCH 3/5] PCI: brcmstb: enable CRS Jim Quinlan 2020-04-30 18:55 ` Jim Quinlan 2020-04-30 19:19 ` Florian Fainelli 2020-04-30 19:19 ` Florian Fainelli 2020-04-30 20:32 ` Bjorn Helgaas [this message] 2020-04-30 20:32 ` Bjorn Helgaas 2020-04-30 21:00 ` Jim Quinlan 2020-04-30 21:00 ` Jim Quinlan 2020-04-30 18:55 ` [PATCH 4/5] dt-bindings: PCI: brcmstb: New prop 'brcm,aspm-en-l0s' Jim Quinlan 2020-04-30 18:55 ` Jim Quinlan 2020-04-30 19:20 ` Florian Fainelli 2020-04-30 19:20 ` Florian Fainelli 2020-04-30 18:55 ` [PATCH 5/5] PCI: brcmstb: disable L0s component of ASPM by default Jim Quinlan 2020-04-30 18:55 ` Jim Quinlan 2020-04-30 19:21 ` Florian Fainelli 2020-04-30 19:21 ` Florian Fainelli 2020-04-30 20:40 ` Bjorn Helgaas 2020-04-30 20:40 ` Bjorn Helgaas 2020-04-30 21:17 ` Jim Quinlan 2020-04-30 21:17 ` Jim Quinlan 2020-04-30 19:05 ` [PATCH 1/5] PCI: brcmstb: don't clk_put() a managed clock Florian Fainelli 2020-04-30 19:05 ` Florian Fainelli
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