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From: Florian Fainelli <f.fainelli@gmail.com>
To: Jim Quinlan <james.quinlan@broadcom.com>
Cc: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Rob Herring <robh@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	"maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE" 
	<bcm-kernel-feedback-list@broadcom.com>,
	"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" 
	<linux-rpi-kernel@lists.infradead.org>,
	"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" 
	<linux-arm-kernel@lists.infradead.org>,
	"open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS" 
	<linux-pci@vger.kernel.org>,
	open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 5/5] PCI: brcmstb: disable L0s component of ASPM by default
Date: Thu, 30 Apr 2020 12:21:06 -0700	[thread overview]
Message-ID: <76b5ed9c-c67b-d565-d0c0-6f2e645657ed@gmail.com> (raw)
In-Reply-To: <20200430185522.4116-5-james.quinlan@broadcom.com>

On 4/30/20 11:55 AM, Jim Quinlan wrote:
> From: Jim Quinlan <jquinlan@broadcom.com>
> 
> Some informal internal experiments has shown that the BrcmSTB ASPM L0s
> savings may introduce an undesirable noise signal on some customers'
> boards.  In addition, L0s was found lacking in realized power savings,
> especially relative to the L1 ASPM component.  This is BrcmSTB's
> experience and may not hold for others.  At any rate, we disable L0s
> savings by default unless the DT node has the 'brcm,aspm-en-l0s'
> property.
> 
> Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>

Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

WARNING: multiple messages have this Message-ID (diff)
From: Florian Fainelli <f.fainelli@gmail.com>
To: Jim Quinlan <james.quinlan@broadcom.com>
Cc: "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
	<linux-arm-kernel@lists.infradead.org>,
	Rob Herring <robh@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	"open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS"
	<linux-pci@vger.kernel.org>,
	open list <linux-kernel@vger.kernel.org>,
	"maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE"
	<bcm-kernel-feedback-list@broadcom.com>,
	"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
	<linux-rpi-kernel@lists.infradead.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Subject: Re: [PATCH 5/5] PCI: brcmstb: disable L0s component of ASPM by default
Date: Thu, 30 Apr 2020 12:21:06 -0700	[thread overview]
Message-ID: <76b5ed9c-c67b-d565-d0c0-6f2e645657ed@gmail.com> (raw)
In-Reply-To: <20200430185522.4116-5-james.quinlan@broadcom.com>

On 4/30/20 11:55 AM, Jim Quinlan wrote:
> From: Jim Quinlan <jquinlan@broadcom.com>
> 
> Some informal internal experiments has shown that the BrcmSTB ASPM L0s
> savings may introduce an undesirable noise signal on some customers'
> boards.  In addition, L0s was found lacking in realized power savings,
> especially relative to the L1 ASPM component.  This is BrcmSTB's
> experience and may not hold for others.  At any rate, we disable L0s
> savings by default unless the DT node has the 'brcm,aspm-en-l0s'
> property.
> 
> Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>

Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2020-04-30 19:21 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-30 18:55 [PATCH 1/5] PCI: brcmstb: don't clk_put() a managed clock Jim Quinlan
2020-04-30 18:55 ` Jim Quinlan
2020-04-30 18:55 ` [PATCH 2/5] PCI: brcmstb: fix window register offset from 4 to 8 Jim Quinlan
2020-04-30 18:55   ` Jim Quinlan
2020-04-30 19:07   ` Florian Fainelli
2020-04-30 19:07     ` Florian Fainelli
2020-04-30 20:43   ` Bjorn Helgaas
2020-04-30 20:43     ` Bjorn Helgaas
2020-04-30 18:55 ` [PATCH 3/5] PCI: brcmstb: enable CRS Jim Quinlan
2020-04-30 18:55   ` Jim Quinlan
2020-04-30 19:19   ` Florian Fainelli
2020-04-30 19:19     ` Florian Fainelli
2020-04-30 20:32   ` Bjorn Helgaas
2020-04-30 20:32     ` Bjorn Helgaas
2020-04-30 21:00     ` Jim Quinlan
2020-04-30 21:00       ` Jim Quinlan
2020-04-30 18:55 ` [PATCH 4/5] dt-bindings: PCI: brcmstb: New prop 'brcm,aspm-en-l0s' Jim Quinlan
2020-04-30 18:55   ` Jim Quinlan
2020-04-30 19:20   ` Florian Fainelli
2020-04-30 19:20     ` Florian Fainelli
2020-04-30 18:55 ` [PATCH 5/5] PCI: brcmstb: disable L0s component of ASPM by default Jim Quinlan
2020-04-30 18:55   ` Jim Quinlan
2020-04-30 19:21   ` Florian Fainelli [this message]
2020-04-30 19:21     ` Florian Fainelli
2020-04-30 20:40   ` Bjorn Helgaas
2020-04-30 20:40     ` Bjorn Helgaas
2020-04-30 21:17     ` Jim Quinlan
2020-04-30 21:17       ` Jim Quinlan
2020-04-30 19:05 ` [PATCH 1/5] PCI: brcmstb: don't clk_put() a managed clock Florian Fainelli
2020-04-30 19:05   ` Florian Fainelli

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