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From: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
To: Kever Yang <kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
	Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
	Philipp Tomsich
	<philipp.tomsich-SN7IsUiht6C/RdPyistoZJqQE7yCjDx5@public.gmane.org>,
	Tom Rini <trini-OWPKS81ov/FWk0Htik3J/w@public.gmane.org>,
	Frank Wang <frank.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
	William Wu <william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
	Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
	Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>,
	Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
Cc: u-boot-0aAXYlwwYIKGBzrmiIFOJg@public.gmane.org,
	linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org,
	Jagan Teki
	<jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: [RFC 5/7] arm64: dts: rk3399: Move pcie_phy into root port
Date: Fri,  1 May 2020 03:15:27 +0530	[thread overview]
Message-ID: <20200430214529.18887-6-jagan@amarulasolutions.com> (raw)
In-Reply-To: <20200430214529.18887-1-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>

Yes, This is changing the actual device tree pcie_phy
structure but the problem with the current Generic PHY
subsystem is unable to find PHY if the PHY node is not
part of the root structure and also PHY parent is
non-PHY type.

This will be reverted once we support the PHY subsystem
to get the PHY whose parent has non-PHY type or any other
relevant solution.   

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 arch/arm/dts/rk3399.dtsi | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 6c77f25f23..dea76032bf 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -1395,17 +1395,17 @@
 			#phy-cells = <0>;
 			status = "disabled";
 		};
+	};
 
-		pcie_phy: pcie-phy {
-			compatible = "rockchip,rk3399-pcie-phy";
-			clocks = <&cru SCLK_PCIEPHY_REF>;
-			clock-names = "refclk";
-			#phy-cells = <1>;
-			resets = <&cru SRST_PCIEPHY>;
-			drive-impedance-ohm = <50>;
-			reset-names = "phy";
-			status = "disabled";
-		};
+	pcie_phy: pcie-phy {
+		compatible = "rockchip,rk3399-pcie-phy";
+		clocks = <&cru SCLK_PCIEPHY_REF>;
+		clock-names = "refclk";
+		#phy-cells = <1>;
+		resets = <&cru SRST_PCIEPHY>;
+		drive-impedance-ohm = <50>;
+		reset-names = "phy";
+		status = "disabled";
 	};
 
 	u2phy0: usb2-phy@e450 {
-- 
2.17.1


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WARNING: multiple messages have this Message-ID (diff)
From: Jagan Teki <jagan@amarulasolutions.com>
To: u-boot@lists.denx.de
Subject: [RFC 5/7] arm64: dts: rk3399: Move pcie_phy into root port
Date: Fri,  1 May 2020 03:15:27 +0530	[thread overview]
Message-ID: <20200430214529.18887-6-jagan@amarulasolutions.com> (raw)
In-Reply-To: <20200430214529.18887-1-jagan@amarulasolutions.com>

Yes, This is changing the actual device tree pcie_phy
structure but the problem with the current Generic PHY
subsystem is unable to find PHY if the PHY node is not
part of the root structure and also PHY parent is
non-PHY type.

This will be reverted once we support the PHY subsystem
to get the PHY whose parent has non-PHY type or any other
relevant solution.? ?

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 arch/arm/dts/rk3399.dtsi | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 6c77f25f23..dea76032bf 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -1395,17 +1395,17 @@
 			#phy-cells = <0>;
 			status = "disabled";
 		};
+	};
 
-		pcie_phy: pcie-phy {
-			compatible = "rockchip,rk3399-pcie-phy";
-			clocks = <&cru SCLK_PCIEPHY_REF>;
-			clock-names = "refclk";
-			#phy-cells = <1>;
-			resets = <&cru SRST_PCIEPHY>;
-			drive-impedance-ohm = <50>;
-			reset-names = "phy";
-			status = "disabled";
-		};
+	pcie_phy: pcie-phy {
+		compatible = "rockchip,rk3399-pcie-phy";
+		clocks = <&cru SCLK_PCIEPHY_REF>;
+		clock-names = "refclk";
+		#phy-cells = <1>;
+		resets = <&cru SRST_PCIEPHY>;
+		drive-impedance-ohm = <50>;
+		reset-names = "phy";
+		status = "disabled";
 	};
 
 	u2phy0: usb2-phy at e450 {
-- 
2.17.1

  parent reply	other threads:[~2020-04-30 21:45 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-30 21:45 [RFC 0/7] rockchip: Add PHY drivers Jagan Teki
2020-04-30 21:45 ` Jagan Teki
     [not found] ` <20200430214529.18887-1-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
2020-04-30 21:45   ` [RFC 1/7] phy: Add Rockchip PCIe PHY driver Jagan Teki
2020-04-30 21:45     ` Jagan Teki
2020-04-30 21:45   ` [RFC 2/7] clk: rk3399: Enable/Disable the USB2PHY clk Jagan Teki
2020-04-30 21:45     ` Jagan Teki
2020-04-30 21:45   ` [RFC 3/7] phy: rockchip: Add Rockchip USB2PHY driver Jagan Teki
2020-04-30 21:45     ` Jagan Teki
2020-04-30 21:45   ` [RFC 4/7] arm64: dts: rk3399: Move u2phy into root port Jagan Teki
2020-04-30 21:45     ` Jagan Teki
2020-04-30 21:45   ` Jagan Teki [this message]
2020-04-30 21:45     ` [RFC 5/7] arm64: dts: rk3399: Move pcie_phy " Jagan Teki
2020-04-30 21:45   ` [RFC 6/7] pci: rockchip: Switch to generic-phy Jagan Teki
2020-04-30 21:45     ` Jagan Teki
2020-04-30 21:45   ` [RFC 7/7] pci: rockchip: Drop legacy PHY driver Jagan Teki
2020-04-30 21:45     ` Jagan Teki

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