* [RFC 1/7] phy: Add Rockchip PCIe PHY driver
2020-04-30 21:45 ` Jagan Teki
@ 2020-04-30 21:45 ` Jagan Teki
-1 siblings, 0 replies; 16+ messages in thread
From: Jagan Teki @ 2020-04-30 21:45 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Frank Wang,
William Wu, Shawn Lin, Heiko Stuebner, Patrice Chotard
Cc: u-boot-0aAXYlwwYIKGBzrmiIFOJg,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Add the Rockchip PCIe PHY driver as part of
Generic PHY framework.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/phy/rockchip/Kconfig | 9 +
drivers/phy/rockchip/Makefile | 6 +
drivers/phy/rockchip/phy-rockchip-pcie.c | 271 +++++++++++++++++++++++
5 files changed, 289 insertions(+)
create mode 100644 drivers/phy/rockchip/Kconfig
create mode 100644 drivers/phy/rockchip/Makefile
create mode 100644 drivers/phy/rockchip/phy-rockchip-pcie.c
diff --git a/drivers/Kconfig b/drivers/Kconfig
index e34a22708c..2fe23f953c 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -76,6 +76,8 @@ source "drivers/phy/allwinner/Kconfig"
source "drivers/phy/marvell/Kconfig"
+source "drivers/phy/rockchip/Kconfig"
+
source "drivers/pinctrl/Kconfig"
source "drivers/power/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 4208750428..94e8c5da17 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -91,6 +91,7 @@ obj-y += dfu/
obj-$(CONFIG_PCH) += pch/
obj-y += phy/allwinner/
obj-y += phy/marvell/
+obj-y += phy/rockchip/
obj-y += rtc/
obj-y += scsi/
obj-y += sound/
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
new file mode 100644
index 0000000000..477c68920b
--- /dev/null
+++ b/drivers/phy/rockchip/Kconfig
@@ -0,0 +1,9 @@
+#
+# Phy drivers for Rockchip platforms
+#
+config PHY_ROCKCHIP_PCIE
+ bool "Rockchip PCIe PHY Driver"
+ depends on ARCH_ROCKCHIP
+ select PHY
+ help
+ Enable this to support the Rockchip PCIe PHY.
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
new file mode 100644
index 0000000000..4d19ccdfd0
--- /dev/null
+++ b/drivers/phy/rockchip/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Amarula Solutions(India)
+#
+
+obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c
new file mode 100644
index 0000000000..83928cffe0
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: (GPL-2.0-only)
+/*
+ * Rockchip PCIe PHY driver
+ *
+ * Copyright (C) 2020 Amarula Solutions(India)
+ * Copyright (C) 2016 Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
+ * Copyright (C) 2016 ROCKCHIP, Inc.
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <generic-phy.h>
+#include <reset.h>
+#include <syscon.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <linux/iopoll.h>
+#include <asm/arch-rockchip/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The higher 16-bit of this register is used for write protection
+ * only if BIT(x + 16) set to 1 the BIT(x) can be written.
+ */
+#define HIWORD_UPDATE(val, mask, shift) \
+ ((val) << (shift) | (mask) << ((shift) + 16))
+
+#define PHY_MAX_LANE_NUM 4
+#define PHY_CFG_DATA_SHIFT 7
+#define PHY_CFG_ADDR_SHIFT 1
+#define PHY_CFG_DATA_MASK 0xf
+#define PHY_CFG_ADDR_MASK 0x3f
+#define PHY_CFG_RD_MASK 0x3ff
+#define PHY_CFG_WR_ENABLE 1
+#define PHY_CFG_WR_DISABLE 1
+#define PHY_CFG_WR_SHIFT 0
+#define PHY_CFG_WR_MASK 1
+#define PHY_CFG_PLL_LOCK 0x10
+#define PHY_CFG_CLK_TEST 0x10
+#define PHY_CFG_CLK_SCC 0x12
+#define PHY_CFG_SEPE_RATE BIT(3)
+#define PHY_CFG_PLL_100M BIT(3)
+#define PHY_PLL_LOCKED BIT(9)
+#define PHY_PLL_OUTPUT BIT(10)
+#define PHY_LANE_RX_DET_SHIFT 11
+#define PHY_LANE_RX_DET_TH 0x1
+#define PHY_LANE_IDLE_OFF 0x1
+#define PHY_LANE_IDLE_MASK 0x1
+#define PHY_LANE_IDLE_A_SHIFT 3
+#define PHY_LANE_IDLE_B_SHIFT 4
+#define PHY_LANE_IDLE_C_SHIFT 5
+#define PHY_LANE_IDLE_D_SHIFT 6
+
+struct rockchip_pcie_phy_data {
+ unsigned int pcie_conf;
+ unsigned int pcie_status;
+ unsigned int pcie_laneoff;
+};
+
+struct rockchip_pcie_phy {
+ void *reg_base;
+ struct clk refclk;
+ struct reset_ctl phy_rst;
+ const struct rockchip_pcie_phy_data *data;
+};
+
+static void phy_wr_cfg(struct rockchip_pcie_phy *priv, u32 addr, u32 data)
+{
+ u32 reg;
+
+ reg = HIWORD_UPDATE(data, PHY_CFG_DATA_MASK, PHY_CFG_DATA_SHIFT);
+ reg |= HIWORD_UPDATE(addr, PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT);
+ writel(reg, priv->reg_base + priv->data->pcie_conf);
+
+ udelay(1);
+
+ reg = HIWORD_UPDATE(PHY_CFG_WR_ENABLE,
+ PHY_CFG_WR_MASK,
+ PHY_CFG_WR_SHIFT);
+ writel(reg, priv->reg_base + priv->data->pcie_conf);
+
+ udelay(1);
+
+ reg = HIWORD_UPDATE(PHY_CFG_WR_DISABLE,
+ PHY_CFG_WR_MASK,
+ PHY_CFG_WR_SHIFT);
+ writel(reg, priv->reg_base + priv->data->pcie_conf);
+}
+
+static int rockchip_pcie_phy_power_on(struct phy *phy)
+{
+ struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
+ int ret = 0;
+ u32 reg, status;
+
+ ret = reset_deassert(&priv->phy_rst);
+ if (ret) {
+ dev_err(dev, "failed to assert phy reset\n");
+ return ret;
+ }
+
+ reg = HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
+ PHY_CFG_ADDR_MASK,
+ PHY_CFG_ADDR_SHIFT);
+ writel(reg, priv->reg_base + priv->data->pcie_conf);
+
+ reg = HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
+ PHY_LANE_IDLE_MASK,
+ PHY_LANE_IDLE_A_SHIFT);
+ writel(reg, priv->reg_base + priv->data->pcie_laneoff);
+
+ ret = -EINVAL;
+ ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status,
+ status,
+ status & PHY_PLL_LOCKED,
+ 20 * 1000,
+ 50);
+ if (ret) {
+ dev_err(&priv->dev, "pll lock timeout!\n");
+ goto err_pll_lock;
+ }
+
+ phy_wr_cfg(priv, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
+ phy_wr_cfg(priv, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
+
+ ret = -ETIMEDOUT;
+ ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status,
+ status,
+ !(status & PHY_PLL_OUTPUT),
+ 20 * 1000,
+ 50);
+ if (ret) {
+ dev_err(&priv->dev, "pll output enable timeout!\n");
+ goto err_pll_lock;
+ }
+
+ reg = HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
+ PHY_CFG_ADDR_MASK,
+ PHY_CFG_ADDR_SHIFT);
+ writel(reg, priv->reg_base + priv->data->pcie_conf);
+
+ ret = -EINVAL;
+ ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status,
+ status,
+ status & PHY_PLL_LOCKED,
+ 20 * 1000,
+ 50);
+ if (ret) {
+ dev_err(&priv->dev, "pll relock timeout!\n");
+ goto err_pll_lock;
+ }
+
+ return 0;
+
+err_pll_lock:
+ reset_assert(&priv->phy_rst);
+ return ret;
+}
+
+static int rockchip_pcie_phy_power_off(struct phy *phy)
+{
+ struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
+ int ret;
+ u32 reg;
+
+ reg = HIWORD_UPDATE(PHY_LANE_IDLE_OFF,
+ PHY_LANE_IDLE_MASK,
+ PHY_LANE_IDLE_A_SHIFT);
+ writel(reg, priv->reg_base + priv->data->pcie_laneoff);
+
+ ret = reset_assert(&priv->phy_rst);
+ if (ret) {
+ dev_err(dev, "failed to assert phy reset\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rockchip_pcie_phy_init(struct phy *phy)
+{
+ struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
+ int ret;
+
+ ret = clk_enable(&priv->refclk);
+ if (ret) {
+ dev_err(dev, "failed to enable refclk clock\n");
+ return ret;
+ }
+
+ ret = reset_assert(&priv->phy_rst);
+ if (ret) {
+ dev_err(dev, "failed to assert phy reset\n");
+ goto err_reset;
+ }
+
+ return 0;
+
+err_reset:
+ clk_disable(&priv->refclk);
+ return ret;
+}
+
+static int rockchip_pcie_phy_exit(struct phy *phy)
+{
+ struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
+
+ clk_disable(&priv->refclk);
+
+ return 0;
+}
+
+static struct phy_ops rockchip_pcie_phy_ops = {
+ .init = rockchip_pcie_phy_init,
+ .power_on = rockchip_pcie_phy_power_on,
+ .power_off = rockchip_pcie_phy_power_off,
+ .exit = rockchip_pcie_phy_exit,
+};
+
+static int rockchip_pcie_phy_probe(struct udevice *dev)
+{
+ struct rockchip_pcie_phy *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->data = (const struct rockchip_pcie_phy_data *)
+ dev_get_driver_data(dev);
+ if (!priv->data)
+ return -EINVAL;
+
+ priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ ret = clk_get_by_name(dev, "refclk", &priv->refclk);
+ if (ret) {
+ dev_err(dev, "failed to get refclk clock phandle\n");
+ return ret;
+ }
+
+ ret = reset_get_by_name(dev, "phy", &priv->phy_rst);
+ if (ret) {
+ dev_err(dev, "failed to get phy reset phandle\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct rockchip_pcie_phy_data rk3399_pcie_data = {
+ .pcie_conf = 0xe220,
+ .pcie_status = 0xe2a4,
+ .pcie_laneoff = 0xe214,
+};
+
+static const struct udevice_id rockchip_pcie_phy_ids[] = {
+ {
+ .compatible = "rockchip,rk3399-pcie-phy",
+ .data = (ulong)&rk3399_pcie_data,
+ },
+ { /* sentile */ }
+};
+
+U_BOOT_DRIVER(rockchip_pcie_phy) = {
+ .name = "rockchip_pcie_phy",
+ .id = UCLASS_PHY,
+ .of_match = rockchip_pcie_phy_ids,
+ .ops = &rockchip_pcie_phy_ops,
+ .probe = rockchip_pcie_phy_probe,
+ .priv_auto_alloc_size = sizeof(struct rockchip_pcie_phy),
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [RFC 1/7] phy: Add Rockchip PCIe PHY driver
@ 2020-04-30 21:45 ` Jagan Teki
0 siblings, 0 replies; 16+ messages in thread
From: Jagan Teki @ 2020-04-30 21:45 UTC (permalink / raw)
To: u-boot
Add the Rockchip PCIe PHY driver as part of
Generic PHY framework.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/phy/rockchip/Kconfig | 9 +
drivers/phy/rockchip/Makefile | 6 +
drivers/phy/rockchip/phy-rockchip-pcie.c | 271 +++++++++++++++++++++++
5 files changed, 289 insertions(+)
create mode 100644 drivers/phy/rockchip/Kconfig
create mode 100644 drivers/phy/rockchip/Makefile
create mode 100644 drivers/phy/rockchip/phy-rockchip-pcie.c
diff --git a/drivers/Kconfig b/drivers/Kconfig
index e34a22708c..2fe23f953c 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -76,6 +76,8 @@ source "drivers/phy/allwinner/Kconfig"
source "drivers/phy/marvell/Kconfig"
+source "drivers/phy/rockchip/Kconfig"
+
source "drivers/pinctrl/Kconfig"
source "drivers/power/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 4208750428..94e8c5da17 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -91,6 +91,7 @@ obj-y += dfu/
obj-$(CONFIG_PCH) += pch/
obj-y += phy/allwinner/
obj-y += phy/marvell/
+obj-y += phy/rockchip/
obj-y += rtc/
obj-y += scsi/
obj-y += sound/
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
new file mode 100644
index 0000000000..477c68920b
--- /dev/null
+++ b/drivers/phy/rockchip/Kconfig
@@ -0,0 +1,9 @@
+#
+# Phy drivers for Rockchip platforms
+#
+config PHY_ROCKCHIP_PCIE
+ bool "Rockchip PCIe PHY Driver"
+ depends on ARCH_ROCKCHIP
+ select PHY
+ help
+ Enable this to support the Rockchip PCIe PHY.
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
new file mode 100644
index 0000000000..4d19ccdfd0
--- /dev/null
+++ b/drivers/phy/rockchip/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Amarula Solutions(India)
+#
+
+obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c
new file mode 100644
index 0000000000..83928cffe0
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: (GPL-2.0-only)
+/*
+ * Rockchip PCIe PHY driver
+ *
+ * Copyright (C) 2020 Amarula Solutions(India)
+ * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
+ * Copyright (C) 2016 ROCKCHIP, Inc.
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <generic-phy.h>
+#include <reset.h>
+#include <syscon.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <linux/iopoll.h>
+#include <asm/arch-rockchip/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The higher 16-bit of this register is used for write protection
+ * only if BIT(x + 16) set to 1 the BIT(x) can be written.
+ */
+#define HIWORD_UPDATE(val, mask, shift) \
+ ((val) << (shift) | (mask) << ((shift) + 16))
+
+#define PHY_MAX_LANE_NUM 4
+#define PHY_CFG_DATA_SHIFT 7
+#define PHY_CFG_ADDR_SHIFT 1
+#define PHY_CFG_DATA_MASK 0xf
+#define PHY_CFG_ADDR_MASK 0x3f
+#define PHY_CFG_RD_MASK 0x3ff
+#define PHY_CFG_WR_ENABLE 1
+#define PHY_CFG_WR_DISABLE 1
+#define PHY_CFG_WR_SHIFT 0
+#define PHY_CFG_WR_MASK 1
+#define PHY_CFG_PLL_LOCK 0x10
+#define PHY_CFG_CLK_TEST 0x10
+#define PHY_CFG_CLK_SCC 0x12
+#define PHY_CFG_SEPE_RATE BIT(3)
+#define PHY_CFG_PLL_100M BIT(3)
+#define PHY_PLL_LOCKED BIT(9)
+#define PHY_PLL_OUTPUT BIT(10)
+#define PHY_LANE_RX_DET_SHIFT 11
+#define PHY_LANE_RX_DET_TH 0x1
+#define PHY_LANE_IDLE_OFF 0x1
+#define PHY_LANE_IDLE_MASK 0x1
+#define PHY_LANE_IDLE_A_SHIFT 3
+#define PHY_LANE_IDLE_B_SHIFT 4
+#define PHY_LANE_IDLE_C_SHIFT 5
+#define PHY_LANE_IDLE_D_SHIFT 6
+
+struct rockchip_pcie_phy_data {
+ unsigned int pcie_conf;
+ unsigned int pcie_status;
+ unsigned int pcie_laneoff;
+};
+
+struct rockchip_pcie_phy {
+ void *reg_base;
+ struct clk refclk;
+ struct reset_ctl phy_rst;
+ const struct rockchip_pcie_phy_data *data;
+};
+
+static void phy_wr_cfg(struct rockchip_pcie_phy *priv, u32 addr, u32 data)
+{
+ u32 reg;
+
+ reg = HIWORD_UPDATE(data, PHY_CFG_DATA_MASK, PHY_CFG_DATA_SHIFT);
+ reg |= HIWORD_UPDATE(addr, PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT);
+ writel(reg, priv->reg_base + priv->data->pcie_conf);
+
+ udelay(1);
+
+ reg = HIWORD_UPDATE(PHY_CFG_WR_ENABLE,
+ PHY_CFG_WR_MASK,
+ PHY_CFG_WR_SHIFT);
+ writel(reg, priv->reg_base + priv->data->pcie_conf);
+
+ udelay(1);
+
+ reg = HIWORD_UPDATE(PHY_CFG_WR_DISABLE,
+ PHY_CFG_WR_MASK,
+ PHY_CFG_WR_SHIFT);
+ writel(reg, priv->reg_base + priv->data->pcie_conf);
+}
+
+static int rockchip_pcie_phy_power_on(struct phy *phy)
+{
+ struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
+ int ret = 0;
+ u32 reg, status;
+
+ ret = reset_deassert(&priv->phy_rst);
+ if (ret) {
+ dev_err(dev, "failed to assert phy reset\n");
+ return ret;
+ }
+
+ reg = HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
+ PHY_CFG_ADDR_MASK,
+ PHY_CFG_ADDR_SHIFT);
+ writel(reg, priv->reg_base + priv->data->pcie_conf);
+
+ reg = HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
+ PHY_LANE_IDLE_MASK,
+ PHY_LANE_IDLE_A_SHIFT);
+ writel(reg, priv->reg_base + priv->data->pcie_laneoff);
+
+ ret = -EINVAL;
+ ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status,
+ status,
+ status & PHY_PLL_LOCKED,
+ 20 * 1000,
+ 50);
+ if (ret) {
+ dev_err(&priv->dev, "pll lock timeout!\n");
+ goto err_pll_lock;
+ }
+
+ phy_wr_cfg(priv, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
+ phy_wr_cfg(priv, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
+
+ ret = -ETIMEDOUT;
+ ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status,
+ status,
+ !(status & PHY_PLL_OUTPUT),
+ 20 * 1000,
+ 50);
+ if (ret) {
+ dev_err(&priv->dev, "pll output enable timeout!\n");
+ goto err_pll_lock;
+ }
+
+ reg = HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
+ PHY_CFG_ADDR_MASK,
+ PHY_CFG_ADDR_SHIFT);
+ writel(reg, priv->reg_base + priv->data->pcie_conf);
+
+ ret = -EINVAL;
+ ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status,
+ status,
+ status & PHY_PLL_LOCKED,
+ 20 * 1000,
+ 50);
+ if (ret) {
+ dev_err(&priv->dev, "pll relock timeout!\n");
+ goto err_pll_lock;
+ }
+
+ return 0;
+
+err_pll_lock:
+ reset_assert(&priv->phy_rst);
+ return ret;
+}
+
+static int rockchip_pcie_phy_power_off(struct phy *phy)
+{
+ struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
+ int ret;
+ u32 reg;
+
+ reg = HIWORD_UPDATE(PHY_LANE_IDLE_OFF,
+ PHY_LANE_IDLE_MASK,
+ PHY_LANE_IDLE_A_SHIFT);
+ writel(reg, priv->reg_base + priv->data->pcie_laneoff);
+
+ ret = reset_assert(&priv->phy_rst);
+ if (ret) {
+ dev_err(dev, "failed to assert phy reset\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rockchip_pcie_phy_init(struct phy *phy)
+{
+ struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
+ int ret;
+
+ ret = clk_enable(&priv->refclk);
+ if (ret) {
+ dev_err(dev, "failed to enable refclk clock\n");
+ return ret;
+ }
+
+ ret = reset_assert(&priv->phy_rst);
+ if (ret) {
+ dev_err(dev, "failed to assert phy reset\n");
+ goto err_reset;
+ }
+
+ return 0;
+
+err_reset:
+ clk_disable(&priv->refclk);
+ return ret;
+}
+
+static int rockchip_pcie_phy_exit(struct phy *phy)
+{
+ struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
+
+ clk_disable(&priv->refclk);
+
+ return 0;
+}
+
+static struct phy_ops rockchip_pcie_phy_ops = {
+ .init = rockchip_pcie_phy_init,
+ .power_on = rockchip_pcie_phy_power_on,
+ .power_off = rockchip_pcie_phy_power_off,
+ .exit = rockchip_pcie_phy_exit,
+};
+
+static int rockchip_pcie_phy_probe(struct udevice *dev)
+{
+ struct rockchip_pcie_phy *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->data = (const struct rockchip_pcie_phy_data *)
+ dev_get_driver_data(dev);
+ if (!priv->data)
+ return -EINVAL;
+
+ priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ ret = clk_get_by_name(dev, "refclk", &priv->refclk);
+ if (ret) {
+ dev_err(dev, "failed to get refclk clock phandle\n");
+ return ret;
+ }
+
+ ret = reset_get_by_name(dev, "phy", &priv->phy_rst);
+ if (ret) {
+ dev_err(dev, "failed to get phy reset phandle\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct rockchip_pcie_phy_data rk3399_pcie_data = {
+ .pcie_conf = 0xe220,
+ .pcie_status = 0xe2a4,
+ .pcie_laneoff = 0xe214,
+};
+
+static const struct udevice_id rockchip_pcie_phy_ids[] = {
+ {
+ .compatible = "rockchip,rk3399-pcie-phy",
+ .data = (ulong)&rk3399_pcie_data,
+ },
+ { /* sentile */ }
+};
+
+U_BOOT_DRIVER(rockchip_pcie_phy) = {
+ .name = "rockchip_pcie_phy",
+ .id = UCLASS_PHY,
+ .of_match = rockchip_pcie_phy_ids,
+ .ops = &rockchip_pcie_phy_ops,
+ .probe = rockchip_pcie_phy_probe,
+ .priv_auto_alloc_size = sizeof(struct rockchip_pcie_phy),
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [RFC 2/7] clk: rk3399: Enable/Disable the USB2PHY clk
2020-04-30 21:45 ` Jagan Teki
@ 2020-04-30 21:45 ` Jagan Teki
-1 siblings, 0 replies; 16+ messages in thread
From: Jagan Teki @ 2020-04-30 21:45 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Frank Wang,
William Wu, Shawn Lin, Heiko Stuebner, Patrice Chotard
Cc: u-boot-0aAXYlwwYIKGBzrmiIFOJg,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Enable/Disable the USB2PHY clk for rk3399.
CLK is clear in enable and set in disable functionality.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 7feba92f9e..b1c89ea127 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1091,6 +1091,12 @@ static int rk3399_clk_enable(struct clk *clk)
case SCLK_MACREF_OUT:
rk_clrreg(&priv->cru->clkgate_con[5], BIT(6));
break;
+ case SCLK_USB2PHY0_REF:
+ rk_clrreg(&priv->cru->clkgate_con[6], BIT(5));
+ break;
+ case SCLK_USB2PHY1_REF:
+ rk_clrreg(&priv->cru->clkgate_con[6], BIT(6));
+ break;
case ACLK_GMAC:
rk_clrreg(&priv->cru->clkgate_con[32], BIT(0));
break;
@@ -1167,6 +1173,12 @@ static int rk3399_clk_disable(struct clk *clk)
case SCLK_MACREF_OUT:
rk_setreg(&priv->cru->clkgate_con[5], BIT(6));
break;
+ case SCLK_USB2PHY0_REF:
+ rk_setreg(&priv->cru->clkgate_con[6], BIT(5));
+ break;
+ case SCLK_USB2PHY1_REF:
+ rk_setreg(&priv->cru->clkgate_con[6], BIT(6));
+ break;
case ACLK_GMAC:
rk_setreg(&priv->cru->clkgate_con[32], BIT(0));
break;
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [RFC 2/7] clk: rk3399: Enable/Disable the USB2PHY clk
@ 2020-04-30 21:45 ` Jagan Teki
0 siblings, 0 replies; 16+ messages in thread
From: Jagan Teki @ 2020-04-30 21:45 UTC (permalink / raw)
To: u-boot
Enable/Disable the USB2PHY clk for rk3399.
CLK is clear in enable and set in disable functionality.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 7feba92f9e..b1c89ea127 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1091,6 +1091,12 @@ static int rk3399_clk_enable(struct clk *clk)
case SCLK_MACREF_OUT:
rk_clrreg(&priv->cru->clkgate_con[5], BIT(6));
break;
+ case SCLK_USB2PHY0_REF:
+ rk_clrreg(&priv->cru->clkgate_con[6], BIT(5));
+ break;
+ case SCLK_USB2PHY1_REF:
+ rk_clrreg(&priv->cru->clkgate_con[6], BIT(6));
+ break;
case ACLK_GMAC:
rk_clrreg(&priv->cru->clkgate_con[32], BIT(0));
break;
@@ -1167,6 +1173,12 @@ static int rk3399_clk_disable(struct clk *clk)
case SCLK_MACREF_OUT:
rk_setreg(&priv->cru->clkgate_con[5], BIT(6));
break;
+ case SCLK_USB2PHY0_REF:
+ rk_setreg(&priv->cru->clkgate_con[6], BIT(5));
+ break;
+ case SCLK_USB2PHY1_REF:
+ rk_setreg(&priv->cru->clkgate_con[6], BIT(6));
+ break;
case ACLK_GMAC:
rk_setreg(&priv->cru->clkgate_con[32], BIT(0));
break;
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [RFC 3/7] phy: rockchip: Add Rockchip USB2PHY driver
2020-04-30 21:45 ` Jagan Teki
@ 2020-04-30 21:45 ` Jagan Teki
-1 siblings, 0 replies; 16+ messages in thread
From: Jagan Teki @ 2020-04-30 21:45 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Frank Wang,
William Wu, Shawn Lin, Heiko Stuebner, Patrice Chotard
Cc: u-boot-0aAXYlwwYIKGBzrmiIFOJg,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Add Rockchip USB2PHY driver with initial support.
This will help to use it for EHCI controller in host
mode, and USB 3.0 controller in otg mode.
More functionality like charge, vbus detection will
add it in future changes.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
drivers/phy/rockchip/Kconfig | 7 +
drivers/phy/rockchip/Makefile | 1 +
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 312 ++++++++++++++++++
3 files changed, 320 insertions(+)
create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb2.c
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index 477c68920b..f7ddac4744 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -7,3 +7,10 @@ config PHY_ROCKCHIP_PCIE
select PHY
help
Enable this to support the Rockchip PCIe PHY.
+
+config PHY_ROCKCHIP_INNO_USB2
+ bool "Rockchip INNO USB2PHY Driver"
+ depends on ARCH_ROCKCHIP
+ select PHY
+ help
+ Support for Rockchip USB2.0 PHY with Innosilicon IP block.
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index 4d19ccdfd0..82d771b70b 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -4,3 +4,4 @@
#
obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
+obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
new file mode 100644
index 0000000000..dd4905d834
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Rockchip USB2.0 PHY with Innosilicon IP block driver
+ *
+ * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (C) 2020 Amarula Solutions(India)
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <generic-phy.h>
+#include <reset.h>
+#include <syscon.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <linux/iopoll.h>
+#include <asm/arch-rockchip/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define usleep_range(a, b) udelay((b))
+#define BIT_WRITEABLE_SHIFT 16
+
+enum rockchip_usb2phy_port_id {
+ USB2PHY_PORT_OTG,
+ USB2PHY_PORT_HOST,
+ USB2PHY_NUM_PORTS,
+};
+
+struct usb2phy_reg {
+ unsigned int offset;
+ unsigned int bitend;
+ unsigned int bitstart;
+ unsigned int disable;
+ unsigned int enable;
+};
+
+struct rockchip_usb2phy_port_cfg {
+ struct usb2phy_reg phy_sus;
+ struct usb2phy_reg bvalid_det_en;
+ struct usb2phy_reg bvalid_det_st;
+ struct usb2phy_reg bvalid_det_clr;
+ struct usb2phy_reg ls_det_en;
+ struct usb2phy_reg ls_det_st;
+ struct usb2phy_reg ls_det_clr;
+ struct usb2phy_reg utmi_avalid;
+ struct usb2phy_reg utmi_bvalid;
+ struct usb2phy_reg utmi_ls;
+ struct usb2phy_reg utmi_hstdet;
+};
+
+struct rockchip_usb2phy_cfg {
+ unsigned int reg;
+ const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
+};
+
+struct rockchip_usb2phy {
+ void *reg_base;
+ struct clk phyclk;
+ const struct rockchip_usb2phy_cfg *phy_cfg;
+};
+
+static inline int property_enable(void *reg_base,
+ const struct usb2phy_reg *reg, bool en)
+{
+ unsigned int val, mask, tmp;
+
+ tmp = en ? reg->enable : reg->disable;
+ mask = GENMASK(reg->bitend, reg->bitstart);
+ val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
+
+ return writel(val, reg_base + reg->offset);
+}
+
+static const
+struct rockchip_usb2phy_port_cfg *us2phy_get_port(struct phy *phy)
+{
+ struct udevice *parent = dev_get_parent(phy->dev);
+ struct rockchip_usb2phy *priv = dev_get_priv(parent);
+ const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
+
+ return &phy_cfg->port_cfgs[phy->id];
+}
+
+static int rockchip_usb2phy_power_on(struct phy *phy)
+{
+ struct udevice *parent = dev_get_parent(phy->dev);
+ struct rockchip_usb2phy *priv = dev_get_priv(parent);
+ const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
+
+ property_enable(priv->reg_base, &port_cfg->phy_sus, false);
+
+ /* waiting for the utmi_clk to become stable */
+ usleep_range(1500, 2000);
+
+ return 0;
+}
+
+static int rockchip_usb2phy_power_off(struct phy *phy)
+{
+ struct udevice *parent = dev_get_parent(phy->dev);
+ struct rockchip_usb2phy *priv = dev_get_priv(parent);
+ const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
+
+ property_enable(priv->reg_base, &port_cfg->phy_sus, true);
+
+ return 0;
+}
+
+static int rockchip_usb2phy_init(struct phy *phy)
+{
+ struct udevice *parent = dev_get_parent(phy->dev);
+ struct rockchip_usb2phy *priv = dev_get_priv(parent);
+ const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
+ int ret;
+
+ ret = clk_enable(&priv->phyclk);
+ if (ret) {
+ dev_err(phy->dev, "failed to enable phyclk (ret=%d)\n", ret);
+ return ret;
+ }
+
+ if (phy->id == USB2PHY_PORT_OTG) {
+ property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true);
+ property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true);
+ } else if (phy->id == USB2PHY_PORT_HOST) {
+ property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true);
+ property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true);
+ }
+
+ return 0;
+}
+
+static int rockchip_usb2phy_exit(struct phy *phy)
+{
+ struct udevice *parent = dev_get_parent(phy->dev);
+ struct rockchip_usb2phy *priv = dev_get_priv(parent);
+
+ clk_disable(&priv->phyclk);
+
+ return 0;
+}
+
+static int rockchip_usb2phy_of_xlate(struct phy *phy,
+ struct ofnode_phandle_args *args)
+{
+ const char *name = phy->dev->name;
+
+ if (!strcasecmp(name, "host-port"))
+ phy->id = USB2PHY_PORT_HOST;
+ else if (!strcasecmp(name, "otg-port"))
+ phy->id = USB2PHY_PORT_OTG;
+ else
+ dev_err(phy->dev, "improper %s device\n", name);
+
+ return 0;
+}
+
+static struct phy_ops rockchip_usb2phy_ops = {
+ .init = rockchip_usb2phy_init,
+ .exit = rockchip_usb2phy_exit,
+ .power_on = rockchip_usb2phy_power_on,
+ .power_off = rockchip_usb2phy_power_off,
+ .of_xlate = rockchip_usb2phy_of_xlate,
+};
+
+static int rockchip_usb2phy_probe(struct udevice *dev)
+{
+ struct rockchip_usb2phy *priv = dev_get_priv(dev);
+ const struct rockchip_usb2phy_cfg *phy_cfgs;
+ unsigned int reg;
+ int index, ret;
+
+ priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ if (IS_ERR(priv->reg_base))
+ return PTR_ERR(priv->reg_base);
+
+ ret = dev_read_u32_index(dev, "reg", 1, ®);
+ if (ret) {
+ dev_err(dev, "failed to read reg property (ret = %d)\n", ret);
+ return ret;
+ }
+
+ phy_cfgs = (const struct rockchip_usb2phy_cfg *)
+ dev_get_driver_data(dev);
+ if (!phy_cfgs)
+ return -EINVAL;
+
+ /* find out a proper config which can be matched with dt. */
+ index = 0;
+ while (phy_cfgs[index].reg) {
+ if (phy_cfgs[index].reg == reg) {
+ priv->phy_cfg = &phy_cfgs[index];
+ break;
+ }
+
+ ++index;
+ }
+
+ if (!priv->phy_cfg) {
+ dev_err(dev, "failed find proper phy-cfg\n");
+ return -EINVAL;
+ }
+
+ ret = clk_get_by_name(dev, "phyclk", &priv->phyclk);
+ if (ret) {
+ dev_err(dev, "failed to get the phyclk (ret=%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rockchip_usb2phy_bind(struct udevice *dev)
+{
+ struct udevice *usb2phy_dev;
+ ofnode node;
+ const char *name;
+ int ret = 0;
+
+ dev_for_each_subnode(node, dev) {
+ if (!ofnode_valid(node)) {
+ dev_info(dev, "subnode %s not found\n", dev->name);
+ return -ENXIO;
+ }
+
+ name = ofnode_get_name(node);
+ dev_dbg(dev, "subnode %s\n", name);
+
+ ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port",
+ name, node, &usb2phy_dev);
+ if (ret) {
+ dev_err(dev,
+ "'%s' cannot bind 'rockchip_usb2phy_port'\n", name);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = {
+ {
+ .reg = 0xe450,
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0xe454, 1, 0, 2, 1 },
+ .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
+ .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
+ .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
+ .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 },
+ .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 },
+ },
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
+ .ls_det_en = { 0xe3c0, 6, 6, 0, 1 },
+ .ls_det_st = { 0xe3e0, 6, 6, 0, 1 },
+ .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 },
+ .utmi_ls = { 0xe2ac, 22, 21, 0, 1 },
+ .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 }
+ }
+ },
+ },
+ {
+ .reg = 0xe460,
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0xe464, 1, 0, 2, 1 },
+ .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 },
+ .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 },
+ .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
+ .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 },
+ .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 },
+ },
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
+ .ls_det_en = { 0xe3c0, 11, 11, 0, 1 },
+ .ls_det_st = { 0xe3e0, 11, 11, 0, 1 },
+ .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 },
+ .utmi_ls = { 0xe2ac, 26, 25, 0, 1 },
+ .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 }
+ }
+ },
+ },
+ { /* sentinel */ }
+};
+
+static const struct udevice_id rockchip_usb2phy_ids[] = {
+ {
+ .compatible = "rockchip,rk3399-usb2phy",
+ .data = (ulong)&rk3399_usb2phy_cfgs,
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(rockchip_usb2phy_port) = {
+ .name = "rockchip_usb2phy_port",
+ .id = UCLASS_PHY,
+ .ops = &rockchip_usb2phy_ops,
+};
+
+U_BOOT_DRIVER(rockchip_usb2phy) = {
+ .name = "rockchip_usb2phy",
+ .id = UCLASS_PHY,
+ .of_match = rockchip_usb2phy_ids,
+ .probe = rockchip_usb2phy_probe,
+ .bind = rockchip_usb2phy_bind,
+ .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy),
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [RFC 3/7] phy: rockchip: Add Rockchip USB2PHY driver
@ 2020-04-30 21:45 ` Jagan Teki
0 siblings, 0 replies; 16+ messages in thread
From: Jagan Teki @ 2020-04-30 21:45 UTC (permalink / raw)
To: u-boot
Add Rockchip USB2PHY driver with initial support.
This will help to use it for EHCI controller in host
mode, and USB 3.0 controller in otg mode.
More functionality like charge, vbus detection will
add it in future changes.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/phy/rockchip/Kconfig | 7 +
drivers/phy/rockchip/Makefile | 1 +
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 312 ++++++++++++++++++
3 files changed, 320 insertions(+)
create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb2.c
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index 477c68920b..f7ddac4744 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -7,3 +7,10 @@ config PHY_ROCKCHIP_PCIE
select PHY
help
Enable this to support the Rockchip PCIe PHY.
+
+config PHY_ROCKCHIP_INNO_USB2
+ bool "Rockchip INNO USB2PHY Driver"
+ depends on ARCH_ROCKCHIP
+ select PHY
+ help
+ Support for Rockchip USB2.0 PHY with Innosilicon IP block.
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index 4d19ccdfd0..82d771b70b 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -4,3 +4,4 @@
#
obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
+obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
new file mode 100644
index 0000000000..dd4905d834
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Rockchip USB2.0 PHY with Innosilicon IP block driver
+ *
+ * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (C) 2020 Amarula Solutions(India)
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <generic-phy.h>
+#include <reset.h>
+#include <syscon.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <linux/iopoll.h>
+#include <asm/arch-rockchip/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define usleep_range(a, b) udelay((b))
+#define BIT_WRITEABLE_SHIFT 16
+
+enum rockchip_usb2phy_port_id {
+ USB2PHY_PORT_OTG,
+ USB2PHY_PORT_HOST,
+ USB2PHY_NUM_PORTS,
+};
+
+struct usb2phy_reg {
+ unsigned int offset;
+ unsigned int bitend;
+ unsigned int bitstart;
+ unsigned int disable;
+ unsigned int enable;
+};
+
+struct rockchip_usb2phy_port_cfg {
+ struct usb2phy_reg phy_sus;
+ struct usb2phy_reg bvalid_det_en;
+ struct usb2phy_reg bvalid_det_st;
+ struct usb2phy_reg bvalid_det_clr;
+ struct usb2phy_reg ls_det_en;
+ struct usb2phy_reg ls_det_st;
+ struct usb2phy_reg ls_det_clr;
+ struct usb2phy_reg utmi_avalid;
+ struct usb2phy_reg utmi_bvalid;
+ struct usb2phy_reg utmi_ls;
+ struct usb2phy_reg utmi_hstdet;
+};
+
+struct rockchip_usb2phy_cfg {
+ unsigned int reg;
+ const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
+};
+
+struct rockchip_usb2phy {
+ void *reg_base;
+ struct clk phyclk;
+ const struct rockchip_usb2phy_cfg *phy_cfg;
+};
+
+static inline int property_enable(void *reg_base,
+ const struct usb2phy_reg *reg, bool en)
+{
+ unsigned int val, mask, tmp;
+
+ tmp = en ? reg->enable : reg->disable;
+ mask = GENMASK(reg->bitend, reg->bitstart);
+ val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
+
+ return writel(val, reg_base + reg->offset);
+}
+
+static const
+struct rockchip_usb2phy_port_cfg *us2phy_get_port(struct phy *phy)
+{
+ struct udevice *parent = dev_get_parent(phy->dev);
+ struct rockchip_usb2phy *priv = dev_get_priv(parent);
+ const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
+
+ return &phy_cfg->port_cfgs[phy->id];
+}
+
+static int rockchip_usb2phy_power_on(struct phy *phy)
+{
+ struct udevice *parent = dev_get_parent(phy->dev);
+ struct rockchip_usb2phy *priv = dev_get_priv(parent);
+ const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
+
+ property_enable(priv->reg_base, &port_cfg->phy_sus, false);
+
+ /* waiting for the utmi_clk to become stable */
+ usleep_range(1500, 2000);
+
+ return 0;
+}
+
+static int rockchip_usb2phy_power_off(struct phy *phy)
+{
+ struct udevice *parent = dev_get_parent(phy->dev);
+ struct rockchip_usb2phy *priv = dev_get_priv(parent);
+ const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
+
+ property_enable(priv->reg_base, &port_cfg->phy_sus, true);
+
+ return 0;
+}
+
+static int rockchip_usb2phy_init(struct phy *phy)
+{
+ struct udevice *parent = dev_get_parent(phy->dev);
+ struct rockchip_usb2phy *priv = dev_get_priv(parent);
+ const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
+ int ret;
+
+ ret = clk_enable(&priv->phyclk);
+ if (ret) {
+ dev_err(phy->dev, "failed to enable phyclk (ret=%d)\n", ret);
+ return ret;
+ }
+
+ if (phy->id == USB2PHY_PORT_OTG) {
+ property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true);
+ property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true);
+ } else if (phy->id == USB2PHY_PORT_HOST) {
+ property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true);
+ property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true);
+ }
+
+ return 0;
+}
+
+static int rockchip_usb2phy_exit(struct phy *phy)
+{
+ struct udevice *parent = dev_get_parent(phy->dev);
+ struct rockchip_usb2phy *priv = dev_get_priv(parent);
+
+ clk_disable(&priv->phyclk);
+
+ return 0;
+}
+
+static int rockchip_usb2phy_of_xlate(struct phy *phy,
+ struct ofnode_phandle_args *args)
+{
+ const char *name = phy->dev->name;
+
+ if (!strcasecmp(name, "host-port"))
+ phy->id = USB2PHY_PORT_HOST;
+ else if (!strcasecmp(name, "otg-port"))
+ phy->id = USB2PHY_PORT_OTG;
+ else
+ dev_err(phy->dev, "improper %s device\n", name);
+
+ return 0;
+}
+
+static struct phy_ops rockchip_usb2phy_ops = {
+ .init = rockchip_usb2phy_init,
+ .exit = rockchip_usb2phy_exit,
+ .power_on = rockchip_usb2phy_power_on,
+ .power_off = rockchip_usb2phy_power_off,
+ .of_xlate = rockchip_usb2phy_of_xlate,
+};
+
+static int rockchip_usb2phy_probe(struct udevice *dev)
+{
+ struct rockchip_usb2phy *priv = dev_get_priv(dev);
+ const struct rockchip_usb2phy_cfg *phy_cfgs;
+ unsigned int reg;
+ int index, ret;
+
+ priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ if (IS_ERR(priv->reg_base))
+ return PTR_ERR(priv->reg_base);
+
+ ret = dev_read_u32_index(dev, "reg", 1, ®);
+ if (ret) {
+ dev_err(dev, "failed to read reg property (ret = %d)\n", ret);
+ return ret;
+ }
+
+ phy_cfgs = (const struct rockchip_usb2phy_cfg *)
+ dev_get_driver_data(dev);
+ if (!phy_cfgs)
+ return -EINVAL;
+
+ /* find out a proper config which can be matched with dt. */
+ index = 0;
+ while (phy_cfgs[index].reg) {
+ if (phy_cfgs[index].reg == reg) {
+ priv->phy_cfg = &phy_cfgs[index];
+ break;
+ }
+
+ ++index;
+ }
+
+ if (!priv->phy_cfg) {
+ dev_err(dev, "failed find proper phy-cfg\n");
+ return -EINVAL;
+ }
+
+ ret = clk_get_by_name(dev, "phyclk", &priv->phyclk);
+ if (ret) {
+ dev_err(dev, "failed to get the phyclk (ret=%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rockchip_usb2phy_bind(struct udevice *dev)
+{
+ struct udevice *usb2phy_dev;
+ ofnode node;
+ const char *name;
+ int ret = 0;
+
+ dev_for_each_subnode(node, dev) {
+ if (!ofnode_valid(node)) {
+ dev_info(dev, "subnode %s not found\n", dev->name);
+ return -ENXIO;
+ }
+
+ name = ofnode_get_name(node);
+ dev_dbg(dev, "subnode %s\n", name);
+
+ ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port",
+ name, node, &usb2phy_dev);
+ if (ret) {
+ dev_err(dev,
+ "'%s' cannot bind 'rockchip_usb2phy_port'\n", name);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = {
+ {
+ .reg = 0xe450,
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0xe454, 1, 0, 2, 1 },
+ .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
+ .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
+ .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
+ .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 },
+ .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 },
+ },
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
+ .ls_det_en = { 0xe3c0, 6, 6, 0, 1 },
+ .ls_det_st = { 0xe3e0, 6, 6, 0, 1 },
+ .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 },
+ .utmi_ls = { 0xe2ac, 22, 21, 0, 1 },
+ .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 }
+ }
+ },
+ },
+ {
+ .reg = 0xe460,
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0xe464, 1, 0, 2, 1 },
+ .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 },
+ .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 },
+ .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
+ .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 },
+ .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 },
+ },
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
+ .ls_det_en = { 0xe3c0, 11, 11, 0, 1 },
+ .ls_det_st = { 0xe3e0, 11, 11, 0, 1 },
+ .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 },
+ .utmi_ls = { 0xe2ac, 26, 25, 0, 1 },
+ .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 }
+ }
+ },
+ },
+ { /* sentinel */ }
+};
+
+static const struct udevice_id rockchip_usb2phy_ids[] = {
+ {
+ .compatible = "rockchip,rk3399-usb2phy",
+ .data = (ulong)&rk3399_usb2phy_cfgs,
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(rockchip_usb2phy_port) = {
+ .name = "rockchip_usb2phy_port",
+ .id = UCLASS_PHY,
+ .ops = &rockchip_usb2phy_ops,
+};
+
+U_BOOT_DRIVER(rockchip_usb2phy) = {
+ .name = "rockchip_usb2phy",
+ .id = UCLASS_PHY,
+ .of_match = rockchip_usb2phy_ids,
+ .probe = rockchip_usb2phy_probe,
+ .bind = rockchip_usb2phy_bind,
+ .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy),
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [RFC 4/7] arm64: dts: rk3399: Move u2phy into root port
2020-04-30 21:45 ` Jagan Teki
@ 2020-04-30 21:45 ` Jagan Teki
-1 siblings, 0 replies; 16+ messages in thread
From: Jagan Teki @ 2020-04-30 21:45 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Frank Wang,
William Wu, Shawn Lin, Heiko Stuebner, Patrice Chotard
Cc: u-boot-0aAXYlwwYIKGBzrmiIFOJg,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Yes, This is changing the actual device tree u2phy
structure but the problem with the current Generic
PHY subsystem is unable to find PHY if the PHY node
is not part of the root structure.
This will be reverted once we support the PHY subsystem
to get the PHY even though it is not part of the root
node or any other relevant solution.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
arch/arm/dts/rk3399.dtsi | 108 +++++++++++++++++++--------------------
1 file changed, 54 insertions(+), 54 deletions(-)
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 74f2c3d490..6c77f25f23 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -1387,60 +1387,6 @@
status = "disabled";
};
- u2phy0: usb2-phy@e450 {
- compatible = "rockchip,rk3399-usb2phy";
- reg = <0xe450 0x10>;
- clocks = <&cru SCLK_USB2PHY0_REF>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- clock-output-names = "clk_usbphy0_480m";
- status = "disabled";
-
- u2phy0_host: host-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "linestate";
- status = "disabled";
- };
-
- u2phy0_otg: otg-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "otg-bvalid", "otg-id",
- "linestate";
- status = "disabled";
- };
- };
-
- u2phy1: usb2-phy@e460 {
- compatible = "rockchip,rk3399-usb2phy";
- reg = <0xe460 0x10>;
- clocks = <&cru SCLK_USB2PHY1_REF>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- clock-output-names = "clk_usbphy1_480m";
- status = "disabled";
-
- u2phy1_host: host-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "linestate";
- status = "disabled";
- };
-
- u2phy1_otg: otg-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "otg-bvalid", "otg-id",
- "linestate";
- status = "disabled";
- };
- };
-
emmc_phy: phy@f780 {
compatible = "rockchip,rk3399-emmc-phy";
reg = <0xf780 0x24>;
@@ -1462,6 +1408,60 @@
};
};
+ u2phy0: usb2-phy@e450 {
+ compatible = "rockchip,rk3399-usb2phy";
+ reg = <0x0 0xe450 0x0 0x10>;
+ clocks = <&cru SCLK_USB2PHY0_REF>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ clock-output-names = "clk_usbphy0_480m";
+ status = "disabled";
+
+ u2phy0_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+
+ u2phy0_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ status = "disabled";
+ };
+ };
+
+ u2phy1: usb2-phy@e460 {
+ compatible = "rockchip,rk3399-usb2phy";
+ reg = <0x0 0xe460 0x0 0x10>;
+ clocks = <&cru SCLK_USB2PHY1_REF>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ clock-output-names = "clk_usbphy1_480m";
+ status = "disabled";
+
+ u2phy1_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+
+ u2phy1_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ status = "disabled";
+ };
+ };
+
tcphy0: phy@ff7c0000 {
compatible = "rockchip,rk3399-typec-phy";
reg = <0x0 0xff7c0000 0x0 0x40000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [RFC 4/7] arm64: dts: rk3399: Move u2phy into root port
@ 2020-04-30 21:45 ` Jagan Teki
0 siblings, 0 replies; 16+ messages in thread
From: Jagan Teki @ 2020-04-30 21:45 UTC (permalink / raw)
To: u-boot
Yes, This is changing the actual device tree u2phy
structure but the problem with the current Generic
PHY subsystem is unable to find PHY if the PHY node
is not part of the root structure.
This will be reverted once we support the PHY subsystem
to get the PHY even though it is not part of the root
node or any other relevant solution.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/rk3399.dtsi | 108 +++++++++++++++++++--------------------
1 file changed, 54 insertions(+), 54 deletions(-)
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 74f2c3d490..6c77f25f23 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -1387,60 +1387,6 @@
status = "disabled";
};
- u2phy0: usb2-phy at e450 {
- compatible = "rockchip,rk3399-usb2phy";
- reg = <0xe450 0x10>;
- clocks = <&cru SCLK_USB2PHY0_REF>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- clock-output-names = "clk_usbphy0_480m";
- status = "disabled";
-
- u2phy0_host: host-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "linestate";
- status = "disabled";
- };
-
- u2phy0_otg: otg-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "otg-bvalid", "otg-id",
- "linestate";
- status = "disabled";
- };
- };
-
- u2phy1: usb2-phy at e460 {
- compatible = "rockchip,rk3399-usb2phy";
- reg = <0xe460 0x10>;
- clocks = <&cru SCLK_USB2PHY1_REF>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- clock-output-names = "clk_usbphy1_480m";
- status = "disabled";
-
- u2phy1_host: host-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "linestate";
- status = "disabled";
- };
-
- u2phy1_otg: otg-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "otg-bvalid", "otg-id",
- "linestate";
- status = "disabled";
- };
- };
-
emmc_phy: phy at f780 {
compatible = "rockchip,rk3399-emmc-phy";
reg = <0xf780 0x24>;
@@ -1462,6 +1408,60 @@
};
};
+ u2phy0: usb2-phy at e450 {
+ compatible = "rockchip,rk3399-usb2phy";
+ reg = <0x0 0xe450 0x0 0x10>;
+ clocks = <&cru SCLK_USB2PHY0_REF>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ clock-output-names = "clk_usbphy0_480m";
+ status = "disabled";
+
+ u2phy0_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+
+ u2phy0_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ status = "disabled";
+ };
+ };
+
+ u2phy1: usb2-phy at e460 {
+ compatible = "rockchip,rk3399-usb2phy";
+ reg = <0x0 0xe460 0x0 0x10>;
+ clocks = <&cru SCLK_USB2PHY1_REF>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ clock-output-names = "clk_usbphy1_480m";
+ status = "disabled";
+
+ u2phy1_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+
+ u2phy1_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ status = "disabled";
+ };
+ };
+
tcphy0: phy at ff7c0000 {
compatible = "rockchip,rk3399-typec-phy";
reg = <0x0 0xff7c0000 0x0 0x40000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [RFC 5/7] arm64: dts: rk3399: Move pcie_phy into root port
2020-04-30 21:45 ` Jagan Teki
@ 2020-04-30 21:45 ` Jagan Teki
-1 siblings, 0 replies; 16+ messages in thread
From: Jagan Teki @ 2020-04-30 21:45 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Frank Wang,
William Wu, Shawn Lin, Heiko Stuebner, Patrice Chotard
Cc: u-boot-0aAXYlwwYIKGBzrmiIFOJg,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Yes, This is changing the actual device tree pcie_phy
structure but the problem with the current Generic PHY
subsystem is unable to find PHY if the PHY node is not
part of the root structure and also PHY parent is
non-PHY type.
This will be reverted once we support the PHY subsystem
to get the PHY whose parent has non-PHY type or any other
relevant solution.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/rk3399.dtsi | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 6c77f25f23..dea76032bf 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -1395,17 +1395,17 @@
#phy-cells = <0>;
status = "disabled";
};
+ };
- pcie_phy: pcie-phy {
- compatible = "rockchip,rk3399-pcie-phy";
- clocks = <&cru SCLK_PCIEPHY_REF>;
- clock-names = "refclk";
- #phy-cells = <1>;
- resets = <&cru SRST_PCIEPHY>;
- drive-impedance-ohm = <50>;
- reset-names = "phy";
- status = "disabled";
- };
+ pcie_phy: pcie-phy {
+ compatible = "rockchip,rk3399-pcie-phy";
+ clocks = <&cru SCLK_PCIEPHY_REF>;
+ clock-names = "refclk";
+ #phy-cells = <1>;
+ resets = <&cru SRST_PCIEPHY>;
+ drive-impedance-ohm = <50>;
+ reset-names = "phy";
+ status = "disabled";
};
u2phy0: usb2-phy@e450 {
--
2.17.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 16+ messages in thread* [RFC 5/7] arm64: dts: rk3399: Move pcie_phy into root port
@ 2020-04-30 21:45 ` Jagan Teki
0 siblings, 0 replies; 16+ messages in thread
From: Jagan Teki @ 2020-04-30 21:45 UTC (permalink / raw)
To: u-boot
Yes, This is changing the actual device tree pcie_phy
structure but the problem with the current Generic PHY
subsystem is unable to find PHY if the PHY node is not
part of the root structure and also PHY parent is
non-PHY type.
This will be reverted once we support the PHY subsystem
to get the PHY whose parent has non-PHY type or any other
relevant solution.? ?
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/rk3399.dtsi | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 6c77f25f23..dea76032bf 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -1395,17 +1395,17 @@
#phy-cells = <0>;
status = "disabled";
};
+ };
- pcie_phy: pcie-phy {
- compatible = "rockchip,rk3399-pcie-phy";
- clocks = <&cru SCLK_PCIEPHY_REF>;
- clock-names = "refclk";
- #phy-cells = <1>;
- resets = <&cru SRST_PCIEPHY>;
- drive-impedance-ohm = <50>;
- reset-names = "phy";
- status = "disabled";
- };
+ pcie_phy: pcie-phy {
+ compatible = "rockchip,rk3399-pcie-phy";
+ clocks = <&cru SCLK_PCIEPHY_REF>;
+ clock-names = "refclk";
+ #phy-cells = <1>;
+ resets = <&cru SRST_PCIEPHY>;
+ drive-impedance-ohm = <50>;
+ reset-names = "phy";
+ status = "disabled";
};
u2phy0: usb2-phy at e450 {
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [RFC 6/7] pci: rockchip: Switch to generic-phy
2020-04-30 21:45 ` Jagan Teki
@ 2020-04-30 21:45 ` Jagan Teki
-1 siblings, 0 replies; 16+ messages in thread
From: Jagan Teki @ 2020-04-30 21:45 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Frank Wang,
William Wu, Shawn Lin, Heiko Stuebner, Patrice Chotard
Cc: u-boot-0aAXYlwwYIKGBzrmiIFOJg,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Now, we have a PCIe PHY driver as part of the Generic
PHY framework. Let's use it instead of legacy PHY driver.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
drivers/pci/pcie_rockchip.c | 20 ++++++++++----------
drivers/pci/pcie_rockchip.h | 5 +++++
2 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c
index 82a8396e42..3e4ba9635f 100644
--- a/drivers/pci/pcie_rockchip.c
+++ b/drivers/pci/pcie_rockchip.c
@@ -159,8 +159,6 @@ static int rockchip_pcie_atr_init(struct rockchip_pcie *priv)
static int rockchip_pcie_init_port(struct udevice *dev)
{
struct rockchip_pcie *priv = dev_get_priv(dev);
- struct rockchip_pcie_phy *phy = pcie_get_phy(priv);
- struct rockchip_pcie_phy_ops *ops = phy_get_ops(phy);
u32 cr, val, status;
int ret;
@@ -185,7 +183,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
return ret;
}
- ret = ops->init(phy);
+ ret = generic_phy_init(&priv->pcie_phy);
if (ret) {
dev_err(dev, "failed to init phy (ret=%d)\n", ret);
goto err_exit_phy;
@@ -242,7 +240,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG);
- ret = ops->power_on(phy);
+ ret = generic_phy_power_on(&priv->pcie_phy);
if (ret) {
dev_err(dev, "failed to power on phy (ret=%d)\n", ret);
goto err_power_off_phy;
@@ -311,9 +309,9 @@ static int rockchip_pcie_init_port(struct udevice *dev)
return 0;
err_power_off_phy:
- ops->power_off(phy);
+ generic_phy_power_off(&priv->pcie_phy);
err_exit_phy:
- ops->exit(phy);
+ generic_phy_exit(&priv->pcie_phy);
return ret;
}
@@ -436,6 +434,12 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
return ret;
}
+ ret = generic_phy_get_by_index(dev, 0, &priv->pcie_phy);
+ if (ret) {
+ dev_err(dev, "failed to get pcie-phy (ret=%d)\n", ret);
+ return ret;
+ }
+
return 0;
}
@@ -453,10 +457,6 @@ static int rockchip_pcie_probe(struct udevice *dev)
if (ret)
return ret;
- ret = rockchip_pcie_phy_get(dev);
- if (ret)
- return ret;
-
ret = rockchip_pcie_set_vpcie(dev);
if (ret)
return ret;
diff --git a/drivers/pci/pcie_rockchip.h b/drivers/pci/pcie_rockchip.h
index c3a0a2846d..4b06110bfe 100644
--- a/drivers/pci/pcie_rockchip.h
+++ b/drivers/pci/pcie_rockchip.h
@@ -9,6 +9,8 @@
*
*/
+#include <generic-phy.h>
+
#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
@@ -126,6 +128,9 @@ struct rockchip_pcie {
struct udevice *vpcie3v3;
struct udevice *vpcie1v8;
struct udevice *vpcie0v9;
+
+ /* phy */
+ struct phy pcie_phy;
};
int rockchip_pcie_phy_get(struct udevice *dev);
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [RFC 6/7] pci: rockchip: Switch to generic-phy
@ 2020-04-30 21:45 ` Jagan Teki
0 siblings, 0 replies; 16+ messages in thread
From: Jagan Teki @ 2020-04-30 21:45 UTC (permalink / raw)
To: u-boot
Now, we have a PCIe PHY driver as part of the Generic
PHY framework. Let's use it instead of legacy PHY driver.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/pci/pcie_rockchip.c | 20 ++++++++++----------
drivers/pci/pcie_rockchip.h | 5 +++++
2 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c
index 82a8396e42..3e4ba9635f 100644
--- a/drivers/pci/pcie_rockchip.c
+++ b/drivers/pci/pcie_rockchip.c
@@ -159,8 +159,6 @@ static int rockchip_pcie_atr_init(struct rockchip_pcie *priv)
static int rockchip_pcie_init_port(struct udevice *dev)
{
struct rockchip_pcie *priv = dev_get_priv(dev);
- struct rockchip_pcie_phy *phy = pcie_get_phy(priv);
- struct rockchip_pcie_phy_ops *ops = phy_get_ops(phy);
u32 cr, val, status;
int ret;
@@ -185,7 +183,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
return ret;
}
- ret = ops->init(phy);
+ ret = generic_phy_init(&priv->pcie_phy);
if (ret) {
dev_err(dev, "failed to init phy (ret=%d)\n", ret);
goto err_exit_phy;
@@ -242,7 +240,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG);
- ret = ops->power_on(phy);
+ ret = generic_phy_power_on(&priv->pcie_phy);
if (ret) {
dev_err(dev, "failed to power on phy (ret=%d)\n", ret);
goto err_power_off_phy;
@@ -311,9 +309,9 @@ static int rockchip_pcie_init_port(struct udevice *dev)
return 0;
err_power_off_phy:
- ops->power_off(phy);
+ generic_phy_power_off(&priv->pcie_phy);
err_exit_phy:
- ops->exit(phy);
+ generic_phy_exit(&priv->pcie_phy);
return ret;
}
@@ -436,6 +434,12 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
return ret;
}
+ ret = generic_phy_get_by_index(dev, 0, &priv->pcie_phy);
+ if (ret) {
+ dev_err(dev, "failed to get pcie-phy (ret=%d)\n", ret);
+ return ret;
+ }
+
return 0;
}
@@ -453,10 +457,6 @@ static int rockchip_pcie_probe(struct udevice *dev)
if (ret)
return ret;
- ret = rockchip_pcie_phy_get(dev);
- if (ret)
- return ret;
-
ret = rockchip_pcie_set_vpcie(dev);
if (ret)
return ret;
diff --git a/drivers/pci/pcie_rockchip.h b/drivers/pci/pcie_rockchip.h
index c3a0a2846d..4b06110bfe 100644
--- a/drivers/pci/pcie_rockchip.h
+++ b/drivers/pci/pcie_rockchip.h
@@ -9,6 +9,8 @@
*
*/
+#include <generic-phy.h>
+
#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
@@ -126,6 +128,9 @@ struct rockchip_pcie {
struct udevice *vpcie3v3;
struct udevice *vpcie1v8;
struct udevice *vpcie0v9;
+
+ /* phy */
+ struct phy pcie_phy;
};
int rockchip_pcie_phy_get(struct udevice *dev);
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [RFC 7/7] pci: rockchip: Drop legacy PHY driver
2020-04-30 21:45 ` Jagan Teki
@ 2020-04-30 21:45 ` Jagan Teki
-1 siblings, 0 replies; 16+ messages in thread
From: Jagan Teki @ 2020-04-30 21:45 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Frank Wang,
William Wu, Shawn Lin, Heiko Stuebner, Patrice Chotard
Cc: u-boot-0aAXYlwwYIKGBzrmiIFOJg,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
Jagan Teki, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Drop the legacy PHY driver and it's associated code since
the PHY handling driver now part of Generic PHY framework.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
drivers/pci/Makefile | 2 +-
drivers/pci/pcie_rockchip.c | 75 +++++++++++-
drivers/pci/pcie_rockchip.h | 147 -----------------------
drivers/pci/pcie_rockchip_phy.c | 205 --------------------------------
4 files changed, 74 insertions(+), 355 deletions(-)
delete mode 100644 drivers/pci/pcie_rockchip.h
delete mode 100644 drivers/pci/pcie_rockchip_phy.c
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 955351c5c2..493e9354dd 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -43,4 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
-obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o pcie_rockchip_phy.o
+obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o
diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c
index 3e4ba9635f..cf24479f85 100644
--- a/drivers/pci/pcie_rockchip.c
+++ b/drivers/pci/pcie_rockchip.c
@@ -15,6 +15,7 @@
#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
+#include <generic-phy.h>
#include <pci.h>
#include <power-domain.h>
#include <power/regulator.h>
@@ -25,10 +26,80 @@
#include <asm/arch-rockchip/clock.h>
#include <linux/iopoll.h>
-#include "pcie_rockchip.h"
-
DECLARE_GLOBAL_DATA_PTR;
+#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
+#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
+
+#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
+#define PCIE_CLIENT_BASE 0x0
+#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
+#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
+#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
+#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
+#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
+#define PCIE_CLIENT_BASIC_STATUS1 0x0048
+#define PCIE_CLIENT_LINK_STATUS_UP GENMASK(21, 20)
+#define PCIE_CLIENT_LINK_STATUS_MASK GENMASK(21, 20)
+#define PCIE_LINK_UP(x) \
+ (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
+#define PCIE_RC_NORMAL_BASE 0x800000
+#define PCIE_LM_BASE 0x900000
+#define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44)
+#define PCIE_LM_VENDOR_ROCKCHIP 0x1d87
+#define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300)
+#define PCIE_LM_RCBARPIE BIT(19)
+#define PCIE_LM_RCBARPIS BIT(20)
+#define PCIE_RC_BASE 0xa00000
+#define PCIE_RC_CONFIG_DCR (PCIE_RC_BASE + 0x0c4)
+#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
+#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
+#define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc)
+#define PCIE_RC_PCIE_LCAP_APMS_L0S BIT(10)
+#define PCIE_ATR_BASE 0xc00000
+#define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20)
+#define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20)
+#define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20)
+#define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20)
+#define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8)
+#define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8)
+#define PCIE_ATR_HDR_MEM 0x2
+#define PCIE_ATR_HDR_IO 0x6
+#define PCIE_ATR_HDR_CFG_TYPE0 0xa
+#define PCIE_ATR_HDR_CFG_TYPE1 0xb
+#define PCIE_ATR_HDR_RID BIT(23)
+
+#define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024)
+#define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024)
+
+struct rockchip_pcie {
+ fdt_addr_t axi_base;
+ fdt_addr_t apb_base;
+ int first_busno;
+ struct udevice *dev;
+
+ /* resets */
+ struct reset_ctl core_rst;
+ struct reset_ctl mgmt_rst;
+ struct reset_ctl mgmt_sticky_rst;
+ struct reset_ctl pipe_rst;
+ struct reset_ctl pm_rst;
+ struct reset_ctl pclk_rst;
+ struct reset_ctl aclk_rst;
+
+ /* gpio */
+ struct gpio_desc ep_gpio;
+
+ /* vpcie regulators */
+ struct udevice *vpcie12v;
+ struct udevice *vpcie3v3;
+ struct udevice *vpcie1v8;
+ struct udevice *vpcie0v9;
+
+ /* phy */
+ struct phy pcie_phy;
+};
+
static int rockchip_pcie_off_conf(pci_dev_t bdf, uint offset)
{
unsigned int bus = PCI_BUS(bdf);
diff --git a/drivers/pci/pcie_rockchip.h b/drivers/pci/pcie_rockchip.h
deleted file mode 100644
index 4b06110bfe..0000000000
--- a/drivers/pci/pcie_rockchip.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Rockchip PCIe Headers
- *
- * Copyright (c) 2016 Rockchip, Inc.
- * Copyright (c) 2020 Amarula Solutions(India)
- * Copyright (c) 2020 Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
- * Copyright (c) 2019 Patrick Wildt <patrick-Er2xLVyhcs+zQB+pC5nmwQ@public.gmane.org>
- *
- */
-
-#include <generic-phy.h>
-
-#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
-#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
-
-#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
-#define PCIE_CLIENT_BASE 0x0
-#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
-#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
-#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
-#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
-#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
-#define PCIE_CLIENT_BASIC_STATUS1 0x0048
-#define PCIE_CLIENT_LINK_STATUS_UP GENMASK(21, 20)
-#define PCIE_CLIENT_LINK_STATUS_MASK GENMASK(21, 20)
-#define PCIE_LINK_UP(x) \
- (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
-#define PCIE_RC_NORMAL_BASE 0x800000
-#define PCIE_LM_BASE 0x900000
-#define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44)
-#define PCIE_LM_VENDOR_ROCKCHIP 0x1d87
-#define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300)
-#define PCIE_LM_RCBARPIE BIT(19)
-#define PCIE_LM_RCBARPIS BIT(20)
-#define PCIE_RC_BASE 0xa00000
-#define PCIE_RC_CONFIG_DCR (PCIE_RC_BASE + 0x0c4)
-#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
-#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
-#define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc)
-#define PCIE_RC_PCIE_LCAP_APMS_L0S BIT(10)
-#define PCIE_ATR_BASE 0xc00000
-#define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20)
-#define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20)
-#define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20)
-#define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20)
-#define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8)
-#define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8)
-#define PCIE_ATR_HDR_MEM 0x2
-#define PCIE_ATR_HDR_IO 0x6
-#define PCIE_ATR_HDR_CFG_TYPE0 0xa
-#define PCIE_ATR_HDR_CFG_TYPE1 0xb
-#define PCIE_ATR_HDR_RID BIT(23)
-
-#define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024)
-#define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024)
-
-/*
- * The higher 16-bit of this register is used for write protection
- * only if BIT(x + 16) set to 1 the BIT(x) can be written.
- */
-#define HIWORD_UPDATE_MASK(val, mask, shift) \
- ((val) << (shift) | (mask) << ((shift) + 16))
-
-#define PHY_CFG_DATA_SHIFT 7
-#define PHY_CFG_ADDR_SHIFT 1
-#define PHY_CFG_DATA_MASK 0xf
-#define PHY_CFG_ADDR_MASK 0x3f
-#define PHY_CFG_RD_MASK 0x3ff
-#define PHY_CFG_WR_ENABLE 1
-#define PHY_CFG_WR_DISABLE 1
-#define PHY_CFG_WR_SHIFT 0
-#define PHY_CFG_WR_MASK 1
-#define PHY_CFG_PLL_LOCK 0x10
-#define PHY_CFG_CLK_TEST 0x10
-#define PHY_CFG_CLK_SCC 0x12
-#define PHY_CFG_SEPE_RATE BIT(3)
-#define PHY_CFG_PLL_100M BIT(3)
-#define PHY_PLL_LOCKED BIT(9)
-#define PHY_PLL_OUTPUT BIT(10)
-#define PHY_LANE_IDLE_OFF 0x1
-#define PHY_LANE_IDLE_MASK 0x1
-#define PHY_LANE_IDLE_A_SHIFT 3
-#define PHY_LANE_IDLE_B_SHIFT 4
-#define PHY_LANE_IDLE_C_SHIFT 5
-#define PHY_LANE_IDLE_D_SHIFT 6
-
-#define PCIE_PHY_CONF 0xe220
-#define PCIE_PHY_STATUS 0xe2a4
-#define PCIE_PHY_LANEOFF 0xe214
-
-struct rockchip_pcie_phy {
- void *reg_base;
- struct clk refclk;
- struct reset_ctl phy_rst;
- struct rockchip_pcie_phy_ops *ops;
-};
-
-struct rockchip_pcie_phy_ops {
- int (*init)(struct rockchip_pcie_phy *phy);
- int (*exit)(struct rockchip_pcie_phy *phy);
- int (*power_on)(struct rockchip_pcie_phy *phy);
- int (*power_off)(struct rockchip_pcie_phy *phy);
-};
-
-struct rockchip_pcie {
- fdt_addr_t axi_base;
- fdt_addr_t apb_base;
- int first_busno;
- struct udevice *dev;
- struct rockchip_pcie_phy rk_phy;
- struct rockchip_pcie_phy *phy;
-
- /* resets */
- struct reset_ctl core_rst;
- struct reset_ctl mgmt_rst;
- struct reset_ctl mgmt_sticky_rst;
- struct reset_ctl pipe_rst;
- struct reset_ctl pm_rst;
- struct reset_ctl pclk_rst;
- struct reset_ctl aclk_rst;
-
- /* gpio */
- struct gpio_desc ep_gpio;
-
- /* vpcie regulators */
- struct udevice *vpcie12v;
- struct udevice *vpcie3v3;
- struct udevice *vpcie1v8;
- struct udevice *vpcie0v9;
-
- /* phy */
- struct phy pcie_phy;
-};
-
-int rockchip_pcie_phy_get(struct udevice *dev);
-
-inline struct rockchip_pcie_phy *pcie_get_phy(struct rockchip_pcie *pcie)
-{
- return pcie->phy;
-}
-
-inline
-struct rockchip_pcie_phy_ops *phy_get_ops(struct rockchip_pcie_phy *phy)
-{
- return (struct rockchip_pcie_phy_ops *)phy->ops;
-}
diff --git a/drivers/pci/pcie_rockchip_phy.c b/drivers/pci/pcie_rockchip_phy.c
deleted file mode 100644
index 47f5d6c7e3..0000000000
--- a/drivers/pci/pcie_rockchip_phy.c
+++ /dev/null
@@ -1,205 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Rockchip PCIe PHY driver
- *
- * Copyright (c) 2016 Rockchip, Inc.
- * Copyright (c) 2020 Amarula Solutions(India)
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <dm/device_compat.h>
-#include <reset.h>
-#include <syscon.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <linux/iopoll.h>
-#include <asm/arch-rockchip/clock.h>
-
-#include "pcie_rockchip.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void phy_wr_cfg(struct rockchip_pcie_phy *phy, u32 addr, u32 data)
-{
- u32 reg;
-
- reg = HIWORD_UPDATE_MASK(data, PHY_CFG_DATA_MASK, PHY_CFG_DATA_SHIFT);
- reg |= HIWORD_UPDATE_MASK(addr, PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT);
- writel(reg, phy->reg_base + PCIE_PHY_CONF);
-
- udelay(1);
-
- reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_ENABLE,
- PHY_CFG_WR_MASK,
- PHY_CFG_WR_SHIFT);
- writel(reg, phy->reg_base + PCIE_PHY_CONF);
-
- udelay(1);
-
- reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_DISABLE,
- PHY_CFG_WR_MASK,
- PHY_CFG_WR_SHIFT);
- writel(reg, phy->reg_base + PCIE_PHY_CONF);
-}
-
-static int rockchip_pcie_phy_power_on(struct rockchip_pcie_phy *phy)
-{
- int ret = 0;
- u32 reg, status;
-
- ret = reset_deassert(&phy->phy_rst);
- if (ret) {
- dev_err(dev, "failed to assert phy reset\n");
- return ret;
- }
-
- reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK,
- PHY_CFG_ADDR_MASK,
- PHY_CFG_ADDR_SHIFT);
- writel(reg, phy->reg_base + PCIE_PHY_CONF);
-
- reg = HIWORD_UPDATE_MASK(!PHY_LANE_IDLE_OFF,
- PHY_LANE_IDLE_MASK,
- PHY_LANE_IDLE_A_SHIFT);
- writel(reg, phy->reg_base + PCIE_PHY_LANEOFF);
-
- ret = -EINVAL;
- ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
- status,
- status & PHY_PLL_LOCKED,
- 20 * 1000,
- 50);
- if (ret) {
- dev_err(&phy->dev, "pll lock timeout!\n");
- goto err_pll_lock;
- }
-
- phy_wr_cfg(phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
- phy_wr_cfg(phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
-
- ret = -ETIMEDOUT;
- ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
- status,
- !(status & PHY_PLL_OUTPUT),
- 20 * 1000,
- 50);
- if (ret) {
- dev_err(&phy->dev, "pll output enable timeout!\n");
- goto err_pll_lock;
- }
-
- reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK,
- PHY_CFG_ADDR_MASK,
- PHY_CFG_ADDR_SHIFT);
- writel(reg, phy->reg_base + PCIE_PHY_CONF);
-
- ret = -EINVAL;
- ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
- status,
- status & PHY_PLL_LOCKED,
- 20 * 1000,
- 50);
- if (ret) {
- dev_err(&phy->dev, "pll relock timeout!\n");
- goto err_pll_lock;
- }
-
- return 0;
-
-err_pll_lock:
- reset_assert(&phy->phy_rst);
- return ret;
-}
-
-static int rockchip_pcie_phy_power_off(struct rockchip_pcie_phy *phy)
-{
- int ret;
- u32 reg;
-
- reg = HIWORD_UPDATE_MASK(PHY_LANE_IDLE_OFF,
- PHY_LANE_IDLE_MASK,
- PHY_LANE_IDLE_A_SHIFT);
- writel(reg, phy->reg_base + PCIE_PHY_LANEOFF);
-
- ret = reset_assert(&phy->phy_rst);
- if (ret) {
- dev_err(dev, "failed to assert phy reset\n");
- return ret;
- }
-
- return 0;
-}
-
-static int rockchip_pcie_phy_init(struct rockchip_pcie_phy *phy)
-{
- int ret;
-
- ret = clk_enable(&phy->refclk);
- if (ret) {
- dev_err(dev, "failed to enable refclk clock\n");
- return ret;
- }
-
- ret = reset_assert(&phy->phy_rst);
- if (ret) {
- dev_err(dev, "failed to assert phy reset\n");
- goto err_reset;
- }
-
- return 0;
-
-err_reset:
- clk_disable(&phy->refclk);
- return ret;
-}
-
-static int rockchip_pcie_phy_exit(struct rockchip_pcie_phy *phy)
-{
- clk_disable(&phy->refclk);
-
- return 0;
-}
-
-static struct rockchip_pcie_phy_ops pcie_phy_ops = {
- .init = rockchip_pcie_phy_init,
- .power_on = rockchip_pcie_phy_power_on,
- .power_off = rockchip_pcie_phy_power_off,
- .exit = rockchip_pcie_phy_exit,
-};
-
-int rockchip_pcie_phy_get(struct udevice *dev)
-{
- struct rockchip_pcie *priv = dev_get_priv(dev);
- struct rockchip_pcie_phy *phy_priv = &priv->rk_phy;
- ofnode phy_node;
- u32 phandle;
- int ret;
-
- phandle = dev_read_u32_default(dev, "phys", 0);
- phy_node = ofnode_get_by_phandle(phandle);
- if (!ofnode_valid(phy_node)) {
- dev_err(dev, "failed to found pcie-phy\n");
- return -ENODEV;
- }
-
- phy_priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-
- ret = clk_get_by_index_nodev(phy_node, 0, &phy_priv->refclk);
- if (ret) {
- dev_err(dev, "failed to get refclk clock phandle\n");
- return ret;
- }
-
- ret = reset_get_by_index_nodev(phy_node, 0, &phy_priv->phy_rst);
- if (ret) {
- dev_err(dev, "failed to get phy reset phandle\n");
- return ret;
- }
-
- phy_priv->ops = &pcie_phy_ops;
- priv->phy = phy_priv;
-
- return 0;
-}
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [RFC 7/7] pci: rockchip: Drop legacy PHY driver
@ 2020-04-30 21:45 ` Jagan Teki
0 siblings, 0 replies; 16+ messages in thread
From: Jagan Teki @ 2020-04-30 21:45 UTC (permalink / raw)
To: u-boot
Drop the legacy PHY driver and it's associated code since
the PHY handling driver now part of Generic PHY framework.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/pci/Makefile | 2 +-
drivers/pci/pcie_rockchip.c | 75 +++++++++++-
drivers/pci/pcie_rockchip.h | 147 -----------------------
drivers/pci/pcie_rockchip_phy.c | 205 --------------------------------
4 files changed, 74 insertions(+), 355 deletions(-)
delete mode 100644 drivers/pci/pcie_rockchip.h
delete mode 100644 drivers/pci/pcie_rockchip_phy.c
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 955351c5c2..493e9354dd 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -43,4 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
-obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o pcie_rockchip_phy.o
+obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o
diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c
index 3e4ba9635f..cf24479f85 100644
--- a/drivers/pci/pcie_rockchip.c
+++ b/drivers/pci/pcie_rockchip.c
@@ -15,6 +15,7 @@
#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
+#include <generic-phy.h>
#include <pci.h>
#include <power-domain.h>
#include <power/regulator.h>
@@ -25,10 +26,80 @@
#include <asm/arch-rockchip/clock.h>
#include <linux/iopoll.h>
-#include "pcie_rockchip.h"
-
DECLARE_GLOBAL_DATA_PTR;
+#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
+#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
+
+#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
+#define PCIE_CLIENT_BASE 0x0
+#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
+#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
+#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
+#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
+#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
+#define PCIE_CLIENT_BASIC_STATUS1 0x0048
+#define PCIE_CLIENT_LINK_STATUS_UP GENMASK(21, 20)
+#define PCIE_CLIENT_LINK_STATUS_MASK GENMASK(21, 20)
+#define PCIE_LINK_UP(x) \
+ (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
+#define PCIE_RC_NORMAL_BASE 0x800000
+#define PCIE_LM_BASE 0x900000
+#define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44)
+#define PCIE_LM_VENDOR_ROCKCHIP 0x1d87
+#define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300)
+#define PCIE_LM_RCBARPIE BIT(19)
+#define PCIE_LM_RCBARPIS BIT(20)
+#define PCIE_RC_BASE 0xa00000
+#define PCIE_RC_CONFIG_DCR (PCIE_RC_BASE + 0x0c4)
+#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
+#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
+#define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc)
+#define PCIE_RC_PCIE_LCAP_APMS_L0S BIT(10)
+#define PCIE_ATR_BASE 0xc00000
+#define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20)
+#define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20)
+#define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20)
+#define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20)
+#define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8)
+#define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8)
+#define PCIE_ATR_HDR_MEM 0x2
+#define PCIE_ATR_HDR_IO 0x6
+#define PCIE_ATR_HDR_CFG_TYPE0 0xa
+#define PCIE_ATR_HDR_CFG_TYPE1 0xb
+#define PCIE_ATR_HDR_RID BIT(23)
+
+#define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024)
+#define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024)
+
+struct rockchip_pcie {
+ fdt_addr_t axi_base;
+ fdt_addr_t apb_base;
+ int first_busno;
+ struct udevice *dev;
+
+ /* resets */
+ struct reset_ctl core_rst;
+ struct reset_ctl mgmt_rst;
+ struct reset_ctl mgmt_sticky_rst;
+ struct reset_ctl pipe_rst;
+ struct reset_ctl pm_rst;
+ struct reset_ctl pclk_rst;
+ struct reset_ctl aclk_rst;
+
+ /* gpio */
+ struct gpio_desc ep_gpio;
+
+ /* vpcie regulators */
+ struct udevice *vpcie12v;
+ struct udevice *vpcie3v3;
+ struct udevice *vpcie1v8;
+ struct udevice *vpcie0v9;
+
+ /* phy */
+ struct phy pcie_phy;
+};
+
static int rockchip_pcie_off_conf(pci_dev_t bdf, uint offset)
{
unsigned int bus = PCI_BUS(bdf);
diff --git a/drivers/pci/pcie_rockchip.h b/drivers/pci/pcie_rockchip.h
deleted file mode 100644
index 4b06110bfe..0000000000
--- a/drivers/pci/pcie_rockchip.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Rockchip PCIe Headers
- *
- * Copyright (c) 2016 Rockchip, Inc.
- * Copyright (c) 2020 Amarula Solutions(India)
- * Copyright (c) 2020 Jagan Teki <jagan@amarulasolutions.com>
- * Copyright (c) 2019 Patrick Wildt <patrick@blueri.se>
- *
- */
-
-#include <generic-phy.h>
-
-#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
-#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
-
-#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
-#define PCIE_CLIENT_BASE 0x0
-#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
-#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
-#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
-#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
-#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
-#define PCIE_CLIENT_BASIC_STATUS1 0x0048
-#define PCIE_CLIENT_LINK_STATUS_UP GENMASK(21, 20)
-#define PCIE_CLIENT_LINK_STATUS_MASK GENMASK(21, 20)
-#define PCIE_LINK_UP(x) \
- (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
-#define PCIE_RC_NORMAL_BASE 0x800000
-#define PCIE_LM_BASE 0x900000
-#define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44)
-#define PCIE_LM_VENDOR_ROCKCHIP 0x1d87
-#define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300)
-#define PCIE_LM_RCBARPIE BIT(19)
-#define PCIE_LM_RCBARPIS BIT(20)
-#define PCIE_RC_BASE 0xa00000
-#define PCIE_RC_CONFIG_DCR (PCIE_RC_BASE + 0x0c4)
-#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
-#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
-#define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc)
-#define PCIE_RC_PCIE_LCAP_APMS_L0S BIT(10)
-#define PCIE_ATR_BASE 0xc00000
-#define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20)
-#define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20)
-#define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20)
-#define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20)
-#define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8)
-#define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8)
-#define PCIE_ATR_HDR_MEM 0x2
-#define PCIE_ATR_HDR_IO 0x6
-#define PCIE_ATR_HDR_CFG_TYPE0 0xa
-#define PCIE_ATR_HDR_CFG_TYPE1 0xb
-#define PCIE_ATR_HDR_RID BIT(23)
-
-#define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024)
-#define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024)
-
-/*
- * The higher 16-bit of this register is used for write protection
- * only if BIT(x + 16) set to 1 the BIT(x) can be written.
- */
-#define HIWORD_UPDATE_MASK(val, mask, shift) \
- ((val) << (shift) | (mask) << ((shift) + 16))
-
-#define PHY_CFG_DATA_SHIFT 7
-#define PHY_CFG_ADDR_SHIFT 1
-#define PHY_CFG_DATA_MASK 0xf
-#define PHY_CFG_ADDR_MASK 0x3f
-#define PHY_CFG_RD_MASK 0x3ff
-#define PHY_CFG_WR_ENABLE 1
-#define PHY_CFG_WR_DISABLE 1
-#define PHY_CFG_WR_SHIFT 0
-#define PHY_CFG_WR_MASK 1
-#define PHY_CFG_PLL_LOCK 0x10
-#define PHY_CFG_CLK_TEST 0x10
-#define PHY_CFG_CLK_SCC 0x12
-#define PHY_CFG_SEPE_RATE BIT(3)
-#define PHY_CFG_PLL_100M BIT(3)
-#define PHY_PLL_LOCKED BIT(9)
-#define PHY_PLL_OUTPUT BIT(10)
-#define PHY_LANE_IDLE_OFF 0x1
-#define PHY_LANE_IDLE_MASK 0x1
-#define PHY_LANE_IDLE_A_SHIFT 3
-#define PHY_LANE_IDLE_B_SHIFT 4
-#define PHY_LANE_IDLE_C_SHIFT 5
-#define PHY_LANE_IDLE_D_SHIFT 6
-
-#define PCIE_PHY_CONF 0xe220
-#define PCIE_PHY_STATUS 0xe2a4
-#define PCIE_PHY_LANEOFF 0xe214
-
-struct rockchip_pcie_phy {
- void *reg_base;
- struct clk refclk;
- struct reset_ctl phy_rst;
- struct rockchip_pcie_phy_ops *ops;
-};
-
-struct rockchip_pcie_phy_ops {
- int (*init)(struct rockchip_pcie_phy *phy);
- int (*exit)(struct rockchip_pcie_phy *phy);
- int (*power_on)(struct rockchip_pcie_phy *phy);
- int (*power_off)(struct rockchip_pcie_phy *phy);
-};
-
-struct rockchip_pcie {
- fdt_addr_t axi_base;
- fdt_addr_t apb_base;
- int first_busno;
- struct udevice *dev;
- struct rockchip_pcie_phy rk_phy;
- struct rockchip_pcie_phy *phy;
-
- /* resets */
- struct reset_ctl core_rst;
- struct reset_ctl mgmt_rst;
- struct reset_ctl mgmt_sticky_rst;
- struct reset_ctl pipe_rst;
- struct reset_ctl pm_rst;
- struct reset_ctl pclk_rst;
- struct reset_ctl aclk_rst;
-
- /* gpio */
- struct gpio_desc ep_gpio;
-
- /* vpcie regulators */
- struct udevice *vpcie12v;
- struct udevice *vpcie3v3;
- struct udevice *vpcie1v8;
- struct udevice *vpcie0v9;
-
- /* phy */
- struct phy pcie_phy;
-};
-
-int rockchip_pcie_phy_get(struct udevice *dev);
-
-inline struct rockchip_pcie_phy *pcie_get_phy(struct rockchip_pcie *pcie)
-{
- return pcie->phy;
-}
-
-inline
-struct rockchip_pcie_phy_ops *phy_get_ops(struct rockchip_pcie_phy *phy)
-{
- return (struct rockchip_pcie_phy_ops *)phy->ops;
-}
diff --git a/drivers/pci/pcie_rockchip_phy.c b/drivers/pci/pcie_rockchip_phy.c
deleted file mode 100644
index 47f5d6c7e3..0000000000
--- a/drivers/pci/pcie_rockchip_phy.c
+++ /dev/null
@@ -1,205 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Rockchip PCIe PHY driver
- *
- * Copyright (c) 2016 Rockchip, Inc.
- * Copyright (c) 2020 Amarula Solutions(India)
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <dm/device_compat.h>
-#include <reset.h>
-#include <syscon.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <linux/iopoll.h>
-#include <asm/arch-rockchip/clock.h>
-
-#include "pcie_rockchip.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void phy_wr_cfg(struct rockchip_pcie_phy *phy, u32 addr, u32 data)
-{
- u32 reg;
-
- reg = HIWORD_UPDATE_MASK(data, PHY_CFG_DATA_MASK, PHY_CFG_DATA_SHIFT);
- reg |= HIWORD_UPDATE_MASK(addr, PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT);
- writel(reg, phy->reg_base + PCIE_PHY_CONF);
-
- udelay(1);
-
- reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_ENABLE,
- PHY_CFG_WR_MASK,
- PHY_CFG_WR_SHIFT);
- writel(reg, phy->reg_base + PCIE_PHY_CONF);
-
- udelay(1);
-
- reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_DISABLE,
- PHY_CFG_WR_MASK,
- PHY_CFG_WR_SHIFT);
- writel(reg, phy->reg_base + PCIE_PHY_CONF);
-}
-
-static int rockchip_pcie_phy_power_on(struct rockchip_pcie_phy *phy)
-{
- int ret = 0;
- u32 reg, status;
-
- ret = reset_deassert(&phy->phy_rst);
- if (ret) {
- dev_err(dev, "failed to assert phy reset\n");
- return ret;
- }
-
- reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK,
- PHY_CFG_ADDR_MASK,
- PHY_CFG_ADDR_SHIFT);
- writel(reg, phy->reg_base + PCIE_PHY_CONF);
-
- reg = HIWORD_UPDATE_MASK(!PHY_LANE_IDLE_OFF,
- PHY_LANE_IDLE_MASK,
- PHY_LANE_IDLE_A_SHIFT);
- writel(reg, phy->reg_base + PCIE_PHY_LANEOFF);
-
- ret = -EINVAL;
- ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
- status,
- status & PHY_PLL_LOCKED,
- 20 * 1000,
- 50);
- if (ret) {
- dev_err(&phy->dev, "pll lock timeout!\n");
- goto err_pll_lock;
- }
-
- phy_wr_cfg(phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
- phy_wr_cfg(phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
-
- ret = -ETIMEDOUT;
- ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
- status,
- !(status & PHY_PLL_OUTPUT),
- 20 * 1000,
- 50);
- if (ret) {
- dev_err(&phy->dev, "pll output enable timeout!\n");
- goto err_pll_lock;
- }
-
- reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK,
- PHY_CFG_ADDR_MASK,
- PHY_CFG_ADDR_SHIFT);
- writel(reg, phy->reg_base + PCIE_PHY_CONF);
-
- ret = -EINVAL;
- ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
- status,
- status & PHY_PLL_LOCKED,
- 20 * 1000,
- 50);
- if (ret) {
- dev_err(&phy->dev, "pll relock timeout!\n");
- goto err_pll_lock;
- }
-
- return 0;
-
-err_pll_lock:
- reset_assert(&phy->phy_rst);
- return ret;
-}
-
-static int rockchip_pcie_phy_power_off(struct rockchip_pcie_phy *phy)
-{
- int ret;
- u32 reg;
-
- reg = HIWORD_UPDATE_MASK(PHY_LANE_IDLE_OFF,
- PHY_LANE_IDLE_MASK,
- PHY_LANE_IDLE_A_SHIFT);
- writel(reg, phy->reg_base + PCIE_PHY_LANEOFF);
-
- ret = reset_assert(&phy->phy_rst);
- if (ret) {
- dev_err(dev, "failed to assert phy reset\n");
- return ret;
- }
-
- return 0;
-}
-
-static int rockchip_pcie_phy_init(struct rockchip_pcie_phy *phy)
-{
- int ret;
-
- ret = clk_enable(&phy->refclk);
- if (ret) {
- dev_err(dev, "failed to enable refclk clock\n");
- return ret;
- }
-
- ret = reset_assert(&phy->phy_rst);
- if (ret) {
- dev_err(dev, "failed to assert phy reset\n");
- goto err_reset;
- }
-
- return 0;
-
-err_reset:
- clk_disable(&phy->refclk);
- return ret;
-}
-
-static int rockchip_pcie_phy_exit(struct rockchip_pcie_phy *phy)
-{
- clk_disable(&phy->refclk);
-
- return 0;
-}
-
-static struct rockchip_pcie_phy_ops pcie_phy_ops = {
- .init = rockchip_pcie_phy_init,
- .power_on = rockchip_pcie_phy_power_on,
- .power_off = rockchip_pcie_phy_power_off,
- .exit = rockchip_pcie_phy_exit,
-};
-
-int rockchip_pcie_phy_get(struct udevice *dev)
-{
- struct rockchip_pcie *priv = dev_get_priv(dev);
- struct rockchip_pcie_phy *phy_priv = &priv->rk_phy;
- ofnode phy_node;
- u32 phandle;
- int ret;
-
- phandle = dev_read_u32_default(dev, "phys", 0);
- phy_node = ofnode_get_by_phandle(phandle);
- if (!ofnode_valid(phy_node)) {
- dev_err(dev, "failed to found pcie-phy\n");
- return -ENODEV;
- }
-
- phy_priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-
- ret = clk_get_by_index_nodev(phy_node, 0, &phy_priv->refclk);
- if (ret) {
- dev_err(dev, "failed to get refclk clock phandle\n");
- return ret;
- }
-
- ret = reset_get_by_index_nodev(phy_node, 0, &phy_priv->phy_rst);
- if (ret) {
- dev_err(dev, "failed to get phy reset phandle\n");
- return ret;
- }
-
- phy_priv->ops = &pcie_phy_ops;
- priv->phy = phy_priv;
-
- return 0;
-}
--
2.17.1
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