* [PATCH 01/13] net: fsl_pq_mdio: Add the compatible "fsl, gianfar-mdio" support
2020-05-05 11:38 [PATCH 00/13] powerpc: covert p1010, p1020 and p2020 RDB board Zhiqiang Hou
@ 2020-05-05 11:38 ` Zhiqiang Hou
2020-06-03 6:52 ` Priyanka Jain
2020-05-05 11:38 ` [PATCH 02/13] net: tsec: Add the compatible string "gianfar" support Zhiqiang Hou
` (11 subsequent siblings)
12 siblings, 1 reply; 16+ messages in thread
From: Zhiqiang Hou @ 2020-05-05 11:38 UTC (permalink / raw)
To: u-boot
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Add compatible string "fsl,gianfar-mdio" support and update the
device-tree-bindings doc.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
doc/device-tree-bindings/net/fsl-tsec-phy.txt | 3 ++-
drivers/net/fsl_mdio.c | 15 +++++++++++++--
include/fsl_mdio.h | 4 ++++
3 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/doc/device-tree-bindings/net/fsl-tsec-phy.txt b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
index 8e8574bc97..a709b89a5c 100644
--- a/doc/device-tree-bindings/net/fsl-tsec-phy.txt
+++ b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
@@ -28,7 +28,8 @@ device that exists on this bus, a PHY node should be created.
Required properties:
- compatible : Should define the compatible device type for the
- mdio. Currently supported string/device is "fsl,etsec2-mdio".
+ mdio. Currently supported string/device is "fsl,etsec2-mdio" and
+ "fsl,gianfar-mdio".
- reg : Offset and length of the register set for the device
Example:
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index 284508062c..ea9c37ad19 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -138,10 +138,12 @@ static int dm_fsl_pq_mdio_write(struct udevice *dev, int addr, int devad,
static int fsl_pq_mdio_probe(struct udevice *dev)
{
struct fsl_pq_mdio_info *info = dev_get_priv(dev);
+ struct fsl_pq_mdio_data *data;
fdt_addr_t reg;
+ data = (struct fsl_pq_mdio_data *)dev_get_driver_data(dev);
reg = devfdt_get_addr(dev);
- info->regs = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0, MAP_NOCACHE);
+ info->regs = map_physmem(reg + data->mdio_regs_off, 0, MAP_NOCACHE);
return fsl_pq_mdio_reset(info->regs);
}
@@ -151,8 +153,17 @@ static const struct mdio_ops fsl_pq_mdio_ops = {
.write = dm_fsl_pq_mdio_write,
};
+static struct fsl_pq_mdio_data etsec2_data = {
+ .mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
+};
+
+static struct fsl_pq_mdio_data gianfar_data = {
+ .mdio_regs_off = 0x0,
+};
+
static const struct udevice_id fsl_pq_mdio_ids[] = {
- { .compatible = "fsl,etsec2-mdio" },
+ { .compatible = "fsl,etsec2-mdio", .data = (ulong)&etsec2_data },
+ { .compatible = "fsl,gianfar-mdio", .data = (ulong)&gianfar_data },
{ }
};
diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h
index 386c477a8b..80e3100cda 100644
--- a/include/fsl_mdio.h
+++ b/include/fsl_mdio.h
@@ -53,6 +53,10 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
int regnum);
int memac_mdio_reset(struct mii_dev *bus);
+struct fsl_pq_mdio_data {
+ u32 mdio_regs_off;
+};
+
struct fsl_pq_mdio_info {
struct tsec_mii_mng __iomem *regs;
char *name;
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 01/13] net: fsl_pq_mdio: Add the compatible "fsl, gianfar-mdio" support
2020-05-05 11:38 ` [PATCH 01/13] net: fsl_pq_mdio: Add the compatible "fsl, gianfar-mdio" support Zhiqiang Hou
@ 2020-06-03 6:52 ` Priyanka Jain
2020-06-03 7:02 ` Z.q. Hou
0 siblings, 1 reply; 16+ messages in thread
From: Priyanka Jain @ 2020-06-03 6:52 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Zhiqiang Hou
>Sent: Tuesday, May 5, 2020 5:08 PM
>To: u-boot at lists.denx.de; bmeng.cn at gmail.com; olteanv at gmail.com;
>Priyanka Jain <priyanka.jain@nxp.com>
>Cc: Z.q. Hou <zhiqiang.hou@nxp.com>
>Subject: [PATCH 01/13] net: fsl_pq_mdio: Add the compatible "fsl, gianfar-
>mdio" support
>
>From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
>Add compatible string "fsl,gianfar-mdio" support and update the device-tree-
>bindings doc.
>
>Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>---
<snip>
Kindly rebase this series on top of
https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
branch:next
Regards
Priyanka
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 01/13] net: fsl_pq_mdio: Add the compatible "fsl, gianfar-mdio" support
2020-06-03 6:52 ` Priyanka Jain
@ 2020-06-03 7:02 ` Z.q. Hou
0 siblings, 0 replies; 16+ messages in thread
From: Z.q. Hou @ 2020-06-03 7:02 UTC (permalink / raw)
To: u-boot
Hi Priyanka,
Thanks a lot for your comments!
> -----Original Message-----
> From: Priyanka Jain (OSS)
> Sent: 2020?6?3? 14:53
> To: Z.q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de;
> bmeng.cn at gmail.com; olteanv at gmail.com
> Cc: Z.q. Hou <zhiqiang.hou@nxp.com>
> Subject: RE: [PATCH 01/13] net: fsl_pq_mdio: Add the compatible "fsl,
> gianfar-mdio" support
>
> >-----Original Message-----
> >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Zhiqiang Hou
> >Sent: Tuesday, May 5, 2020 5:08 PM
> >To: u-boot at lists.denx.de; bmeng.cn at gmail.com; olteanv at gmail.com;
> >Priyanka Jain <priyanka.jain@nxp.com>
> >Cc: Z.q. Hou <zhiqiang.hou@nxp.com>
> >Subject: [PATCH 01/13] net: fsl_pq_mdio: Add the compatible "fsl,
> >gianfar- mdio" support
> >
> >From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> >Add compatible string "fsl,gianfar-mdio" support and update the
> >device-tree- bindings doc.
> >
> >Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >---
> <snip>
>
> Kindly rebase this series on top of
> https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
> branch:next
Yes, I'll.
Thanks,
Zhiqiang
>
> Regards
> Priyanka
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 02/13] net: tsec: Add the compatible string "gianfar" support
2020-05-05 11:38 [PATCH 00/13] powerpc: covert p1010, p1020 and p2020 RDB board Zhiqiang Hou
2020-05-05 11:38 ` [PATCH 01/13] net: fsl_pq_mdio: Add the compatible "fsl, gianfar-mdio" support Zhiqiang Hou
@ 2020-05-05 11:38 ` Zhiqiang Hou
2020-05-05 11:38 ` [PATCH 03/13] powerpc: mpc8xxx: Don't compile cpu_eth_init() when DM_ETH enabled Zhiqiang Hou
` (10 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Zhiqiang Hou @ 2020-05-05 11:38 UTC (permalink / raw)
To: u-boot
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Add compatible string "gianfar" support and update the
device-tree-bindings doc.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
doc/device-tree-bindings/net/fsl-tsec-phy.txt | 2 +-
drivers/net/tsec.c | 16 ++++++++++++++--
include/tsec.h | 4 ++++
3 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/doc/device-tree-bindings/net/fsl-tsec-phy.txt b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
index a709b89a5c..fae6770cbe 100644
--- a/doc/device-tree-bindings/net/fsl-tsec-phy.txt
+++ b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
@@ -2,7 +2,7 @@
Properties:
- - compatible : Should be "fsl,etsec2"
+ - compatible : Should be "fsl,etsec2" or "gianfar"
- reg : Offset and length of the register set for the device
- phy-handle : See ethernet.txt file in the same directory.
- phy-connection-type : See ethernet.txt file in the same directory. This
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 93f151a8a6..f7c70bb08d 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -804,11 +804,14 @@ int tsec_probe(struct udevice *dev)
struct tsec_private *priv = dev_get_priv(dev);
struct ofnode_phandle_args phandle_args;
u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
+ struct tsec_data *data;
const char *phy_mode;
fdt_addr_t reg;
ofnode parent;
int ret;
+ data = (struct tsec_data *)dev_get_driver_data(dev);
+
pdata->iobase = (phys_addr_t)dev_read_addr(dev);
priv->regs = dev_remap_addr(dev);
@@ -829,7 +832,7 @@ int tsec_probe(struct udevice *dev)
return -ENOENT;
}
- priv->phyregs_sgmii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET,
+ priv->phyregs_sgmii = map_physmem(reg + data->mdio_regs_off,
0, MAP_NOCACHE);
}
@@ -883,8 +886,17 @@ static const struct eth_ops tsec_ops = {
.mcast = tsec_mcast_addr,
};
+static struct tsec_data etsec2_data = {
+ .mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
+};
+
+static struct tsec_data gianfar_data = {
+ .mdio_regs_off = 0x0,
+};
+
static const struct udevice_id tsec_ids[] = {
- { .compatible = "fsl,etsec2" },
+ { .compatible = "fsl,etsec2", .data = (ulong)&etsec2_data },
+ { .compatible = "gianfar", .data = (ulong)&gianfar_data },
{ }
};
diff --git a/include/tsec.h b/include/tsec.h
index b17fa957df..047dd3c373 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -394,6 +394,10 @@ struct tsec {
#define TX_BUF_CNT 2
+struct tsec_data {
+ u32 mdio_regs_off;
+};
+
struct tsec_private {
struct txbd8 __iomem txbd[TX_BUF_CNT];
struct rxbd8 __iomem rxbd[PKTBUFSRX];
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 03/13] powerpc: mpc8xxx: Don't compile cpu_eth_init() when DM_ETH enabled
2020-05-05 11:38 [PATCH 00/13] powerpc: covert p1010, p1020 and p2020 RDB board Zhiqiang Hou
2020-05-05 11:38 ` [PATCH 01/13] net: fsl_pq_mdio: Add the compatible "fsl, gianfar-mdio" support Zhiqiang Hou
2020-05-05 11:38 ` [PATCH 02/13] net: tsec: Add the compatible string "gianfar" support Zhiqiang Hou
@ 2020-05-05 11:38 ` Zhiqiang Hou
2020-05-05 11:38 ` [PATCH 04/13] fsl: p1_p2_rdb: Move vsc7835 firmware uploading to board_early_init_r() Zhiqiang Hou
` (9 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Zhiqiang Hou @ 2020-05-05 11:38 UTC (permalink / raw)
To: u-boot
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
The cpu_eth_init() is only used by the legacy ethernet driver framework.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
arch/powerpc/cpu/mpc8xxx/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index ed482a9c09..d41d6a6110 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -345,6 +345,7 @@ int fixup_cpu(void)
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
+#ifndef CONFIG_DM_ETH
int cpu_eth_init(bd_t *bis)
{
#if defined(CONFIG_ETHER_ON_FCC)
@@ -368,3 +369,4 @@ int cpu_eth_init(bd_t *bis)
#endif
return 0;
}
+#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 04/13] fsl: p1_p2_rdb: Move vsc7835 firmware uploading to board_early_init_r()
2020-05-05 11:38 [PATCH 00/13] powerpc: covert p1010, p1020 and p2020 RDB board Zhiqiang Hou
` (2 preceding siblings ...)
2020-05-05 11:38 ` [PATCH 03/13] powerpc: mpc8xxx: Don't compile cpu_eth_init() when DM_ETH enabled Zhiqiang Hou
@ 2020-05-05 11:38 ` Zhiqiang Hou
2020-05-05 11:38 ` [PATCH 05/13] configs: p1_p2_rdb: Add the default address of vsc7385 firmware Zhiqiang Hou
` (8 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Zhiqiang Hou @ 2020-05-05 11:38 UTC (permalink / raw)
To: u-boot
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Move vsc7835 firmware uploading to board_early_init_r(), so that
the switch also can work in DM eTSEC driver.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 35 +++++++++++----------
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 71fca8ca1e..890abd76b5 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -291,6 +291,10 @@ int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
+#ifdef CONFIG_VSC7385_ENET
+ unsigned int vscfw_addr;
+ char *tmp;
+#endif
/*
* Remap Boot flash region to caching-inhibited
@@ -313,6 +317,20 @@ int board_early_init_r(void)
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
+
+#ifdef CONFIG_VSC7385_ENET
+ /* If a VSC7385 microcode image is present, then upload it. */
+ tmp = env_get("vscfw_addr");
+ if (tmp) {
+ vscfw_addr = simple_strtoul(tmp, NULL, 16);
+ printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
+ if (vsc7385_upload_firmware((void *)vscfw_addr,
+ CONFIG_VSC7385_IMAGE_SIZE))
+ puts("Failure uploading VSC7385 microcode.\n");
+ } else {
+ puts("No address specified for VSC7385 microcode.\n");
+ }
+#endif
return 0;
}
@@ -323,10 +341,6 @@ int board_eth_init(bd_t *bis)
ccsr_gur_t *gur __attribute__((unused)) =
(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int num = 0;
-#ifdef CONFIG_VSC7385_ENET
- char *tmp;
- unsigned int vscfw_addr;
-#endif
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
@@ -350,19 +364,6 @@ int board_eth_init(bd_t *bis)
return 0;
}
-#ifdef CONFIG_VSC7385_ENET
- /* If a VSC7385 microcode image is present, then upload it. */
- tmp = env_get("vscfw_addr");
- if (tmp) {
- vscfw_addr = simple_strtoul(tmp, NULL, 16);
- printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
- if (vsc7385_upload_firmware((void *) vscfw_addr,
- CONFIG_VSC7385_IMAGE_SIZE))
- puts("Failure uploading VSC7385 microcode.\n");
- } else
- puts("No address specified for VSC7385 microcode.\n");
-#endif
-
mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
mdio_info.name = DEFAULT_MII_NAME;
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 05/13] configs: p1_p2_rdb: Add the default address of vsc7385 firmware
2020-05-05 11:38 [PATCH 00/13] powerpc: covert p1010, p1020 and p2020 RDB board Zhiqiang Hou
` (3 preceding siblings ...)
2020-05-05 11:38 ` [PATCH 04/13] fsl: p1_p2_rdb: Move vsc7835 firmware uploading to board_early_init_r() Zhiqiang Hou
@ 2020-05-05 11:38 ` Zhiqiang Hou
2020-05-05 11:38 ` [PATCH 06/13] dts: powerpc: p1020rdb: Add eTSEC DT nodes Zhiqiang Hou
` (7 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Zhiqiang Hou @ 2020-05-05 11:38 UTC (permalink / raw)
To: u-boot
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Add the environment 'vscfw_addr' to assign a default address for
vsc7385 firmware uploading.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
include/configs/p1_p2_rdb_pc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index c42f1a9fce..b2fdf47104 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -460,6 +460,7 @@
/* Vsc7385 switch */
#ifdef CONFIG_VSC7385_ENET
+#define __VSCFW_ADDR "vscfw_addr=ef000000"
#define CONFIG_SYS_VSC7385_BASE 0xffb00000
#ifdef CONFIG_PHYS_64BIT
@@ -813,6 +814,7 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset
"ramdisk_size=120000\0" \
"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
+__stringify(__VSCFW_ADDR)"\0" \
__stringify(__NOR_RST_CMD)"\0" \
__stringify(__SPI_RST_CMD)"\0" \
__stringify(__SD_RST_CMD)"\0" \
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 06/13] dts: powerpc: p1020rdb: Add eTSEC DT nodes
2020-05-05 11:38 [PATCH 00/13] powerpc: covert p1010, p1020 and p2020 RDB board Zhiqiang Hou
` (4 preceding siblings ...)
2020-05-05 11:38 ` [PATCH 05/13] configs: p1_p2_rdb: Add the default address of vsc7385 firmware Zhiqiang Hou
@ 2020-05-05 11:38 ` Zhiqiang Hou
2020-05-05 11:38 ` [PATCH 07/13] powerpc: p1_p2_rdb: Don't compile board_eth_init() when DM_ETH enabled Zhiqiang Hou
` (6 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Zhiqiang Hou @ 2020-05-05 11:38 UTC (permalink / raw)
To: u-boot
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
P1020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII PHY VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
arch/powerpc/dts/p1020-post.dtsi | 15 +++++++
arch/powerpc/dts/p1020rdb-pc.dts | 1 +
arch/powerpc/dts/p1020rdb-pc.dtsi | 55 ++++++++++++++++++++++++
arch/powerpc/dts/p1020rdb-pc_36b.dts | 1 +
arch/powerpc/dts/p1020rdb-pd.dts | 57 +++++++++++++++++++++++++
arch/powerpc/dts/pq3-etsec2-0.dtsi | 35 +++++++++++++++
arch/powerpc/dts/pq3-etsec2-1.dtsi | 35 +++++++++++++++
arch/powerpc/dts/pq3-etsec2-2.dtsi | 35 +++++++++++++++
arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi | 16 +++++++
arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi | 16 +++++++
arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi | 16 +++++++
11 files changed, 282 insertions(+)
create mode 100644 arch/powerpc/dts/p1020rdb-pc.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-0.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-1.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-2.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi
diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi
index 1c77702f01..d7b10a9ae9 100644
--- a/arch/powerpc/dts/p1020-post.dtsi
+++ b/arch/powerpc/dts/p1020-post.dtsi
@@ -44,8 +44,23 @@
clock-frequency = <0>;
};
+/include/ "pq3-etsec2-0.dtsi"
+ enet0: enet0_grp2: ethernet at b0000 {
+ };
+
+/include/ "pq3-etsec2-1.dtsi"
+ enet1: enet1_grp2: ethernet at b1000 {
+ };
+
+/include/ "pq3-etsec2-2.dtsi"
+ enet2: enet2_grp2: ethernet at b2000 {
+ };
};
+/include/ "pq3-etsec2-grp2-0.dtsi"
+/include/ "pq3-etsec2-grp2-1.dtsi"
+/include/ "pq3-etsec2-grp2-2.dtsi"
+
/* PCIe controller base address 0x9000 */
&pci1 {
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts
index 7ebaa619df..715330dc50 100644
--- a/arch/powerpc/dts/p1020rdb-pc.dts
+++ b/arch/powerpc/dts/p1020rdb-pc.dts
@@ -32,4 +32,5 @@
};
};
+/include/ "p1020rdb-pc.dtsi"
/include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pc.dtsi b/arch/powerpc/dts/p1020rdb-pc.dtsi
new file mode 100644
index 0000000000..6bf424fd3f
--- /dev/null
+++ b/arch/powerpc/dts/p1020rdb-pc.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&soc {
+ mdio at 24000 {
+ phy0: ethernet-phy at 0 {
+ interrupt-parent = <&mpic>;
+ interrupts = <3 1 0 0>;
+ reg = <0x0>;
+ };
+
+ phy1: ethernet-phy at 1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <2 1 0 0>;
+ reg = <0x1>;
+ };
+
+ tbi0: tbi-phy at 11 {
+ device_type = "tbi-phy";
+ reg = <0x11>;
+ };
+ };
+
+ mdio at 25000 {
+ tbi1: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet0: ethernet at b0000 {
+ phy-connection-type = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+
+ };
+
+ enet1: ethernet at b1000 {
+ phy-handle = <&phy0>;
+ tbi-handle = <&tbi1>;
+ phy-connection-type = "sgmii";
+ };
+
+ enet2: ethernet at b2000 {
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+ };
+};
diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts b/arch/powerpc/dts/p1020rdb-pc_36b.dts
index c0e5ef4cf4..7680b7c7e1 100644
--- a/arch/powerpc/dts/p1020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts
@@ -32,4 +32,5 @@
};
};
+/include/ "p1020rdb-pc.dtsi"
/include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts
index 21174a09be..7868c9b95c 100644
--- a/arch/powerpc/dts/p1020rdb-pd.dts
+++ b/arch/powerpc/dts/p1020rdb-pd.dts
@@ -17,6 +17,63 @@
soc: soc at ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+ mdio at 24000 {
+ phy0: ethernet-phy at 0 {
+ interrupts = <3 1 0 0>;
+ reg = <0x0>;
+ };
+
+ phy1: ethernet-phy at 1 {
+ interrupts = <2 1 0 0>;
+ reg = <0x1>;
+ };
+ };
+
+ mdio at 25000 {
+ tbi1: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ mdio at 26000 {
+ tbi2: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ ptp_clock at b0e00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0xb0e00 0xb0>;
+ interrupts = <68 2 0 0 69 2 0 0>;
+ fsl,tclk-period = <10>;
+ fsl,tmr-prsc = <2>;
+ fsl,tmr-add = <0x80000016>;
+ fsl,tmr-fiper1 = <999999990>;
+ fsl,tmr-fiper2 = <99990>;
+ fsl,max-adj = <199999999>;
+ };
+
+ enet0: ethernet at b0000 {
+ phy-connection-type = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ enet1: ethernet at b1000 {
+ phy-handle = <&phy0>;
+ tbi-handle = <&tbi1>;
+ phy-connection-type = "sgmii";
+ };
+
+ enet2: ethernet at b2000 {
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+ };
};
pci1: pcie at ffe09000 {
diff --git a/arch/powerpc/dts/pq3-etsec2-0.dtsi b/arch/powerpc/dts/pq3-etsec2-0.dtsi
new file mode 100644
index 0000000000..f9d3d04650
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec2-0.dtsi
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 device tree stub [ @ offsets 0x24000/0xb0000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+mdio at 24000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,etsec2-mdio";
+ reg = <0x24000 0x1000 0xb0030 0x4>;
+};
+
+ethernet at b0000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ reg = <0xb0000 0x1000>;
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ fsl,magic-packet;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ ranges;
+
+ queue-group at b0000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb0000 0x1000>;
+ interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
+ };
+};
diff --git a/arch/powerpc/dts/pq3-etsec2-1.dtsi b/arch/powerpc/dts/pq3-etsec2-1.dtsi
new file mode 100644
index 0000000000..6c01481909
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec2-1.dtsi
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 device tree stub [ @ offsets 0x25000/0xb1000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+mdio at 25000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,etsec2-tbi";
+ reg = <0x25000 0x1000 0xb1030 0x4>;
+};
+
+ethernet at b1000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ reg = <0xb1000 0x1000>;
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ fsl,magic-packet;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ ranges;
+
+ queue-group at b1000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb1000 0x1000>;
+ interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
+ };
+};
diff --git a/arch/powerpc/dts/pq3-etsec2-2.dtsi b/arch/powerpc/dts/pq3-etsec2-2.dtsi
new file mode 100644
index 0000000000..2a597c0db6
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec2-2.dtsi
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 device tree stub [ @ offsets 0x26000/0xb2000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+mdio at 26000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,etsec2-tbi";
+ reg = <0x26000 0x1000 0xb1030 0x4>;
+};
+
+ethernet at b2000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ reg = <0xb2000 0x1000>;
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ fsl,magic-packet;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ ranges;
+
+ queue-group at b2000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb2000 0x1000>;
+ interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
+ };
+};
diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi
new file mode 100644
index 0000000000..16752a7c45
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb4000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&enet0_grp2 {
+ queue-group at b4000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb4000 0x1000>;
+ interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
+ };
+};
diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi
new file mode 100644
index 0000000000..0464938424
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb5000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&enet1_grp2 {
+ queue-group at b5000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb5000 0x1000>;
+ interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
+ };
+};
diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi
new file mode 100644
index 0000000000..fe8003c44a
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb6000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&enet2_grp2 {
+ queue-group at b6000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb6000 0x1000>;
+ interrupts = <25 2 0 0 26 2 0 0 27 2 0 0>;
+ };
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 07/13] powerpc: p1_p2_rdb: Don't compile board_eth_init() when DM_ETH enabled
2020-05-05 11:38 [PATCH 00/13] powerpc: covert p1010, p1020 and p2020 RDB board Zhiqiang Hou
` (5 preceding siblings ...)
2020-05-05 11:38 ` [PATCH 06/13] dts: powerpc: p1020rdb: Add eTSEC DT nodes Zhiqiang Hou
@ 2020-05-05 11:38 ` Zhiqiang Hou
2020-05-05 11:38 ` [PATCH 08/13] configs: P1020RDB: Enable DM_ETH config Zhiqiang Hou
` (5 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Zhiqiang Hou @ 2020-05-05 11:38 UTC (permalink / raw)
To: u-boot
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 890abd76b5..5349df5910 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -334,6 +334,7 @@ int board_early_init_r(void)
return 0;
}
+#ifndef CONFIG_DM_ETH
int board_eth_init(bd_t *bis)
{
struct fsl_pq_mdio_info mdio_info;
@@ -381,6 +382,7 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);
}
+#endif
#if defined(CONFIG_QE) && \
(defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 08/13] configs: P1020RDB: Enable DM_ETH config
2020-05-05 11:38 [PATCH 00/13] powerpc: covert p1010, p1020 and p2020 RDB board Zhiqiang Hou
` (6 preceding siblings ...)
2020-05-05 11:38 ` [PATCH 07/13] powerpc: p1_p2_rdb: Don't compile board_eth_init() when DM_ETH enabled Zhiqiang Hou
@ 2020-05-05 11:38 ` Zhiqiang Hou
2020-05-05 11:38 ` [PATCH 09/13] dts: powerpc: p1010rdb: Add eTSEC DT nodes Zhiqiang Hou
` (4 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Zhiqiang Hou @ 2020-05-05 11:38 UTC (permalink / raw)
To: u-boot
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Enable the DM_ETH and DM_MDIO config.
On P1020RDB, the eTSEC1 is connecting with a switch VSC7385,
so also enable the fixed PHY support.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 +++
configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 3 +++
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 3 +++
configs/P1020RDB-PC_36BIT_defconfig | 3 +++
configs/P1020RDB-PC_NAND_defconfig | 3 +++
configs/P1020RDB-PC_SDCARD_defconfig | 3 +++
configs/P1020RDB-PC_SPIFLASH_defconfig | 3 +++
configs/P1020RDB-PC_defconfig | 3 +++
configs/P1020RDB-PD_NAND_defconfig | 3 +++
configs/P1020RDB-PD_SDCARD_defconfig | 3 +++
configs/P1020RDB-PD_SPIFLASH_defconfig | 3 +++
configs/P1020RDB-PD_defconfig | 3 +++
12 files changed, 36 insertions(+)
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 2396d91011..847dad4072 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -61,6 +61,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@@ -72,8 +73,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index 745200da51..a3f8761c9b 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -56,6 +56,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@@ -67,8 +68,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index 3eadd3d83c..da3e2b3563 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -58,6 +58,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@@ -69,8 +70,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index 9b7901f5c3..5c6281ef11 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -45,6 +45,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@@ -56,8 +57,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index e99709a2b8..78948e4a06 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -60,6 +60,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@@ -71,8 +72,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index ef007e5fe4..0518083cd9 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -55,6 +55,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@@ -66,8 +67,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index c8b0923cb5..284ef2c55a 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -57,6 +57,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@@ -68,8 +69,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index 1a30c97f7f..a3a4979f45 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -44,6 +44,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@@ -55,8 +56,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index e1858e4cac..d3b7a5e23c 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -64,6 +64,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@@ -75,8 +76,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index e24c89f726..3f28607428 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -59,6 +59,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@@ -70,8 +71,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index c89201f978..e9fa7b8d2f 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -61,6 +61,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@@ -72,8 +73,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index c79d599b60..856ee4f7d0 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -48,6 +48,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@@ -59,8 +60,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 09/13] dts: powerpc: p1010rdb: Add eTSEC DT nodes
2020-05-05 11:38 [PATCH 00/13] powerpc: covert p1010, p1020 and p2020 RDB board Zhiqiang Hou
` (7 preceding siblings ...)
2020-05-05 11:38 ` [PATCH 08/13] configs: P1020RDB: Enable DM_ETH config Zhiqiang Hou
@ 2020-05-05 11:38 ` Zhiqiang Hou
2020-05-05 11:38 ` [PATCH 10/13] powerpc: p1010rdb: Compile legacy ethernet init function when no DM_ETH Zhiqiang Hou
` (3 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Zhiqiang Hou @ 2020-05-05 11:38 UTC (permalink / raw)
To: u-boot
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
P1010RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII PHY AR8033
eTSEC2: Connected to SGMII PHY AR8033
eTSEC3: Connected to SGMII PHY AR8033
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
arch/powerpc/dts/p1010rdb-pa.dts | 1 +
arch/powerpc/dts/p1010rdb-pa_36b.dts | 1 +
arch/powerpc/dts/p1010rdb-pb.dts | 1 +
arch/powerpc/dts/p1010rdb-pb_36b.dts | 1 +
arch/powerpc/dts/p1010rdb.dtsi | 71 ++++++++++++++++++++++++++++
arch/powerpc/dts/p1010si-post.dtsi | 25 ++++++++++
6 files changed, 100 insertions(+)
create mode 100644 arch/powerpc/dts/p1010rdb.dtsi
diff --git a/arch/powerpc/dts/p1010rdb-pa.dts b/arch/powerpc/dts/p1010rdb-pa.dts
index c66c4923ac..d46080d3ba 100644
--- a/arch/powerpc/dts/p1010rdb-pa.dts
+++ b/arch/powerpc/dts/p1010rdb-pa.dts
@@ -14,4 +14,5 @@
/include/ "p1010rdb_32b.dtsi"
};
+/include/ "p1010rdb.dtsi"
/include/ "p1010si-post.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb-pa_36b.dts b/arch/powerpc/dts/p1010rdb-pa_36b.dts
index b943de7cbb..b9df5d46b2 100644
--- a/arch/powerpc/dts/p1010rdb-pa_36b.dts
+++ b/arch/powerpc/dts/p1010rdb-pa_36b.dts
@@ -14,4 +14,5 @@
/include/ "p1010rdb_36b.dtsi"
};
+/include/ "p1010rdb.dtsi"
/include/ "p1010si-post.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb-pb.dts b/arch/powerpc/dts/p1010rdb-pb.dts
index 2675d5d92b..65deabd288 100644
--- a/arch/powerpc/dts/p1010rdb-pb.dts
+++ b/arch/powerpc/dts/p1010rdb-pb.dts
@@ -14,4 +14,5 @@
/include/ "p1010rdb_32b.dtsi"
};
+/include/ "p1010rdb.dtsi"
/include/ "p1010si-post.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb-pb_36b.dts b/arch/powerpc/dts/p1010rdb-pb_36b.dts
index 45ccf91c41..1ba65a9f22 100644
--- a/arch/powerpc/dts/p1010rdb-pb_36b.dts
+++ b/arch/powerpc/dts/p1010rdb-pb_36b.dts
@@ -14,4 +14,5 @@
/include/ "p1010rdb_36b.dtsi"
};
+/include/ "p1010rdb.dtsi"
/include/ "p1010si-post.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb.dtsi b/arch/powerpc/dts/p1010rdb.dtsi
new file mode 100644
index 0000000000..2040465bf4
--- /dev/null
+++ b/arch/powerpc/dts/p1010rdb.dtsi
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1010 RDB Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&soc {
+ mdio at 24000 {
+ phy0: ethernet-phy at 0 {
+ reg = <0x1>;
+ };
+
+ phy1: ethernet-phy at 1 {
+ reg = <0x0>;
+ };
+
+ phy2: ethernet-phy at 2 {
+ reg = <0x2>;
+ };
+
+ tbi-phy at 3 {
+ device_type = "tbi-phy";
+ reg = <0x3>;
+ };
+ };
+
+ mdio at 25000 {
+ tbi0: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ mdio at 26000 {
+ tbi1: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ ptp_clock at b0e00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0xb0e00 0xb0>;
+ interrupts = <68 2 0 0 69 2 0 0>;
+ fsl,tclk-period = <10>;
+ fsl,tmr-prsc = <2>;
+ fsl,tmr-add = <0x80000016>;
+ fsl,tmr-fiper1 = <999999990>;
+ fsl,tmr-fiper2 = <99990>;
+ fsl,max-adj = <199999999>;
+ };
+
+ enet0: ethernet at b0000 {
+ phy-handle = <&phy0>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ enet1: ethernet at b1000 {
+ phy-handle = <&phy1>;
+ tbi-handle = <&tbi0>;
+ phy-connection-type = "sgmii";
+ };
+
+ enet2: ethernet at b2000 {
+ phy-handle = <&phy2>;
+ tbi-handle = <&tbi1>;
+ phy-connection-type = "sgmii";
+ };
+};
diff --git a/arch/powerpc/dts/p1010si-post.dtsi b/arch/powerpc/dts/p1010si-post.dtsi
index e24b5e4063..10de94a2e6 100644
--- a/arch/powerpc/dts/p1010si-post.dtsi
+++ b/arch/powerpc/dts/p1010si-post.dtsi
@@ -23,6 +23,31 @@
single-cpu-affinity;
last-interrupt-source = <255>;
};
+
+/include/ "pq3-etsec2-0.dtsi"
+ enet0: ethernet at b0000 {
+ queue-group at b0000 {
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ };
+ };
+
+/include/ "pq3-etsec2-1.dtsi"
+ enet1: ethernet at b1000 {
+ queue-group at b1000 {
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ };
+ };
+
+/include/ "pq3-etsec2-2.dtsi"
+ enet2: ethernet at b2000 {
+ queue-group at b2000 {
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ };
+
+ };
};
/* controller at 0x9000 */
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 10/13] powerpc: p1010rdb: Compile legacy ethernet init function when no DM_ETH
2020-05-05 11:38 [PATCH 00/13] powerpc: covert p1010, p1020 and p2020 RDB board Zhiqiang Hou
` (8 preceding siblings ...)
2020-05-05 11:38 ` [PATCH 09/13] dts: powerpc: p1010rdb: Add eTSEC DT nodes Zhiqiang Hou
@ 2020-05-05 11:38 ` Zhiqiang Hou
2020-05-05 11:38 ` [PATCH 11/13] configs: P1010RDB: Enable DM_ETH config Zhiqiang Hou
` (2 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Zhiqiang Hou @ 2020-05-05 11:38 UTC (permalink / raw)
To: u-boot
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
board/freescale/p1010rdb/p1010rdb.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index 5057eac38a..8b51d0cd75 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -327,6 +327,7 @@ int checkboard(void)
return 0;
}
+#ifndef CONFIG_DM_ETH
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
@@ -367,6 +368,7 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);
}
+#endif
#if defined(CONFIG_OF_BOARD_SETUP)
void fdt_del_flexcan(void *blob)
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 11/13] configs: P1010RDB: Enable DM_ETH config
2020-05-05 11:38 [PATCH 00/13] powerpc: covert p1010, p1020 and p2020 RDB board Zhiqiang Hou
` (9 preceding siblings ...)
2020-05-05 11:38 ` [PATCH 10/13] powerpc: p1010rdb: Compile legacy ethernet init function when no DM_ETH Zhiqiang Hou
@ 2020-05-05 11:38 ` Zhiqiang Hou
2020-05-05 11:38 ` [PATCH 12/13] dts: powerpc: p2020rdb: Add eTSEC DT nodes Zhiqiang Hou
2020-05-05 11:38 ` [PATCH 13/13] configs: P2020RDB: Enable DM_ETH config Zhiqiang Hou
12 siblings, 0 replies; 16+ messages in thread
From: Zhiqiang Hou @ 2020-05-05 11:38 UTC (permalink / raw)
To: u-boot
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Enable the DM_ETH and DM_MDIO config.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 ++
configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 ++
configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 ++
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 ++
configs/P1010RDB-PA_NAND_defconfig | 2 ++
configs/P1010RDB-PA_NOR_defconfig | 2 ++
configs/P1010RDB-PA_SDCARD_defconfig | 2 ++
configs/P1010RDB-PA_SPIFLASH_defconfig | 2 ++
configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 ++
configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 ++
configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 2 ++
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 ++
configs/P1010RDB-PB_NAND_defconfig | 2 ++
configs/P1010RDB-PB_NOR_defconfig | 2 ++
configs/P1010RDB-PB_SDCARD_defconfig | 2 ++
configs/P1010RDB-PB_SPIFLASH_defconfig | 2 ++
16 files changed, 32 insertions(+)
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index 83de3cee2c..f597a935e0 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -71,12 +71,14 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index 7c1a3c8ee6..2817950cbd 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -53,12 +53,14 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index 1de064ca8d..2db103da54 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -65,12 +65,14 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index d23d42a8b0..b618235f03 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -67,12 +67,14 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index a218d143f5..375e7cf94c 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -70,12 +70,14 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index f1e6553030..002f9ce208 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -52,12 +52,14 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index 554e26febf..901e0ea794 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -64,12 +64,14 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index 6211977901..4dbde0edfa 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -66,12 +66,14 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 294d344d6e..18b693a7ff 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -71,12 +71,14 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index bf0ae9c6c6..b12ff0e69a 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -53,12 +53,14 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index 458cfb77f5..0439ee1859 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -65,12 +65,14 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index 39a09746ec..9580ae6a38 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -67,12 +67,14 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index 4219adf122..57cfb7311a 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -74,8 +74,10 @@ CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index 0028017bce..cbb543d370 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -56,8 +56,10 @@ CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index 69f174c84a..6ccda62029 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -64,12 +64,14 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index 44525f452c..58686b288e 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -66,12 +66,14 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 12/13] dts: powerpc: p2020rdb: Add eTSEC DT nodes
2020-05-05 11:38 [PATCH 00/13] powerpc: covert p1010, p1020 and p2020 RDB board Zhiqiang Hou
` (10 preceding siblings ...)
2020-05-05 11:38 ` [PATCH 11/13] configs: P1010RDB: Enable DM_ETH config Zhiqiang Hou
@ 2020-05-05 11:38 ` Zhiqiang Hou
2020-05-05 11:38 ` [PATCH 13/13] configs: P2020RDB: Enable DM_ETH config Zhiqiang Hou
12 siblings, 0 replies; 16+ messages in thread
From: Zhiqiang Hou @ 2020-05-05 11:38 UTC (permalink / raw)
To: u-boot
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
P2020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII PHY VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
arch/powerpc/dts/p2020-post.dtsi | 10 ++++
arch/powerpc/dts/p2020rdb-pc.dts | 1 +
arch/powerpc/dts/p2020rdb-pc.dtsi | 59 ++++++++++++++++++++++++
arch/powerpc/dts/p2020rdb-pc_36b.dts | 1 +
arch/powerpc/dts/pq3-etsec1-0.dtsi | 28 +++++++++++
arch/powerpc/dts/pq3-etsec1-1.dtsi | 28 +++++++++++
arch/powerpc/dts/pq3-etsec1-2.dtsi | 28 +++++++++++
arch/powerpc/dts/pq3-etsec1-3.dtsi | 28 +++++++++++
arch/powerpc/dts/pq3-etsec1-timer-0.dtsi | 13 ++++++
9 files changed, 196 insertions(+)
create mode 100644 arch/powerpc/dts/p2020rdb-pc.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-0.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-1.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-2.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-3.dtsi
create mode 100644 arch/powerpc/dts/pq3-etsec1-timer-0.dtsi
diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index 5bbd5c5468..5cdc1655d9 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -37,6 +37,16 @@
/* Filled in by U-Boot */
clock-frequency = <0>;
};
+
+/include/ "pq3-etsec1-0.dtsi"
+/include/ "pq3-etsec1-timer-0.dtsi"
+
+ ptp_clock at 24e00 {
+ interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
+ };
+
+/include/ "pq3-etsec1-1.dtsi"
+/include/ "pq3-etsec1-2.dtsi"
};
/* PCIe controller base address 0x8000 */
diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts
index 08befd4c59..f3f6be1080 100644
--- a/arch/powerpc/dts/p2020rdb-pc.dts
+++ b/arch/powerpc/dts/p2020rdb-pc.dts
@@ -37,4 +37,5 @@
};
};
+/include/ "p2020rdb-pc.dtsi"
/include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/p2020rdb-pc.dtsi b/arch/powerpc/dts/p2020rdb-pc.dtsi
new file mode 100644
index 0000000000..9abd700999
--- /dev/null
+++ b/arch/powerpc/dts/p2020rdb-pc.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&soc {
+ mdio at 24520 {
+ phy0: ethernet-phy at 0 {
+ interrupts = <3 1 0 0>;
+ reg = <0x0>;
+ };
+ phy1: ethernet-phy at 1 {
+ interrupts = <2 1 0 0>;
+ reg = <0x1>;
+ };
+ };
+
+ mdio at 25520 {
+ tbi0: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ mdio at 26520 {
+ status = "disabled";
+ };
+
+ ptp_clock at 24e00 {
+ fsl,tclk-period = <5>;
+ fsl,tmr-prsc = <2>;
+ fsl,tmr-add = <0xaaaaaaab>;
+ fsl,tmr-fiper1 = <999999995>;
+ fsl,tmr-fiper2 = <99990>;
+ fsl,max-adj = <299999999>;
+ };
+
+ enet0: ethernet at 24000 {
+ phy-connection-type = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ enet1: ethernet at 25000 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy0>;
+ phy-connection-type = "sgmii";
+ };
+
+ enet2: ethernet at 26000 {
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+ };
+};
diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts
index 04b2519e1a..6d983b7d71 100644
--- a/arch/powerpc/dts/p2020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts
@@ -37,4 +37,5 @@
};
};
+/include/ "p2020rdb-pc.dtsi"
/include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/pq3-etsec1-0.dtsi b/arch/powerpc/dts/pq3-etsec1-0.dtsi
new file mode 100644
index 0000000000..8800243f34
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-0.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet at 24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ fsl,magic-packet;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
+};
+
+mdio at 24520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x24520 0x20>;
+};
diff --git a/arch/powerpc/dts/pq3-etsec1-1.dtsi b/arch/powerpc/dts/pq3-etsec1-1.dtsi
new file mode 100644
index 0000000000..2bc62d1a57
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-1.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet at 25000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ ranges = <0x0 0x25000 0x1000>;
+ fsl,magic-packet;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
+};
+
+mdio at 25520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x25520 0x20>;
+};
diff --git a/arch/powerpc/dts/pq3-etsec1-2.dtsi b/arch/powerpc/dts/pq3-etsec1-2.dtsi
new file mode 100644
index 0000000000..d45865fe03
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-2.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet at 26000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <2>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x26000 0x1000>;
+ ranges = <0x0 0x26000 0x1000>;
+ fsl,magic-packet;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
+};
+
+mdio at 26520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x26520 0x20>;
+};
diff --git a/arch/powerpc/dts/pq3-etsec1-3.dtsi b/arch/powerpc/dts/pq3-etsec1-3.dtsi
new file mode 100644
index 0000000000..853a27359d
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-3.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x27000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet at 27000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <3>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x27000 0x1000>;
+ ranges = <0x0 0x27000 0x1000>;
+ fsl,magic-packet;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>;
+};
+
+mdio at 27520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x27520 0x20>;
+};
diff --git a/arch/powerpc/dts/pq3-etsec1-timer-0.dtsi b/arch/powerpc/dts/pq3-etsec1-timer-0.dtsi
new file mode 100644
index 0000000000..19b37aca1d
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-timer-0.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC Timer (IEEE 1588) device tree stub [ @ offsets 0x24e00 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ptp_clock at 24e00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24e00 0xb0>;
+ interrupts = <68 2 0 0 69 2 0 0>;
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 13/13] configs: P2020RDB: Enable DM_ETH config
2020-05-05 11:38 [PATCH 00/13] powerpc: covert p1010, p1020 and p2020 RDB board Zhiqiang Hou
` (11 preceding siblings ...)
2020-05-05 11:38 ` [PATCH 12/13] dts: powerpc: p2020rdb: Add eTSEC DT nodes Zhiqiang Hou
@ 2020-05-05 11:38 ` Zhiqiang Hou
12 siblings, 0 replies; 16+ messages in thread
From: Zhiqiang Hou @ 2020-05-05 11:38 UTC (permalink / raw)
To: u-boot
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Enable the DM_ETH and DM_MDIO config.
On P2020RDB, the eTSEC1 is connecting with a switch VSC7385,
so also enable the fixed PHY support.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 +++
configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 3 +++
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 3 +++
configs/P2020RDB-PC_36BIT_defconfig | 3 +++
configs/P2020RDB-PC_NAND_defconfig | 3 +++
configs/P2020RDB-PC_SDCARD_defconfig | 3 +++
configs/P2020RDB-PC_SPIFLASH_defconfig | 3 +++
configs/P2020RDB-PC_defconfig | 3 +++
8 files changed, 24 insertions(+)
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index b419367e7e..85b08c6769 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -66,6 +66,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@@ -77,8 +78,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index 0afddc2ed9..c4aa0abbfd 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -61,6 +61,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@@ -72,8 +73,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index 1a700a867f..d191a6010c 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -63,6 +63,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@@ -74,8 +75,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index 8b98cb8b9a..dc8a05c2d1 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -50,6 +50,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@@ -61,8 +62,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index b1a26af0f4..f462f23355 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -65,6 +65,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@@ -76,8 +77,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index c76958e1f3..1cf317297f 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -60,6 +60,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@@ -71,8 +72,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index 0892596fd6..c5e027959a 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -62,6 +62,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@@ -73,8 +74,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index e37ca66d1f..3a5fc8733e 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -49,6 +49,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@@ -60,8 +61,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
--
2.17.1
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