From: Frank Wang <frank.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
To: heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org,
marex-ynQEQJNshbs@public.gmane.org,
bmeng.cn-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
philipp.tomsich-SN7IsUiht6C/RdPyistoZJqQE7yCjDx5@public.gmane.org,
klaus.goger-SN7IsUiht6C/RdPyistoZJqQE7yCjDx5@public.gmane.org,
jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org,
sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org
Cc: jianing.ren-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
marek.belisko-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
wmc-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
u-boot-0aAXYlwwYIKGBzrmiIFOJg@public.gmane.org,
william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org,
chenjh-TNX95d0MmH7DzftRWevZcw@public.gmane.org
Subject: [PATCH v4 05/16] arm64: dts: rk3399: Move u2phy into root port
Date: Mon, 11 May 2020 15:55:09 +0800 [thread overview]
Message-ID: <20200511075520.26557-1-frank.wang@rock-chips.com> (raw)
In-Reply-To: <20200511075330.26462-1-frank.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
From: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Yes, This is changing the actual device tree u2phy
structure but the problem with the current Generic
PHY subsystem is unable to find PHY if the PHY node
is not part of the root structure.
This will be reverted,
- Once we support the PHY subsystem to get the PHY
even though it is not part of the root node or
- any other relevant solution that get the phy
directly without traversing all nodes.
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
arch/arm/dts/rk3399.dtsi | 108 +++++++++++++++++++--------------------
1 file changed, 54 insertions(+), 54 deletions(-)
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 74f2c3d490..6c77f25f23 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -1387,60 +1387,6 @@
status = "disabled";
};
- u2phy0: usb2-phy@e450 {
- compatible = "rockchip,rk3399-usb2phy";
- reg = <0xe450 0x10>;
- clocks = <&cru SCLK_USB2PHY0_REF>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- clock-output-names = "clk_usbphy0_480m";
- status = "disabled";
-
- u2phy0_host: host-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "linestate";
- status = "disabled";
- };
-
- u2phy0_otg: otg-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "otg-bvalid", "otg-id",
- "linestate";
- status = "disabled";
- };
- };
-
- u2phy1: usb2-phy@e460 {
- compatible = "rockchip,rk3399-usb2phy";
- reg = <0xe460 0x10>;
- clocks = <&cru SCLK_USB2PHY1_REF>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- clock-output-names = "clk_usbphy1_480m";
- status = "disabled";
-
- u2phy1_host: host-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "linestate";
- status = "disabled";
- };
-
- u2phy1_otg: otg-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "otg-bvalid", "otg-id",
- "linestate";
- status = "disabled";
- };
- };
-
emmc_phy: phy@f780 {
compatible = "rockchip,rk3399-emmc-phy";
reg = <0xf780 0x24>;
@@ -1462,6 +1408,60 @@
};
};
+ u2phy0: usb2-phy@e450 {
+ compatible = "rockchip,rk3399-usb2phy";
+ reg = <0x0 0xe450 0x0 0x10>;
+ clocks = <&cru SCLK_USB2PHY0_REF>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ clock-output-names = "clk_usbphy0_480m";
+ status = "disabled";
+
+ u2phy0_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+
+ u2phy0_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ status = "disabled";
+ };
+ };
+
+ u2phy1: usb2-phy@e460 {
+ compatible = "rockchip,rk3399-usb2phy";
+ reg = <0x0 0xe460 0x0 0x10>;
+ clocks = <&cru SCLK_USB2PHY1_REF>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ clock-output-names = "clk_usbphy1_480m";
+ status = "disabled";
+
+ u2phy1_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+
+ u2phy1_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ status = "disabled";
+ };
+ };
+
tcphy0: phy@ff7c0000 {
compatible = "rockchip,rk3399-typec-phy";
reg = <0x0 0xff7c0000 0x0 0x40000>;
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Frank Wang <frank.wang@rock-chips.com>
To: u-boot@lists.denx.de
Subject: [PATCH v4 05/16] arm64: dts: rk3399: Move u2phy into root port
Date: Mon, 11 May 2020 15:55:09 +0800 [thread overview]
Message-ID: <20200511075520.26557-1-frank.wang@rock-chips.com> (raw)
In-Reply-To: <20200511075330.26462-1-frank.wang@rock-chips.com>
From: Jagan Teki <jagan@amarulasolutions.com>
Yes, This is changing the actual device tree u2phy
structure but the problem with the current Generic
PHY subsystem is unable to find PHY if the PHY node
is not part of the root structure.
This will be reverted,
- Once we support the PHY subsystem to get the PHY
even though it is not part of the root node or
- any other relevant solution that get the phy
directly without traversing all nodes.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
arch/arm/dts/rk3399.dtsi | 108 +++++++++++++++++++--------------------
1 file changed, 54 insertions(+), 54 deletions(-)
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 74f2c3d490..6c77f25f23 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -1387,60 +1387,6 @@
status = "disabled";
};
- u2phy0: usb2-phy at e450 {
- compatible = "rockchip,rk3399-usb2phy";
- reg = <0xe450 0x10>;
- clocks = <&cru SCLK_USB2PHY0_REF>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- clock-output-names = "clk_usbphy0_480m";
- status = "disabled";
-
- u2phy0_host: host-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "linestate";
- status = "disabled";
- };
-
- u2phy0_otg: otg-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "otg-bvalid", "otg-id",
- "linestate";
- status = "disabled";
- };
- };
-
- u2phy1: usb2-phy at e460 {
- compatible = "rockchip,rk3399-usb2phy";
- reg = <0xe460 0x10>;
- clocks = <&cru SCLK_USB2PHY1_REF>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- clock-output-names = "clk_usbphy1_480m";
- status = "disabled";
-
- u2phy1_host: host-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "linestate";
- status = "disabled";
- };
-
- u2phy1_otg: otg-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "otg-bvalid", "otg-id",
- "linestate";
- status = "disabled";
- };
- };
-
emmc_phy: phy at f780 {
compatible = "rockchip,rk3399-emmc-phy";
reg = <0xf780 0x24>;
@@ -1462,6 +1408,60 @@
};
};
+ u2phy0: usb2-phy at e450 {
+ compatible = "rockchip,rk3399-usb2phy";
+ reg = <0x0 0xe450 0x0 0x10>;
+ clocks = <&cru SCLK_USB2PHY0_REF>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ clock-output-names = "clk_usbphy0_480m";
+ status = "disabled";
+
+ u2phy0_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+
+ u2phy0_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ status = "disabled";
+ };
+ };
+
+ u2phy1: usb2-phy at e460 {
+ compatible = "rockchip,rk3399-usb2phy";
+ reg = <0x0 0xe460 0x0 0x10>;
+ clocks = <&cru SCLK_USB2PHY1_REF>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ clock-output-names = "clk_usbphy1_480m";
+ status = "disabled";
+
+ u2phy1_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+
+ u2phy1_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ status = "disabled";
+ };
+ };
+
tcphy0: phy at ff7c0000 {
compatible = "rockchip,rk3399-typec-phy";
reg = <0x0 0xff7c0000 0x0 0x40000>;
--
2.17.1
next prev parent reply other threads:[~2020-05-11 7:55 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-11 7:53 [PATCH v4 00/16] Add Rockchip RK3399 USB3.0 Host support Frank Wang
2020-05-11 7:53 ` Frank Wang
2020-05-11 7:53 ` [PATCH v4 01/16] clk: rk3399: Enable/Disable the USB2PHY clk Frank Wang
2020-05-11 7:53 ` Frank Wang
[not found] ` <20200511075330.26462-1-frank.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2020-05-11 7:53 ` [PATCH v4 02/16] clk: rk3399: Set empty for TCPHY assigned-clocks Frank Wang
2020-05-11 7:53 ` Frank Wang
2020-05-11 7:53 ` [PATCH v4 03/16] clk: rk3399: Enable/Disable TCPHY clocks Frank Wang
2020-05-11 7:53 ` Frank Wang
2020-05-11 7:53 ` [PATCH v4 04/16] phy: rockchip: Add Rockchip USB2PHY driver Frank Wang
2020-05-11 7:53 ` Frank Wang
2020-05-11 7:55 ` Frank Wang [this message]
2020-05-11 7:55 ` [PATCH v4 05/16] arm64: dts: rk3399: Move u2phy into root port Frank Wang
[not found] ` <20200511075520.26557-1-frank.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2020-05-11 7:55 ` [PATCH v4 06/16] phy: rockchip: Add Rockchip USB TypeC PHY driver Frank Wang
2020-05-11 7:55 ` Frank Wang
2020-05-11 7:55 ` [PATCH v4 07/16] usb: dwc3: add dis_enblslpm_quirk Frank Wang
2020-05-11 7:55 ` Frank Wang
2020-05-11 8:49 ` Jagan Teki
2020-05-11 8:49 ` Jagan Teki
2020-05-11 7:55 ` [PATCH v4 08/16] usb: dwc3: add dis_u2_freeclk_exists_quirk Frank Wang
2020-05-11 7:55 ` Frank Wang
2020-05-11 8:50 ` Jagan Teki
2020-05-11 8:50 ` Jagan Teki
2020-05-11 7:55 ` [PATCH v4 09/16] usb: dwc3: Add disable u2mac linestate check quirk Frank Wang
2020-05-11 7:55 ` Frank Wang
2020-05-11 7:57 ` [PATCH v4 10/16] usb: dwc3: Enable AutoRetry feature in the controller Frank Wang
2020-05-11 7:57 ` Frank Wang
[not found] ` <20200511075725.26665-1-frank.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2020-05-11 7:57 ` [PATCH v4 11/16] usb: dwc3: amend UTMI/UTMIW phy interface setup Frank Wang
2020-05-11 7:57 ` Frank Wang
2020-05-11 7:57 ` [PATCH v4 12/16] usb: dwc3: add make compatible for rockchip platform Frank Wang
2020-05-11 7:57 ` Frank Wang
2020-05-11 9:48 ` Marek Vasut
2020-05-11 9:48 ` Marek Vasut
2020-05-12 1:08 ` Frank Wang
2020-05-12 1:08 ` Frank Wang
2020-05-12 7:26 ` Marek Vasut
2020-05-12 7:26 ` Marek Vasut
2020-05-13 0:47 ` Frank Wang
2020-05-13 0:47 ` Frank Wang
2020-05-13 11:41 ` Marek Vasut
2020-05-13 11:41 ` Marek Vasut
2020-05-11 7:57 ` [PATCH v4 13/16] driver: usb: drop legacy rockchip xhci driver Frank Wang
2020-05-11 7:57 ` Frank Wang
2020-05-11 7:57 ` [PATCH v4 14/16] ARM: dts: rk3399-evb: usb3.0 host support Frank Wang
2020-05-11 7:57 ` Frank Wang
2020-05-11 7:58 ` [PATCH v4 15/16] configs: evb-rk3399: update support usb3.0 host Frank Wang
2020-05-11 7:58 ` Frank Wang
[not found] ` <20200511075830.26754-1-frank.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2020-05-11 7:58 ` [PATCH v4 16/16] roc-rk3399-pc: Enable USB3.0 Host Frank Wang
2020-05-11 7:58 ` Frank Wang
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