* [PATCH 1/2] arch: arm64: dts: msm8996: Fix CSI IRQ types
@ 2020-04-21 12:00 Loic Poulain
2020-04-21 12:00 ` [PATCH 2/2] arch: arm64: dts: msm8996: Add CCI node Loic Poulain
2020-05-11 23:54 ` [PATCH 1/2] arch: arm64: dts: msm8996: Fix CSI IRQ types Bjorn Andersson
0 siblings, 2 replies; 3+ messages in thread
From: Loic Poulain @ 2020-04-21 12:00 UTC (permalink / raw)
To: bjorn.andersson; +Cc: linux-arm-msm, agross, Loic Poulain
Each IRQ_TYPE_NONE interrupt causes a warning at boot.
Fix that by defining an appropriate type.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 951c53a..24a4625 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1001,16 +1001,16 @@
"csi_clk_mux",
"vfe0",
"vfe1";
- interrupts = <GIC_SPI 78 0>,
- <GIC_SPI 79 0>,
- <GIC_SPI 80 0>,
- <GIC_SPI 296 0>,
- <GIC_SPI 297 0>,
- <GIC_SPI 298 0>,
- <GIC_SPI 299 0>,
- <GIC_SPI 309 0>,
- <GIC_SPI 314 0>,
- <GIC_SPI 315 0>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csiphy0",
"csiphy1",
"csiphy2",
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] arch: arm64: dts: msm8996: Add CCI node
2020-04-21 12:00 [PATCH 1/2] arch: arm64: dts: msm8996: Fix CSI IRQ types Loic Poulain
@ 2020-04-21 12:00 ` Loic Poulain
2020-05-11 23:54 ` [PATCH 1/2] arch: arm64: dts: msm8996: Fix CSI IRQ types Bjorn Andersson
1 sibling, 0 replies; 3+ messages in thread
From: Loic Poulain @ 2020-04-21 12:00 UTC (permalink / raw)
To: bjorn.andersson; +Cc: linux-arm-msm, agross, Loic Poulain
Add CCI controller node, which can be used to communicate with
camera sensors (I2C subset). MSM8996 CCI offers two masters,
i2c-bus@0 and i2c-bus@1.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 37 +++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 24a4625..5bd0d8a0 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1105,6 +1105,43 @@
};
};
+ cci: cci@a0c000 {
+ compatible = "qcom,msm8996-cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xa0c000 0x1000>;
+ interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&mmcc CAMSS_GDSC>;
+ clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
+ <&mmcc CAMSS_CCI_AHB_CLK>,
+ <&mmcc CAMSS_CCI_CLK>,
+ <&mmcc CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb",
+ "cci_ahb",
+ "cci",
+ "camss_ahb";
+ assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
+ <&mmcc CAMSS_CCI_CLK>;
+ assigned-clock-rates = <80000000>, <37500000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cci0_default &cci1_default>;
+ status = "disabled";
+
+ cci_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
adreno_smmu: iommu@b40000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
reg = <0x00b40000 0x10000>;
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 1/2] arch: arm64: dts: msm8996: Fix CSI IRQ types
2020-04-21 12:00 [PATCH 1/2] arch: arm64: dts: msm8996: Fix CSI IRQ types Loic Poulain
2020-04-21 12:00 ` [PATCH 2/2] arch: arm64: dts: msm8996: Add CCI node Loic Poulain
@ 2020-05-11 23:54 ` Bjorn Andersson
1 sibling, 0 replies; 3+ messages in thread
From: Bjorn Andersson @ 2020-05-11 23:54 UTC (permalink / raw)
To: Loic Poulain; +Cc: linux-arm-msm, agross
On Tue 21 Apr 05:00 PDT 2020, Loic Poulain wrote:
> Each IRQ_TYPE_NONE interrupt causes a warning at boot.
> Fix that by defining an appropriate type.
>
Dropped "arch: " from $subject, added Fixes and applied both patches.
Thanks,
Bjorn
> Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index 951c53a..24a4625 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -1001,16 +1001,16 @@
> "csi_clk_mux",
> "vfe0",
> "vfe1";
> - interrupts = <GIC_SPI 78 0>,
> - <GIC_SPI 79 0>,
> - <GIC_SPI 80 0>,
> - <GIC_SPI 296 0>,
> - <GIC_SPI 297 0>,
> - <GIC_SPI 298 0>,
> - <GIC_SPI 299 0>,
> - <GIC_SPI 309 0>,
> - <GIC_SPI 314 0>,
> - <GIC_SPI 315 0>;
> + interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
> interrupt-names = "csiphy0",
> "csiphy1",
> "csiphy2",
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2020-05-11 23:56 UTC | newest]
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2020-04-21 12:00 [PATCH 1/2] arch: arm64: dts: msm8996: Fix CSI IRQ types Loic Poulain
2020-04-21 12:00 ` [PATCH 2/2] arch: arm64: dts: msm8996: Add CCI node Loic Poulain
2020-05-11 23:54 ` [PATCH 1/2] arch: arm64: dts: msm8996: Fix CSI IRQ types Bjorn Andersson
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