From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> To: linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au, linux-nvdimm@lists.01.org Cc: alistair@popple.id.au, "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> Subject: [PATCH v2 3/5] libnvdimm/nvdimm/flush: Allow architecture to override the flush barrier Date: Wed, 13 May 2020 09:17:03 +0530 [thread overview] Message-ID: <20200513034705.172983-3-aneesh.kumar@linux.ibm.com> (raw) In-Reply-To: <20200513034705.172983-1-aneesh.kumar@linux.ibm.com> Architectures like ppc64 provide persistent memory specific barriers that will ensure that all stores for which the modifications are written to persistent storage by preceding dcbfps and dcbstps instructions have updated persistent storage before any data access or data transfer caused by subsequent instructions is initiated. This is in addition to the ordering done by wmb() Update nvdimm core such that architecture can use barriers other than wmb to ensure all previous writes are architecturally visible for the platform buffer flush. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> --- drivers/nvdimm/region_devs.c | 8 ++++---- include/linux/libnvdimm.h | 4 ++++ 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/nvdimm/region_devs.c b/drivers/nvdimm/region_devs.c index ccbb5b43b8b2..88ea34a9c7fd 100644 --- a/drivers/nvdimm/region_devs.c +++ b/drivers/nvdimm/region_devs.c @@ -1216,13 +1216,13 @@ int generic_nvdimm_flush(struct nd_region *nd_region) idx = this_cpu_add_return(flush_idx, hash_32(current->pid + idx, 8)); /* - * The first wmb() is needed to 'sfence' all previous writes - * such that they are architecturally visible for the platform - * buffer flush. Note that we've already arranged for pmem + * The first arch_pmem_flush_barrier() is needed to 'sfence' all + * previous writes such that they are architecturally visible for + * the platform buffer flush. Note that we've already arranged for pmem * writes to avoid the cache via memcpy_flushcache(). The final * wmb() ensures ordering for the NVDIMM flush write. */ - wmb(); + arch_pmem_flush_barrier(); for (i = 0; i < nd_region->ndr_mappings; i++) if (ndrd_get_flush_wpq(ndrd, i, 0)) writeq(1, ndrd_get_flush_wpq(ndrd, i, idx)); diff --git a/include/linux/libnvdimm.h b/include/linux/libnvdimm.h index 18da4059be09..66f6c65bd789 100644 --- a/include/linux/libnvdimm.h +++ b/include/linux/libnvdimm.h @@ -286,4 +286,8 @@ static inline void arch_invalidate_pmem(void *addr, size_t size) } #endif +#ifndef arch_pmem_flush_barrier +#define arch_pmem_flush_barrier() wmb() +#endif + #endif /* __LIBNVDIMM_H__ */ -- 2.26.2 _______________________________________________ Linux-nvdimm mailing list -- linux-nvdimm@lists.01.org To unsubscribe send an email to linux-nvdimm-leave@lists.01.org
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From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> To: linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au, linux-nvdimm@lists.01.org Cc: alistair@popple.id.au, dan.j.williams@intel.com, oohall@gmail.com, "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> Subject: [PATCH v2 3/5] libnvdimm/nvdimm/flush: Allow architecture to override the flush barrier Date: Wed, 13 May 2020 09:17:03 +0530 [thread overview] Message-ID: <20200513034705.172983-3-aneesh.kumar@linux.ibm.com> (raw) In-Reply-To: <20200513034705.172983-1-aneesh.kumar@linux.ibm.com> Architectures like ppc64 provide persistent memory specific barriers that will ensure that all stores for which the modifications are written to persistent storage by preceding dcbfps and dcbstps instructions have updated persistent storage before any data access or data transfer caused by subsequent instructions is initiated. This is in addition to the ordering done by wmb() Update nvdimm core such that architecture can use barriers other than wmb to ensure all previous writes are architecturally visible for the platform buffer flush. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> --- drivers/nvdimm/region_devs.c | 8 ++++---- include/linux/libnvdimm.h | 4 ++++ 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/nvdimm/region_devs.c b/drivers/nvdimm/region_devs.c index ccbb5b43b8b2..88ea34a9c7fd 100644 --- a/drivers/nvdimm/region_devs.c +++ b/drivers/nvdimm/region_devs.c @@ -1216,13 +1216,13 @@ int generic_nvdimm_flush(struct nd_region *nd_region) idx = this_cpu_add_return(flush_idx, hash_32(current->pid + idx, 8)); /* - * The first wmb() is needed to 'sfence' all previous writes - * such that they are architecturally visible for the platform - * buffer flush. Note that we've already arranged for pmem + * The first arch_pmem_flush_barrier() is needed to 'sfence' all + * previous writes such that they are architecturally visible for + * the platform buffer flush. Note that we've already arranged for pmem * writes to avoid the cache via memcpy_flushcache(). The final * wmb() ensures ordering for the NVDIMM flush write. */ - wmb(); + arch_pmem_flush_barrier(); for (i = 0; i < nd_region->ndr_mappings; i++) if (ndrd_get_flush_wpq(ndrd, i, 0)) writeq(1, ndrd_get_flush_wpq(ndrd, i, idx)); diff --git a/include/linux/libnvdimm.h b/include/linux/libnvdimm.h index 18da4059be09..66f6c65bd789 100644 --- a/include/linux/libnvdimm.h +++ b/include/linux/libnvdimm.h @@ -286,4 +286,8 @@ static inline void arch_invalidate_pmem(void *addr, size_t size) } #endif +#ifndef arch_pmem_flush_barrier +#define arch_pmem_flush_barrier() wmb() +#endif + #endif /* __LIBNVDIMM_H__ */ -- 2.26.2
next prev parent reply other threads:[~2020-05-13 3:48 UTC|newest] Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-05-13 3:47 [PATCH v2 1/5] powerpc/pmem: Add new instructions for persistent storage and sync Aneesh Kumar K.V 2020-05-13 3:47 ` Aneesh Kumar K.V 2020-05-13 3:47 ` [PATCH v2 2/5] powerpc/pmem: Add flush routines using new pmem store and sync instruction Aneesh Kumar K.V 2020-05-13 3:47 ` Aneesh Kumar K.V 2020-05-13 3:47 ` Aneesh Kumar K.V [this message] 2020-05-13 3:47 ` [PATCH v2 3/5] libnvdimm/nvdimm/flush: Allow architecture to override the flush barrier Aneesh Kumar K.V 2020-05-13 16:14 ` Dan Williams 2020-05-13 16:14 ` Dan Williams 2020-05-19 5:30 ` Aneesh Kumar K.V 2020-05-19 5:30 ` Aneesh Kumar K.V 2020-05-19 7:09 ` Dan Williams 2020-05-19 7:09 ` Dan Williams 2020-05-19 13:52 ` Aneesh Kumar K.V 2020-05-19 13:52 ` Aneesh Kumar K.V 2020-05-19 18:59 ` Dan Williams 2020-05-19 18:59 ` Dan Williams 2020-05-20 18:43 ` Aneesh Kumar K.V 2020-05-20 18:43 ` Aneesh Kumar K.V 2020-05-21 14:38 ` Jeff Moyer 2020-05-21 14:38 ` Jeff Moyer 2020-05-21 17:02 ` Aneesh Kumar K.V 2020-05-21 17:02 ` Aneesh Kumar K.V 2020-05-21 18:25 ` Dan Williams 2020-05-21 18:25 ` Dan Williams 2020-05-21 18:52 ` Mikulas Patocka 2020-05-21 18:52 ` Mikulas Patocka 2020-05-22 9:31 ` Michal Suchánek 2020-05-22 9:31 ` Michal Suchánek 2020-05-22 10:08 ` Aneesh Kumar K.V 2020-05-22 10:08 ` Aneesh Kumar K.V 2020-05-22 13:01 ` Mikulas Patocka 2020-05-22 13:01 ` Mikulas Patocka 2020-06-26 10:20 ` Michal Suchánek 2020-06-26 10:20 ` Michal Suchánek 2020-05-21 18:34 ` Dan Williams 2020-05-21 18:34 ` Dan Williams 2020-05-13 3:47 ` [PATCH v2 4/5] powerpc/pmem/of_pmem: Update of_pmem to use the new barrier instruction Aneesh Kumar K.V 2020-05-13 3:47 ` Aneesh Kumar K.V 2020-05-13 6:44 ` kbuild test robot 2020-05-13 6:44 ` kbuild test robot 2020-05-13 6:44 ` kbuild test robot 2020-05-13 3:47 ` [PATCH v2 5/5] powerpc/pmem: Avoid the barrier in flush routines Aneesh Kumar K.V 2020-05-13 3:47 ` Aneesh Kumar K.V
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