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From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
To: linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au,
	linux-nvdimm@lists.01.org
Cc: alistair@popple.id.au, "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
Subject: [PATCH v2 4/5] powerpc/pmem/of_pmem: Update of_pmem to use the new barrier instruction.
Date: Wed, 13 May 2020 09:17:04 +0530	[thread overview]
Message-ID: <20200513034705.172983-4-aneesh.kumar@linux.ibm.com> (raw)
In-Reply-To: <20200513034705.172983-1-aneesh.kumar@linux.ibm.com>

of_pmem on POWER10 can now use phwsync instead of hwsync to ensure
all previous writes are architecturally visible for the platform
buffer flush.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
 arch/powerpc/include/asm/cacheflush.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h
index e92191b390f3..f22057dc9dd0 100644
--- a/arch/powerpc/include/asm/cacheflush.h
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -119,6 +119,16 @@ static inline void invalidate_dcache_range(unsigned long start,
 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
 	memcpy(dst, src, len)
 
+
+#define arch_pmem_flush_barrier arch_pmem_flush_barrier
+static inline void  arch_pmem_flush_barrier(void)
+{
+	if (cpu_has_feature(CPU_FTR_ARCH_31))
+		asm volatile(PPC_PHWSYNC ::: "memory");
+	else
+		asm volatile("hwsync" ::: "memory");
+}
+
 #endif /* __KERNEL__ */
 
 #endif /* _ASM_POWERPC_CACHEFLUSH_H */
-- 
2.26.2
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WARNING: multiple messages have this Message-ID (diff)
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
To: linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au,
	linux-nvdimm@lists.01.org
Cc: alistair@popple.id.au, dan.j.williams@intel.com,
	oohall@gmail.com, "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
Subject: [PATCH v2 4/5] powerpc/pmem/of_pmem: Update of_pmem to use the new barrier instruction.
Date: Wed, 13 May 2020 09:17:04 +0530	[thread overview]
Message-ID: <20200513034705.172983-4-aneesh.kumar@linux.ibm.com> (raw)
In-Reply-To: <20200513034705.172983-1-aneesh.kumar@linux.ibm.com>

of_pmem on POWER10 can now use phwsync instead of hwsync to ensure
all previous writes are architecturally visible for the platform
buffer flush.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
 arch/powerpc/include/asm/cacheflush.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h
index e92191b390f3..f22057dc9dd0 100644
--- a/arch/powerpc/include/asm/cacheflush.h
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -119,6 +119,16 @@ static inline void invalidate_dcache_range(unsigned long start,
 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
 	memcpy(dst, src, len)
 
+
+#define arch_pmem_flush_barrier arch_pmem_flush_barrier
+static inline void  arch_pmem_flush_barrier(void)
+{
+	if (cpu_has_feature(CPU_FTR_ARCH_31))
+		asm volatile(PPC_PHWSYNC ::: "memory");
+	else
+		asm volatile("hwsync" ::: "memory");
+}
+
 #endif /* __KERNEL__ */
 
 #endif /* _ASM_POWERPC_CACHEFLUSH_H */
-- 
2.26.2


  parent reply	other threads:[~2020-05-13  3:48 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-13  3:47 [PATCH v2 1/5] powerpc/pmem: Add new instructions for persistent storage and sync Aneesh Kumar K.V
2020-05-13  3:47 ` Aneesh Kumar K.V
2020-05-13  3:47 ` [PATCH v2 2/5] powerpc/pmem: Add flush routines using new pmem store and sync instruction Aneesh Kumar K.V
2020-05-13  3:47   ` Aneesh Kumar K.V
2020-05-13  3:47 ` [PATCH v2 3/5] libnvdimm/nvdimm/flush: Allow architecture to override the flush barrier Aneesh Kumar K.V
2020-05-13  3:47   ` Aneesh Kumar K.V
2020-05-13 16:14   ` Dan Williams
2020-05-13 16:14     ` Dan Williams
2020-05-19  5:30     ` Aneesh Kumar K.V
2020-05-19  5:30       ` Aneesh Kumar K.V
2020-05-19  7:09       ` Dan Williams
2020-05-19  7:09         ` Dan Williams
2020-05-19 13:52         ` Aneesh Kumar K.V
2020-05-19 13:52           ` Aneesh Kumar K.V
2020-05-19 18:59           ` Dan Williams
2020-05-19 18:59             ` Dan Williams
2020-05-20 18:43             ` Aneesh Kumar K.V
2020-05-20 18:43               ` Aneesh Kumar K.V
2020-05-21 14:38             ` Jeff Moyer
2020-05-21 14:38               ` Jeff Moyer
2020-05-21 17:02               ` Aneesh Kumar K.V
2020-05-21 17:02                 ` Aneesh Kumar K.V
2020-05-21 18:25                 ` Dan Williams
2020-05-21 18:25                   ` Dan Williams
2020-05-21 18:52                   ` Mikulas Patocka
2020-05-21 18:52                     ` Mikulas Patocka
2020-05-22  9:31                     ` Michal Suchánek
2020-05-22  9:31                       ` Michal Suchánek
2020-05-22 10:08                       ` Aneesh Kumar K.V
2020-05-22 10:08                         ` Aneesh Kumar K.V
2020-05-22 13:01                         ` Mikulas Patocka
2020-05-22 13:01                           ` Mikulas Patocka
2020-06-26 10:20                           ` Michal Suchánek
2020-06-26 10:20                             ` Michal Suchánek
2020-05-21 18:34               ` Dan Williams
2020-05-21 18:34                 ` Dan Williams
2020-05-13  3:47 ` Aneesh Kumar K.V [this message]
2020-05-13  3:47   ` [PATCH v2 4/5] powerpc/pmem/of_pmem: Update of_pmem to use the new barrier instruction Aneesh Kumar K.V
2020-05-13  6:44   ` kbuild test robot
2020-05-13  6:44     ` kbuild test robot
2020-05-13  6:44     ` kbuild test robot
2020-05-13  3:47 ` [PATCH v2 5/5] powerpc/pmem: Avoid the barrier in flush routines Aneesh Kumar K.V
2020-05-13  3:47   ` Aneesh Kumar K.V

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