From: Manasi Navare <manasi.d.navare@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Manasi Navare <manasi.d.navare@intel.com>, Aditya Swarup <aditya.swarup@intel.com> Subject: [PATCH v5 2/3] drm/i915/dp: Attach and set drm connector VRR property Date: Tue, 12 May 2020 22:34:30 -0700 [thread overview] Message-ID: <20200513053431.2138-2-manasi.d.navare@intel.com> (raw) In-Reply-To: <20200513053431.2138-1-manasi.d.navare@intel.com> From: Aditya Swarup <aditya.swarup@intel.com> This function sets the VRR property for connector based on the platform support, EDID monitor range and DP sink DPCD capability of outputing video without msa timing information. v5: * Fix the vrr prop not being set in kernel (Manasi) * Unset the prop on connector disconnect (Manasi) v4: * Rebase (Mansi) v3: * intel_dp_is_vrr_capable can be used for debugfs, make it non static (Manasi) v2: * Just set this in intel_dp_get_modes instead of new hook (Jani) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 27 +++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ 2 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 67723dede1d1..8957a9f50f0e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6153,6 +6153,9 @@ intel_dp_detect(struct drm_connector *connector, if (status == connector_status_disconnected) { memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); + /*Reset the immutable VRR Capable property */ + drm_connector_set_vrr_capable_property(connector, + false); if (intel_dp->is_mst) { drm_dbg_kms(&dev_priv->drm, @@ -6260,6 +6263,23 @@ intel_dp_force(struct drm_connector *connector) intel_display_power_put(dev_priv, aux_domain, wakeref); } +bool intel_dp_is_vrr_capable(struct drm_connector *connector) +{ + struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); + const struct drm_display_info *info = &connector->display_info; + struct drm_i915_private *dev_priv = to_i915(connector->dev); + + /* + * DP Sink is capable of Variable refresh video timings if + * Ignore MSA bit is set in DPCD. + * EDID monitor range also should be atleast 10 for reasonable + * Adaptive sync/ VRR end user experience. + */ + return INTEL_GEN(dev_priv) >= 12 && + drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) && + info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10; +} + static int intel_dp_get_modes(struct drm_connector *connector) { struct intel_connector *intel_connector = to_intel_connector(connector); @@ -6268,6 +6288,10 @@ static int intel_dp_get_modes(struct drm_connector *connector) edid = intel_connector->detect_edid; if (edid) { int ret = intel_connector_update_modes(connector, edid); + + if (intel_dp_is_vrr_capable(connector)) + drm_connector_set_vrr_capable_property(connector, + true); if (ret) return ret; } @@ -7354,6 +7378,9 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; } + + if (INTEL_GEN(dev_priv) >= 12) + drm_connector_attach_vrr_capable_property(connector); } static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 6659ce15a693..aa7c1f530d5e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -14,6 +14,7 @@ enum pipe; enum port; struct drm_connector_state; struct drm_encoder; +struct drm_connector; struct drm_i915_private; struct drm_modeset_acquire_ctx; struct intel_connector; @@ -119,6 +120,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable, const struct drm_connector_state *conn_state); bool intel_digital_port_connected(struct intel_encoder *encoder); void intel_dp_process_phy_request(struct intel_dp *intel_dp); +bool intel_dp_is_vrr_capable(struct drm_connector *connector); static inline unsigned int intel_dp_unused_lane_mask(int lane_count) { -- 2.19.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Manasi Navare <manasi.d.navare@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v5 2/3] drm/i915/dp: Attach and set drm connector VRR property Date: Tue, 12 May 2020 22:34:30 -0700 [thread overview] Message-ID: <20200513053431.2138-2-manasi.d.navare@intel.com> (raw) In-Reply-To: <20200513053431.2138-1-manasi.d.navare@intel.com> From: Aditya Swarup <aditya.swarup@intel.com> This function sets the VRR property for connector based on the platform support, EDID monitor range and DP sink DPCD capability of outputing video without msa timing information. v5: * Fix the vrr prop not being set in kernel (Manasi) * Unset the prop on connector disconnect (Manasi) v4: * Rebase (Mansi) v3: * intel_dp_is_vrr_capable can be used for debugfs, make it non static (Manasi) v2: * Just set this in intel_dp_get_modes instead of new hook (Jani) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 27 +++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ 2 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 67723dede1d1..8957a9f50f0e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6153,6 +6153,9 @@ intel_dp_detect(struct drm_connector *connector, if (status == connector_status_disconnected) { memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); + /*Reset the immutable VRR Capable property */ + drm_connector_set_vrr_capable_property(connector, + false); if (intel_dp->is_mst) { drm_dbg_kms(&dev_priv->drm, @@ -6260,6 +6263,23 @@ intel_dp_force(struct drm_connector *connector) intel_display_power_put(dev_priv, aux_domain, wakeref); } +bool intel_dp_is_vrr_capable(struct drm_connector *connector) +{ + struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); + const struct drm_display_info *info = &connector->display_info; + struct drm_i915_private *dev_priv = to_i915(connector->dev); + + /* + * DP Sink is capable of Variable refresh video timings if + * Ignore MSA bit is set in DPCD. + * EDID monitor range also should be atleast 10 for reasonable + * Adaptive sync/ VRR end user experience. + */ + return INTEL_GEN(dev_priv) >= 12 && + drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) && + info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10; +} + static int intel_dp_get_modes(struct drm_connector *connector) { struct intel_connector *intel_connector = to_intel_connector(connector); @@ -6268,6 +6288,10 @@ static int intel_dp_get_modes(struct drm_connector *connector) edid = intel_connector->detect_edid; if (edid) { int ret = intel_connector_update_modes(connector, edid); + + if (intel_dp_is_vrr_capable(connector)) + drm_connector_set_vrr_capable_property(connector, + true); if (ret) return ret; } @@ -7354,6 +7378,9 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; } + + if (INTEL_GEN(dev_priv) >= 12) + drm_connector_attach_vrr_capable_property(connector); } static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 6659ce15a693..aa7c1f530d5e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -14,6 +14,7 @@ enum pipe; enum port; struct drm_connector_state; struct drm_encoder; +struct drm_connector; struct drm_i915_private; struct drm_modeset_acquire_ctx; struct intel_connector; @@ -119,6 +120,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable, const struct drm_connector_state *conn_state); bool intel_digital_port_connected(struct intel_encoder *encoder); void intel_dp_process_phy_request(struct intel_dp *intel_dp); +bool intel_dp_is_vrr_capable(struct drm_connector *connector); static inline unsigned int intel_dp_unused_lane_mask(int lane_count) { -- 2.19.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-05-13 5:33 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-05-13 5:34 [PATCH v5 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD Manasi Navare 2020-05-13 5:34 ` [Intel-gfx] " Manasi Navare 2020-05-13 5:34 ` Manasi Navare [this message] 2020-05-13 5:34 ` [Intel-gfx] [PATCH v5 2/3] drm/i915/dp: Attach and set drm connector VRR property Manasi Navare 2020-05-13 5:34 ` [PATCH v5 3/3] drm/i915/dp: Expose connector VRR info via debugfs Manasi Navare 2020-05-13 5:34 ` [Intel-gfx] " Manasi Navare 2020-05-13 11:08 ` Modem, Bhanuprakash 2020-05-13 11:08 ` [Intel-gfx] " Modem, Bhanuprakash 2020-05-13 18:21 ` Manasi Navare 2020-05-13 18:21 ` [Intel-gfx] " Manasi Navare 2020-05-14 3:42 ` Modem, Bhanuprakash 2020-05-14 3:42 ` [Intel-gfx] " Modem, Bhanuprakash 2020-05-13 5:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD Patchwork 2020-05-13 6:26 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 2020-05-13 12:22 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [v5,1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD (rev2) Patchwork 2020-05-14 5:02 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [v5,1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD (rev3) Patchwork
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