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From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Manasi Navare <manasi.d.navare@intel.com>,
	Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Subject: [PATCH v5 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD
Date: Tue, 12 May 2020 22:34:29 -0700	[thread overview]
Message-ID: <20200513053431.2138-1-manasi.d.navare@intel.com> (raw)

DP sink device sets the Ignore MSA bit in its
DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to
ignore the MSA video timing parameters and its ability to support
seamless video timing change over a range of timing exposed by
DisplayID and EDID.
This is required for the sink to indicate that it is Adaptive sync
capable.

v3:
* Fi the typo in commit message (Manasi)
v2:
* Rename to describe what the function does (Jani Nikula)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
---
 include/drm/drm_dp_helper.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 6c4b53dcb851..d43b5c9705d4 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1454,6 +1454,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 			DP_ALTERNATE_SCRAMBLER_RESET_CAP;
 }
 
+/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
+static inline bool
+drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+	return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
+		DP_MSA_TIMING_PAR_IGNORED;
+}
+
 /*
  * DisplayPort AUX channel
  */
-- 
2.19.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

WARNING: multiple messages have this Message-ID (diff)
From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Harry Wentland <harry.wentland@amd.com>,
	Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Subject: [Intel-gfx] [PATCH v5 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD
Date: Tue, 12 May 2020 22:34:29 -0700	[thread overview]
Message-ID: <20200513053431.2138-1-manasi.d.navare@intel.com> (raw)

DP sink device sets the Ignore MSA bit in its
DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to
ignore the MSA video timing parameters and its ability to support
seamless video timing change over a range of timing exposed by
DisplayID and EDID.
This is required for the sink to indicate that it is Adaptive sync
capable.

v3:
* Fi the typo in commit message (Manasi)
v2:
* Rename to describe what the function does (Jani Nikula)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
---
 include/drm/drm_dp_helper.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 6c4b53dcb851..d43b5c9705d4 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1454,6 +1454,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 			DP_ALTERNATE_SCRAMBLER_RESET_CAP;
 }
 
+/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
+static inline bool
+drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+	return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
+		DP_MSA_TIMING_PAR_IGNORED;
+}
+
 /*
  * DisplayPort AUX channel
  */
-- 
2.19.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

             reply	other threads:[~2020-05-13  5:33 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-13  5:34 Manasi Navare [this message]
2020-05-13  5:34 ` [Intel-gfx] [PATCH v5 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD Manasi Navare
2020-05-13  5:34 ` [PATCH v5 2/3] drm/i915/dp: Attach and set drm connector VRR property Manasi Navare
2020-05-13  5:34   ` [Intel-gfx] " Manasi Navare
2020-05-13  5:34 ` [PATCH v5 3/3] drm/i915/dp: Expose connector VRR info via debugfs Manasi Navare
2020-05-13  5:34   ` [Intel-gfx] " Manasi Navare
2020-05-13 11:08   ` Modem, Bhanuprakash
2020-05-13 11:08     ` [Intel-gfx] " Modem, Bhanuprakash
2020-05-13 18:21     ` Manasi Navare
2020-05-13 18:21       ` [Intel-gfx] " Manasi Navare
2020-05-14  3:42   ` Modem, Bhanuprakash
2020-05-14  3:42     ` [Intel-gfx] " Modem, Bhanuprakash
2020-05-13  5:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD Patchwork
2020-05-13  6:26 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-05-13 12:22 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [v5,1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD (rev2) Patchwork
2020-05-14  5:02 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [v5,1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD (rev3) Patchwork

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