[PATCH v5 00/16] Add Rockchip RK3399 USB3.0 Host support

[PATCH v5 00/16] Add Rockchip RK3399 USB3.0 Host support

[Frank Wang]

This series add quirks for DWC3 and add Rockchip RK3399 USB3.0 host support.

The function has been tested pass on rk3399-evb and roc-rk3399-pc board.

For V5 update:
 - Fix dwc3-generic driver followed Marek's comments for [PATCH v4 12/16].
 - Add 'Reviewed-by' and 'Tested-by' tag for [PATCH v4 07/16] and [PATCH v4 08/16].

For V4 update:
 - Collect Jagan's all fixed patches [1].
 - Amend specific u-boot changes from dts to dtsi for [PATCH v3 6/7].

For V3 update:
 - Fix compile error for [PATCH v2 1/9].
 - Use Jagan's Type-C driver instead of [PATCH v2 5/9].
 - Cleanup dts changes for [PATCH v2 7/9].
 - Cleanup config changes for [PATCH v2 8/9] and [PATCH v2 9/9].

For V2 update:
 - Amend type-c driver followed Jagan's comments for [PATCH 5/8].
 - Fix dts commit for [PATCH 7/8].
 - Split RK3399 default config for [PATCH 8/8].
 - Add 'Reviewed-by' tag for [PATCH 1/8], [PATCH 2/8] and [PATCH 3/8].

[1] https://patchwork.ozlabs.org/project/uboot/cover/20200506075025.1677-1-jagan@amarulasolutions.com

BR,
Frank

Frank Wang (7):
  usb: dwc3: add dis_enblslpm_quirk
  usb: dwc3: add dis_u2_freeclk_exists_quirk
  usb: dwc3: amend UTMI/UTMIW phy interface setup
  usb: dwc3: add make compatible for rockchip platform
  driver: usb: drop legacy rockchip xhci driver
  ARM: dts: rk3399-evb: usb3.0 host support
  configs: evb-rk3399: update support usb3.0 host

Jagan Teki (9):
  clk: rk3399: Enable/Disable the USB2PHY clk
  clk: rk3399: Set empty for TCPHY assigned-clocks
  clk: rk3399: Enable/Disable TCPHY clocks
  phy: rockchip: Add Rockchip USB2PHY driver
  arm64: dts: rk3399: Move u2phy into root port
  phy: rockchip: Add Rockchip USB TypeC PHY driver
  usb: dwc3: Add disable u2mac linestate check quirk
  usb: dwc3: Enable AutoRetry feature in the controller
  roc-rk3399-pc: Enable USB3.0 Host

 arch/arm/dts/rk3399-evb-u-boot.dtsi           |  13 +
 arch/arm/dts/rk3399.dtsi                      | 108 +--
 configs/evb-rk3399_defconfig                  |   6 +
 configs/roc-pc-mezzanine-rk3399_defconfig     |   5 +
 configs/roc-pc-rk3399_defconfig               |   6 +
 drivers/Makefile                              |   1 +
 drivers/clk/rockchip/clk_rk3399.c             |  38 +
 drivers/phy/Kconfig                           |   1 +
 drivers/phy/rockchip/Kconfig                  |  21 +
 drivers/phy/rockchip/Makefile                 |   7 +
 drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 312 +++++++
 drivers/phy/rockchip/phy-rockchip-typec.c     | 796 ++++++++++++++++++
 drivers/usb/common/common.c                   |  25 +
 drivers/usb/dwc3/core.c                       | 106 ++-
 drivers/usb/dwc3/core.h                       |  19 +
 drivers/usb/dwc3/dwc3-generic.c               |  33 +-
 drivers/usb/host/Kconfig                      |   9 -
 drivers/usb/host/Makefile                     |   1 -
 drivers/usb/host/xhci-rockchip.c              | 196 -----
 include/dwc3-uboot.h                          |   3 +
 include/linux/usb/phy.h                       |  18 +
 21 files changed, 1427 insertions(+), 297 deletions(-)
 create mode 100644 drivers/phy/rockchip/Kconfig
 create mode 100644 drivers/phy/rockchip/Makefile
 create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb2.c
 create mode 100644 drivers/phy/rockchip/phy-rockchip-typec.c
 delete mode 100644 drivers/usb/host/xhci-rockchip.c

-- 
2.17.1

[PATCH v5 00/16] Add Rockchip RK3399 USB3.0 Host support

[Frank Wang]

This series add quirks for DWC3 and add Rockchip RK3399 USB3.0 host support.

The function has been tested pass on rk3399-evb and roc-rk3399-pc board.

For V5 update:
 - Fix dwc3-generic driver followed Marek's comments for [PATCH v4 12/16].
 - Add 'Reviewed-by' and 'Tested-by' tag for [PATCH v4 07/16] and [PATCH v4 08/16].

For V4 update:
 - Collect Jagan's all fixed patches [1].
 - Amend specific u-boot changes from dts to dtsi for [PATCH v3 6/7].

For V3 update:
 - Fix compile error for [PATCH v2 1/9].
 - Use Jagan's Type-C driver instead of [PATCH v2 5/9].
 - Cleanup dts changes for [PATCH v2 7/9].
 - Cleanup config changes for [PATCH v2 8/9] and [PATCH v2 9/9].

For V2 update:
 - Amend type-c driver followed Jagan's comments for [PATCH 5/8].
 - Fix dts commit for [PATCH 7/8].
 - Split RK3399 default config for [PATCH 8/8].
 - Add 'Reviewed-by' tag for [PATCH 1/8], [PATCH 2/8] and [PATCH 3/8].

[1] https://patchwork.ozlabs.org/project/uboot/cover/20200506075025.1677-1-jagan at amarulasolutions.com

BR,
Frank

Frank Wang (7):
  usb: dwc3: add dis_enblslpm_quirk
  usb: dwc3: add dis_u2_freeclk_exists_quirk
  usb: dwc3: amend UTMI/UTMIW phy interface setup
  usb: dwc3: add make compatible for rockchip platform
  driver: usb: drop legacy rockchip xhci driver
  ARM: dts: rk3399-evb: usb3.0 host support
  configs: evb-rk3399: update support usb3.0 host

Jagan Teki (9):
  clk: rk3399: Enable/Disable the USB2PHY clk
  clk: rk3399: Set empty for TCPHY assigned-clocks
  clk: rk3399: Enable/Disable TCPHY clocks
  phy: rockchip: Add Rockchip USB2PHY driver
  arm64: dts: rk3399: Move u2phy into root port
  phy: rockchip: Add Rockchip USB TypeC PHY driver
  usb: dwc3: Add disable u2mac linestate check quirk
  usb: dwc3: Enable AutoRetry feature in the controller
  roc-rk3399-pc: Enable USB3.0 Host

 arch/arm/dts/rk3399-evb-u-boot.dtsi           |  13 +
 arch/arm/dts/rk3399.dtsi                      | 108 +--
 configs/evb-rk3399_defconfig                  |   6 +
 configs/roc-pc-mezzanine-rk3399_defconfig     |   5 +
 configs/roc-pc-rk3399_defconfig               |   6 +
 drivers/Makefile                              |   1 +
 drivers/clk/rockchip/clk_rk3399.c             |  38 +
 drivers/phy/Kconfig                           |   1 +
 drivers/phy/rockchip/Kconfig                  |  21 +
 drivers/phy/rockchip/Makefile                 |   7 +
 drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 312 +++++++
 drivers/phy/rockchip/phy-rockchip-typec.c     | 796 ++++++++++++++++++
 drivers/usb/common/common.c                   |  25 +
 drivers/usb/dwc3/core.c                       | 106 ++-
 drivers/usb/dwc3/core.h                       |  19 +
 drivers/usb/dwc3/dwc3-generic.c               |  33 +-
 drivers/usb/host/Kconfig                      |   9 -
 drivers/usb/host/Makefile                     |   1 -
 drivers/usb/host/xhci-rockchip.c              | 196 -----
 include/dwc3-uboot.h                          |   3 +
 include/linux/usb/phy.h                       |  18 +
 21 files changed, 1427 insertions(+), 297 deletions(-)
 create mode 100644 drivers/phy/rockchip/Kconfig
 create mode 100644 drivers/phy/rockchip/Makefile
 create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb2.c
 create mode 100644 drivers/phy/rockchip/phy-rockchip-typec.c
 delete mode 100644 drivers/usb/host/xhci-rockchip.c

-- 
2.17.1

[PATCH v5 01/16] clk: rk3399: Enable/Disable the USB2PHY clk

[Frank Wang]

From: Jagan Teki <jagan@amarulasolutions.com>

Enable/Disable the USB2PHY clk for rk3399.

CLK is clear in enable and set in disable functionality.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 5fb72d83c2..b53f2f984e 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1091,6 +1091,12 @@ static int rk3399_clk_enable(struct clk *clk)
 	case SCLK_MACREF_OUT:
 		rk_clrreg(&priv->cru->clkgate_con[5], BIT(6));
 		break;
+	case SCLK_USB2PHY0_REF:
+		rk_clrreg(&priv->cru->clkgate_con[6], BIT(5));
+		break;
+	case SCLK_USB2PHY1_REF:
+		rk_clrreg(&priv->cru->clkgate_con[6], BIT(6));
+		break;
 	case ACLK_GMAC:
 		rk_clrreg(&priv->cru->clkgate_con[32], BIT(0));
 		break;
@@ -1167,6 +1173,12 @@ static int rk3399_clk_disable(struct clk *clk)
 	case SCLK_MACREF_OUT:
 		rk_setreg(&priv->cru->clkgate_con[5], BIT(6));
 		break;
+	case SCLK_USB2PHY0_REF:
+		rk_setreg(&priv->cru->clkgate_con[6], BIT(5));
+		break;
+	case SCLK_USB2PHY1_REF:
+		rk_setreg(&priv->cru->clkgate_con[6], BIT(6));
+		break;
 	case ACLK_GMAC:
 		rk_setreg(&priv->cru->clkgate_con[32], BIT(0));
 		break;
-- 
2.17.1

[PATCH v5 01/16] clk: rk3399: Enable/Disable the USB2PHY clk

[Frank Wang]

From: Jagan Teki <jagan@amarulasolutions.com>

Enable/Disable the USB2PHY clk for rk3399.

CLK is clear in enable and set in disable functionality.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 5fb72d83c2..b53f2f984e 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1091,6 +1091,12 @@ static int rk3399_clk_enable(struct clk *clk)
 	case SCLK_MACREF_OUT:
 		rk_clrreg(&priv->cru->clkgate_con[5], BIT(6));
 		break;
+	case SCLK_USB2PHY0_REF:
+		rk_clrreg(&priv->cru->clkgate_con[6], BIT(5));
+		break;
+	case SCLK_USB2PHY1_REF:
+		rk_clrreg(&priv->cru->clkgate_con[6], BIT(6));
+		break;
 	case ACLK_GMAC:
 		rk_clrreg(&priv->cru->clkgate_con[32], BIT(0));
 		break;
@@ -1167,6 +1173,12 @@ static int rk3399_clk_disable(struct clk *clk)
 	case SCLK_MACREF_OUT:
 		rk_setreg(&priv->cru->clkgate_con[5], BIT(6));
 		break;
+	case SCLK_USB2PHY0_REF:
+		rk_setreg(&priv->cru->clkgate_con[6], BIT(5));
+		break;
+	case SCLK_USB2PHY1_REF:
+		rk_setreg(&priv->cru->clkgate_con[6], BIT(6));
+		break;
 	case ACLK_GMAC:
 		rk_setreg(&priv->cru->clkgate_con[32], BIT(0));
 		break;
-- 
2.17.1

Re: [PATCH v5 01/16] clk: rk3399: Enable/Disable the USB2PHY clk

[Kever Yang]

On 2020/5/13 下午3:13, Frank Wang wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Enable/Disable the USB2PHY clk for rk3399.
>
> CLK is clear in enable and set in disable functionality.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index 5fb72d83c2..b53f2f984e 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -1091,6 +1091,12 @@ static int rk3399_clk_enable(struct clk *clk)
>   	case SCLK_MACREF_OUT:
>   		rk_clrreg(&priv->cru->clkgate_con[5], BIT(6));
>   		break;
> +	case SCLK_USB2PHY0_REF:
> +		rk_clrreg(&priv->cru->clkgate_con[6], BIT(5));
> +		break;
> +	case SCLK_USB2PHY1_REF:
> +		rk_clrreg(&priv->cru->clkgate_con[6], BIT(6));
> +		break;
>   	case ACLK_GMAC:
>   		rk_clrreg(&priv->cru->clkgate_con[32], BIT(0));
>   		break;
> @@ -1167,6 +1173,12 @@ static int rk3399_clk_disable(struct clk *clk)
>   	case SCLK_MACREF_OUT:
>   		rk_setreg(&priv->cru->clkgate_con[5], BIT(6));
>   		break;
> +	case SCLK_USB2PHY0_REF:
> +		rk_setreg(&priv->cru->clkgate_con[6], BIT(5));
> +		break;
> +	case SCLK_USB2PHY1_REF:
> +		rk_setreg(&priv->cru->clkgate_con[6], BIT(6));
> +		break;
>   	case ACLK_GMAC:
>   		rk_setreg(&priv->cru->clkgate_con[32], BIT(0));
>   		break;

[PATCH v5 01/16] clk: rk3399: Enable/Disable the USB2PHY clk

[Kever Yang]

On 2020/5/13 ??3:13, Frank Wang wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Enable/Disable the USB2PHY clk for rk3399.
>
> CLK is clear in enable and set in disable functionality.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index 5fb72d83c2..b53f2f984e 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -1091,6 +1091,12 @@ static int rk3399_clk_enable(struct clk *clk)
>   	case SCLK_MACREF_OUT:
>   		rk_clrreg(&priv->cru->clkgate_con[5], BIT(6));
>   		break;
> +	case SCLK_USB2PHY0_REF:
> +		rk_clrreg(&priv->cru->clkgate_con[6], BIT(5));
> +		break;
> +	case SCLK_USB2PHY1_REF:
> +		rk_clrreg(&priv->cru->clkgate_con[6], BIT(6));
> +		break;
>   	case ACLK_GMAC:
>   		rk_clrreg(&priv->cru->clkgate_con[32], BIT(0));
>   		break;
> @@ -1167,6 +1173,12 @@ static int rk3399_clk_disable(struct clk *clk)
>   	case SCLK_MACREF_OUT:
>   		rk_setreg(&priv->cru->clkgate_con[5], BIT(6));
>   		break;
> +	case SCLK_USB2PHY0_REF:
> +		rk_setreg(&priv->cru->clkgate_con[6], BIT(5));
> +		break;
> +	case SCLK_USB2PHY1_REF:
> +		rk_setreg(&priv->cru->clkgate_con[6], BIT(6));
> +		break;
>   	case ACLK_GMAC:
>   		rk_setreg(&priv->cru->clkgate_con[32], BIT(0));
>   		break;

[PATCH v5 02/16] clk: rk3399: Set empty for TCPHY assigned-clocks

[Frank Wang]

From: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>

Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi
have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks
which are usually required for Linux and don't require to
handle them in U-Boot.

  assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
  assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;

So, mark them as empty in clock otherwise device probe on
those typec phy driver would fail.

Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 drivers/clk/rockchip/clk_rk3399.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index b53f2f984e..98fc6a3267 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -997,6 +997,8 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
 	case ACLK_VOP1:
 	case HCLK_VOP1:
 	case HCLK_SD:
+	case SCLK_UPHY0_TCPDCORE:
+	case SCLK_UPHY1_TCPDCORE:
 		/**
 		 * assigned-clocks handling won't require for vopl, so
 		 * return 0 to satisfy clk_set_defaults during device probe.
-- 
2.17.1

[PATCH v5 02/16] clk: rk3399: Set empty for TCPHY assigned-clocks

[Frank Wang]

From: Jagan Teki <jagan@amarulasolutions.com>

Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi
have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks
which are usually required for Linux and don't require to
handle them in U-Boot.

  assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
  assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;

So, mark them as empty in clock otherwise device probe on
those typec phy driver would fail.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/clk/rockchip/clk_rk3399.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index b53f2f984e..98fc6a3267 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -997,6 +997,8 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
 	case ACLK_VOP1:
 	case HCLK_VOP1:
 	case HCLK_SD:
+	case SCLK_UPHY0_TCPDCORE:
+	case SCLK_UPHY1_TCPDCORE:
 		/**
 		 * assigned-clocks handling won't require for vopl, so
 		 * return 0 to satisfy clk_set_defaults during device probe.
-- 
2.17.1

Re: [PATCH v5 02/16] clk: rk3399: Set empty for TCPHY assigned-clocks

[Kever Yang]

On 2020/5/13 下午3:13, Frank Wang wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi
> have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks
> which are usually required for Linux and don't require to
> handle them in U-Boot.
>
>    assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
>    assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
>
> So, mark them as empty in clock otherwise device probe on
> those typec phy driver would fail.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/clk/rockchip/clk_rk3399.c | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index b53f2f984e..98fc6a3267 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -997,6 +997,8 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
>   	case ACLK_VOP1:
>   	case HCLK_VOP1:
>   	case HCLK_SD:
> +	case SCLK_UPHY0_TCPDCORE:
> +	case SCLK_UPHY1_TCPDCORE:
>   		/**
>   		 * assigned-clocks handling won't require for vopl, so
>   		 * return 0 to satisfy clk_set_defaults during device probe.

[PATCH v5 02/16] clk: rk3399: Set empty for TCPHY assigned-clocks

[Kever Yang]

On 2020/5/13 ??3:13, Frank Wang wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi
> have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks
> which are usually required for Linux and don't require to
> handle them in U-Boot.
>
>    assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
>    assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
>
> So, mark them as empty in clock otherwise device probe on
> those typec phy driver would fail.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/clk/rockchip/clk_rk3399.c | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index b53f2f984e..98fc6a3267 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -997,6 +997,8 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
>   	case ACLK_VOP1:
>   	case HCLK_VOP1:
>   	case HCLK_SD:
> +	case SCLK_UPHY0_TCPDCORE:
> +	case SCLK_UPHY1_TCPDCORE:
>   		/**
>   		 * assigned-clocks handling won't require for vopl, so
>   		 * return 0 to satisfy clk_set_defaults during device probe.

[PATCH v5 03/16] clk: rk3399: Enable/Disable TCPHY clocks

[Frank Wang]

From: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>

Enable/Disable TCPHY clock for rk3399 platform.

Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 drivers/clk/rockchip/clk_rk3399.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 98fc6a3267..06232f1903 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1144,6 +1144,18 @@ static int rk3399_clk_enable(struct clk *clk)
 	case HCLK_HOST1_ARB:
 		rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
 		break;
+	case SCLK_UPHY0_TCPDPHY_REF:
+		rk_clrreg(&priv->cru->clkgate_con[13], BIT(4));
+		break;
+	case SCLK_UPHY0_TCPDCORE:
+		rk_clrreg(&priv->cru->clkgate_con[13], BIT(5));
+		break;
+	case SCLK_UPHY1_TCPDPHY_REF:
+		rk_clrreg(&priv->cru->clkgate_con[13], BIT(6));
+		break;
+	case SCLK_UPHY1_TCPDCORE:
+		rk_clrreg(&priv->cru->clkgate_con[13], BIT(7));
+		break;
 	case SCLK_PCIEPHY_REF:
 		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
 		break;
@@ -1226,6 +1238,18 @@ static int rk3399_clk_disable(struct clk *clk)
 	case HCLK_HOST1_ARB:
 		rk_setreg(&priv->cru->clksel_con[20], BIT(8));
 		break;
+	case SCLK_UPHY0_TCPDPHY_REF:
+		rk_setreg(&priv->cru->clkgate_con[13], BIT(4));
+		break;
+	case SCLK_UPHY0_TCPDCORE:
+		rk_setreg(&priv->cru->clkgate_con[13], BIT(5));
+		break;
+	case SCLK_UPHY1_TCPDPHY_REF:
+		rk_setreg(&priv->cru->clkgate_con[13], BIT(6));
+		break;
+	case SCLK_UPHY1_TCPDCORE:
+		rk_setreg(&priv->cru->clkgate_con[13], BIT(7));
+		break;
 	case SCLK_PCIEPHY_REF:
 		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
 		break;
-- 
2.17.1

[PATCH v5 03/16] clk: rk3399: Enable/Disable TCPHY clocks

[Frank Wang]

From: Jagan Teki <jagan@amarulasolutions.com>

Enable/Disable TCPHY clock for rk3399 platform.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/clk/rockchip/clk_rk3399.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 98fc6a3267..06232f1903 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1144,6 +1144,18 @@ static int rk3399_clk_enable(struct clk *clk)
 	case HCLK_HOST1_ARB:
 		rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
 		break;
+	case SCLK_UPHY0_TCPDPHY_REF:
+		rk_clrreg(&priv->cru->clkgate_con[13], BIT(4));
+		break;
+	case SCLK_UPHY0_TCPDCORE:
+		rk_clrreg(&priv->cru->clkgate_con[13], BIT(5));
+		break;
+	case SCLK_UPHY1_TCPDPHY_REF:
+		rk_clrreg(&priv->cru->clkgate_con[13], BIT(6));
+		break;
+	case SCLK_UPHY1_TCPDCORE:
+		rk_clrreg(&priv->cru->clkgate_con[13], BIT(7));
+		break;
 	case SCLK_PCIEPHY_REF:
 		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
 		break;
@@ -1226,6 +1238,18 @@ static int rk3399_clk_disable(struct clk *clk)
 	case HCLK_HOST1_ARB:
 		rk_setreg(&priv->cru->clksel_con[20], BIT(8));
 		break;
+	case SCLK_UPHY0_TCPDPHY_REF:
+		rk_setreg(&priv->cru->clkgate_con[13], BIT(4));
+		break;
+	case SCLK_UPHY0_TCPDCORE:
+		rk_setreg(&priv->cru->clkgate_con[13], BIT(5));
+		break;
+	case SCLK_UPHY1_TCPDPHY_REF:
+		rk_setreg(&priv->cru->clkgate_con[13], BIT(6));
+		break;
+	case SCLK_UPHY1_TCPDCORE:
+		rk_setreg(&priv->cru->clkgate_con[13], BIT(7));
+		break;
 	case SCLK_PCIEPHY_REF:
 		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
 		break;
-- 
2.17.1

Re: [PATCH v5 03/16] clk: rk3399: Enable/Disable TCPHY clocks

[Kever Yang]

On 2020/5/13 下午3:13, Frank Wang wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Enable/Disable TCPHY clock for rk3399 platform.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/clk/rockchip/clk_rk3399.c | 24 ++++++++++++++++++++++++
>   1 file changed, 24 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index 98fc6a3267..06232f1903 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -1144,6 +1144,18 @@ static int rk3399_clk_enable(struct clk *clk)
>   	case HCLK_HOST1_ARB:
>   		rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
>   		break;
> +	case SCLK_UPHY0_TCPDPHY_REF:
> +		rk_clrreg(&priv->cru->clkgate_con[13], BIT(4));
> +		break;
> +	case SCLK_UPHY0_TCPDCORE:
> +		rk_clrreg(&priv->cru->clkgate_con[13], BIT(5));
> +		break;
> +	case SCLK_UPHY1_TCPDPHY_REF:
> +		rk_clrreg(&priv->cru->clkgate_con[13], BIT(6));
> +		break;
> +	case SCLK_UPHY1_TCPDCORE:
> +		rk_clrreg(&priv->cru->clkgate_con[13], BIT(7));
> +		break;
>   	case SCLK_PCIEPHY_REF:
>   		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
>   		break;
> @@ -1226,6 +1238,18 @@ static int rk3399_clk_disable(struct clk *clk)
>   	case HCLK_HOST1_ARB:
>   		rk_setreg(&priv->cru->clksel_con[20], BIT(8));
>   		break;
> +	case SCLK_UPHY0_TCPDPHY_REF:
> +		rk_setreg(&priv->cru->clkgate_con[13], BIT(4));
> +		break;
> +	case SCLK_UPHY0_TCPDCORE:
> +		rk_setreg(&priv->cru->clkgate_con[13], BIT(5));
> +		break;
> +	case SCLK_UPHY1_TCPDPHY_REF:
> +		rk_setreg(&priv->cru->clkgate_con[13], BIT(6));
> +		break;
> +	case SCLK_UPHY1_TCPDCORE:
> +		rk_setreg(&priv->cru->clkgate_con[13], BIT(7));
> +		break;
>   	case SCLK_PCIEPHY_REF:
>   		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
>   		break;



_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v5 03/16] clk: rk3399: Enable/Disable TCPHY clocks

[Kever Yang]

On 2020/5/13 ??3:13, Frank Wang wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Enable/Disable TCPHY clock for rk3399 platform.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/clk/rockchip/clk_rk3399.c | 24 ++++++++++++++++++++++++
>   1 file changed, 24 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index 98fc6a3267..06232f1903 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -1144,6 +1144,18 @@ static int rk3399_clk_enable(struct clk *clk)
>   	case HCLK_HOST1_ARB:
>   		rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
>   		break;
> +	case SCLK_UPHY0_TCPDPHY_REF:
> +		rk_clrreg(&priv->cru->clkgate_con[13], BIT(4));
> +		break;
> +	case SCLK_UPHY0_TCPDCORE:
> +		rk_clrreg(&priv->cru->clkgate_con[13], BIT(5));
> +		break;
> +	case SCLK_UPHY1_TCPDPHY_REF:
> +		rk_clrreg(&priv->cru->clkgate_con[13], BIT(6));
> +		break;
> +	case SCLK_UPHY1_TCPDCORE:
> +		rk_clrreg(&priv->cru->clkgate_con[13], BIT(7));
> +		break;
>   	case SCLK_PCIEPHY_REF:
>   		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
>   		break;
> @@ -1226,6 +1238,18 @@ static int rk3399_clk_disable(struct clk *clk)
>   	case HCLK_HOST1_ARB:
>   		rk_setreg(&priv->cru->clksel_con[20], BIT(8));
>   		break;
> +	case SCLK_UPHY0_TCPDPHY_REF:
> +		rk_setreg(&priv->cru->clkgate_con[13], BIT(4));
> +		break;
> +	case SCLK_UPHY0_TCPDCORE:
> +		rk_setreg(&priv->cru->clkgate_con[13], BIT(5));
> +		break;
> +	case SCLK_UPHY1_TCPDPHY_REF:
> +		rk_setreg(&priv->cru->clkgate_con[13], BIT(6));
> +		break;
> +	case SCLK_UPHY1_TCPDCORE:
> +		rk_setreg(&priv->cru->clkgate_con[13], BIT(7));
> +		break;
>   	case SCLK_PCIEPHY_REF:
>   		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
>   		break;

[PATCH v5 04/16] phy: rockchip: Add Rockchip USB2PHY driver

[Frank Wang]

From: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>

Add Rockchip USB2PHY driver with initial support.

This will help to use it for EHCI controller in host
mode, and USB 3.0 controller in otg mode.

More functionality like charge, vbus detection will
add it in future changes.

Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 drivers/Makefile                              |   1 +
 drivers/phy/Kconfig                           |   1 +
 drivers/phy/rockchip/Kconfig                  |  14 +
 drivers/phy/rockchip/Makefile                 |   6 +
 drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 312 ++++++++++++++++++
 5 files changed, 334 insertions(+)
 create mode 100644 drivers/phy/rockchip/Kconfig
 create mode 100644 drivers/phy/rockchip/Makefile
 create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb2.c

diff --git a/drivers/Makefile b/drivers/Makefile
index 4208750428..94e8c5da17 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -91,6 +91,7 @@ obj-y += dfu/
 obj-$(CONFIG_PCH) += pch/
 obj-y += phy/allwinner/
 obj-y += phy/marvell/
+obj-y += phy/rockchip/
 obj-y += rtc/
 obj-y += scsi/
 obj-y += sound/
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 1e38c8741f..9c775107e9 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -225,4 +225,5 @@ config PHY_MTK_TPHY
 	  multi-ports is first version, otherwise is second veriosn,
 	  so you can easily distinguish them by banks layout.
 
+source "drivers/phy/rockchip/Kconfig"
 endmenu
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
new file mode 100644
index 0000000000..d73ac695e1
--- /dev/null
+++ b/drivers/phy/rockchip/Kconfig
@@ -0,0 +1,14 @@
+#
+# Phy drivers for Rockchip platforms
+#
+
+menu "Rockchip PHY driver"
+
+config PHY_ROCKCHIP_INNO_USB2
+	bool "Rockchip INNO USB2PHY Driver"
+	depends on ARCH_ROCKCHIP
+	select PHY
+	help
+	  Support for Rockchip USB2.0 PHY with Innosilicon IP block.
+
+endmenu
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
new file mode 100644
index 0000000000..9b0cbc6acf
--- /dev/null
+++ b/drivers/phy/rockchip/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Amarula Solutions(India)
+#
+
+obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
new file mode 100644
index 0000000000..dd4905d834
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Rockchip USB2.0 PHY with Innosilicon IP block driver
+ *
+ * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (C) 2020 Amarula Solutions(India)
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <generic-phy.h>
+#include <reset.h>
+#include <syscon.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <linux/iopoll.h>
+#include <asm/arch-rockchip/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define usleep_range(a, b) udelay((b))
+#define BIT_WRITEABLE_SHIFT	16
+
+enum rockchip_usb2phy_port_id {
+	USB2PHY_PORT_OTG,
+	USB2PHY_PORT_HOST,
+	USB2PHY_NUM_PORTS,
+};
+
+struct usb2phy_reg {
+	unsigned int	offset;
+	unsigned int	bitend;
+	unsigned int	bitstart;
+	unsigned int	disable;
+	unsigned int	enable;
+};
+
+struct rockchip_usb2phy_port_cfg {
+	struct usb2phy_reg	phy_sus;
+	struct usb2phy_reg	bvalid_det_en;
+	struct usb2phy_reg	bvalid_det_st;
+	struct usb2phy_reg	bvalid_det_clr;
+	struct usb2phy_reg	ls_det_en;
+	struct usb2phy_reg	ls_det_st;
+	struct usb2phy_reg	ls_det_clr;
+	struct usb2phy_reg	utmi_avalid;
+	struct usb2phy_reg	utmi_bvalid;
+	struct usb2phy_reg	utmi_ls;
+	struct usb2phy_reg	utmi_hstdet;
+};
+
+struct rockchip_usb2phy_cfg {
+	unsigned int reg;
+	const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
+};
+
+struct rockchip_usb2phy {
+	void *reg_base;
+	struct clk phyclk;
+	const struct rockchip_usb2phy_cfg *phy_cfg;
+};
+
+static inline int property_enable(void *reg_base,
+				  const struct usb2phy_reg *reg, bool en)
+{
+	unsigned int val, mask, tmp;
+
+	tmp = en ? reg->enable : reg->disable;
+	mask = GENMASK(reg->bitend, reg->bitstart);
+	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
+
+	return writel(val, reg_base + reg->offset);
+}
+
+static const
+struct rockchip_usb2phy_port_cfg *us2phy_get_port(struct phy *phy)
+{
+	struct udevice *parent = dev_get_parent(phy->dev);
+	struct rockchip_usb2phy *priv = dev_get_priv(parent);
+	const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
+
+	return &phy_cfg->port_cfgs[phy->id];
+}
+
+static int rockchip_usb2phy_power_on(struct phy *phy)
+{
+	struct udevice *parent = dev_get_parent(phy->dev);
+	struct rockchip_usb2phy *priv = dev_get_priv(parent);
+	const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
+
+	property_enable(priv->reg_base, &port_cfg->phy_sus, false);
+
+	/* waiting for the utmi_clk to become stable */
+	usleep_range(1500, 2000);
+
+	return 0;
+}
+
+static int rockchip_usb2phy_power_off(struct phy *phy)
+{
+	struct udevice *parent = dev_get_parent(phy->dev);
+	struct rockchip_usb2phy *priv = dev_get_priv(parent);
+	const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
+
+	property_enable(priv->reg_base, &port_cfg->phy_sus, true);
+
+	return 0;
+}
+
+static int rockchip_usb2phy_init(struct phy *phy)
+{
+	struct udevice *parent = dev_get_parent(phy->dev);
+	struct rockchip_usb2phy *priv = dev_get_priv(parent);
+	const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
+	int ret;
+
+	ret = clk_enable(&priv->phyclk);
+	if (ret) {
+		dev_err(phy->dev, "failed to enable phyclk (ret=%d)\n", ret);
+		return ret;
+	}
+
+	if (phy->id == USB2PHY_PORT_OTG) {
+		property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true);
+		property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true);
+	} else if (phy->id == USB2PHY_PORT_HOST) {
+		property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true);
+		property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true);
+	}
+
+	return 0;
+}
+
+static int rockchip_usb2phy_exit(struct phy *phy)
+{
+	struct udevice *parent = dev_get_parent(phy->dev);
+	struct rockchip_usb2phy *priv = dev_get_priv(parent);
+
+	clk_disable(&priv->phyclk);
+
+	return 0;
+}
+
+static int rockchip_usb2phy_of_xlate(struct phy *phy,
+				     struct ofnode_phandle_args *args)
+{
+	const char *name = phy->dev->name;
+
+	if (!strcasecmp(name, "host-port"))
+		phy->id = USB2PHY_PORT_HOST;
+	else if (!strcasecmp(name, "otg-port"))
+		phy->id = USB2PHY_PORT_OTG;
+	else
+		dev_err(phy->dev, "improper %s device\n", name);
+
+	return 0;
+}
+
+static struct phy_ops rockchip_usb2phy_ops = {
+	.init = rockchip_usb2phy_init,
+	.exit = rockchip_usb2phy_exit,
+	.power_on = rockchip_usb2phy_power_on,
+	.power_off = rockchip_usb2phy_power_off,
+	.of_xlate = rockchip_usb2phy_of_xlate,
+};
+
+static int rockchip_usb2phy_probe(struct udevice *dev)
+{
+	struct rockchip_usb2phy *priv = dev_get_priv(dev);
+	const struct rockchip_usb2phy_cfg *phy_cfgs;
+	unsigned int reg;
+	int index, ret;
+
+	priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	if (IS_ERR(priv->reg_base))
+		return PTR_ERR(priv->reg_base);
+
+	ret = dev_read_u32_index(dev, "reg", 1, &reg);
+	if (ret) {
+		dev_err(dev, "failed to read reg property (ret = %d)\n", ret);
+		return ret;
+	}
+
+	phy_cfgs = (const struct rockchip_usb2phy_cfg *)
+					dev_get_driver_data(dev);
+	if (!phy_cfgs)
+		return -EINVAL;
+
+	/* find out a proper config which can be matched with dt. */
+	index = 0;
+	while (phy_cfgs[index].reg) {
+		if (phy_cfgs[index].reg == reg) {
+			priv->phy_cfg = &phy_cfgs[index];
+			break;
+		}
+
+		++index;
+	}
+
+	if (!priv->phy_cfg) {
+		dev_err(dev, "failed find proper phy-cfg\n");
+		return -EINVAL;
+	}
+
+	ret = clk_get_by_name(dev, "phyclk", &priv->phyclk);
+	if (ret) {
+		dev_err(dev, "failed to get the phyclk (ret=%d)\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_usb2phy_bind(struct udevice *dev)
+{
+	struct udevice *usb2phy_dev;
+	ofnode node;
+	const char *name;
+	int ret = 0;
+
+	dev_for_each_subnode(node, dev) {
+		if (!ofnode_valid(node)) {
+			dev_info(dev, "subnode %s not found\n", dev->name);
+			return -ENXIO;
+		}
+
+		name = ofnode_get_name(node);
+		dev_dbg(dev, "subnode %s\n", name);
+
+		ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port",
+						 name, node, &usb2phy_dev);
+		if (ret) {
+			dev_err(dev,
+				"'%s' cannot bind 'rockchip_usb2phy_port'\n", name);
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
+static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = {
+	{
+		.reg		= 0xe450,
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus	= { 0xe454, 1, 0, 2, 1 },
+				.bvalid_det_en	= { 0xe3c0, 3, 3, 0, 1 },
+				.bvalid_det_st	= { 0xe3e0, 3, 3, 0, 1 },
+				.bvalid_det_clr	= { 0xe3d0, 3, 3, 0, 1 },
+				.utmi_avalid	= { 0xe2ac, 7, 7, 0, 1 },
+				.utmi_bvalid	= { 0xe2ac, 12, 12, 0, 1 },
+			},
+			[USB2PHY_PORT_HOST] = {
+				.phy_sus	= { 0xe458, 1, 0, 0x2, 0x1 },
+				.ls_det_en	= { 0xe3c0, 6, 6, 0, 1 },
+				.ls_det_st	= { 0xe3e0, 6, 6, 0, 1 },
+				.ls_det_clr	= { 0xe3d0, 6, 6, 0, 1 },
+				.utmi_ls	= { 0xe2ac, 22, 21, 0, 1 },
+				.utmi_hstdet	= { 0xe2ac, 23, 23, 0, 1 }
+			}
+		},
+	},
+	{
+		.reg		= 0xe460,
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus        = { 0xe464, 1, 0, 2, 1 },
+				.bvalid_det_en  = { 0xe3c0, 8, 8, 0, 1 },
+				.bvalid_det_st  = { 0xe3e0, 8, 8, 0, 1 },
+				.bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
+				.utmi_avalid	= { 0xe2ac, 10, 10, 0, 1 },
+				.utmi_bvalid    = { 0xe2ac, 16, 16, 0, 1 },
+			},
+			[USB2PHY_PORT_HOST] = {
+				.phy_sus	= { 0xe468, 1, 0, 0x2, 0x1 },
+				.ls_det_en	= { 0xe3c0, 11, 11, 0, 1 },
+				.ls_det_st	= { 0xe3e0, 11, 11, 0, 1 },
+				.ls_det_clr	= { 0xe3d0, 11, 11, 0, 1 },
+				.utmi_ls	= { 0xe2ac, 26, 25, 0, 1 },
+				.utmi_hstdet	= { 0xe2ac, 27, 27, 0, 1 }
+			}
+		},
+	},
+	{ /* sentinel */ }
+};
+
+static const struct udevice_id rockchip_usb2phy_ids[] = {
+	{
+		.compatible = "rockchip,rk3399-usb2phy",
+		.data = (ulong)&rk3399_usb2phy_cfgs,
+	},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(rockchip_usb2phy_port) = {
+	.name		= "rockchip_usb2phy_port",
+	.id		= UCLASS_PHY,
+	.ops		= &rockchip_usb2phy_ops,
+};
+
+U_BOOT_DRIVER(rockchip_usb2phy) = {
+	.name	= "rockchip_usb2phy",
+	.id	= UCLASS_PHY,
+	.of_match = rockchip_usb2phy_ids,
+	.probe = rockchip_usb2phy_probe,
+	.bind = rockchip_usb2phy_bind,
+	.priv_auto_alloc_size = sizeof(struct rockchip_usb2phy),
+};
-- 
2.17.1

[PATCH v5 04/16] phy: rockchip: Add Rockchip USB2PHY driver

[Frank Wang]

From: Jagan Teki <jagan@amarulasolutions.com>

Add Rockchip USB2PHY driver with initial support.

This will help to use it for EHCI controller in host
mode, and USB 3.0 controller in otg mode.

More functionality like charge, vbus detection will
add it in future changes.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/Makefile                              |   1 +
 drivers/phy/Kconfig                           |   1 +
 drivers/phy/rockchip/Kconfig                  |  14 +
 drivers/phy/rockchip/Makefile                 |   6 +
 drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 312 ++++++++++++++++++
 5 files changed, 334 insertions(+)
 create mode 100644 drivers/phy/rockchip/Kconfig
 create mode 100644 drivers/phy/rockchip/Makefile
 create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb2.c

diff --git a/drivers/Makefile b/drivers/Makefile
index 4208750428..94e8c5da17 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -91,6 +91,7 @@ obj-y += dfu/
 obj-$(CONFIG_PCH) += pch/
 obj-y += phy/allwinner/
 obj-y += phy/marvell/
+obj-y += phy/rockchip/
 obj-y += rtc/
 obj-y += scsi/
 obj-y += sound/
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 1e38c8741f..9c775107e9 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -225,4 +225,5 @@ config PHY_MTK_TPHY
 	  multi-ports is first version, otherwise is second veriosn,
 	  so you can easily distinguish them by banks layout.
 
+source "drivers/phy/rockchip/Kconfig"
 endmenu
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
new file mode 100644
index 0000000000..d73ac695e1
--- /dev/null
+++ b/drivers/phy/rockchip/Kconfig
@@ -0,0 +1,14 @@
+#
+# Phy drivers for Rockchip platforms
+#
+
+menu "Rockchip PHY driver"
+
+config PHY_ROCKCHIP_INNO_USB2
+	bool "Rockchip INNO USB2PHY Driver"
+	depends on ARCH_ROCKCHIP
+	select PHY
+	help
+	  Support for Rockchip USB2.0 PHY with Innosilicon IP block.
+
+endmenu
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
new file mode 100644
index 0000000000..9b0cbc6acf
--- /dev/null
+++ b/drivers/phy/rockchip/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Amarula Solutions(India)
+#
+
+obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
new file mode 100644
index 0000000000..dd4905d834
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Rockchip USB2.0 PHY with Innosilicon IP block driver
+ *
+ * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (C) 2020 Amarula Solutions(India)
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <generic-phy.h>
+#include <reset.h>
+#include <syscon.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <linux/iopoll.h>
+#include <asm/arch-rockchip/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define usleep_range(a, b) udelay((b))
+#define BIT_WRITEABLE_SHIFT	16
+
+enum rockchip_usb2phy_port_id {
+	USB2PHY_PORT_OTG,
+	USB2PHY_PORT_HOST,
+	USB2PHY_NUM_PORTS,
+};
+
+struct usb2phy_reg {
+	unsigned int	offset;
+	unsigned int	bitend;
+	unsigned int	bitstart;
+	unsigned int	disable;
+	unsigned int	enable;
+};
+
+struct rockchip_usb2phy_port_cfg {
+	struct usb2phy_reg	phy_sus;
+	struct usb2phy_reg	bvalid_det_en;
+	struct usb2phy_reg	bvalid_det_st;
+	struct usb2phy_reg	bvalid_det_clr;
+	struct usb2phy_reg	ls_det_en;
+	struct usb2phy_reg	ls_det_st;
+	struct usb2phy_reg	ls_det_clr;
+	struct usb2phy_reg	utmi_avalid;
+	struct usb2phy_reg	utmi_bvalid;
+	struct usb2phy_reg	utmi_ls;
+	struct usb2phy_reg	utmi_hstdet;
+};
+
+struct rockchip_usb2phy_cfg {
+	unsigned int reg;
+	const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
+};
+
+struct rockchip_usb2phy {
+	void *reg_base;
+	struct clk phyclk;
+	const struct rockchip_usb2phy_cfg *phy_cfg;
+};
+
+static inline int property_enable(void *reg_base,
+				  const struct usb2phy_reg *reg, bool en)
+{
+	unsigned int val, mask, tmp;
+
+	tmp = en ? reg->enable : reg->disable;
+	mask = GENMASK(reg->bitend, reg->bitstart);
+	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
+
+	return writel(val, reg_base + reg->offset);
+}
+
+static const
+struct rockchip_usb2phy_port_cfg *us2phy_get_port(struct phy *phy)
+{
+	struct udevice *parent = dev_get_parent(phy->dev);
+	struct rockchip_usb2phy *priv = dev_get_priv(parent);
+	const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
+
+	return &phy_cfg->port_cfgs[phy->id];
+}
+
+static int rockchip_usb2phy_power_on(struct phy *phy)
+{
+	struct udevice *parent = dev_get_parent(phy->dev);
+	struct rockchip_usb2phy *priv = dev_get_priv(parent);
+	const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
+
+	property_enable(priv->reg_base, &port_cfg->phy_sus, false);
+
+	/* waiting for the utmi_clk to become stable */
+	usleep_range(1500, 2000);
+
+	return 0;
+}
+
+static int rockchip_usb2phy_power_off(struct phy *phy)
+{
+	struct udevice *parent = dev_get_parent(phy->dev);
+	struct rockchip_usb2phy *priv = dev_get_priv(parent);
+	const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
+
+	property_enable(priv->reg_base, &port_cfg->phy_sus, true);
+
+	return 0;
+}
+
+static int rockchip_usb2phy_init(struct phy *phy)
+{
+	struct udevice *parent = dev_get_parent(phy->dev);
+	struct rockchip_usb2phy *priv = dev_get_priv(parent);
+	const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
+	int ret;
+
+	ret = clk_enable(&priv->phyclk);
+	if (ret) {
+		dev_err(phy->dev, "failed to enable phyclk (ret=%d)\n", ret);
+		return ret;
+	}
+
+	if (phy->id == USB2PHY_PORT_OTG) {
+		property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true);
+		property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true);
+	} else if (phy->id == USB2PHY_PORT_HOST) {
+		property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true);
+		property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true);
+	}
+
+	return 0;
+}
+
+static int rockchip_usb2phy_exit(struct phy *phy)
+{
+	struct udevice *parent = dev_get_parent(phy->dev);
+	struct rockchip_usb2phy *priv = dev_get_priv(parent);
+
+	clk_disable(&priv->phyclk);
+
+	return 0;
+}
+
+static int rockchip_usb2phy_of_xlate(struct phy *phy,
+				     struct ofnode_phandle_args *args)
+{
+	const char *name = phy->dev->name;
+
+	if (!strcasecmp(name, "host-port"))
+		phy->id = USB2PHY_PORT_HOST;
+	else if (!strcasecmp(name, "otg-port"))
+		phy->id = USB2PHY_PORT_OTG;
+	else
+		dev_err(phy->dev, "improper %s device\n", name);
+
+	return 0;
+}
+
+static struct phy_ops rockchip_usb2phy_ops = {
+	.init = rockchip_usb2phy_init,
+	.exit = rockchip_usb2phy_exit,
+	.power_on = rockchip_usb2phy_power_on,
+	.power_off = rockchip_usb2phy_power_off,
+	.of_xlate = rockchip_usb2phy_of_xlate,
+};
+
+static int rockchip_usb2phy_probe(struct udevice *dev)
+{
+	struct rockchip_usb2phy *priv = dev_get_priv(dev);
+	const struct rockchip_usb2phy_cfg *phy_cfgs;
+	unsigned int reg;
+	int index, ret;
+
+	priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	if (IS_ERR(priv->reg_base))
+		return PTR_ERR(priv->reg_base);
+
+	ret = dev_read_u32_index(dev, "reg", 1, &reg);
+	if (ret) {
+		dev_err(dev, "failed to read reg property (ret = %d)\n", ret);
+		return ret;
+	}
+
+	phy_cfgs = (const struct rockchip_usb2phy_cfg *)
+					dev_get_driver_data(dev);
+	if (!phy_cfgs)
+		return -EINVAL;
+
+	/* find out a proper config which can be matched with dt. */
+	index = 0;
+	while (phy_cfgs[index].reg) {
+		if (phy_cfgs[index].reg == reg) {
+			priv->phy_cfg = &phy_cfgs[index];
+			break;
+		}
+
+		++index;
+	}
+
+	if (!priv->phy_cfg) {
+		dev_err(dev, "failed find proper phy-cfg\n");
+		return -EINVAL;
+	}
+
+	ret = clk_get_by_name(dev, "phyclk", &priv->phyclk);
+	if (ret) {
+		dev_err(dev, "failed to get the phyclk (ret=%d)\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_usb2phy_bind(struct udevice *dev)
+{
+	struct udevice *usb2phy_dev;
+	ofnode node;
+	const char *name;
+	int ret = 0;
+
+	dev_for_each_subnode(node, dev) {
+		if (!ofnode_valid(node)) {
+			dev_info(dev, "subnode %s not found\n", dev->name);
+			return -ENXIO;
+		}
+
+		name = ofnode_get_name(node);
+		dev_dbg(dev, "subnode %s\n", name);
+
+		ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port",
+						 name, node, &usb2phy_dev);
+		if (ret) {
+			dev_err(dev,
+				"'%s' cannot bind 'rockchip_usb2phy_port'\n", name);
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
+static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = {
+	{
+		.reg		= 0xe450,
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus	= { 0xe454, 1, 0, 2, 1 },
+				.bvalid_det_en	= { 0xe3c0, 3, 3, 0, 1 },
+				.bvalid_det_st	= { 0xe3e0, 3, 3, 0, 1 },
+				.bvalid_det_clr	= { 0xe3d0, 3, 3, 0, 1 },
+				.utmi_avalid	= { 0xe2ac, 7, 7, 0, 1 },
+				.utmi_bvalid	= { 0xe2ac, 12, 12, 0, 1 },
+			},
+			[USB2PHY_PORT_HOST] = {
+				.phy_sus	= { 0xe458, 1, 0, 0x2, 0x1 },
+				.ls_det_en	= { 0xe3c0, 6, 6, 0, 1 },
+				.ls_det_st	= { 0xe3e0, 6, 6, 0, 1 },
+				.ls_det_clr	= { 0xe3d0, 6, 6, 0, 1 },
+				.utmi_ls	= { 0xe2ac, 22, 21, 0, 1 },
+				.utmi_hstdet	= { 0xe2ac, 23, 23, 0, 1 }
+			}
+		},
+	},
+	{
+		.reg		= 0xe460,
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus        = { 0xe464, 1, 0, 2, 1 },
+				.bvalid_det_en  = { 0xe3c0, 8, 8, 0, 1 },
+				.bvalid_det_st  = { 0xe3e0, 8, 8, 0, 1 },
+				.bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
+				.utmi_avalid	= { 0xe2ac, 10, 10, 0, 1 },
+				.utmi_bvalid    = { 0xe2ac, 16, 16, 0, 1 },
+			},
+			[USB2PHY_PORT_HOST] = {
+				.phy_sus	= { 0xe468, 1, 0, 0x2, 0x1 },
+				.ls_det_en	= { 0xe3c0, 11, 11, 0, 1 },
+				.ls_det_st	= { 0xe3e0, 11, 11, 0, 1 },
+				.ls_det_clr	= { 0xe3d0, 11, 11, 0, 1 },
+				.utmi_ls	= { 0xe2ac, 26, 25, 0, 1 },
+				.utmi_hstdet	= { 0xe2ac, 27, 27, 0, 1 }
+			}
+		},
+	},
+	{ /* sentinel */ }
+};
+
+static const struct udevice_id rockchip_usb2phy_ids[] = {
+	{
+		.compatible = "rockchip,rk3399-usb2phy",
+		.data = (ulong)&rk3399_usb2phy_cfgs,
+	},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(rockchip_usb2phy_port) = {
+	.name		= "rockchip_usb2phy_port",
+	.id		= UCLASS_PHY,
+	.ops		= &rockchip_usb2phy_ops,
+};
+
+U_BOOT_DRIVER(rockchip_usb2phy) = {
+	.name	= "rockchip_usb2phy",
+	.id	= UCLASS_PHY,
+	.of_match = rockchip_usb2phy_ids,
+	.probe = rockchip_usb2phy_probe,
+	.bind = rockchip_usb2phy_bind,
+	.priv_auto_alloc_size = sizeof(struct rockchip_usb2phy),
+};
-- 
2.17.1

Re: [PATCH v5 04/16] phy: rockchip: Add Rockchip USB2PHY driver

[Kever Yang]

On 2020/5/13 下午3:13, Frank Wang wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Add Rockchip USB2PHY driver with initial support.
>
> This will help to use it for EHCI controller in host
> mode, and USB 3.0 controller in otg mode.
>
> More functionality like charge, vbus detection will
> add it in future changes.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/Makefile                              |   1 +
>   drivers/phy/Kconfig                           |   1 +
>   drivers/phy/rockchip/Kconfig                  |  14 +
>   drivers/phy/rockchip/Makefile                 |   6 +
>   drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 312 ++++++++++++++++++
>   5 files changed, 334 insertions(+)
>   create mode 100644 drivers/phy/rockchip/Kconfig
>   create mode 100644 drivers/phy/rockchip/Makefile
>   create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb2.c
>
> diff --git a/drivers/Makefile b/drivers/Makefile
> index 4208750428..94e8c5da17 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -91,6 +91,7 @@ obj-y += dfu/
>   obj-$(CONFIG_PCH) += pch/
>   obj-y += phy/allwinner/
>   obj-y += phy/marvell/
> +obj-y += phy/rockchip/
>   obj-y += rtc/
>   obj-y += scsi/
>   obj-y += sound/
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 1e38c8741f..9c775107e9 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -225,4 +225,5 @@ config PHY_MTK_TPHY
>   	  multi-ports is first version, otherwise is second veriosn,
>   	  so you can easily distinguish them by banks layout.
>   
> +source "drivers/phy/rockchip/Kconfig"
>   endmenu
> diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
> new file mode 100644
> index 0000000000..d73ac695e1
> --- /dev/null
> +++ b/drivers/phy/rockchip/Kconfig
> @@ -0,0 +1,14 @@
> +#
> +# Phy drivers for Rockchip platforms
> +#
> +
> +menu "Rockchip PHY driver"
> +
> +config PHY_ROCKCHIP_INNO_USB2
> +	bool "Rockchip INNO USB2PHY Driver"
> +	depends on ARCH_ROCKCHIP
> +	select PHY
> +	help
> +	  Support for Rockchip USB2.0 PHY with Innosilicon IP block.
> +
> +endmenu
> diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
> new file mode 100644
> index 0000000000..9b0cbc6acf
> --- /dev/null
> +++ b/drivers/phy/rockchip/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (C) 2020 Amarula Solutions(India)
> +#
> +
> +obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
> diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> new file mode 100644
> index 0000000000..dd4905d834
> --- /dev/null
> +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> @@ -0,0 +1,312 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Rockchip USB2.0 PHY with Innosilicon IP block driver
> + *
> + * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
> + * Copyright (C) 2020 Amarula Solutions(India)
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <dm/device_compat.h>
> +#include <dm/lists.h>
> +#include <generic-phy.h>
> +#include <reset.h>
> +#include <syscon.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <linux/iopoll.h>
> +#include <asm/arch-rockchip/clock.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define usleep_range(a, b) udelay((b))
> +#define BIT_WRITEABLE_SHIFT	16
> +
> +enum rockchip_usb2phy_port_id {
> +	USB2PHY_PORT_OTG,
> +	USB2PHY_PORT_HOST,
> +	USB2PHY_NUM_PORTS,
> +};
> +
> +struct usb2phy_reg {
> +	unsigned int	offset;
> +	unsigned int	bitend;
> +	unsigned int	bitstart;
> +	unsigned int	disable;
> +	unsigned int	enable;
> +};
> +
> +struct rockchip_usb2phy_port_cfg {
> +	struct usb2phy_reg	phy_sus;
> +	struct usb2phy_reg	bvalid_det_en;
> +	struct usb2phy_reg	bvalid_det_st;
> +	struct usb2phy_reg	bvalid_det_clr;
> +	struct usb2phy_reg	ls_det_en;
> +	struct usb2phy_reg	ls_det_st;
> +	struct usb2phy_reg	ls_det_clr;
> +	struct usb2phy_reg	utmi_avalid;
> +	struct usb2phy_reg	utmi_bvalid;
> +	struct usb2phy_reg	utmi_ls;
> +	struct usb2phy_reg	utmi_hstdet;
> +};
> +
> +struct rockchip_usb2phy_cfg {
> +	unsigned int reg;
> +	const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
> +};
> +
> +struct rockchip_usb2phy {
> +	void *reg_base;
> +	struct clk phyclk;
> +	const struct rockchip_usb2phy_cfg *phy_cfg;
> +};
> +
> +static inline int property_enable(void *reg_base,
> +				  const struct usb2phy_reg *reg, bool en)
> +{
> +	unsigned int val, mask, tmp;
> +
> +	tmp = en ? reg->enable : reg->disable;
> +	mask = GENMASK(reg->bitend, reg->bitstart);
> +	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
> +
> +	return writel(val, reg_base + reg->offset);
> +}
> +
> +static const
> +struct rockchip_usb2phy_port_cfg *us2phy_get_port(struct phy *phy)
> +{
> +	struct udevice *parent = dev_get_parent(phy->dev);
> +	struct rockchip_usb2phy *priv = dev_get_priv(parent);
> +	const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
> +
> +	return &phy_cfg->port_cfgs[phy->id];
> +}
> +
> +static int rockchip_usb2phy_power_on(struct phy *phy)
> +{
> +	struct udevice *parent = dev_get_parent(phy->dev);
> +	struct rockchip_usb2phy *priv = dev_get_priv(parent);
> +	const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
> +
> +	property_enable(priv->reg_base, &port_cfg->phy_sus, false);
> +
> +	/* waiting for the utmi_clk to become stable */
> +	usleep_range(1500, 2000);
> +
> +	return 0;
> +}
> +
> +static int rockchip_usb2phy_power_off(struct phy *phy)
> +{
> +	struct udevice *parent = dev_get_parent(phy->dev);
> +	struct rockchip_usb2phy *priv = dev_get_priv(parent);
> +	const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
> +
> +	property_enable(priv->reg_base, &port_cfg->phy_sus, true);
> +
> +	return 0;
> +}
> +
> +static int rockchip_usb2phy_init(struct phy *phy)
> +{
> +	struct udevice *parent = dev_get_parent(phy->dev);
> +	struct rockchip_usb2phy *priv = dev_get_priv(parent);
> +	const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
> +	int ret;
> +
> +	ret = clk_enable(&priv->phyclk);
> +	if (ret) {
> +		dev_err(phy->dev, "failed to enable phyclk (ret=%d)\n", ret);
> +		return ret;
> +	}
> +
> +	if (phy->id == USB2PHY_PORT_OTG) {
> +		property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true);
> +		property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true);
> +	} else if (phy->id == USB2PHY_PORT_HOST) {
> +		property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true);
> +		property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true);
> +	}
> +
> +	return 0;
> +}
> +
> +static int rockchip_usb2phy_exit(struct phy *phy)
> +{
> +	struct udevice *parent = dev_get_parent(phy->dev);
> +	struct rockchip_usb2phy *priv = dev_get_priv(parent);
> +
> +	clk_disable(&priv->phyclk);
> +
> +	return 0;
> +}
> +
> +static int rockchip_usb2phy_of_xlate(struct phy *phy,
> +				     struct ofnode_phandle_args *args)
> +{
> +	const char *name = phy->dev->name;
> +
> +	if (!strcasecmp(name, "host-port"))
> +		phy->id = USB2PHY_PORT_HOST;
> +	else if (!strcasecmp(name, "otg-port"))
> +		phy->id = USB2PHY_PORT_OTG;
> +	else
> +		dev_err(phy->dev, "improper %s device\n", name);
> +
> +	return 0;
> +}
> +
> +static struct phy_ops rockchip_usb2phy_ops = {
> +	.init = rockchip_usb2phy_init,
> +	.exit = rockchip_usb2phy_exit,
> +	.power_on = rockchip_usb2phy_power_on,
> +	.power_off = rockchip_usb2phy_power_off,
> +	.of_xlate = rockchip_usb2phy_of_xlate,
> +};
> +
> +static int rockchip_usb2phy_probe(struct udevice *dev)
> +{
> +	struct rockchip_usb2phy *priv = dev_get_priv(dev);
> +	const struct rockchip_usb2phy_cfg *phy_cfgs;
> +	unsigned int reg;
> +	int index, ret;
> +
> +	priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +	if (IS_ERR(priv->reg_base))
> +		return PTR_ERR(priv->reg_base);
> +
> +	ret = dev_read_u32_index(dev, "reg", 1, &reg);
> +	if (ret) {
> +		dev_err(dev, "failed to read reg property (ret = %d)\n", ret);
> +		return ret;
> +	}
> +
> +	phy_cfgs = (const struct rockchip_usb2phy_cfg *)
> +					dev_get_driver_data(dev);
> +	if (!phy_cfgs)
> +		return -EINVAL;
> +
> +	/* find out a proper config which can be matched with dt. */
> +	index = 0;
> +	while (phy_cfgs[index].reg) {
> +		if (phy_cfgs[index].reg == reg) {
> +			priv->phy_cfg = &phy_cfgs[index];
> +			break;
> +		}
> +
> +		++index;
> +	}
> +
> +	if (!priv->phy_cfg) {
> +		dev_err(dev, "failed find proper phy-cfg\n");
> +		return -EINVAL;
> +	}
> +
> +	ret = clk_get_by_name(dev, "phyclk", &priv->phyclk);
> +	if (ret) {
> +		dev_err(dev, "failed to get the phyclk (ret=%d)\n", ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int rockchip_usb2phy_bind(struct udevice *dev)
> +{
> +	struct udevice *usb2phy_dev;
> +	ofnode node;
> +	const char *name;
> +	int ret = 0;
> +
> +	dev_for_each_subnode(node, dev) {
> +		if (!ofnode_valid(node)) {
> +			dev_info(dev, "subnode %s not found\n", dev->name);
> +			return -ENXIO;
> +		}
> +
> +		name = ofnode_get_name(node);
> +		dev_dbg(dev, "subnode %s\n", name);
> +
> +		ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port",
> +						 name, node, &usb2phy_dev);
> +		if (ret) {
> +			dev_err(dev,
> +				"'%s' cannot bind 'rockchip_usb2phy_port'\n", name);
> +			return ret;
> +		}
> +	}
> +
> +	return ret;
> +}
> +
> +static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = {
> +	{
> +		.reg		= 0xe450,
> +		.port_cfgs	= {
> +			[USB2PHY_PORT_OTG] = {
> +				.phy_sus	= { 0xe454, 1, 0, 2, 1 },
> +				.bvalid_det_en	= { 0xe3c0, 3, 3, 0, 1 },
> +				.bvalid_det_st	= { 0xe3e0, 3, 3, 0, 1 },
> +				.bvalid_det_clr	= { 0xe3d0, 3, 3, 0, 1 },
> +				.utmi_avalid	= { 0xe2ac, 7, 7, 0, 1 },
> +				.utmi_bvalid	= { 0xe2ac, 12, 12, 0, 1 },
> +			},
> +			[USB2PHY_PORT_HOST] = {
> +				.phy_sus	= { 0xe458, 1, 0, 0x2, 0x1 },
> +				.ls_det_en	= { 0xe3c0, 6, 6, 0, 1 },
> +				.ls_det_st	= { 0xe3e0, 6, 6, 0, 1 },
> +				.ls_det_clr	= { 0xe3d0, 6, 6, 0, 1 },
> +				.utmi_ls	= { 0xe2ac, 22, 21, 0, 1 },
> +				.utmi_hstdet	= { 0xe2ac, 23, 23, 0, 1 }
> +			}
> +		},
> +	},
> +	{
> +		.reg		= 0xe460,
> +		.port_cfgs	= {
> +			[USB2PHY_PORT_OTG] = {
> +				.phy_sus        = { 0xe464, 1, 0, 2, 1 },
> +				.bvalid_det_en  = { 0xe3c0, 8, 8, 0, 1 },
> +				.bvalid_det_st  = { 0xe3e0, 8, 8, 0, 1 },
> +				.bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
> +				.utmi_avalid	= { 0xe2ac, 10, 10, 0, 1 },
> +				.utmi_bvalid    = { 0xe2ac, 16, 16, 0, 1 },
> +			},
> +			[USB2PHY_PORT_HOST] = {
> +				.phy_sus	= { 0xe468, 1, 0, 0x2, 0x1 },
> +				.ls_det_en	= { 0xe3c0, 11, 11, 0, 1 },
> +				.ls_det_st	= { 0xe3e0, 11, 11, 0, 1 },
> +				.ls_det_clr	= { 0xe3d0, 11, 11, 0, 1 },
> +				.utmi_ls	= { 0xe2ac, 26, 25, 0, 1 },
> +				.utmi_hstdet	= { 0xe2ac, 27, 27, 0, 1 }
> +			}
> +		},
> +	},
> +	{ /* sentinel */ }
> +};
> +
> +static const struct udevice_id rockchip_usb2phy_ids[] = {
> +	{
> +		.compatible = "rockchip,rk3399-usb2phy",
> +		.data = (ulong)&rk3399_usb2phy_cfgs,
> +	},
> +	{ /* sentinel */ }
> +};
> +
> +U_BOOT_DRIVER(rockchip_usb2phy_port) = {
> +	.name		= "rockchip_usb2phy_port",
> +	.id		= UCLASS_PHY,
> +	.ops		= &rockchip_usb2phy_ops,
> +};
> +
> +U_BOOT_DRIVER(rockchip_usb2phy) = {
> +	.name	= "rockchip_usb2phy",
> +	.id	= UCLASS_PHY,
> +	.of_match = rockchip_usb2phy_ids,
> +	.probe = rockchip_usb2phy_probe,
> +	.bind = rockchip_usb2phy_bind,
> +	.priv_auto_alloc_size = sizeof(struct rockchip_usb2phy),
> +};

[PATCH v5 04/16] phy: rockchip: Add Rockchip USB2PHY driver

[Kever Yang]

On 2020/5/13 ??3:13, Frank Wang wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Add Rockchip USB2PHY driver with initial support.
>
> This will help to use it for EHCI controller in host
> mode, and USB 3.0 controller in otg mode.
>
> More functionality like charge, vbus detection will
> add it in future changes.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/Makefile                              |   1 +
>   drivers/phy/Kconfig                           |   1 +
>   drivers/phy/rockchip/Kconfig                  |  14 +
>   drivers/phy/rockchip/Makefile                 |   6 +
>   drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 312 ++++++++++++++++++
>   5 files changed, 334 insertions(+)
>   create mode 100644 drivers/phy/rockchip/Kconfig
>   create mode 100644 drivers/phy/rockchip/Makefile
>   create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb2.c
>
> diff --git a/drivers/Makefile b/drivers/Makefile
> index 4208750428..94e8c5da17 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -91,6 +91,7 @@ obj-y += dfu/
>   obj-$(CONFIG_PCH) += pch/
>   obj-y += phy/allwinner/
>   obj-y += phy/marvell/
> +obj-y += phy/rockchip/
>   obj-y += rtc/
>   obj-y += scsi/
>   obj-y += sound/
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 1e38c8741f..9c775107e9 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -225,4 +225,5 @@ config PHY_MTK_TPHY
>   	  multi-ports is first version, otherwise is second veriosn,
>   	  so you can easily distinguish them by banks layout.
>   
> +source "drivers/phy/rockchip/Kconfig"
>   endmenu
> diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
> new file mode 100644
> index 0000000000..d73ac695e1
> --- /dev/null
> +++ b/drivers/phy/rockchip/Kconfig
> @@ -0,0 +1,14 @@
> +#
> +# Phy drivers for Rockchip platforms
> +#
> +
> +menu "Rockchip PHY driver"
> +
> +config PHY_ROCKCHIP_INNO_USB2
> +	bool "Rockchip INNO USB2PHY Driver"
> +	depends on ARCH_ROCKCHIP
> +	select PHY
> +	help
> +	  Support for Rockchip USB2.0 PHY with Innosilicon IP block.
> +
> +endmenu
> diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
> new file mode 100644
> index 0000000000..9b0cbc6acf
> --- /dev/null
> +++ b/drivers/phy/rockchip/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (C) 2020 Amarula Solutions(India)
> +#
> +
> +obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
> diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> new file mode 100644
> index 0000000000..dd4905d834
> --- /dev/null
> +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> @@ -0,0 +1,312 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Rockchip USB2.0 PHY with Innosilicon IP block driver
> + *
> + * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
> + * Copyright (C) 2020 Amarula Solutions(India)
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <dm/device_compat.h>
> +#include <dm/lists.h>
> +#include <generic-phy.h>
> +#include <reset.h>
> +#include <syscon.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <linux/iopoll.h>
> +#include <asm/arch-rockchip/clock.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define usleep_range(a, b) udelay((b))
> +#define BIT_WRITEABLE_SHIFT	16
> +
> +enum rockchip_usb2phy_port_id {
> +	USB2PHY_PORT_OTG,
> +	USB2PHY_PORT_HOST,
> +	USB2PHY_NUM_PORTS,
> +};
> +
> +struct usb2phy_reg {
> +	unsigned int	offset;
> +	unsigned int	bitend;
> +	unsigned int	bitstart;
> +	unsigned int	disable;
> +	unsigned int	enable;
> +};
> +
> +struct rockchip_usb2phy_port_cfg {
> +	struct usb2phy_reg	phy_sus;
> +	struct usb2phy_reg	bvalid_det_en;
> +	struct usb2phy_reg	bvalid_det_st;
> +	struct usb2phy_reg	bvalid_det_clr;
> +	struct usb2phy_reg	ls_det_en;
> +	struct usb2phy_reg	ls_det_st;
> +	struct usb2phy_reg	ls_det_clr;
> +	struct usb2phy_reg	utmi_avalid;
> +	struct usb2phy_reg	utmi_bvalid;
> +	struct usb2phy_reg	utmi_ls;
> +	struct usb2phy_reg	utmi_hstdet;
> +};
> +
> +struct rockchip_usb2phy_cfg {
> +	unsigned int reg;
> +	const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
> +};
> +
> +struct rockchip_usb2phy {
> +	void *reg_base;
> +	struct clk phyclk;
> +	const struct rockchip_usb2phy_cfg *phy_cfg;
> +};
> +
> +static inline int property_enable(void *reg_base,
> +				  const struct usb2phy_reg *reg, bool en)
> +{
> +	unsigned int val, mask, tmp;
> +
> +	tmp = en ? reg->enable : reg->disable;
> +	mask = GENMASK(reg->bitend, reg->bitstart);
> +	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
> +
> +	return writel(val, reg_base + reg->offset);
> +}
> +
> +static const
> +struct rockchip_usb2phy_port_cfg *us2phy_get_port(struct phy *phy)
> +{
> +	struct udevice *parent = dev_get_parent(phy->dev);
> +	struct rockchip_usb2phy *priv = dev_get_priv(parent);
> +	const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
> +
> +	return &phy_cfg->port_cfgs[phy->id];
> +}
> +
> +static int rockchip_usb2phy_power_on(struct phy *phy)
> +{
> +	struct udevice *parent = dev_get_parent(phy->dev);
> +	struct rockchip_usb2phy *priv = dev_get_priv(parent);
> +	const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
> +
> +	property_enable(priv->reg_base, &port_cfg->phy_sus, false);
> +
> +	/* waiting for the utmi_clk to become stable */
> +	usleep_range(1500, 2000);
> +
> +	return 0;
> +}
> +
> +static int rockchip_usb2phy_power_off(struct phy *phy)
> +{
> +	struct udevice *parent = dev_get_parent(phy->dev);
> +	struct rockchip_usb2phy *priv = dev_get_priv(parent);
> +	const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
> +
> +	property_enable(priv->reg_base, &port_cfg->phy_sus, true);
> +
> +	return 0;
> +}
> +
> +static int rockchip_usb2phy_init(struct phy *phy)
> +{
> +	struct udevice *parent = dev_get_parent(phy->dev);
> +	struct rockchip_usb2phy *priv = dev_get_priv(parent);
> +	const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
> +	int ret;
> +
> +	ret = clk_enable(&priv->phyclk);
> +	if (ret) {
> +		dev_err(phy->dev, "failed to enable phyclk (ret=%d)\n", ret);
> +		return ret;
> +	}
> +
> +	if (phy->id == USB2PHY_PORT_OTG) {
> +		property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true);
> +		property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true);
> +	} else if (phy->id == USB2PHY_PORT_HOST) {
> +		property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true);
> +		property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true);
> +	}
> +
> +	return 0;
> +}
> +
> +static int rockchip_usb2phy_exit(struct phy *phy)
> +{
> +	struct udevice *parent = dev_get_parent(phy->dev);
> +	struct rockchip_usb2phy *priv = dev_get_priv(parent);
> +
> +	clk_disable(&priv->phyclk);
> +
> +	return 0;
> +}
> +
> +static int rockchip_usb2phy_of_xlate(struct phy *phy,
> +				     struct ofnode_phandle_args *args)
> +{
> +	const char *name = phy->dev->name;
> +
> +	if (!strcasecmp(name, "host-port"))
> +		phy->id = USB2PHY_PORT_HOST;
> +	else if (!strcasecmp(name, "otg-port"))
> +		phy->id = USB2PHY_PORT_OTG;
> +	else
> +		dev_err(phy->dev, "improper %s device\n", name);
> +
> +	return 0;
> +}
> +
> +static struct phy_ops rockchip_usb2phy_ops = {
> +	.init = rockchip_usb2phy_init,
> +	.exit = rockchip_usb2phy_exit,
> +	.power_on = rockchip_usb2phy_power_on,
> +	.power_off = rockchip_usb2phy_power_off,
> +	.of_xlate = rockchip_usb2phy_of_xlate,
> +};
> +
> +static int rockchip_usb2phy_probe(struct udevice *dev)
> +{
> +	struct rockchip_usb2phy *priv = dev_get_priv(dev);
> +	const struct rockchip_usb2phy_cfg *phy_cfgs;
> +	unsigned int reg;
> +	int index, ret;
> +
> +	priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +	if (IS_ERR(priv->reg_base))
> +		return PTR_ERR(priv->reg_base);
> +
> +	ret = dev_read_u32_index(dev, "reg", 1, &reg);
> +	if (ret) {
> +		dev_err(dev, "failed to read reg property (ret = %d)\n", ret);
> +		return ret;
> +	}
> +
> +	phy_cfgs = (const struct rockchip_usb2phy_cfg *)
> +					dev_get_driver_data(dev);
> +	if (!phy_cfgs)
> +		return -EINVAL;
> +
> +	/* find out a proper config which can be matched with dt. */
> +	index = 0;
> +	while (phy_cfgs[index].reg) {
> +		if (phy_cfgs[index].reg == reg) {
> +			priv->phy_cfg = &phy_cfgs[index];
> +			break;
> +		}
> +
> +		++index;
> +	}
> +
> +	if (!priv->phy_cfg) {
> +		dev_err(dev, "failed find proper phy-cfg\n");
> +		return -EINVAL;
> +	}
> +
> +	ret = clk_get_by_name(dev, "phyclk", &priv->phyclk);
> +	if (ret) {
> +		dev_err(dev, "failed to get the phyclk (ret=%d)\n", ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int rockchip_usb2phy_bind(struct udevice *dev)
> +{
> +	struct udevice *usb2phy_dev;
> +	ofnode node;
> +	const char *name;
> +	int ret = 0;
> +
> +	dev_for_each_subnode(node, dev) {
> +		if (!ofnode_valid(node)) {
> +			dev_info(dev, "subnode %s not found\n", dev->name);
> +			return -ENXIO;
> +		}
> +
> +		name = ofnode_get_name(node);
> +		dev_dbg(dev, "subnode %s\n", name);
> +
> +		ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port",
> +						 name, node, &usb2phy_dev);
> +		if (ret) {
> +			dev_err(dev,
> +				"'%s' cannot bind 'rockchip_usb2phy_port'\n", name);
> +			return ret;
> +		}
> +	}
> +
> +	return ret;
> +}
> +
> +static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = {
> +	{
> +		.reg		= 0xe450,
> +		.port_cfgs	= {
> +			[USB2PHY_PORT_OTG] = {
> +				.phy_sus	= { 0xe454, 1, 0, 2, 1 },
> +				.bvalid_det_en	= { 0xe3c0, 3, 3, 0, 1 },
> +				.bvalid_det_st	= { 0xe3e0, 3, 3, 0, 1 },
> +				.bvalid_det_clr	= { 0xe3d0, 3, 3, 0, 1 },
> +				.utmi_avalid	= { 0xe2ac, 7, 7, 0, 1 },
> +				.utmi_bvalid	= { 0xe2ac, 12, 12, 0, 1 },
> +			},
> +			[USB2PHY_PORT_HOST] = {
> +				.phy_sus	= { 0xe458, 1, 0, 0x2, 0x1 },
> +				.ls_det_en	= { 0xe3c0, 6, 6, 0, 1 },
> +				.ls_det_st	= { 0xe3e0, 6, 6, 0, 1 },
> +				.ls_det_clr	= { 0xe3d0, 6, 6, 0, 1 },
> +				.utmi_ls	= { 0xe2ac, 22, 21, 0, 1 },
> +				.utmi_hstdet	= { 0xe2ac, 23, 23, 0, 1 }
> +			}
> +		},
> +	},
> +	{
> +		.reg		= 0xe460,
> +		.port_cfgs	= {
> +			[USB2PHY_PORT_OTG] = {
> +				.phy_sus        = { 0xe464, 1, 0, 2, 1 },
> +				.bvalid_det_en  = { 0xe3c0, 8, 8, 0, 1 },
> +				.bvalid_det_st  = { 0xe3e0, 8, 8, 0, 1 },
> +				.bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
> +				.utmi_avalid	= { 0xe2ac, 10, 10, 0, 1 },
> +				.utmi_bvalid    = { 0xe2ac, 16, 16, 0, 1 },
> +			},
> +			[USB2PHY_PORT_HOST] = {
> +				.phy_sus	= { 0xe468, 1, 0, 0x2, 0x1 },
> +				.ls_det_en	= { 0xe3c0, 11, 11, 0, 1 },
> +				.ls_det_st	= { 0xe3e0, 11, 11, 0, 1 },
> +				.ls_det_clr	= { 0xe3d0, 11, 11, 0, 1 },
> +				.utmi_ls	= { 0xe2ac, 26, 25, 0, 1 },
> +				.utmi_hstdet	= { 0xe2ac, 27, 27, 0, 1 }
> +			}
> +		},
> +	},
> +	{ /* sentinel */ }
> +};
> +
> +static const struct udevice_id rockchip_usb2phy_ids[] = {
> +	{
> +		.compatible = "rockchip,rk3399-usb2phy",
> +		.data = (ulong)&rk3399_usb2phy_cfgs,
> +	},
> +	{ /* sentinel */ }
> +};
> +
> +U_BOOT_DRIVER(rockchip_usb2phy_port) = {
> +	.name		= "rockchip_usb2phy_port",
> +	.id		= UCLASS_PHY,
> +	.ops		= &rockchip_usb2phy_ops,
> +};
> +
> +U_BOOT_DRIVER(rockchip_usb2phy) = {
> +	.name	= "rockchip_usb2phy",
> +	.id	= UCLASS_PHY,
> +	.of_match = rockchip_usb2phy_ids,
> +	.probe = rockchip_usb2phy_probe,
> +	.bind = rockchip_usb2phy_bind,
> +	.priv_auto_alloc_size = sizeof(struct rockchip_usb2phy),
> +};

[PATCH v5 15/16] configs: evb-rk3399: update support usb3.0 host

[Frank Wang]

Update evb-rk3399 default config to support USB3.0 Host.

Signed-off-by: Frank Wang <frank.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Reviewed-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 configs/evb-rk3399_defconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index 7f14e18b1b..6cfb4e5dac 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -28,6 +28,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
@@ -35,10 +36,13 @@ CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
+CONFIG_DM_RESET=y
 CONFIG_DM_RNG=y
 CONFIG_RNG_ROCKCHIP=y
 CONFIG_BAUDRATE=1500000
@@ -49,6 +53,8 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_ASIX88179=y
-- 
2.17.1

[PATCH v5 15/16] configs: evb-rk3399: update support usb3.0 host

[Frank Wang]

Update evb-rk3399 default config to support USB3.0 Host.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
---
 configs/evb-rk3399_defconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index 7f14e18b1b..6cfb4e5dac 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -28,6 +28,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
@@ -35,10 +36,13 @@ CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
+CONFIG_DM_RESET=y
 CONFIG_DM_RNG=y
 CONFIG_RNG_ROCKCHIP=y
 CONFIG_BAUDRATE=1500000
@@ -49,6 +53,8 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_ASIX88179=y
-- 
2.17.1

Re: [PATCH v5 15/16] configs: evb-rk3399: update support usb3.0 host

[Kever Yang]

On 2020/5/13 下午3:17, Frank Wang wrote:
> Update evb-rk3399 default config to support USB3.0 Host.
>
> Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   configs/evb-rk3399_defconfig | 6 ++++++
>   1 file changed, 6 insertions(+)
>
> diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
> index 7f14e18b1b..6cfb4e5dac 100644
> --- a/configs/evb-rk3399_defconfig
> +++ b/configs/evb-rk3399_defconfig
> @@ -28,6 +28,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>   CONFIG_NET_RANDOM_ETHADDR=y
>   CONFIG_ROCKCHIP_GPIO=y
>   CONFIG_SYS_I2C_ROCKCHIP=y
> +CONFIG_MISC=y
>   CONFIG_MMC_DW=y
>   CONFIG_MMC_SDHCI=y
>   CONFIG_MMC_SDHCI_ROCKCHIP=y
> @@ -35,10 +36,13 @@ CONFIG_SF_DEFAULT_SPEED=20000000
>   CONFIG_DM_ETH=y
>   CONFIG_ETH_DESIGNWARE=y
>   CONFIG_GMAC_ROCKCHIP=y
> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> +CONFIG_PHY_ROCKCHIP_TYPEC=y
>   CONFIG_PMIC_RK8XX=y
>   CONFIG_REGULATOR_PWM=y
>   CONFIG_REGULATOR_RK8XX=y
>   CONFIG_PWM_ROCKCHIP=y
> +CONFIG_DM_RESET=y
>   CONFIG_DM_RNG=y
>   CONFIG_RNG_ROCKCHIP=y
>   CONFIG_BAUDRATE=1500000
> @@ -49,6 +53,8 @@ CONFIG_USB_XHCI_HCD=y
>   CONFIG_USB_XHCI_DWC3=y
>   CONFIG_USB_EHCI_HCD=y
>   CONFIG_USB_EHCI_GENERIC=y
> +CONFIG_USB_DWC3=y
> +CONFIG_USB_DWC3_GENERIC=y
>   CONFIG_USB_HOST_ETHER=y
>   CONFIG_USB_ETHER_ASIX=y
>   CONFIG_USB_ETHER_ASIX88179=y

[PATCH v5 15/16] configs: evb-rk3399: update support usb3.0 host

[Kever Yang]

On 2020/5/13 ??3:17, Frank Wang wrote:
> Update evb-rk3399 default config to support USB3.0 Host.
>
> Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   configs/evb-rk3399_defconfig | 6 ++++++
>   1 file changed, 6 insertions(+)
>
> diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
> index 7f14e18b1b..6cfb4e5dac 100644
> --- a/configs/evb-rk3399_defconfig
> +++ b/configs/evb-rk3399_defconfig
> @@ -28,6 +28,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>   CONFIG_NET_RANDOM_ETHADDR=y
>   CONFIG_ROCKCHIP_GPIO=y
>   CONFIG_SYS_I2C_ROCKCHIP=y
> +CONFIG_MISC=y
>   CONFIG_MMC_DW=y
>   CONFIG_MMC_SDHCI=y
>   CONFIG_MMC_SDHCI_ROCKCHIP=y
> @@ -35,10 +36,13 @@ CONFIG_SF_DEFAULT_SPEED=20000000
>   CONFIG_DM_ETH=y
>   CONFIG_ETH_DESIGNWARE=y
>   CONFIG_GMAC_ROCKCHIP=y
> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> +CONFIG_PHY_ROCKCHIP_TYPEC=y
>   CONFIG_PMIC_RK8XX=y
>   CONFIG_REGULATOR_PWM=y
>   CONFIG_REGULATOR_RK8XX=y
>   CONFIG_PWM_ROCKCHIP=y
> +CONFIG_DM_RESET=y
>   CONFIG_DM_RNG=y
>   CONFIG_RNG_ROCKCHIP=y
>   CONFIG_BAUDRATE=1500000
> @@ -49,6 +53,8 @@ CONFIG_USB_XHCI_HCD=y
>   CONFIG_USB_XHCI_DWC3=y
>   CONFIG_USB_EHCI_HCD=y
>   CONFIG_USB_EHCI_GENERIC=y
> +CONFIG_USB_DWC3=y
> +CONFIG_USB_DWC3_GENERIC=y
>   CONFIG_USB_HOST_ETHER=y
>   CONFIG_USB_ETHER_ASIX=y
>   CONFIG_USB_ETHER_ASIX88179=y

[PATCH v5 16/16] roc-rk3399-pc: Enable USB3.0 Host

[Frank Wang]

From: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>

Enable USB3.0 Host support for ROC-RK3399-PC boards.

Tested USB3.0 SSD on Type C1 port on board.

=> usb start
starting USB...
Bus usb@fe380000: USB EHCI 1.00
Bus usb@fe3c0000: USB EHCI 1.00
Bus dwc3: usb maximum-speed not found
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
scanning bus usb@fe380000 for devices... 1 USB Device(s) found
scanning bus usb@fe3c0000 for devices... 2 USB Device(s) found
scanning bus dwc3 for devices... 6 USB Device(s) found
       scanning usb for storage devices... 1 Storage Device(s) found
=> usb tree
USB device tree:
  1  Hub (480 Mb/s, 0mA)
     u-boot EHCI Host Controller

  1  Hub (480 Mb/s, 0mA)
  |  u-boot EHCI Host Controller
  |
  +-2  Hub (480 Mb/s, 100mA)
        USB 2.0 Hub [MTT]

  1  Hub (5 Gb/s, 0mA)
  |  U-Boot XHCI Host Controller
  |
  +-2  Hub (480 Mb/s, 0mA)
  | |  VIA Labs, Inc. USB2.0 Hub
  | |
  | +-4  Hub (480 Mb/s, 100mA)
  |   |   USB 2.0 Hub
  |   |
  |   +-5   (480 Mb/s, 100mA)
  |        VIA Technologies Inc. USB 2.0 BILLBOARD  0000000000000001
  |
  +-3  Hub (5 Gb/s, 0mA)
    |  VIA Labs, Inc. USB3.0 Hub
    |
    +-6  Mass Storage (5 Gb/s, 224mA)
         JMicron External Disk 3.0 DB12345678A2

=> usb reset
resetting USB...
Bus usb@fe380000: USB EHCI 1.00
Bus usb@fe3c0000: USB EHCI 1.00
Bus dwc3: usb maximum-speed not found
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
scanning bus usb@fe380000 for devices... 1 USB Device(s) found
scanning bus usb@fe3c0000 for devices... 2 USB Device(s) found
scanning bus dwc3 for devices... 6 USB Device(s) found
       scanning usb for storage devices... 1 Storage Device(s) found

Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 configs/roc-pc-mezzanine-rk3399_defconfig | 5 +++++
 configs/roc-pc-rk3399_defconfig           | 6 ++++++
 2 files changed, 11 insertions(+)

diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig
index 0b853805f3..1f10856caa 100644
--- a/configs/roc-pc-mezzanine-rk3399_defconfig
+++ b/configs/roc-pc-mezzanine-rk3399_defconfig
@@ -29,6 +29,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
@@ -39,6 +40,8 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_NVME=y
 CONFIG_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
@@ -54,6 +57,8 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_ASIX88179=y
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index aff690f039..76e76c160e 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig
@@ -28,6 +28,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
@@ -36,11 +37,14 @@ CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_DM_RESET=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_ROCKCHIP_SPI=y
@@ -50,6 +54,8 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
-- 
2.17.1

[PATCH v5 16/16] roc-rk3399-pc: Enable USB3.0 Host

[Frank Wang]

From: Jagan Teki <jagan@amarulasolutions.com>

Enable USB3.0 Host support for ROC-RK3399-PC boards.

Tested USB3.0 SSD on Type C1 port on board.

=> usb start
starting USB...
Bus usb at fe380000: USB EHCI 1.00
Bus usb at fe3c0000: USB EHCI 1.00
Bus dwc3: usb maximum-speed not found
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
scanning bus usb at fe380000 for devices... 1 USB Device(s) found
scanning bus usb at fe3c0000 for devices... 2 USB Device(s) found
scanning bus dwc3 for devices... 6 USB Device(s) found
       scanning usb for storage devices... 1 Storage Device(s) found
=> usb tree
USB device tree:
  1  Hub (480 Mb/s, 0mA)
     u-boot EHCI Host Controller

  1  Hub (480 Mb/s, 0mA)
  |  u-boot EHCI Host Controller
  |
  +-2  Hub (480 Mb/s, 100mA)
        USB 2.0 Hub [MTT]

  1  Hub (5 Gb/s, 0mA)
  |  U-Boot XHCI Host Controller
  |
  +-2  Hub (480 Mb/s, 0mA)
  | |  VIA Labs, Inc. USB2.0 Hub
  | |
  | +-4  Hub (480 Mb/s, 100mA)
  |   |   USB 2.0 Hub
  |   |
  |   +-5   (480 Mb/s, 100mA)
  |        VIA Technologies Inc. USB 2.0 BILLBOARD  0000000000000001
  |
  +-3  Hub (5 Gb/s, 0mA)
    |  VIA Labs, Inc. USB3.0 Hub
    |
    +-6  Mass Storage (5 Gb/s, 224mA)
         JMicron External Disk 3.0 DB12345678A2

=> usb reset
resetting USB...
Bus usb at fe380000: USB EHCI 1.00
Bus usb at fe3c0000: USB EHCI 1.00
Bus dwc3: usb maximum-speed not found
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
scanning bus usb at fe380000 for devices... 1 USB Device(s) found
scanning bus usb at fe3c0000 for devices... 2 USB Device(s) found
scanning bus dwc3 for devices... 6 USB Device(s) found
       scanning usb for storage devices... 1 Storage Device(s) found

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 configs/roc-pc-mezzanine-rk3399_defconfig | 5 +++++
 configs/roc-pc-rk3399_defconfig           | 6 ++++++
 2 files changed, 11 insertions(+)

diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig
index 0b853805f3..1f10856caa 100644
--- a/configs/roc-pc-mezzanine-rk3399_defconfig
+++ b/configs/roc-pc-mezzanine-rk3399_defconfig
@@ -29,6 +29,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
@@ -39,6 +40,8 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_NVME=y
 CONFIG_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
@@ -54,6 +57,8 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_ASIX88179=y
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index aff690f039..76e76c160e 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig
@@ -28,6 +28,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
@@ -36,11 +37,14 @@ CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_DM_RESET=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_ROCKCHIP_SPI=y
@@ -50,6 +54,8 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
-- 
2.17.1

Re: [PATCH v5 16/16] roc-rk3399-pc: Enable USB3.0 Host

[Kever Yang]

On 2020/5/13 下午3:18, Frank Wang wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Enable USB3.0 Host support for ROC-RK3399-PC boards.
>
> Tested USB3.0 SSD on Type C1 port on board.
>
> => usb start
> starting USB...
> Bus usb@fe380000: USB EHCI 1.00
> Bus usb@fe3c0000: USB EHCI 1.00
> Bus dwc3: usb maximum-speed not found
> Register 2000140 NbrPorts 2
> Starting the controller
> USB XHCI 1.10
> scanning bus usb@fe380000 for devices... 1 USB Device(s) found
> scanning bus usb@fe3c0000 for devices... 2 USB Device(s) found
> scanning bus dwc3 for devices... 6 USB Device(s) found
>         scanning usb for storage devices... 1 Storage Device(s) found
> => usb tree
> USB device tree:
>    1  Hub (480 Mb/s, 0mA)
>       u-boot EHCI Host Controller
>
>    1  Hub (480 Mb/s, 0mA)
>    |  u-boot EHCI Host Controller
>    |
>    +-2  Hub (480 Mb/s, 100mA)
>          USB 2.0 Hub [MTT]
>
>    1  Hub (5 Gb/s, 0mA)
>    |  U-Boot XHCI Host Controller
>    |
>    +-2  Hub (480 Mb/s, 0mA)
>    | |  VIA Labs, Inc. USB2.0 Hub
>    | |
>    | +-4  Hub (480 Mb/s, 100mA)
>    |   |   USB 2.0 Hub
>    |   |
>    |   +-5   (480 Mb/s, 100mA)
>    |        VIA Technologies Inc. USB 2.0 BILLBOARD  0000000000000001
>    |
>    +-3  Hub (5 Gb/s, 0mA)
>      |  VIA Labs, Inc. USB3.0 Hub
>      |
>      +-6  Mass Storage (5 Gb/s, 224mA)
>           JMicron External Disk 3.0 DB12345678A2
>
> => usb reset
> resetting USB...
> Bus usb@fe380000: USB EHCI 1.00
> Bus usb@fe3c0000: USB EHCI 1.00
> Bus dwc3: usb maximum-speed not found
> Register 2000140 NbrPorts 2
> Starting the controller
> USB XHCI 1.10
> scanning bus usb@fe380000 for devices... 1 USB Device(s) found
> scanning bus usb@fe3c0000 for devices... 2 USB Device(s) found
> scanning bus dwc3 for devices... 6 USB Device(s) found
>         scanning usb for storage devices... 1 Storage Device(s) found
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   configs/roc-pc-mezzanine-rk3399_defconfig | 5 +++++
>   configs/roc-pc-rk3399_defconfig           | 6 ++++++
>   2 files changed, 11 insertions(+)
>
> diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig
> index 0b853805f3..1f10856caa 100644
> --- a/configs/roc-pc-mezzanine-rk3399_defconfig
> +++ b/configs/roc-pc-mezzanine-rk3399_defconfig
> @@ -29,6 +29,7 @@ CONFIG_ENV_IS_IN_MMC=y
>   CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>   CONFIG_ROCKCHIP_GPIO=y
>   CONFIG_SYS_I2C_ROCKCHIP=y
> +CONFIG_MISC=y
>   CONFIG_MMC_DW=y
>   CONFIG_MMC_DW_ROCKCHIP=y
>   CONFIG_MMC_SDHCI=y
> @@ -39,6 +40,8 @@ CONFIG_ETH_DESIGNWARE=y
>   CONFIG_GMAC_ROCKCHIP=y
>   CONFIG_NVME=y
>   CONFIG_PCI=y
> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> +CONFIG_PHY_ROCKCHIP_TYPEC=y
>   CONFIG_PMIC_RK8XX=y
>   CONFIG_REGULATOR_PWM=y
>   CONFIG_REGULATOR_RK8XX=y
> @@ -54,6 +57,8 @@ CONFIG_USB_XHCI_HCD=y
>   CONFIG_USB_XHCI_DWC3=y
>   CONFIG_USB_EHCI_HCD=y
>   CONFIG_USB_EHCI_GENERIC=y
> +CONFIG_USB_DWC3=y
> +CONFIG_USB_DWC3_GENERIC=y
>   CONFIG_USB_HOST_ETHER=y
>   CONFIG_USB_ETHER_ASIX=y
>   CONFIG_USB_ETHER_ASIX88179=y
> diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
> index aff690f039..76e76c160e 100644
> --- a/configs/roc-pc-rk3399_defconfig
> +++ b/configs/roc-pc-rk3399_defconfig
> @@ -28,6 +28,7 @@ CONFIG_ENV_IS_IN_MMC=y
>   CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>   CONFIG_ROCKCHIP_GPIO=y
>   CONFIG_SYS_I2C_ROCKCHIP=y
> +CONFIG_MISC=y
>   CONFIG_MMC_DW=y
>   CONFIG_MMC_DW_ROCKCHIP=y
>   CONFIG_MMC_SDHCI=y
> @@ -36,11 +37,14 @@ CONFIG_SPI_FLASH_WINBOND=y
>   CONFIG_DM_ETH=y
>   CONFIG_ETH_DESIGNWARE=y
>   CONFIG_GMAC_ROCKCHIP=y
> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> +CONFIG_PHY_ROCKCHIP_TYPEC=y
>   CONFIG_PMIC_RK8XX=y
>   CONFIG_REGULATOR_PWM=y
>   CONFIG_REGULATOR_RK8XX=y
>   CONFIG_PWM_ROCKCHIP=y
>   CONFIG_RAM_RK3399_LPDDR4=y
> +CONFIG_DM_RESET=y
>   CONFIG_BAUDRATE=1500000
>   CONFIG_DEBUG_UART_SHIFT=2
>   CONFIG_ROCKCHIP_SPI=y
> @@ -50,6 +54,8 @@ CONFIG_USB_XHCI_HCD=y
>   CONFIG_USB_XHCI_DWC3=y
>   CONFIG_USB_EHCI_HCD=y
>   CONFIG_USB_EHCI_GENERIC=y
> +CONFIG_USB_DWC3=y
> +CONFIG_USB_DWC3_GENERIC=y
>   CONFIG_USB_KEYBOARD=y
>   CONFIG_USB_HOST_ETHER=y
>   CONFIG_USB_ETHER_ASIX=y

[PATCH v5 16/16] roc-rk3399-pc: Enable USB3.0 Host

[Kever Yang]

On 2020/5/13 ??3:18, Frank Wang wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Enable USB3.0 Host support for ROC-RK3399-PC boards.
>
> Tested USB3.0 SSD on Type C1 port on board.
>
> => usb start
> starting USB...
> Bus usb at fe380000: USB EHCI 1.00
> Bus usb at fe3c0000: USB EHCI 1.00
> Bus dwc3: usb maximum-speed not found
> Register 2000140 NbrPorts 2
> Starting the controller
> USB XHCI 1.10
> scanning bus usb at fe380000 for devices... 1 USB Device(s) found
> scanning bus usb at fe3c0000 for devices... 2 USB Device(s) found
> scanning bus dwc3 for devices... 6 USB Device(s) found
>         scanning usb for storage devices... 1 Storage Device(s) found
> => usb tree
> USB device tree:
>    1  Hub (480 Mb/s, 0mA)
>       u-boot EHCI Host Controller
>
>    1  Hub (480 Mb/s, 0mA)
>    |  u-boot EHCI Host Controller
>    |
>    +-2  Hub (480 Mb/s, 100mA)
>          USB 2.0 Hub [MTT]
>
>    1  Hub (5 Gb/s, 0mA)
>    |  U-Boot XHCI Host Controller
>    |
>    +-2  Hub (480 Mb/s, 0mA)
>    | |  VIA Labs, Inc. USB2.0 Hub
>    | |
>    | +-4  Hub (480 Mb/s, 100mA)
>    |   |   USB 2.0 Hub
>    |   |
>    |   +-5   (480 Mb/s, 100mA)
>    |        VIA Technologies Inc. USB 2.0 BILLBOARD  0000000000000001
>    |
>    +-3  Hub (5 Gb/s, 0mA)
>      |  VIA Labs, Inc. USB3.0 Hub
>      |
>      +-6  Mass Storage (5 Gb/s, 224mA)
>           JMicron External Disk 3.0 DB12345678A2
>
> => usb reset
> resetting USB...
> Bus usb at fe380000: USB EHCI 1.00
> Bus usb at fe3c0000: USB EHCI 1.00
> Bus dwc3: usb maximum-speed not found
> Register 2000140 NbrPorts 2
> Starting the controller
> USB XHCI 1.10
> scanning bus usb at fe380000 for devices... 1 USB Device(s) found
> scanning bus usb at fe3c0000 for devices... 2 USB Device(s) found
> scanning bus dwc3 for devices... 6 USB Device(s) found
>         scanning usb for storage devices... 1 Storage Device(s) found
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   configs/roc-pc-mezzanine-rk3399_defconfig | 5 +++++
>   configs/roc-pc-rk3399_defconfig           | 6 ++++++
>   2 files changed, 11 insertions(+)
>
> diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig
> index 0b853805f3..1f10856caa 100644
> --- a/configs/roc-pc-mezzanine-rk3399_defconfig
> +++ b/configs/roc-pc-mezzanine-rk3399_defconfig
> @@ -29,6 +29,7 @@ CONFIG_ENV_IS_IN_MMC=y
>   CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>   CONFIG_ROCKCHIP_GPIO=y
>   CONFIG_SYS_I2C_ROCKCHIP=y
> +CONFIG_MISC=y
>   CONFIG_MMC_DW=y
>   CONFIG_MMC_DW_ROCKCHIP=y
>   CONFIG_MMC_SDHCI=y
> @@ -39,6 +40,8 @@ CONFIG_ETH_DESIGNWARE=y
>   CONFIG_GMAC_ROCKCHIP=y
>   CONFIG_NVME=y
>   CONFIG_PCI=y
> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> +CONFIG_PHY_ROCKCHIP_TYPEC=y
>   CONFIG_PMIC_RK8XX=y
>   CONFIG_REGULATOR_PWM=y
>   CONFIG_REGULATOR_RK8XX=y
> @@ -54,6 +57,8 @@ CONFIG_USB_XHCI_HCD=y
>   CONFIG_USB_XHCI_DWC3=y
>   CONFIG_USB_EHCI_HCD=y
>   CONFIG_USB_EHCI_GENERIC=y
> +CONFIG_USB_DWC3=y
> +CONFIG_USB_DWC3_GENERIC=y
>   CONFIG_USB_HOST_ETHER=y
>   CONFIG_USB_ETHER_ASIX=y
>   CONFIG_USB_ETHER_ASIX88179=y
> diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
> index aff690f039..76e76c160e 100644
> --- a/configs/roc-pc-rk3399_defconfig
> +++ b/configs/roc-pc-rk3399_defconfig
> @@ -28,6 +28,7 @@ CONFIG_ENV_IS_IN_MMC=y
>   CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>   CONFIG_ROCKCHIP_GPIO=y
>   CONFIG_SYS_I2C_ROCKCHIP=y
> +CONFIG_MISC=y
>   CONFIG_MMC_DW=y
>   CONFIG_MMC_DW_ROCKCHIP=y
>   CONFIG_MMC_SDHCI=y
> @@ -36,11 +37,14 @@ CONFIG_SPI_FLASH_WINBOND=y
>   CONFIG_DM_ETH=y
>   CONFIG_ETH_DESIGNWARE=y
>   CONFIG_GMAC_ROCKCHIP=y
> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> +CONFIG_PHY_ROCKCHIP_TYPEC=y
>   CONFIG_PMIC_RK8XX=y
>   CONFIG_REGULATOR_PWM=y
>   CONFIG_REGULATOR_RK8XX=y
>   CONFIG_PWM_ROCKCHIP=y
>   CONFIG_RAM_RK3399_LPDDR4=y
> +CONFIG_DM_RESET=y
>   CONFIG_BAUDRATE=1500000
>   CONFIG_DEBUG_UART_SHIFT=2
>   CONFIG_ROCKCHIP_SPI=y
> @@ -50,6 +54,8 @@ CONFIG_USB_XHCI_HCD=y
>   CONFIG_USB_XHCI_DWC3=y
>   CONFIG_USB_EHCI_HCD=y
>   CONFIG_USB_EHCI_GENERIC=y
> +CONFIG_USB_DWC3=y
> +CONFIG_USB_DWC3_GENERIC=y
>   CONFIG_USB_KEYBOARD=y
>   CONFIG_USB_HOST_ETHER=y
>   CONFIG_USB_ETHER_ASIX=y

[PATCH v5 05/16] arm64: dts: rk3399: Move u2phy into root port

[Frank Wang]

From: Jagan Teki <jagan@amarulasolutions.com>

Yes, This is changing the actual device tree u2phy
structure but the problem with the current Generic
PHY subsystem is unable to find PHY if the PHY node
is not part of the root structure.

This will be reverted,
- Once we support the PHY subsystem to get the PHY
  even though it is not part of the root node or
- any other relevant solution that get the phy
  directly without traversing all nodes.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 arch/arm/dts/rk3399.dtsi | 108 +++++++++++++++++++--------------------
 1 file changed, 54 insertions(+), 54 deletions(-)

diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 74f2c3d490..6c77f25f23 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -1387,60 +1387,6 @@
 			status = "disabled";
 		};
 
-		u2phy0: usb2-phy@e450 {
-			compatible = "rockchip,rk3399-usb2phy";
-			reg = <0xe450 0x10>;
-			clocks = <&cru SCLK_USB2PHY0_REF>;
-			clock-names = "phyclk";
-			#clock-cells = <0>;
-			clock-output-names = "clk_usbphy0_480m";
-			status = "disabled";
-
-			u2phy0_host: host-port {
-				#phy-cells = <0>;
-				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
-				interrupt-names = "linestate";
-				status = "disabled";
-			};
-
-			u2phy0_otg: otg-port {
-				#phy-cells = <0>;
-				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
-					     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
-					     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
-				interrupt-names = "otg-bvalid", "otg-id",
-						  "linestate";
-				status = "disabled";
-			};
-		};
-
-		u2phy1: usb2-phy@e460 {
-			compatible = "rockchip,rk3399-usb2phy";
-			reg = <0xe460 0x10>;
-			clocks = <&cru SCLK_USB2PHY1_REF>;
-			clock-names = "phyclk";
-			#clock-cells = <0>;
-			clock-output-names = "clk_usbphy1_480m";
-			status = "disabled";
-
-			u2phy1_host: host-port {
-				#phy-cells = <0>;
-				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
-				interrupt-names = "linestate";
-				status = "disabled";
-			};
-
-			u2phy1_otg: otg-port {
-				#phy-cells = <0>;
-				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
-					     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
-					     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
-				interrupt-names = "otg-bvalid", "otg-id",
-						  "linestate";
-				status = "disabled";
-			};
-		};
-
 		emmc_phy: phy@f780 {
 			compatible = "rockchip,rk3399-emmc-phy";
 			reg = <0xf780 0x24>;
@@ -1462,6 +1408,60 @@
 		};
 	};
 
+	u2phy0: usb2-phy@e450 {
+		compatible = "rockchip,rk3399-usb2phy";
+		reg = <0x0 0xe450 0x0 0x10>;
+		clocks = <&cru SCLK_USB2PHY0_REF>;
+		clock-names = "phyclk";
+		#clock-cells = <0>;
+		clock-output-names = "clk_usbphy0_480m";
+		status = "disabled";
+
+		u2phy0_host: host-port {
+			#phy-cells = <0>;
+			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
+			interrupt-names = "linestate";
+			status = "disabled";
+		};
+
+		u2phy0_otg: otg-port {
+			#phy-cells = <0>;
+			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
+			interrupt-names = "otg-bvalid", "otg-id",
+					  "linestate";
+			status = "disabled";
+		};
+	};
+
+	u2phy1: usb2-phy@e460 {
+		compatible = "rockchip,rk3399-usb2phy";
+		reg = <0x0 0xe460 0x0 0x10>;
+		clocks = <&cru SCLK_USB2PHY1_REF>;
+		clock-names = "phyclk";
+		#clock-cells = <0>;
+		clock-output-names = "clk_usbphy1_480m";
+		status = "disabled";
+
+		u2phy1_host: host-port {
+			#phy-cells = <0>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
+			interrupt-names = "linestate";
+			status = "disabled";
+		};
+
+		u2phy1_otg: otg-port {
+			#phy-cells = <0>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
+			interrupt-names = "otg-bvalid", "otg-id",
+					  "linestate";
+			status = "disabled";
+		};
+	};
+
 	tcphy0: phy@ff7c0000 {
 		compatible = "rockchip,rk3399-typec-phy";
 		reg = <0x0 0xff7c0000 0x0 0x40000>;
-- 
2.17.1

[PATCH v5 05/16] arm64: dts: rk3399: Move u2phy into root port

[Frank Wang]

From: Jagan Teki <jagan@amarulasolutions.com>

Yes, This is changing the actual device tree u2phy
structure but the problem with the current Generic
PHY subsystem is unable to find PHY if the PHY node
is not part of the root structure.

This will be reverted,
- Once we support the PHY subsystem to get the PHY
  even though it is not part of the root node or
- any other relevant solution that get the phy
  directly without traversing all nodes.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 arch/arm/dts/rk3399.dtsi | 108 +++++++++++++++++++--------------------
 1 file changed, 54 insertions(+), 54 deletions(-)

diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 74f2c3d490..6c77f25f23 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -1387,60 +1387,6 @@
 			status = "disabled";
 		};
 
-		u2phy0: usb2-phy at e450 {
-			compatible = "rockchip,rk3399-usb2phy";
-			reg = <0xe450 0x10>;
-			clocks = <&cru SCLK_USB2PHY0_REF>;
-			clock-names = "phyclk";
-			#clock-cells = <0>;
-			clock-output-names = "clk_usbphy0_480m";
-			status = "disabled";
-
-			u2phy0_host: host-port {
-				#phy-cells = <0>;
-				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
-				interrupt-names = "linestate";
-				status = "disabled";
-			};
-
-			u2phy0_otg: otg-port {
-				#phy-cells = <0>;
-				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
-					     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
-					     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
-				interrupt-names = "otg-bvalid", "otg-id",
-						  "linestate";
-				status = "disabled";
-			};
-		};
-
-		u2phy1: usb2-phy at e460 {
-			compatible = "rockchip,rk3399-usb2phy";
-			reg = <0xe460 0x10>;
-			clocks = <&cru SCLK_USB2PHY1_REF>;
-			clock-names = "phyclk";
-			#clock-cells = <0>;
-			clock-output-names = "clk_usbphy1_480m";
-			status = "disabled";
-
-			u2phy1_host: host-port {
-				#phy-cells = <0>;
-				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
-				interrupt-names = "linestate";
-				status = "disabled";
-			};
-
-			u2phy1_otg: otg-port {
-				#phy-cells = <0>;
-				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
-					     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
-					     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
-				interrupt-names = "otg-bvalid", "otg-id",
-						  "linestate";
-				status = "disabled";
-			};
-		};
-
 		emmc_phy: phy at f780 {
 			compatible = "rockchip,rk3399-emmc-phy";
 			reg = <0xf780 0x24>;
@@ -1462,6 +1408,60 @@
 		};
 	};
 
+	u2phy0: usb2-phy at e450 {
+		compatible = "rockchip,rk3399-usb2phy";
+		reg = <0x0 0xe450 0x0 0x10>;
+		clocks = <&cru SCLK_USB2PHY0_REF>;
+		clock-names = "phyclk";
+		#clock-cells = <0>;
+		clock-output-names = "clk_usbphy0_480m";
+		status = "disabled";
+
+		u2phy0_host: host-port {
+			#phy-cells = <0>;
+			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
+			interrupt-names = "linestate";
+			status = "disabled";
+		};
+
+		u2phy0_otg: otg-port {
+			#phy-cells = <0>;
+			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
+			interrupt-names = "otg-bvalid", "otg-id",
+					  "linestate";
+			status = "disabled";
+		};
+	};
+
+	u2phy1: usb2-phy at e460 {
+		compatible = "rockchip,rk3399-usb2phy";
+		reg = <0x0 0xe460 0x0 0x10>;
+		clocks = <&cru SCLK_USB2PHY1_REF>;
+		clock-names = "phyclk";
+		#clock-cells = <0>;
+		clock-output-names = "clk_usbphy1_480m";
+		status = "disabled";
+
+		u2phy1_host: host-port {
+			#phy-cells = <0>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
+			interrupt-names = "linestate";
+			status = "disabled";
+		};
+
+		u2phy1_otg: otg-port {
+			#phy-cells = <0>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
+			interrupt-names = "otg-bvalid", "otg-id",
+					  "linestate";
+			status = "disabled";
+		};
+	};
+
 	tcphy0: phy at ff7c0000 {
 		compatible = "rockchip,rk3399-typec-phy";
 		reg = <0x0 0xff7c0000 0x0 0x40000>;
-- 
2.17.1

[PATCH v5 06/16] phy: rockchip: Add Rockchip USB TypeC PHY driver

[Frank Wang]

From: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>

Add USB TYPEC PHY driver for rockchip platform.

Referenced from Linux TypeC PHY driver, currently
supporting usb3-port and dp-port need to add it
in the future.

Signed-off-by: Frank Wang <frank.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 drivers/phy/rockchip/Kconfig              |   7 +
 drivers/phy/rockchip/Makefile             |   1 +
 drivers/phy/rockchip/phy-rockchip-typec.c | 796 ++++++++++++++++++++++
 3 files changed, 804 insertions(+)
 create mode 100644 drivers/phy/rockchip/phy-rockchip-typec.c

diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index d73ac695e1..84cc7c876d 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -11,4 +11,11 @@ config PHY_ROCKCHIP_INNO_USB2
 	help
 	  Support for Rockchip USB2.0 PHY with Innosilicon IP block.
 
+config PHY_ROCKCHIP_TYPEC
+	bool "Rockchip TYPEC PHY Driver"
+	depends on ARCH_ROCKCHIP
+	select PHY
+	help
+	  Enable this to support the Rockchip USB TYPEC PHY.
+
 endmenu
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index 9b0cbc6acf..95b2f8a3c0 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -4,3 +4,4 @@
 #
 
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
+obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)	+= phy-rockchip-typec.o
diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
new file mode 100644
index 0000000000..c9c8e1c542
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
@@ -0,0 +1,796 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * ROCKCHIP Type-C PHY driver.
+ *
+ * Copyright (C) 2020 Amarula Solutions(India)
+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
+ * Author: Chris Zhong <zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
+ *         Kever Yang <kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <generic-phy.h>
+#include <reset.h>
+#include <syscon.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <linux/iopoll.h>
+#include <asm/arch-rockchip/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define usleep_range(a, b) udelay((b))
+
+#define CMN_SSM_BANDGAP			(0x21 << 2)
+#define CMN_SSM_BIAS			(0x22 << 2)
+#define CMN_PLLSM0_PLLEN		(0x29 << 2)
+#define CMN_PLLSM0_PLLPRE		(0x2a << 2)
+#define CMN_PLLSM0_PLLVREF		(0x2b << 2)
+#define CMN_PLLSM0_PLLLOCK		(0x2c << 2)
+#define CMN_PLLSM1_PLLEN		(0x31 << 2)
+#define CMN_PLLSM1_PLLPRE		(0x32 << 2)
+#define CMN_PLLSM1_PLLVREF		(0x33 << 2)
+#define CMN_PLLSM1_PLLLOCK		(0x34 << 2)
+#define CMN_PLLSM1_USER_DEF_CTRL	(0x37 << 2)
+#define CMN_ICAL_OVRD			(0xc1 << 2)
+#define CMN_PLL0_VCOCAL_OVRD		(0x83 << 2)
+#define CMN_PLL0_VCOCAL_INIT		(0x84 << 2)
+#define CMN_PLL0_VCOCAL_ITER		(0x85 << 2)
+#define CMN_PLL0_LOCK_REFCNT_START	(0x90 << 2)
+#define CMN_PLL0_LOCK_PLLCNT_START	(0x92 << 2)
+#define CMN_PLL0_LOCK_PLLCNT_THR	(0x93 << 2)
+#define CMN_PLL0_INTDIV			(0x94 << 2)
+#define CMN_PLL0_FRACDIV		(0x95 << 2)
+#define CMN_PLL0_HIGH_THR		(0x96 << 2)
+#define CMN_PLL0_DSM_DIAG		(0x97 << 2)
+#define CMN_PLL0_SS_CTRL1		(0x98 << 2)
+#define CMN_PLL0_SS_CTRL2		(0x99 << 2)
+#define CMN_PLL1_VCOCAL_START		(0xa1 << 2)
+#define CMN_PLL1_VCOCAL_OVRD		(0xa3 << 2)
+#define CMN_PLL1_VCOCAL_INIT		(0xa4 << 2)
+#define CMN_PLL1_VCOCAL_ITER		(0xa5 << 2)
+#define CMN_PLL1_LOCK_REFCNT_START	(0xb0 << 2)
+#define CMN_PLL1_LOCK_PLLCNT_START	(0xb2 << 2)
+#define CMN_PLL1_LOCK_PLLCNT_THR	(0xb3 << 2)
+#define CMN_PLL1_INTDIV			(0xb4 << 2)
+#define CMN_PLL1_FRACDIV		(0xb5 << 2)
+#define CMN_PLL1_HIGH_THR		(0xb6 << 2)
+#define CMN_PLL1_DSM_DIAG		(0xb7 << 2)
+#define CMN_PLL1_SS_CTRL1		(0xb8 << 2)
+#define CMN_PLL1_SS_CTRL2		(0xb9 << 2)
+#define CMN_RXCAL_OVRD			(0xd1 << 2)
+
+#define CMN_TXPUCAL_CTRL		(0xe0 << 2)
+#define CMN_TXPUCAL_OVRD		(0xe1 << 2)
+#define CMN_TXPDCAL_CTRL		(0xf0 << 2)
+#define CMN_TXPDCAL_OVRD		(0xf1 << 2)
+
+/* For CMN_TXPUCAL_CTRL, CMN_TXPDCAL_CTRL */
+#define CMN_TXPXCAL_START		BIT(15)
+#define CMN_TXPXCAL_DONE		BIT(14)
+#define CMN_TXPXCAL_NO_RESPONSE		BIT(13)
+#define CMN_TXPXCAL_CURRENT_RESPONSE	BIT(12)
+
+#define CMN_TXPU_ADJ_CTRL		(0x108 << 2)
+#define CMN_TXPD_ADJ_CTRL		(0x10c << 2)
+
+/*
+ * For CMN_TXPUCAL_CTRL, CMN_TXPDCAL_CTRL,
+ *     CMN_TXPU_ADJ_CTRL, CMN_TXPDCAL_CTRL
+ *
+ * NOTE: some of these registers are documented to be 2's complement
+ * signed numbers, but then documented to be always positive.  Weird.
+ * In such a case, using CMN_CALIB_CODE_POS() avoids the unnecessary
+ * sign extension.
+ */
+#define CMN_CALIB_CODE_WIDTH	7
+#define CMN_CALIB_CODE_OFFSET	0
+#define CMN_CALIB_CODE_MASK	GENMASK(CMN_CALIB_CODE_WIDTH, 0)
+#define CMN_CALIB_CODE(x)	\
+	sign_extend32((x) >> CMN_CALIB_CODE_OFFSET, CMN_CALIB_CODE_WIDTH)
+
+#define CMN_CALIB_CODE_POS_MASK	GENMASK(CMN_CALIB_CODE_WIDTH - 1, 0)
+#define CMN_CALIB_CODE_POS(x)	\
+	(((x) >> CMN_CALIB_CODE_OFFSET) & CMN_CALIB_CODE_POS_MASK)
+
+#define CMN_DIAG_PLL0_FBH_OVRD		(0x1c0 << 2)
+#define CMN_DIAG_PLL0_FBL_OVRD		(0x1c1 << 2)
+#define CMN_DIAG_PLL0_OVRD		(0x1c2 << 2)
+#define CMN_DIAG_PLL0_V2I_TUNE		(0x1c5 << 2)
+#define CMN_DIAG_PLL0_CP_TUNE		(0x1c6 << 2)
+#define CMN_DIAG_PLL0_LF_PROG		(0x1c7 << 2)
+#define CMN_DIAG_PLL1_FBH_OVRD		(0x1d0 << 2)
+#define CMN_DIAG_PLL1_FBL_OVRD		(0x1d1 << 2)
+#define CMN_DIAG_PLL1_OVRD		(0x1d2 << 2)
+#define CMN_DIAG_PLL1_V2I_TUNE		(0x1d5 << 2)
+#define CMN_DIAG_PLL1_CP_TUNE		(0x1d6 << 2)
+#define CMN_DIAG_PLL1_LF_PROG		(0x1d7 << 2)
+#define CMN_DIAG_PLL1_PTATIS_TUNE1	(0x1d8 << 2)
+#define CMN_DIAG_PLL1_PTATIS_TUNE2	(0x1d9 << 2)
+#define CMN_DIAG_PLL1_INCLK_CTRL	(0x1da << 2)
+#define CMN_DIAG_HSCLK_SEL		(0x1e0 << 2)
+
+#define XCVR_PSM_RCTRL(n)		((0x4001 | ((n) << 9)) << 2)
+#define XCVR_PSM_CAL_TMR(n)		((0x4002 | ((n) << 9)) << 2)
+#define XCVR_PSM_A0IN_TMR(n)		((0x4003 | ((n) << 9)) << 2)
+#define TX_TXCC_CAL_SCLR_MULT(n)	((0x4047 | ((n) << 9)) << 2)
+#define TX_TXCC_CPOST_MULT_00(n)	((0x404c | ((n) << 9)) << 2)
+#define TX_TXCC_CPOST_MULT_01(n)	((0x404d | ((n) << 9)) << 2)
+#define TX_TXCC_CPOST_MULT_10(n)	((0x404e | ((n) << 9)) << 2)
+#define TX_TXCC_CPOST_MULT_11(n)	((0x404f | ((n) << 9)) << 2)
+#define TX_TXCC_MGNFS_MULT_000(n)	((0x4050 | ((n) << 9)) << 2)
+#define TX_TXCC_MGNFS_MULT_001(n)	((0x4051 | ((n) << 9)) << 2)
+#define TX_TXCC_MGNFS_MULT_010(n)	((0x4052 | ((n) << 9)) << 2)
+#define TX_TXCC_MGNFS_MULT_011(n)	((0x4053 | ((n) << 9)) << 2)
+#define TX_TXCC_MGNFS_MULT_100(n)	((0x4054 | ((n) << 9)) << 2)
+#define TX_TXCC_MGNFS_MULT_101(n)	((0x4055 | ((n) << 9)) << 2)
+#define TX_TXCC_MGNFS_MULT_110(n)	((0x4056 | ((n) << 9)) << 2)
+#define TX_TXCC_MGNFS_MULT_111(n)	((0x4057 | ((n) << 9)) << 2)
+#define TX_TXCC_MGNLS_MULT_000(n)	((0x4058 | ((n) << 9)) << 2)
+#define TX_TXCC_MGNLS_MULT_001(n)	((0x4059 | ((n) << 9)) << 2)
+#define TX_TXCC_MGNLS_MULT_010(n)	((0x405a | ((n) << 9)) << 2)
+#define TX_TXCC_MGNLS_MULT_011(n)	((0x405b | ((n) << 9)) << 2)
+#define TX_TXCC_MGNLS_MULT_100(n)	((0x405c | ((n) << 9)) << 2)
+#define TX_TXCC_MGNLS_MULT_101(n)	((0x405d | ((n) << 9)) << 2)
+#define TX_TXCC_MGNLS_MULT_110(n)	((0x405e | ((n) << 9)) << 2)
+#define TX_TXCC_MGNLS_MULT_111(n)	((0x405f | ((n) << 9)) << 2)
+
+#define XCVR_DIAG_PLLDRC_CTRL(n)	((0x40e0 | ((n) << 9)) << 2)
+#define XCVR_DIAG_BIDI_CTRL(n)		((0x40e8 | ((n) << 9)) << 2)
+#define XCVR_DIAG_LANE_FCM_EN_MGN(n)	((0x40f2 | ((n) << 9)) << 2)
+#define TX_PSC_A0(n)			((0x4100 | ((n) << 9)) << 2)
+#define TX_PSC_A1(n)			((0x4101 | ((n) << 9)) << 2)
+#define TX_PSC_A2(n)			((0x4102 | ((n) << 9)) << 2)
+#define TX_PSC_A3(n)			((0x4103 | ((n) << 9)) << 2)
+#define TX_RCVDET_CTRL(n)		((0x4120 | ((n) << 9)) << 2)
+#define TX_RCVDET_EN_TMR(n)		((0x4122 | ((n) << 9)) << 2)
+#define TX_RCVDET_ST_TMR(n)		((0x4123 | ((n) << 9)) << 2)
+#define TX_DIAG_TX_DRV(n)		((0x41e1 | ((n) << 9)) << 2)
+#define TX_DIAG_BGREF_PREDRV_DELAY	(0x41e7 << 2)
+
+/* Use this for "n" in macros like "_MULT_XXX" to target the aux channel */
+#define AUX_CH_LANE			8
+
+#define TX_ANA_CTRL_REG_1		(0x5020 << 2)
+
+#define TXDA_DP_AUX_EN			BIT(15)
+#define AUXDA_SE_EN			BIT(14)
+#define TXDA_CAL_LATCH_EN		BIT(13)
+#define AUXDA_POLARITY			BIT(12)
+#define TXDA_DRV_POWER_ISOLATION_EN	BIT(11)
+#define TXDA_DRV_POWER_EN_PH_2_N	BIT(10)
+#define TXDA_DRV_POWER_EN_PH_1_N	BIT(9)
+#define TXDA_BGREF_EN			BIT(8)
+#define TXDA_DRV_LDO_EN			BIT(7)
+#define TXDA_DECAP_EN_DEL		BIT(6)
+#define TXDA_DECAP_EN			BIT(5)
+#define TXDA_UPHY_SUPPLY_EN_DEL		BIT(4)
+#define TXDA_UPHY_SUPPLY_EN		BIT(3)
+#define TXDA_LOW_LEAKAGE_EN		BIT(2)
+#define TXDA_DRV_IDLE_LOWI_EN		BIT(1)
+#define TXDA_DRV_CMN_MODE_EN		BIT(0)
+
+#define TX_ANA_CTRL_REG_2		(0x5021 << 2)
+
+#define AUXDA_DEBOUNCING_CLK		BIT(15)
+#define TXDA_LPBK_RECOVERED_CLK_EN	BIT(14)
+#define TXDA_LPBK_ISI_GEN_EN		BIT(13)
+#define TXDA_LPBK_SERIAL_EN		BIT(12)
+#define TXDA_LPBK_LINE_EN		BIT(11)
+#define TXDA_DRV_LDO_REDC_SINKIQ	BIT(10)
+#define XCVR_DECAP_EN_DEL		BIT(9)
+#define XCVR_DECAP_EN			BIT(8)
+#define TXDA_MPHY_ENABLE_HS_NT		BIT(7)
+#define TXDA_MPHY_SA_MODE		BIT(6)
+#define TXDA_DRV_LDO_RBYR_FB_EN		BIT(5)
+#define TXDA_DRV_RST_PULL_DOWN		BIT(4)
+#define TXDA_DRV_LDO_BG_FB_EN		BIT(3)
+#define TXDA_DRV_LDO_BG_REF_EN		BIT(2)
+#define TXDA_DRV_PREDRV_EN_DEL		BIT(1)
+#define TXDA_DRV_PREDRV_EN		BIT(0)
+
+#define TXDA_COEFF_CALC_CTRL		(0x5022 << 2)
+
+#define TX_HIGH_Z			BIT(6)
+#define TX_VMARGIN_OFFSET		3
+#define TX_VMARGIN_MASK			0x7
+#define LOW_POWER_SWING_EN		BIT(2)
+#define TX_FCM_DRV_MAIN_EN		BIT(1)
+#define TX_FCM_FULL_MARGIN		BIT(0)
+
+#define TX_DIG_CTRL_REG_2		(0x5024 << 2)
+
+#define TX_HIGH_Z_TM_EN			BIT(15)
+#define TX_RESCAL_CODE_OFFSET		0
+#define TX_RESCAL_CODE_MASK		0x3f
+
+#define TXDA_CYA_AUXDA_CYA		(0x5025 << 2)
+#define TX_ANA_CTRL_REG_3		(0x5026 << 2)
+#define TX_ANA_CTRL_REG_4		(0x5027 << 2)
+#define TX_ANA_CTRL_REG_5		(0x5029 << 2)
+
+#define RX_PSC_A0(n)			((0x8000 | ((n) << 9)) << 2)
+#define RX_PSC_A1(n)			((0x8001 | ((n) << 9)) << 2)
+#define RX_PSC_A2(n)			((0x8002 | ((n) << 9)) << 2)
+#define RX_PSC_A3(n)			((0x8003 | ((n) << 9)) << 2)
+#define RX_PSC_CAL(n)			((0x8006 | ((n) << 9)) << 2)
+#define RX_PSC_RDY(n)			((0x8007 | ((n) << 9)) << 2)
+#define RX_IQPI_ILL_CAL_OVRD		(0x8023 << 2)
+#define RX_EPI_ILL_CAL_OVRD		(0x8033 << 2)
+#define RX_SDCAL0_OVRD			(0x8041 << 2)
+#define RX_SDCAL1_OVRD			(0x8049 << 2)
+#define RX_SLC_INIT			(0x806d << 2)
+#define RX_SLC_RUN			(0x806e << 2)
+#define RX_CDRLF_CNFG2			(0x8081 << 2)
+#define RX_SIGDET_HL_FILT_TMR(n)	((0x8090 | ((n) << 9)) << 2)
+#define RX_SLC_IOP0_OVRD		(0x8101 << 2)
+#define RX_SLC_IOP1_OVRD		(0x8105 << 2)
+#define RX_SLC_QOP0_OVRD		(0x8109 << 2)
+#define RX_SLC_QOP1_OVRD		(0x810d << 2)
+#define RX_SLC_EOP0_OVRD		(0x8111 << 2)
+#define RX_SLC_EOP1_OVRD		(0x8115 << 2)
+#define RX_SLC_ION0_OVRD		(0x8119 << 2)
+#define RX_SLC_ION1_OVRD		(0x811d << 2)
+#define RX_SLC_QON0_OVRD		(0x8121 << 2)
+#define RX_SLC_QON1_OVRD		(0x8125 << 2)
+#define RX_SLC_EON0_OVRD		(0x8129 << 2)
+#define RX_SLC_EON1_OVRD		(0x812d << 2)
+#define RX_SLC_IEP0_OVRD		(0x8131 << 2)
+#define RX_SLC_IEP1_OVRD		(0x8135 << 2)
+#define RX_SLC_QEP0_OVRD		(0x8139 << 2)
+#define RX_SLC_QEP1_OVRD		(0x813d << 2)
+#define RX_SLC_EEP0_OVRD		(0x8141 << 2)
+#define RX_SLC_EEP1_OVRD		(0x8145 << 2)
+#define RX_SLC_IEN0_OVRD		(0x8149 << 2)
+#define RX_SLC_IEN1_OVRD		(0x814d << 2)
+#define RX_SLC_QEN0_OVRD		(0x8151 << 2)
+#define RX_SLC_QEN1_OVRD		(0x8155 << 2)
+#define RX_SLC_EEN0_OVRD		(0x8159 << 2)
+#define RX_SLC_EEN1_OVRD		(0x815d << 2)
+#define RX_REE_CTRL_DATA_MASK(n)	((0x81bb | ((n) << 9)) << 2)
+#define RX_DIAG_SIGDET_TUNE(n)		((0x81dc | ((n) << 9)) << 2)
+#define RX_DIAG_SC2C_DELAY		(0x81e1 << 2)
+
+#define PMA_LANE_CFG			(0xc000 << 2)
+#define PIPE_CMN_CTRL1			(0xc001 << 2)
+#define PIPE_CMN_CTRL2			(0xc002 << 2)
+#define PIPE_COM_LOCK_CFG1		(0xc003 << 2)
+#define PIPE_COM_LOCK_CFG2		(0xc004 << 2)
+#define PIPE_RCV_DET_INH		(0xc005 << 2)
+#define DP_MODE_CTL			(0xc008 << 2)
+#define DP_CLK_CTL			(0xc009 << 2)
+#define STS				(0xc00F << 2)
+#define PHY_ISO_CMN_CTRL		(0xc010 << 2)
+#define PHY_DP_TX_CTL			(0xc408 << 2)
+#define PMA_CMN_CTRL1			(0xc800 << 2)
+#define PHY_PMA_ISO_CMN_CTRL		(0xc810 << 2)
+#define PHY_ISOLATION_CTRL		(0xc81f << 2)
+#define PHY_PMA_ISO_XCVR_CTRL(n)	((0xcc11 | ((n) << 6)) << 2)
+#define PHY_PMA_ISO_LINK_MODE(n)	((0xcc12 | ((n) << 6)) << 2)
+#define PHY_PMA_ISO_PWRST_CTRL(n)	((0xcc13 | ((n) << 6)) << 2)
+#define PHY_PMA_ISO_TX_DATA_LO(n)	((0xcc14 | ((n) << 6)) << 2)
+#define PHY_PMA_ISO_TX_DATA_HI(n)	((0xcc15 | ((n) << 6)) << 2)
+#define PHY_PMA_ISO_RX_DATA_LO(n)	((0xcc16 | ((n) << 6)) << 2)
+#define PHY_PMA_ISO_RX_DATA_HI(n)	((0xcc17 | ((n) << 6)) << 2)
+#define TX_BIST_CTRL(n)			((0x4140 | ((n) << 9)) << 2)
+#define TX_BIST_UDDWR(n)		((0x4141 | ((n) << 9)) << 2)
+
+/*
+ * Selects which PLL clock will be driven on the analog high speed
+ * clock 0: PLL 0 div 1
+ * clock 1: PLL 1 div 2
+ */
+#define CLK_PLL_CONFIG			0X30
+#define CLK_PLL_MASK			0x33
+
+#define CMN_READY			BIT(0)
+
+#define DP_PLL_CLOCK_ENABLE		BIT(2)
+#define DP_PLL_ENABLE			BIT(0)
+#define DP_PLL_DATA_RATE_RBR		((2 << 12) | (4 << 8))
+#define DP_PLL_DATA_RATE_HBR		((2 << 12) | (4 << 8))
+#define DP_PLL_DATA_RATE_HBR2		((1 << 12) | (2 << 8))
+
+#define DP_MODE_A0			BIT(4)
+#define DP_MODE_A2			BIT(6)
+#define DP_MODE_ENTER_A0		0xc101
+#define DP_MODE_ENTER_A2		0xc104
+
+#define PHY_MODE_SET_TIMEOUT		100000
+
+#define PIN_ASSIGN_C_E			0x51d9
+#define PIN_ASSIGN_D_F			0x5100
+
+#define MODE_DISCONNECT			0
+#define MODE_UFP_USB			BIT(0)
+#define MODE_DFP_USB			BIT(1)
+#define MODE_DFP_DP			BIT(2)
+
+struct usb3phy_reg {
+	u32 offset;
+	u32 enable_bit;
+	u32 write_enable;
+};
+
+/**
+ * struct rockchip_usb3phy_port_cfg: usb3-phy port configuration.
+ * @reg: the base address for usb3-phy config.
+ * @typec_conn_dir: the register of type-c connector direction.
+ * @usb3tousb2_en: the register of type-c force usb2 to usb2 enable.
+ * @external_psm: the register of type-c phy external psm clock.
+ * @pipe_status: the register of type-c phy pipe status.
+ * @usb3_host_disable: the register of type-c usb3 host disable.
+ * @usb3_host_port: the register of type-c usb3 host port.
+ * @uphy_dp_sel: the register of type-c phy DP select control.
+ */
+struct rockchip_usb3phy_port_cfg {
+	unsigned int reg;
+	struct usb3phy_reg typec_conn_dir;
+	struct usb3phy_reg usb3tousb2_en;
+	struct usb3phy_reg external_psm;
+	struct usb3phy_reg pipe_status;
+	struct usb3phy_reg usb3_host_disable;
+	struct usb3phy_reg usb3_host_port;
+	struct usb3phy_reg uphy_dp_sel;
+};
+
+struct rockchip_tcphy {
+	void __iomem *reg_base;
+	void __iomem *grf_base;
+	struct clk clk_core;
+	struct clk clk_ref;
+	struct reset_ctl uphy_rst;
+	struct reset_ctl pipe_rst;
+	struct reset_ctl tcphy_rst;
+	const struct rockchip_usb3phy_port_cfg *port_cfgs;
+	u8 mode;
+};
+
+struct phy_reg {
+	u16 value;
+	u32 addr;
+};
+
+static struct phy_reg usb3_pll_cfg[] = {
+	{ 0xf0,		CMN_PLL0_VCOCAL_INIT },
+	{ 0x18,		CMN_PLL0_VCOCAL_ITER },
+	{ 0xd0,		CMN_PLL0_INTDIV },
+	{ 0x4a4a,	CMN_PLL0_FRACDIV },
+	{ 0x34,		CMN_PLL0_HIGH_THR },
+	{ 0x1ee,	CMN_PLL0_SS_CTRL1 },
+	{ 0x7f03,	CMN_PLL0_SS_CTRL2 },
+	{ 0x20,		CMN_PLL0_DSM_DIAG },
+	{ 0,		CMN_DIAG_PLL0_OVRD },
+	{ 0,		CMN_DIAG_PLL0_FBH_OVRD },
+	{ 0,		CMN_DIAG_PLL0_FBL_OVRD },
+	{ 0x7,		CMN_DIAG_PLL0_V2I_TUNE },
+	{ 0x45,		CMN_DIAG_PLL0_CP_TUNE },
+	{ 0x8,		CMN_DIAG_PLL0_LF_PROG },
+};
+
+static inline int property_enable(struct rockchip_tcphy *priv,
+				  const struct usb3phy_reg *reg, bool en)
+{
+	u32 mask = 1 << reg->write_enable;
+	u32 val = en << reg->enable_bit;
+
+	return writel(val | mask, priv->grf_base + reg->offset);
+}
+
+static int rockchip_tcphy_get_mode(struct rockchip_tcphy *priv)
+{
+	/* TODO: Add proper logic to find DP or USB3 mode */
+	return MODE_DFP_USB | MODE_UFP_USB;
+}
+
+static void rockchip_tcphy_cfg_24m(struct rockchip_tcphy *priv)
+{
+	u32 i, rdata;
+
+	/*
+	 * cmn_ref_clk_sel = 3, select the 24Mhz for clk parent
+	 * cmn_psm_clk_dig_div = 2, set the clk division to 2
+	 */
+	writel(0x830, priv->reg_base + PMA_CMN_CTRL1);
+	for (i = 0; i < 4; i++) {
+		/*
+		 * The following PHY configuration assumes a 24 MHz reference
+		 * clock.
+		 */
+		writel(0x90, priv->reg_base + XCVR_DIAG_LANE_FCM_EN_MGN(i));
+		writel(0x960, priv->reg_base + TX_RCVDET_EN_TMR(i));
+		writel(0x30, priv->reg_base + TX_RCVDET_ST_TMR(i));
+	}
+
+	rdata = readl(priv->reg_base + CMN_DIAG_HSCLK_SEL);
+	rdata &= ~CLK_PLL_MASK;
+	rdata |= CLK_PLL_CONFIG;
+	writel(rdata, priv->reg_base + CMN_DIAG_HSCLK_SEL);
+}
+
+static void rockchip_tcphy_cfg_usb3_pll(struct rockchip_tcphy *priv)
+{
+	u32 i;
+
+	/* load the configuration of PLL0 */
+	for (i = 0; i < ARRAY_SIZE(usb3_pll_cfg); i++)
+		writel(usb3_pll_cfg[i].value,
+		       priv->reg_base + usb3_pll_cfg[i].addr);
+}
+
+static void rockchip_tcphy_tx_usb3_cfg_lane(struct rockchip_tcphy *priv,
+					    u32 lane)
+{
+	writel(0x7799, priv->reg_base + TX_PSC_A0(lane));
+	writel(0x7798, priv->reg_base + TX_PSC_A1(lane));
+	writel(0x5098, priv->reg_base + TX_PSC_A2(lane));
+	writel(0x5098, priv->reg_base + TX_PSC_A3(lane));
+	writel(0, priv->reg_base + TX_TXCC_MGNFS_MULT_000(lane));
+	writel(0xbf, priv->reg_base + XCVR_DIAG_BIDI_CTRL(lane));
+}
+
+static void rockchip_tcphy_rx_usb3_cfg_lane(struct rockchip_tcphy *priv,
+					    u32 lane)
+{
+	writel(0xa6fd, priv->reg_base + RX_PSC_A0(lane));
+	writel(0xa6fd, priv->reg_base + RX_PSC_A1(lane));
+	writel(0xa410, priv->reg_base + RX_PSC_A2(lane));
+	writel(0x2410, priv->reg_base + RX_PSC_A3(lane));
+	writel(0x23ff, priv->reg_base + RX_PSC_CAL(lane));
+	writel(0x13, priv->reg_base + RX_SIGDET_HL_FILT_TMR(lane));
+	writel(0x03e7, priv->reg_base + RX_REE_CTRL_DATA_MASK(lane));
+	writel(0x1004, priv->reg_base + RX_DIAG_SIGDET_TUNE(lane));
+	writel(0x2010, priv->reg_base + RX_PSC_RDY(lane));
+	writel(0xfb, priv->reg_base + XCVR_DIAG_BIDI_CTRL(lane));
+}
+
+static int rockchip_tcphy_init(struct rockchip_tcphy *priv)
+{
+	const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
+	u32 val;
+	int ret;
+
+	ret = clk_enable(&priv->clk_core);
+	if (ret) {
+		dev_err(phy->dev, "failed to enable core clk (ret=%d)\n", ret);
+		return ret;
+	}
+
+	ret = clk_enable(&priv->clk_ref);
+	if (ret) {
+		dev_err(phy->dev, "failed to enable ref clk (ret=%d)\n", ret);
+		goto err_clk_core;
+	}
+
+	ret = reset_deassert(&priv->tcphy_rst);
+	if (ret) {
+		dev_err(phy->dev, "failed to deassert uphy-tcphy reset (ret=%d)\n",
+			ret);
+		goto err_clk_ref;
+	}
+
+	property_enable(priv, &cfg->typec_conn_dir, 0);
+
+	rockchip_tcphy_cfg_24m(priv);
+
+	rockchip_tcphy_cfg_usb3_pll(priv);
+
+	rockchip_tcphy_tx_usb3_cfg_lane(priv, 0);
+	rockchip_tcphy_rx_usb3_cfg_lane(priv, 1);
+
+	ret = reset_deassert(&priv->uphy_rst);
+	if (ret) {
+		dev_err(phy->dev, "failed to deassert uphy rst (ret=%d)\n",
+			ret);
+		goto err_tcphy_rst;
+	}
+
+	ret = readl_poll_sleep_timeout(priv->reg_base + PMA_CMN_CTRL1,
+				       val, val & CMN_READY, 10,
+				       PHY_MODE_SET_TIMEOUT);
+	if (ret < 0) {
+		dev_err(phy->dev, "PMA Timeout!\n");
+		ret = -ETIMEDOUT;
+		goto err_uphy_rst;
+	}
+
+	ret = reset_deassert(&priv->pipe_rst);
+	if (ret) {
+		dev_err(phy->dev, "failed to deassert pipe rst (ret=%d)\n",
+			ret);
+		goto err_uphy_rst;
+	}
+
+	return 0;
+
+err_uphy_rst:
+	reset_assert(&priv->uphy_rst);
+err_tcphy_rst:
+	reset_assert(&priv->tcphy_rst);
+err_clk_ref:
+	clk_disable(&priv->clk_ref);
+err_clk_core:
+	clk_disable(&priv->clk_core);
+	return ret;
+}
+
+static void rockchip_tcphy_exit(struct rockchip_tcphy *priv)
+{
+	reset_assert(&priv->tcphy_rst);
+	reset_assert(&priv->uphy_rst);
+	reset_assert(&priv->pipe_rst);
+	clk_disable(&priv->clk_core);
+	clk_disable(&priv->clk_ref);
+}
+
+static int tcphy_cfg_usb3_to_usb2_only(struct rockchip_tcphy *priv,
+				       bool value)
+{
+	const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
+
+	property_enable(priv, &cfg->usb3tousb2_en, value);
+	property_enable(priv, &cfg->usb3_host_disable, value);
+	property_enable(priv, &cfg->usb3_host_port, !value);
+
+	return 0;
+}
+
+static int rockchip_usb3_phy_power_on(struct phy *phy)
+{
+	struct udevice *parent = dev_get_parent(phy->dev);
+	struct rockchip_tcphy *priv = dev_get_priv(parent);
+	const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
+	const struct usb3phy_reg *reg = &cfg->pipe_status;
+	int timeout, new_mode;
+	u32 val;
+	int ret;
+
+	new_mode = rockchip_tcphy_get_mode(priv);
+	if (new_mode < 0) {
+		dev_err(phy->dev, "invalid mode %d\n", new_mode);
+		return new_mode;
+	}
+
+	if (priv->mode == new_mode)
+		return 0;
+
+	if (priv->mode == MODE_DISCONNECT) {
+		ret = rockchip_tcphy_init(priv);
+		if (ret) {
+			dev_err(dev, "failed to init tcphy (ret=%d)\n", ret);
+			return ret;
+		}
+	}
+
+	/* wait TCPHY for pipe ready */
+	for (timeout = 0; timeout < 100; timeout++) {
+		val = readl(priv->grf_base + reg->offset);
+		if (!(val & BIT(reg->enable_bit))) {
+			priv->mode |= new_mode & (MODE_DFP_USB | MODE_UFP_USB);
+
+			/* enable usb3 host */
+			tcphy_cfg_usb3_to_usb2_only(priv, false);
+			return 0;
+		}
+		usleep_range(10, 20);
+	}
+
+	if (priv->mode == MODE_DISCONNECT)
+		rockchip_tcphy_exit(priv);
+
+	return -ETIMEDOUT;
+}
+
+static int rockchip_usb3_phy_power_off(struct phy *phy)
+{
+	struct udevice *parent = dev_get_parent(phy->dev);
+	struct rockchip_tcphy *priv = dev_get_priv(parent);
+
+	tcphy_cfg_usb3_to_usb2_only(priv, false);
+
+	if (priv->mode == MODE_DISCONNECT)
+		goto exit;
+
+	priv->mode &= ~(MODE_UFP_USB | MODE_DFP_USB);
+	if (priv->mode == MODE_DISCONNECT)
+		rockchip_tcphy_exit(priv);
+
+exit:
+	return 0;
+}
+
+static struct phy_ops rockchip_tcphy_usb3_ops = {
+	.power_on = rockchip_usb3_phy_power_on,
+	.power_off = rockchip_usb3_phy_power_off,
+};
+
+static void rockchip_tcphy_pre_init(struct udevice *dev)
+{
+	struct rockchip_tcphy *priv = dev_get_priv(dev);
+	const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
+
+	reset_assert(&priv->tcphy_rst);
+	reset_assert(&priv->uphy_rst);
+	reset_assert(&priv->pipe_rst);
+
+	/* select external psm clock */
+	property_enable(priv, &cfg->external_psm, 1);
+	property_enable(priv, &cfg->usb3tousb2_en, 0);
+
+	priv->mode = MODE_DISCONNECT;
+}
+
+static int rockchip_tcphy_parse_dt(struct udevice *dev)
+{
+	struct rockchip_tcphy *priv = dev_get_priv(dev);
+	int ret;
+
+	priv->grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	if (IS_ERR(priv->grf_base))
+		return PTR_ERR(priv->grf_base);
+
+	ret = clk_get_by_name(dev, "tcpdcore", &priv->clk_core);
+	if (ret) {
+		dev_err(dev, "failed to get tcpdcore clk (ret=%d)\n", ret);
+		return ret;
+	}
+
+	ret = clk_get_by_name(dev, "tcpdphy-ref", &priv->clk_ref);
+	if (ret) {
+		dev_err(dev, "failed to get tcpdphy-ref clk (ret=%d)\n", ret);
+		return ret;
+	}
+
+	ret = reset_get_by_name(dev, "uphy", &priv->uphy_rst);
+	if (ret) {
+		dev_err(dev, "failed to get uphy reset (ret=%d)\n", ret);
+		return ret;
+	}
+
+	ret = reset_get_by_name(dev, "uphy-pipe", &priv->pipe_rst);
+	if (ret) {
+		dev_err(dev, "failed to get uphy-pipe reset (ret=%d)\n", ret);
+		return ret;
+	}
+
+	ret = reset_get_by_name(dev, "uphy-tcphy", &priv->tcphy_rst);
+	if (ret) {
+		dev_err(dev, "failed to get uphy-tcphy reset (ret=%d)\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_tcphy_probe(struct udevice *dev)
+{
+	struct rockchip_tcphy *priv = dev_get_priv(dev);
+	const struct rockchip_usb3phy_port_cfg *phy_cfgs;
+	unsigned int reg;
+	int index, ret;
+
+	priv->reg_base = (void __iomem *)dev_read_addr(dev);
+	if (IS_ERR(priv->reg_base))
+		return PTR_ERR(priv->reg_base);
+
+	ret = dev_read_u32_index(dev, "reg", 1, &reg);
+	if (ret) {
+		dev_err(dev, "failed to read reg property (ret = %d)\n", ret);
+		return ret;
+	}
+
+	phy_cfgs = (const struct rockchip_usb3phy_port_cfg *)
+					dev_get_driver_data(dev);
+	if (!phy_cfgs)
+		return -EINVAL;
+
+	/* find out a proper config which can be matched with dt. */
+	index = 0;
+	while (phy_cfgs[index].reg) {
+		if (phy_cfgs[index].reg == reg) {
+			priv->port_cfgs = &phy_cfgs[index];
+			break;
+		}
+
+		++index;
+	}
+
+	if (!priv->port_cfgs) {
+		dev_err(dev, "failed find proper phy-cfg\n");
+		return -EINVAL;
+	}
+
+	ret = rockchip_tcphy_parse_dt(dev);
+	if (ret)
+		return ret;
+
+	rockchip_tcphy_pre_init(dev);
+
+	return 0;
+}
+
+static int rockchip_tcphy_bind(struct udevice *dev)
+{
+	struct udevice *tcphy_dev;
+	ofnode node;
+	const char *name;
+	int ret = 0;
+
+	dev_for_each_subnode(node, dev) {
+		if (!ofnode_valid(node)) {
+			dev_info(dev, "subnode %s not found\n", dev->name);
+			return -ENXIO;
+		}
+
+		name = ofnode_get_name(node);
+		dev_dbg(dev, "subnode %s\n", name);
+
+		if (!strcasecmp(name, "dp-port")) {
+			dev_dbg(dev, "Warning: dp-port not supported yet!\n");
+			continue;
+		} else if (!strcasecmp(name, "usb3-port")) {
+			ret = device_bind_driver_to_node(dev,
+							 "rockchip_tcphy_usb3_port",
+							 name, node, &tcphy_dev);
+			if (ret) {
+				dev_err(dev,
+					"'%s' cannot bind 'rockchip_tcphy_usb3_port'\n",
+					name);
+				return ret;
+			}
+		}
+	}
+
+	return ret;
+}
+
+static const struct rockchip_usb3phy_port_cfg rk3399_typec_phy_cfgs[] = {
+	{
+		.reg			= 0xff7c0000,
+		.typec_conn_dir		= { 0xe580, 0, 16 },
+		.usb3tousb2_en		= { 0xe580, 3, 19 },
+		.external_psm		= { 0xe588, 14, 30 },
+		.pipe_status		= { 0xe5c0, 0, 0 },
+		.usb3_host_disable	= { 0x2434, 0, 16 },
+		.usb3_host_port		= { 0x2434, 12, 28 },
+		.uphy_dp_sel		= { 0x6268, 19, 19 },
+	},
+	{
+		.reg			= 0xff800000,
+		.typec_conn_dir		= { 0xe58c, 0, 16 },
+		.usb3tousb2_en		= { 0xe58c, 3, 19 },
+		.external_psm		= { 0xe594, 14, 30 },
+		.pipe_status		= { 0xe5c0, 16, 16 },
+		.usb3_host_disable	= { 0x2444, 0, 16 },
+		.usb3_host_port		= { 0x2444, 12, 28 },
+		.uphy_dp_sel		= { 0x6268, 3, 19 },
+	},
+	{ /* sentinel */ }
+};
+
+static const struct udevice_id rockchip_typec_phy_ids[] = {
+	{
+		.compatible = "rockchip,rk3399-typec-phy",
+		.data = (ulong)&rk3399_typec_phy_cfgs,
+	},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(rockchip_tcphy_usb3_port) = {
+	.name		= "rockchip_tcphy_usb3_port",
+	.id		= UCLASS_PHY,
+	.ops		= &rockchip_tcphy_usb3_ops,
+};
+
+U_BOOT_DRIVER(rockchip_typec_phy) = {
+	.name	= "rockchip_typec_phy",
+	.id	= UCLASS_PHY,
+	.of_match = rockchip_typec_phy_ids,
+	.probe = rockchip_tcphy_probe,
+	.bind = rockchip_tcphy_bind,
+	.priv_auto_alloc_size = sizeof(struct rockchip_tcphy),
+};
-- 
2.17.1

[PATCH v5 06/16] phy: rockchip: Add Rockchip USB TypeC PHY driver

[Frank Wang]

From: Jagan Teki <jagan@amarulasolutions.com>

Add USB TYPEC PHY driver for rockchip platform.

Referenced from Linux TypeC PHY driver, currently
supporting usb3-port and dp-port need to add it
in the future.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/phy/rockchip/Kconfig              |   7 +
 drivers/phy/rockchip/Makefile             |   1 +
 drivers/phy/rockchip/phy-rockchip-typec.c | 796 ++++++++++++++++++++++
 3 files changed, 804 insertions(+)
 create mode 100644 drivers/phy/rockchip/phy-rockchip-typec.c

diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index d73ac695e1..84cc7c876d 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -11,4 +11,11 @@ config PHY_ROCKCHIP_INNO_USB2
 	help
 	  Support for Rockchip USB2.0 PHY with Innosilicon IP block.
 
+config PHY_ROCKCHIP_TYPEC
+	bool "Rockchip TYPEC PHY Driver"
+	depends on ARCH_ROCKCHIP
+	select PHY
+	help
+	  Enable this to support the Rockchip USB TYPEC PHY.
+
 endmenu
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index 9b0cbc6acf..95b2f8a3c0 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -4,3 +4,4 @@
 #
 
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
+obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)	+= phy-rockchip-typec.o
diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
new file mode 100644
index 0000000000..c9c8e1c542
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
@@ -0,0 +1,796 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * ROCKCHIP Type-C PHY driver.
+ *
+ * Copyright (C) 2020 Amarula Solutions(India)
+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
+ * Author: Chris Zhong <zyw@rock-chips.com>
+ *         Kever Yang <kever.yang@rock-chips.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <generic-phy.h>
+#include <reset.h>
+#include <syscon.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <linux/iopoll.h>
+#include <asm/arch-rockchip/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define usleep_range(a, b) udelay((b))
+
+#define CMN_SSM_BANDGAP			(0x21 << 2)
+#define CMN_SSM_BIAS			(0x22 << 2)
+#define CMN_PLLSM0_PLLEN		(0x29 << 2)
+#define CMN_PLLSM0_PLLPRE		(0x2a << 2)
+#define CMN_PLLSM0_PLLVREF		(0x2b << 2)
+#define CMN_PLLSM0_PLLLOCK		(0x2c << 2)
+#define CMN_PLLSM1_PLLEN		(0x31 << 2)
+#define CMN_PLLSM1_PLLPRE		(0x32 << 2)
+#define CMN_PLLSM1_PLLVREF		(0x33 << 2)
+#define CMN_PLLSM1_PLLLOCK		(0x34 << 2)
+#define CMN_PLLSM1_USER_DEF_CTRL	(0x37 << 2)
+#define CMN_ICAL_OVRD			(0xc1 << 2)
+#define CMN_PLL0_VCOCAL_OVRD		(0x83 << 2)
+#define CMN_PLL0_VCOCAL_INIT		(0x84 << 2)
+#define CMN_PLL0_VCOCAL_ITER		(0x85 << 2)
+#define CMN_PLL0_LOCK_REFCNT_START	(0x90 << 2)
+#define CMN_PLL0_LOCK_PLLCNT_START	(0x92 << 2)
+#define CMN_PLL0_LOCK_PLLCNT_THR	(0x93 << 2)
+#define CMN_PLL0_INTDIV			(0x94 << 2)
+#define CMN_PLL0_FRACDIV		(0x95 << 2)
+#define CMN_PLL0_HIGH_THR		(0x96 << 2)
+#define CMN_PLL0_DSM_DIAG		(0x97 << 2)
+#define CMN_PLL0_SS_CTRL1		(0x98 << 2)
+#define CMN_PLL0_SS_CTRL2		(0x99 << 2)
+#define CMN_PLL1_VCOCAL_START		(0xa1 << 2)
+#define CMN_PLL1_VCOCAL_OVRD		(0xa3 << 2)
+#define CMN_PLL1_VCOCAL_INIT		(0xa4 << 2)
+#define CMN_PLL1_VCOCAL_ITER		(0xa5 << 2)
+#define CMN_PLL1_LOCK_REFCNT_START	(0xb0 << 2)
+#define CMN_PLL1_LOCK_PLLCNT_START	(0xb2 << 2)
+#define CMN_PLL1_LOCK_PLLCNT_THR	(0xb3 << 2)
+#define CMN_PLL1_INTDIV			(0xb4 << 2)
+#define CMN_PLL1_FRACDIV		(0xb5 << 2)
+#define CMN_PLL1_HIGH_THR		(0xb6 << 2)
+#define CMN_PLL1_DSM_DIAG		(0xb7 << 2)
+#define CMN_PLL1_SS_CTRL1		(0xb8 << 2)
+#define CMN_PLL1_SS_CTRL2		(0xb9 << 2)
+#define CMN_RXCAL_OVRD			(0xd1 << 2)
+
+#define CMN_TXPUCAL_CTRL		(0xe0 << 2)
+#define CMN_TXPUCAL_OVRD		(0xe1 << 2)
+#define CMN_TXPDCAL_CTRL		(0xf0 << 2)
+#define CMN_TXPDCAL_OVRD		(0xf1 << 2)
+
+/* For CMN_TXPUCAL_CTRL, CMN_TXPDCAL_CTRL */
+#define CMN_TXPXCAL_START		BIT(15)
+#define CMN_TXPXCAL_DONE		BIT(14)
+#define CMN_TXPXCAL_NO_RESPONSE		BIT(13)
+#define CMN_TXPXCAL_CURRENT_RESPONSE	BIT(12)
+
+#define CMN_TXPU_ADJ_CTRL		(0x108 << 2)
+#define CMN_TXPD_ADJ_CTRL		(0x10c << 2)
+
+/*
+ * For CMN_TXPUCAL_CTRL, CMN_TXPDCAL_CTRL,
+ *     CMN_TXPU_ADJ_CTRL, CMN_TXPDCAL_CTRL
+ *
+ * NOTE: some of these registers are documented to be 2's complement
+ * signed numbers, but then documented to be always positive.  Weird.
+ * In such a case, using CMN_CALIB_CODE_POS() avoids the unnecessary
+ * sign extension.
+ */
+#define CMN_CALIB_CODE_WIDTH	7
+#define CMN_CALIB_CODE_OFFSET	0
+#define CMN_CALIB_CODE_MASK	GENMASK(CMN_CALIB_CODE_WIDTH, 0)
+#define CMN_CALIB_CODE(x)	\
+	sign_extend32((x) >> CMN_CALIB_CODE_OFFSET, CMN_CALIB_CODE_WIDTH)
+
+#define CMN_CALIB_CODE_POS_MASK	GENMASK(CMN_CALIB_CODE_WIDTH - 1, 0)
+#define CMN_CALIB_CODE_POS(x)	\
+	(((x) >> CMN_CALIB_CODE_OFFSET) & CMN_CALIB_CODE_POS_MASK)
+
+#define CMN_DIAG_PLL0_FBH_OVRD		(0x1c0 << 2)
+#define CMN_DIAG_PLL0_FBL_OVRD		(0x1c1 << 2)
+#define CMN_DIAG_PLL0_OVRD		(0x1c2 << 2)
+#define CMN_DIAG_PLL0_V2I_TUNE		(0x1c5 << 2)
+#define CMN_DIAG_PLL0_CP_TUNE		(0x1c6 << 2)
+#define CMN_DIAG_PLL0_LF_PROG		(0x1c7 << 2)
+#define CMN_DIAG_PLL1_FBH_OVRD		(0x1d0 << 2)
+#define CMN_DIAG_PLL1_FBL_OVRD		(0x1d1 << 2)
+#define CMN_DIAG_PLL1_OVRD		(0x1d2 << 2)
+#define CMN_DIAG_PLL1_V2I_TUNE		(0x1d5 << 2)
+#define CMN_DIAG_PLL1_CP_TUNE		(0x1d6 << 2)
+#define CMN_DIAG_PLL1_LF_PROG		(0x1d7 << 2)
+#define CMN_DIAG_PLL1_PTATIS_TUNE1	(0x1d8 << 2)
+#define CMN_DIAG_PLL1_PTATIS_TUNE2	(0x1d9 << 2)
+#define CMN_DIAG_PLL1_INCLK_CTRL	(0x1da << 2)
+#define CMN_DIAG_HSCLK_SEL		(0x1e0 << 2)
+
+#define XCVR_PSM_RCTRL(n)		((0x4001 | ((n) << 9)) << 2)
+#define XCVR_PSM_CAL_TMR(n)		((0x4002 | ((n) << 9)) << 2)
+#define XCVR_PSM_A0IN_TMR(n)		((0x4003 | ((n) << 9)) << 2)
+#define TX_TXCC_CAL_SCLR_MULT(n)	((0x4047 | ((n) << 9)) << 2)
+#define TX_TXCC_CPOST_MULT_00(n)	((0x404c | ((n) << 9)) << 2)
+#define TX_TXCC_CPOST_MULT_01(n)	((0x404d | ((n) << 9)) << 2)
+#define TX_TXCC_CPOST_MULT_10(n)	((0x404e | ((n) << 9)) << 2)
+#define TX_TXCC_CPOST_MULT_11(n)	((0x404f | ((n) << 9)) << 2)
+#define TX_TXCC_MGNFS_MULT_000(n)	((0x4050 | ((n) << 9)) << 2)
+#define TX_TXCC_MGNFS_MULT_001(n)	((0x4051 | ((n) << 9)) << 2)
+#define TX_TXCC_MGNFS_MULT_010(n)	((0x4052 | ((n) << 9)) << 2)
+#define TX_TXCC_MGNFS_MULT_011(n)	((0x4053 | ((n) << 9)) << 2)
+#define TX_TXCC_MGNFS_MULT_100(n)	((0x4054 | ((n) << 9)) << 2)
+#define TX_TXCC_MGNFS_MULT_101(n)	((0x4055 | ((n) << 9)) << 2)
+#define TX_TXCC_MGNFS_MULT_110(n)	((0x4056 | ((n) << 9)) << 2)
+#define TX_TXCC_MGNFS_MULT_111(n)	((0x4057 | ((n) << 9)) << 2)
+#define TX_TXCC_MGNLS_MULT_000(n)	((0x4058 | ((n) << 9)) << 2)
+#define TX_TXCC_MGNLS_MULT_001(n)	((0x4059 | ((n) << 9)) << 2)
+#define TX_TXCC_MGNLS_MULT_010(n)	((0x405a | ((n) << 9)) << 2)
+#define TX_TXCC_MGNLS_MULT_011(n)	((0x405b | ((n) << 9)) << 2)
+#define TX_TXCC_MGNLS_MULT_100(n)	((0x405c | ((n) << 9)) << 2)
+#define TX_TXCC_MGNLS_MULT_101(n)	((0x405d | ((n) << 9)) << 2)
+#define TX_TXCC_MGNLS_MULT_110(n)	((0x405e | ((n) << 9)) << 2)
+#define TX_TXCC_MGNLS_MULT_111(n)	((0x405f | ((n) << 9)) << 2)
+
+#define XCVR_DIAG_PLLDRC_CTRL(n)	((0x40e0 | ((n) << 9)) << 2)
+#define XCVR_DIAG_BIDI_CTRL(n)		((0x40e8 | ((n) << 9)) << 2)
+#define XCVR_DIAG_LANE_FCM_EN_MGN(n)	((0x40f2 | ((n) << 9)) << 2)
+#define TX_PSC_A0(n)			((0x4100 | ((n) << 9)) << 2)
+#define TX_PSC_A1(n)			((0x4101 | ((n) << 9)) << 2)
+#define TX_PSC_A2(n)			((0x4102 | ((n) << 9)) << 2)
+#define TX_PSC_A3(n)			((0x4103 | ((n) << 9)) << 2)
+#define TX_RCVDET_CTRL(n)		((0x4120 | ((n) << 9)) << 2)
+#define TX_RCVDET_EN_TMR(n)		((0x4122 | ((n) << 9)) << 2)
+#define TX_RCVDET_ST_TMR(n)		((0x4123 | ((n) << 9)) << 2)
+#define TX_DIAG_TX_DRV(n)		((0x41e1 | ((n) << 9)) << 2)
+#define TX_DIAG_BGREF_PREDRV_DELAY	(0x41e7 << 2)
+
+/* Use this for "n" in macros like "_MULT_XXX" to target the aux channel */
+#define AUX_CH_LANE			8
+
+#define TX_ANA_CTRL_REG_1		(0x5020 << 2)
+
+#define TXDA_DP_AUX_EN			BIT(15)
+#define AUXDA_SE_EN			BIT(14)
+#define TXDA_CAL_LATCH_EN		BIT(13)
+#define AUXDA_POLARITY			BIT(12)
+#define TXDA_DRV_POWER_ISOLATION_EN	BIT(11)
+#define TXDA_DRV_POWER_EN_PH_2_N	BIT(10)
+#define TXDA_DRV_POWER_EN_PH_1_N	BIT(9)
+#define TXDA_BGREF_EN			BIT(8)
+#define TXDA_DRV_LDO_EN			BIT(7)
+#define TXDA_DECAP_EN_DEL		BIT(6)
+#define TXDA_DECAP_EN			BIT(5)
+#define TXDA_UPHY_SUPPLY_EN_DEL		BIT(4)
+#define TXDA_UPHY_SUPPLY_EN		BIT(3)
+#define TXDA_LOW_LEAKAGE_EN		BIT(2)
+#define TXDA_DRV_IDLE_LOWI_EN		BIT(1)
+#define TXDA_DRV_CMN_MODE_EN		BIT(0)
+
+#define TX_ANA_CTRL_REG_2		(0x5021 << 2)
+
+#define AUXDA_DEBOUNCING_CLK		BIT(15)
+#define TXDA_LPBK_RECOVERED_CLK_EN	BIT(14)
+#define TXDA_LPBK_ISI_GEN_EN		BIT(13)
+#define TXDA_LPBK_SERIAL_EN		BIT(12)
+#define TXDA_LPBK_LINE_EN		BIT(11)
+#define TXDA_DRV_LDO_REDC_SINKIQ	BIT(10)
+#define XCVR_DECAP_EN_DEL		BIT(9)
+#define XCVR_DECAP_EN			BIT(8)
+#define TXDA_MPHY_ENABLE_HS_NT		BIT(7)
+#define TXDA_MPHY_SA_MODE		BIT(6)
+#define TXDA_DRV_LDO_RBYR_FB_EN		BIT(5)
+#define TXDA_DRV_RST_PULL_DOWN		BIT(4)
+#define TXDA_DRV_LDO_BG_FB_EN		BIT(3)
+#define TXDA_DRV_LDO_BG_REF_EN		BIT(2)
+#define TXDA_DRV_PREDRV_EN_DEL		BIT(1)
+#define TXDA_DRV_PREDRV_EN		BIT(0)
+
+#define TXDA_COEFF_CALC_CTRL		(0x5022 << 2)
+
+#define TX_HIGH_Z			BIT(6)
+#define TX_VMARGIN_OFFSET		3
+#define TX_VMARGIN_MASK			0x7
+#define LOW_POWER_SWING_EN		BIT(2)
+#define TX_FCM_DRV_MAIN_EN		BIT(1)
+#define TX_FCM_FULL_MARGIN		BIT(0)
+
+#define TX_DIG_CTRL_REG_2		(0x5024 << 2)
+
+#define TX_HIGH_Z_TM_EN			BIT(15)
+#define TX_RESCAL_CODE_OFFSET		0
+#define TX_RESCAL_CODE_MASK		0x3f
+
+#define TXDA_CYA_AUXDA_CYA		(0x5025 << 2)
+#define TX_ANA_CTRL_REG_3		(0x5026 << 2)
+#define TX_ANA_CTRL_REG_4		(0x5027 << 2)
+#define TX_ANA_CTRL_REG_5		(0x5029 << 2)
+
+#define RX_PSC_A0(n)			((0x8000 | ((n) << 9)) << 2)
+#define RX_PSC_A1(n)			((0x8001 | ((n) << 9)) << 2)
+#define RX_PSC_A2(n)			((0x8002 | ((n) << 9)) << 2)
+#define RX_PSC_A3(n)			((0x8003 | ((n) << 9)) << 2)
+#define RX_PSC_CAL(n)			((0x8006 | ((n) << 9)) << 2)
+#define RX_PSC_RDY(n)			((0x8007 | ((n) << 9)) << 2)
+#define RX_IQPI_ILL_CAL_OVRD		(0x8023 << 2)
+#define RX_EPI_ILL_CAL_OVRD		(0x8033 << 2)
+#define RX_SDCAL0_OVRD			(0x8041 << 2)
+#define RX_SDCAL1_OVRD			(0x8049 << 2)
+#define RX_SLC_INIT			(0x806d << 2)
+#define RX_SLC_RUN			(0x806e << 2)
+#define RX_CDRLF_CNFG2			(0x8081 << 2)
+#define RX_SIGDET_HL_FILT_TMR(n)	((0x8090 | ((n) << 9)) << 2)
+#define RX_SLC_IOP0_OVRD		(0x8101 << 2)
+#define RX_SLC_IOP1_OVRD		(0x8105 << 2)
+#define RX_SLC_QOP0_OVRD		(0x8109 << 2)
+#define RX_SLC_QOP1_OVRD		(0x810d << 2)
+#define RX_SLC_EOP0_OVRD		(0x8111 << 2)
+#define RX_SLC_EOP1_OVRD		(0x8115 << 2)
+#define RX_SLC_ION0_OVRD		(0x8119 << 2)
+#define RX_SLC_ION1_OVRD		(0x811d << 2)
+#define RX_SLC_QON0_OVRD		(0x8121 << 2)
+#define RX_SLC_QON1_OVRD		(0x8125 << 2)
+#define RX_SLC_EON0_OVRD		(0x8129 << 2)
+#define RX_SLC_EON1_OVRD		(0x812d << 2)
+#define RX_SLC_IEP0_OVRD		(0x8131 << 2)
+#define RX_SLC_IEP1_OVRD		(0x8135 << 2)
+#define RX_SLC_QEP0_OVRD		(0x8139 << 2)
+#define RX_SLC_QEP1_OVRD		(0x813d << 2)
+#define RX_SLC_EEP0_OVRD		(0x8141 << 2)
+#define RX_SLC_EEP1_OVRD		(0x8145 << 2)
+#define RX_SLC_IEN0_OVRD		(0x8149 << 2)
+#define RX_SLC_IEN1_OVRD		(0x814d << 2)
+#define RX_SLC_QEN0_OVRD		(0x8151 << 2)
+#define RX_SLC_QEN1_OVRD		(0x8155 << 2)
+#define RX_SLC_EEN0_OVRD		(0x8159 << 2)
+#define RX_SLC_EEN1_OVRD		(0x815d << 2)
+#define RX_REE_CTRL_DATA_MASK(n)	((0x81bb | ((n) << 9)) << 2)
+#define RX_DIAG_SIGDET_TUNE(n)		((0x81dc | ((n) << 9)) << 2)
+#define RX_DIAG_SC2C_DELAY		(0x81e1 << 2)
+
+#define PMA_LANE_CFG			(0xc000 << 2)
+#define PIPE_CMN_CTRL1			(0xc001 << 2)
+#define PIPE_CMN_CTRL2			(0xc002 << 2)
+#define PIPE_COM_LOCK_CFG1		(0xc003 << 2)
+#define PIPE_COM_LOCK_CFG2		(0xc004 << 2)
+#define PIPE_RCV_DET_INH		(0xc005 << 2)
+#define DP_MODE_CTL			(0xc008 << 2)
+#define DP_CLK_CTL			(0xc009 << 2)
+#define STS				(0xc00F << 2)
+#define PHY_ISO_CMN_CTRL		(0xc010 << 2)
+#define PHY_DP_TX_CTL			(0xc408 << 2)
+#define PMA_CMN_CTRL1			(0xc800 << 2)
+#define PHY_PMA_ISO_CMN_CTRL		(0xc810 << 2)
+#define PHY_ISOLATION_CTRL		(0xc81f << 2)
+#define PHY_PMA_ISO_XCVR_CTRL(n)	((0xcc11 | ((n) << 6)) << 2)
+#define PHY_PMA_ISO_LINK_MODE(n)	((0xcc12 | ((n) << 6)) << 2)
+#define PHY_PMA_ISO_PWRST_CTRL(n)	((0xcc13 | ((n) << 6)) << 2)
+#define PHY_PMA_ISO_TX_DATA_LO(n)	((0xcc14 | ((n) << 6)) << 2)
+#define PHY_PMA_ISO_TX_DATA_HI(n)	((0xcc15 | ((n) << 6)) << 2)
+#define PHY_PMA_ISO_RX_DATA_LO(n)	((0xcc16 | ((n) << 6)) << 2)
+#define PHY_PMA_ISO_RX_DATA_HI(n)	((0xcc17 | ((n) << 6)) << 2)
+#define TX_BIST_CTRL(n)			((0x4140 | ((n) << 9)) << 2)
+#define TX_BIST_UDDWR(n)		((0x4141 | ((n) << 9)) << 2)
+
+/*
+ * Selects which PLL clock will be driven on the analog high speed
+ * clock 0: PLL 0 div 1
+ * clock 1: PLL 1 div 2
+ */
+#define CLK_PLL_CONFIG			0X30
+#define CLK_PLL_MASK			0x33
+
+#define CMN_READY			BIT(0)
+
+#define DP_PLL_CLOCK_ENABLE		BIT(2)
+#define DP_PLL_ENABLE			BIT(0)
+#define DP_PLL_DATA_RATE_RBR		((2 << 12) | (4 << 8))
+#define DP_PLL_DATA_RATE_HBR		((2 << 12) | (4 << 8))
+#define DP_PLL_DATA_RATE_HBR2		((1 << 12) | (2 << 8))
+
+#define DP_MODE_A0			BIT(4)
+#define DP_MODE_A2			BIT(6)
+#define DP_MODE_ENTER_A0		0xc101
+#define DP_MODE_ENTER_A2		0xc104
+
+#define PHY_MODE_SET_TIMEOUT		100000
+
+#define PIN_ASSIGN_C_E			0x51d9
+#define PIN_ASSIGN_D_F			0x5100
+
+#define MODE_DISCONNECT			0
+#define MODE_UFP_USB			BIT(0)
+#define MODE_DFP_USB			BIT(1)
+#define MODE_DFP_DP			BIT(2)
+
+struct usb3phy_reg {
+	u32 offset;
+	u32 enable_bit;
+	u32 write_enable;
+};
+
+/**
+ * struct rockchip_usb3phy_port_cfg: usb3-phy port configuration.
+ * @reg: the base address for usb3-phy config.
+ * @typec_conn_dir: the register of type-c connector direction.
+ * @usb3tousb2_en: the register of type-c force usb2 to usb2 enable.
+ * @external_psm: the register of type-c phy external psm clock.
+ * @pipe_status: the register of type-c phy pipe status.
+ * @usb3_host_disable: the register of type-c usb3 host disable.
+ * @usb3_host_port: the register of type-c usb3 host port.
+ * @uphy_dp_sel: the register of type-c phy DP select control.
+ */
+struct rockchip_usb3phy_port_cfg {
+	unsigned int reg;
+	struct usb3phy_reg typec_conn_dir;
+	struct usb3phy_reg usb3tousb2_en;
+	struct usb3phy_reg external_psm;
+	struct usb3phy_reg pipe_status;
+	struct usb3phy_reg usb3_host_disable;
+	struct usb3phy_reg usb3_host_port;
+	struct usb3phy_reg uphy_dp_sel;
+};
+
+struct rockchip_tcphy {
+	void __iomem *reg_base;
+	void __iomem *grf_base;
+	struct clk clk_core;
+	struct clk clk_ref;
+	struct reset_ctl uphy_rst;
+	struct reset_ctl pipe_rst;
+	struct reset_ctl tcphy_rst;
+	const struct rockchip_usb3phy_port_cfg *port_cfgs;
+	u8 mode;
+};
+
+struct phy_reg {
+	u16 value;
+	u32 addr;
+};
+
+static struct phy_reg usb3_pll_cfg[] = {
+	{ 0xf0,		CMN_PLL0_VCOCAL_INIT },
+	{ 0x18,		CMN_PLL0_VCOCAL_ITER },
+	{ 0xd0,		CMN_PLL0_INTDIV },
+	{ 0x4a4a,	CMN_PLL0_FRACDIV },
+	{ 0x34,		CMN_PLL0_HIGH_THR },
+	{ 0x1ee,	CMN_PLL0_SS_CTRL1 },
+	{ 0x7f03,	CMN_PLL0_SS_CTRL2 },
+	{ 0x20,		CMN_PLL0_DSM_DIAG },
+	{ 0,		CMN_DIAG_PLL0_OVRD },
+	{ 0,		CMN_DIAG_PLL0_FBH_OVRD },
+	{ 0,		CMN_DIAG_PLL0_FBL_OVRD },
+	{ 0x7,		CMN_DIAG_PLL0_V2I_TUNE },
+	{ 0x45,		CMN_DIAG_PLL0_CP_TUNE },
+	{ 0x8,		CMN_DIAG_PLL0_LF_PROG },
+};
+
+static inline int property_enable(struct rockchip_tcphy *priv,
+				  const struct usb3phy_reg *reg, bool en)
+{
+	u32 mask = 1 << reg->write_enable;
+	u32 val = en << reg->enable_bit;
+
+	return writel(val | mask, priv->grf_base + reg->offset);
+}
+
+static int rockchip_tcphy_get_mode(struct rockchip_tcphy *priv)
+{
+	/* TODO: Add proper logic to find DP or USB3 mode */
+	return MODE_DFP_USB | MODE_UFP_USB;
+}
+
+static void rockchip_tcphy_cfg_24m(struct rockchip_tcphy *priv)
+{
+	u32 i, rdata;
+
+	/*
+	 * cmn_ref_clk_sel = 3, select the 24Mhz for clk parent
+	 * cmn_psm_clk_dig_div = 2, set the clk division to 2
+	 */
+	writel(0x830, priv->reg_base + PMA_CMN_CTRL1);
+	for (i = 0; i < 4; i++) {
+		/*
+		 * The following PHY configuration assumes a 24 MHz reference
+		 * clock.
+		 */
+		writel(0x90, priv->reg_base + XCVR_DIAG_LANE_FCM_EN_MGN(i));
+		writel(0x960, priv->reg_base + TX_RCVDET_EN_TMR(i));
+		writel(0x30, priv->reg_base + TX_RCVDET_ST_TMR(i));
+	}
+
+	rdata = readl(priv->reg_base + CMN_DIAG_HSCLK_SEL);
+	rdata &= ~CLK_PLL_MASK;
+	rdata |= CLK_PLL_CONFIG;
+	writel(rdata, priv->reg_base + CMN_DIAG_HSCLK_SEL);
+}
+
+static void rockchip_tcphy_cfg_usb3_pll(struct rockchip_tcphy *priv)
+{
+	u32 i;
+
+	/* load the configuration of PLL0 */
+	for (i = 0; i < ARRAY_SIZE(usb3_pll_cfg); i++)
+		writel(usb3_pll_cfg[i].value,
+		       priv->reg_base + usb3_pll_cfg[i].addr);
+}
+
+static void rockchip_tcphy_tx_usb3_cfg_lane(struct rockchip_tcphy *priv,
+					    u32 lane)
+{
+	writel(0x7799, priv->reg_base + TX_PSC_A0(lane));
+	writel(0x7798, priv->reg_base + TX_PSC_A1(lane));
+	writel(0x5098, priv->reg_base + TX_PSC_A2(lane));
+	writel(0x5098, priv->reg_base + TX_PSC_A3(lane));
+	writel(0, priv->reg_base + TX_TXCC_MGNFS_MULT_000(lane));
+	writel(0xbf, priv->reg_base + XCVR_DIAG_BIDI_CTRL(lane));
+}
+
+static void rockchip_tcphy_rx_usb3_cfg_lane(struct rockchip_tcphy *priv,
+					    u32 lane)
+{
+	writel(0xa6fd, priv->reg_base + RX_PSC_A0(lane));
+	writel(0xa6fd, priv->reg_base + RX_PSC_A1(lane));
+	writel(0xa410, priv->reg_base + RX_PSC_A2(lane));
+	writel(0x2410, priv->reg_base + RX_PSC_A3(lane));
+	writel(0x23ff, priv->reg_base + RX_PSC_CAL(lane));
+	writel(0x13, priv->reg_base + RX_SIGDET_HL_FILT_TMR(lane));
+	writel(0x03e7, priv->reg_base + RX_REE_CTRL_DATA_MASK(lane));
+	writel(0x1004, priv->reg_base + RX_DIAG_SIGDET_TUNE(lane));
+	writel(0x2010, priv->reg_base + RX_PSC_RDY(lane));
+	writel(0xfb, priv->reg_base + XCVR_DIAG_BIDI_CTRL(lane));
+}
+
+static int rockchip_tcphy_init(struct rockchip_tcphy *priv)
+{
+	const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
+	u32 val;
+	int ret;
+
+	ret = clk_enable(&priv->clk_core);
+	if (ret) {
+		dev_err(phy->dev, "failed to enable core clk (ret=%d)\n", ret);
+		return ret;
+	}
+
+	ret = clk_enable(&priv->clk_ref);
+	if (ret) {
+		dev_err(phy->dev, "failed to enable ref clk (ret=%d)\n", ret);
+		goto err_clk_core;
+	}
+
+	ret = reset_deassert(&priv->tcphy_rst);
+	if (ret) {
+		dev_err(phy->dev, "failed to deassert uphy-tcphy reset (ret=%d)\n",
+			ret);
+		goto err_clk_ref;
+	}
+
+	property_enable(priv, &cfg->typec_conn_dir, 0);
+
+	rockchip_tcphy_cfg_24m(priv);
+
+	rockchip_tcphy_cfg_usb3_pll(priv);
+
+	rockchip_tcphy_tx_usb3_cfg_lane(priv, 0);
+	rockchip_tcphy_rx_usb3_cfg_lane(priv, 1);
+
+	ret = reset_deassert(&priv->uphy_rst);
+	if (ret) {
+		dev_err(phy->dev, "failed to deassert uphy rst (ret=%d)\n",
+			ret);
+		goto err_tcphy_rst;
+	}
+
+	ret = readl_poll_sleep_timeout(priv->reg_base + PMA_CMN_CTRL1,
+				       val, val & CMN_READY, 10,
+				       PHY_MODE_SET_TIMEOUT);
+	if (ret < 0) {
+		dev_err(phy->dev, "PMA Timeout!\n");
+		ret = -ETIMEDOUT;
+		goto err_uphy_rst;
+	}
+
+	ret = reset_deassert(&priv->pipe_rst);
+	if (ret) {
+		dev_err(phy->dev, "failed to deassert pipe rst (ret=%d)\n",
+			ret);
+		goto err_uphy_rst;
+	}
+
+	return 0;
+
+err_uphy_rst:
+	reset_assert(&priv->uphy_rst);
+err_tcphy_rst:
+	reset_assert(&priv->tcphy_rst);
+err_clk_ref:
+	clk_disable(&priv->clk_ref);
+err_clk_core:
+	clk_disable(&priv->clk_core);
+	return ret;
+}
+
+static void rockchip_tcphy_exit(struct rockchip_tcphy *priv)
+{
+	reset_assert(&priv->tcphy_rst);
+	reset_assert(&priv->uphy_rst);
+	reset_assert(&priv->pipe_rst);
+	clk_disable(&priv->clk_core);
+	clk_disable(&priv->clk_ref);
+}
+
+static int tcphy_cfg_usb3_to_usb2_only(struct rockchip_tcphy *priv,
+				       bool value)
+{
+	const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
+
+	property_enable(priv, &cfg->usb3tousb2_en, value);
+	property_enable(priv, &cfg->usb3_host_disable, value);
+	property_enable(priv, &cfg->usb3_host_port, !value);
+
+	return 0;
+}
+
+static int rockchip_usb3_phy_power_on(struct phy *phy)
+{
+	struct udevice *parent = dev_get_parent(phy->dev);
+	struct rockchip_tcphy *priv = dev_get_priv(parent);
+	const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
+	const struct usb3phy_reg *reg = &cfg->pipe_status;
+	int timeout, new_mode;
+	u32 val;
+	int ret;
+
+	new_mode = rockchip_tcphy_get_mode(priv);
+	if (new_mode < 0) {
+		dev_err(phy->dev, "invalid mode %d\n", new_mode);
+		return new_mode;
+	}
+
+	if (priv->mode == new_mode)
+		return 0;
+
+	if (priv->mode == MODE_DISCONNECT) {
+		ret = rockchip_tcphy_init(priv);
+		if (ret) {
+			dev_err(dev, "failed to init tcphy (ret=%d)\n", ret);
+			return ret;
+		}
+	}
+
+	/* wait TCPHY for pipe ready */
+	for (timeout = 0; timeout < 100; timeout++) {
+		val = readl(priv->grf_base + reg->offset);
+		if (!(val & BIT(reg->enable_bit))) {
+			priv->mode |= new_mode & (MODE_DFP_USB | MODE_UFP_USB);
+
+			/* enable usb3 host */
+			tcphy_cfg_usb3_to_usb2_only(priv, false);
+			return 0;
+		}
+		usleep_range(10, 20);
+	}
+
+	if (priv->mode == MODE_DISCONNECT)
+		rockchip_tcphy_exit(priv);
+
+	return -ETIMEDOUT;
+}
+
+static int rockchip_usb3_phy_power_off(struct phy *phy)
+{
+	struct udevice *parent = dev_get_parent(phy->dev);
+	struct rockchip_tcphy *priv = dev_get_priv(parent);
+
+	tcphy_cfg_usb3_to_usb2_only(priv, false);
+
+	if (priv->mode == MODE_DISCONNECT)
+		goto exit;
+
+	priv->mode &= ~(MODE_UFP_USB | MODE_DFP_USB);
+	if (priv->mode == MODE_DISCONNECT)
+		rockchip_tcphy_exit(priv);
+
+exit:
+	return 0;
+}
+
+static struct phy_ops rockchip_tcphy_usb3_ops = {
+	.power_on = rockchip_usb3_phy_power_on,
+	.power_off = rockchip_usb3_phy_power_off,
+};
+
+static void rockchip_tcphy_pre_init(struct udevice *dev)
+{
+	struct rockchip_tcphy *priv = dev_get_priv(dev);
+	const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
+
+	reset_assert(&priv->tcphy_rst);
+	reset_assert(&priv->uphy_rst);
+	reset_assert(&priv->pipe_rst);
+
+	/* select external psm clock */
+	property_enable(priv, &cfg->external_psm, 1);
+	property_enable(priv, &cfg->usb3tousb2_en, 0);
+
+	priv->mode = MODE_DISCONNECT;
+}
+
+static int rockchip_tcphy_parse_dt(struct udevice *dev)
+{
+	struct rockchip_tcphy *priv = dev_get_priv(dev);
+	int ret;
+
+	priv->grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	if (IS_ERR(priv->grf_base))
+		return PTR_ERR(priv->grf_base);
+
+	ret = clk_get_by_name(dev, "tcpdcore", &priv->clk_core);
+	if (ret) {
+		dev_err(dev, "failed to get tcpdcore clk (ret=%d)\n", ret);
+		return ret;
+	}
+
+	ret = clk_get_by_name(dev, "tcpdphy-ref", &priv->clk_ref);
+	if (ret) {
+		dev_err(dev, "failed to get tcpdphy-ref clk (ret=%d)\n", ret);
+		return ret;
+	}
+
+	ret = reset_get_by_name(dev, "uphy", &priv->uphy_rst);
+	if (ret) {
+		dev_err(dev, "failed to get uphy reset (ret=%d)\n", ret);
+		return ret;
+	}
+
+	ret = reset_get_by_name(dev, "uphy-pipe", &priv->pipe_rst);
+	if (ret) {
+		dev_err(dev, "failed to get uphy-pipe reset (ret=%d)\n", ret);
+		return ret;
+	}
+
+	ret = reset_get_by_name(dev, "uphy-tcphy", &priv->tcphy_rst);
+	if (ret) {
+		dev_err(dev, "failed to get uphy-tcphy reset (ret=%d)\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_tcphy_probe(struct udevice *dev)
+{
+	struct rockchip_tcphy *priv = dev_get_priv(dev);
+	const struct rockchip_usb3phy_port_cfg *phy_cfgs;
+	unsigned int reg;
+	int index, ret;
+
+	priv->reg_base = (void __iomem *)dev_read_addr(dev);
+	if (IS_ERR(priv->reg_base))
+		return PTR_ERR(priv->reg_base);
+
+	ret = dev_read_u32_index(dev, "reg", 1, &reg);
+	if (ret) {
+		dev_err(dev, "failed to read reg property (ret = %d)\n", ret);
+		return ret;
+	}
+
+	phy_cfgs = (const struct rockchip_usb3phy_port_cfg *)
+					dev_get_driver_data(dev);
+	if (!phy_cfgs)
+		return -EINVAL;
+
+	/* find out a proper config which can be matched with dt. */
+	index = 0;
+	while (phy_cfgs[index].reg) {
+		if (phy_cfgs[index].reg == reg) {
+			priv->port_cfgs = &phy_cfgs[index];
+			break;
+		}
+
+		++index;
+	}
+
+	if (!priv->port_cfgs) {
+		dev_err(dev, "failed find proper phy-cfg\n");
+		return -EINVAL;
+	}
+
+	ret = rockchip_tcphy_parse_dt(dev);
+	if (ret)
+		return ret;
+
+	rockchip_tcphy_pre_init(dev);
+
+	return 0;
+}
+
+static int rockchip_tcphy_bind(struct udevice *dev)
+{
+	struct udevice *tcphy_dev;
+	ofnode node;
+	const char *name;
+	int ret = 0;
+
+	dev_for_each_subnode(node, dev) {
+		if (!ofnode_valid(node)) {
+			dev_info(dev, "subnode %s not found\n", dev->name);
+			return -ENXIO;
+		}
+
+		name = ofnode_get_name(node);
+		dev_dbg(dev, "subnode %s\n", name);
+
+		if (!strcasecmp(name, "dp-port")) {
+			dev_dbg(dev, "Warning: dp-port not supported yet!\n");
+			continue;
+		} else if (!strcasecmp(name, "usb3-port")) {
+			ret = device_bind_driver_to_node(dev,
+							 "rockchip_tcphy_usb3_port",
+							 name, node, &tcphy_dev);
+			if (ret) {
+				dev_err(dev,
+					"'%s' cannot bind 'rockchip_tcphy_usb3_port'\n",
+					name);
+				return ret;
+			}
+		}
+	}
+
+	return ret;
+}
+
+static const struct rockchip_usb3phy_port_cfg rk3399_typec_phy_cfgs[] = {
+	{
+		.reg			= 0xff7c0000,
+		.typec_conn_dir		= { 0xe580, 0, 16 },
+		.usb3tousb2_en		= { 0xe580, 3, 19 },
+		.external_psm		= { 0xe588, 14, 30 },
+		.pipe_status		= { 0xe5c0, 0, 0 },
+		.usb3_host_disable	= { 0x2434, 0, 16 },
+		.usb3_host_port		= { 0x2434, 12, 28 },
+		.uphy_dp_sel		= { 0x6268, 19, 19 },
+	},
+	{
+		.reg			= 0xff800000,
+		.typec_conn_dir		= { 0xe58c, 0, 16 },
+		.usb3tousb2_en		= { 0xe58c, 3, 19 },
+		.external_psm		= { 0xe594, 14, 30 },
+		.pipe_status		= { 0xe5c0, 16, 16 },
+		.usb3_host_disable	= { 0x2444, 0, 16 },
+		.usb3_host_port		= { 0x2444, 12, 28 },
+		.uphy_dp_sel		= { 0x6268, 3, 19 },
+	},
+	{ /* sentinel */ }
+};
+
+static const struct udevice_id rockchip_typec_phy_ids[] = {
+	{
+		.compatible = "rockchip,rk3399-typec-phy",
+		.data = (ulong)&rk3399_typec_phy_cfgs,
+	},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(rockchip_tcphy_usb3_port) = {
+	.name		= "rockchip_tcphy_usb3_port",
+	.id		= UCLASS_PHY,
+	.ops		= &rockchip_tcphy_usb3_ops,
+};
+
+U_BOOT_DRIVER(rockchip_typec_phy) = {
+	.name	= "rockchip_typec_phy",
+	.id	= UCLASS_PHY,
+	.of_match = rockchip_typec_phy_ids,
+	.probe = rockchip_tcphy_probe,
+	.bind = rockchip_tcphy_bind,
+	.priv_auto_alloc_size = sizeof(struct rockchip_tcphy),
+};
-- 
2.17.1

Re: [PATCH v5 06/16] phy: rockchip: Add Rockchip USB TypeC PHY driver

[Kever Yang]

On 2020/5/13 下午3:15, Frank Wang wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Add USB TYPEC PHY driver for rockchip platform.
>
> Referenced from Linux TypeC PHY driver, currently
> supporting usb3-port and dp-port need to add it
> in the future.
>
> Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/phy/rockchip/Kconfig              |   7 +
>   drivers/phy/rockchip/Makefile             |   1 +
>   drivers/phy/rockchip/phy-rockchip-typec.c | 796 ++++++++++++++++++++++
>   3 files changed, 804 insertions(+)
>   create mode 100644 drivers/phy/rockchip/phy-rockchip-typec.c
>
> diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
> index d73ac695e1..84cc7c876d 100644
> --- a/drivers/phy/rockchip/Kconfig
> +++ b/drivers/phy/rockchip/Kconfig
> @@ -11,4 +11,11 @@ config PHY_ROCKCHIP_INNO_USB2
>   	help
>   	  Support for Rockchip USB2.0 PHY with Innosilicon IP block.
>   
> +config PHY_ROCKCHIP_TYPEC
> +	bool "Rockchip TYPEC PHY Driver"
> +	depends on ARCH_ROCKCHIP
> +	select PHY
> +	help
> +	  Enable this to support the Rockchip USB TYPEC PHY.
> +
>   endmenu
> diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
> index 9b0cbc6acf..95b2f8a3c0 100644
> --- a/drivers/phy/rockchip/Makefile
> +++ b/drivers/phy/rockchip/Makefile
> @@ -4,3 +4,4 @@
>   #
>   
>   obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
> +obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)	+= phy-rockchip-typec.o
> diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
> new file mode 100644
> index 0000000000..c9c8e1c542
> --- /dev/null
> +++ b/drivers/phy/rockchip/phy-rockchip-typec.c
> @@ -0,0 +1,796 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * ROCKCHIP Type-C PHY driver.
> + *
> + * Copyright (C) 2020 Amarula Solutions(India)
> + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
> + * Author: Chris Zhong <zyw@rock-chips.com>
> + *         Kever Yang <kever.yang@rock-chips.com>
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <dm/device_compat.h>
> +#include <dm/lists.h>
> +#include <generic-phy.h>
> +#include <reset.h>
> +#include <syscon.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <linux/iopoll.h>
> +#include <asm/arch-rockchip/clock.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define usleep_range(a, b) udelay((b))
> +
> +#define CMN_SSM_BANDGAP			(0x21 << 2)
> +#define CMN_SSM_BIAS			(0x22 << 2)
> +#define CMN_PLLSM0_PLLEN		(0x29 << 2)
> +#define CMN_PLLSM0_PLLPRE		(0x2a << 2)
> +#define CMN_PLLSM0_PLLVREF		(0x2b << 2)
> +#define CMN_PLLSM0_PLLLOCK		(0x2c << 2)
> +#define CMN_PLLSM1_PLLEN		(0x31 << 2)
> +#define CMN_PLLSM1_PLLPRE		(0x32 << 2)
> +#define CMN_PLLSM1_PLLVREF		(0x33 << 2)
> +#define CMN_PLLSM1_PLLLOCK		(0x34 << 2)
> +#define CMN_PLLSM1_USER_DEF_CTRL	(0x37 << 2)
> +#define CMN_ICAL_OVRD			(0xc1 << 2)
> +#define CMN_PLL0_VCOCAL_OVRD		(0x83 << 2)
> +#define CMN_PLL0_VCOCAL_INIT		(0x84 << 2)
> +#define CMN_PLL0_VCOCAL_ITER		(0x85 << 2)
> +#define CMN_PLL0_LOCK_REFCNT_START	(0x90 << 2)
> +#define CMN_PLL0_LOCK_PLLCNT_START	(0x92 << 2)
> +#define CMN_PLL0_LOCK_PLLCNT_THR	(0x93 << 2)
> +#define CMN_PLL0_INTDIV			(0x94 << 2)
> +#define CMN_PLL0_FRACDIV		(0x95 << 2)
> +#define CMN_PLL0_HIGH_THR		(0x96 << 2)
> +#define CMN_PLL0_DSM_DIAG		(0x97 << 2)
> +#define CMN_PLL0_SS_CTRL1		(0x98 << 2)
> +#define CMN_PLL0_SS_CTRL2		(0x99 << 2)
> +#define CMN_PLL1_VCOCAL_START		(0xa1 << 2)
> +#define CMN_PLL1_VCOCAL_OVRD		(0xa3 << 2)
> +#define CMN_PLL1_VCOCAL_INIT		(0xa4 << 2)
> +#define CMN_PLL1_VCOCAL_ITER		(0xa5 << 2)
> +#define CMN_PLL1_LOCK_REFCNT_START	(0xb0 << 2)
> +#define CMN_PLL1_LOCK_PLLCNT_START	(0xb2 << 2)
> +#define CMN_PLL1_LOCK_PLLCNT_THR	(0xb3 << 2)
> +#define CMN_PLL1_INTDIV			(0xb4 << 2)
> +#define CMN_PLL1_FRACDIV		(0xb5 << 2)
> +#define CMN_PLL1_HIGH_THR		(0xb6 << 2)
> +#define CMN_PLL1_DSM_DIAG		(0xb7 << 2)
> +#define CMN_PLL1_SS_CTRL1		(0xb8 << 2)
> +#define CMN_PLL1_SS_CTRL2		(0xb9 << 2)
> +#define CMN_RXCAL_OVRD			(0xd1 << 2)
> +
> +#define CMN_TXPUCAL_CTRL		(0xe0 << 2)
> +#define CMN_TXPUCAL_OVRD		(0xe1 << 2)
> +#define CMN_TXPDCAL_CTRL		(0xf0 << 2)
> +#define CMN_TXPDCAL_OVRD		(0xf1 << 2)
> +
> +/* For CMN_TXPUCAL_CTRL, CMN_TXPDCAL_CTRL */
> +#define CMN_TXPXCAL_START		BIT(15)
> +#define CMN_TXPXCAL_DONE		BIT(14)
> +#define CMN_TXPXCAL_NO_RESPONSE		BIT(13)
> +#define CMN_TXPXCAL_CURRENT_RESPONSE	BIT(12)
> +
> +#define CMN_TXPU_ADJ_CTRL		(0x108 << 2)
> +#define CMN_TXPD_ADJ_CTRL		(0x10c << 2)
> +
> +/*
> + * For CMN_TXPUCAL_CTRL, CMN_TXPDCAL_CTRL,
> + *     CMN_TXPU_ADJ_CTRL, CMN_TXPDCAL_CTRL
> + *
> + * NOTE: some of these registers are documented to be 2's complement
> + * signed numbers, but then documented to be always positive.  Weird.
> + * In such a case, using CMN_CALIB_CODE_POS() avoids the unnecessary
> + * sign extension.
> + */
> +#define CMN_CALIB_CODE_WIDTH	7
> +#define CMN_CALIB_CODE_OFFSET	0
> +#define CMN_CALIB_CODE_MASK	GENMASK(CMN_CALIB_CODE_WIDTH, 0)
> +#define CMN_CALIB_CODE(x)	\
> +	sign_extend32((x) >> CMN_CALIB_CODE_OFFSET, CMN_CALIB_CODE_WIDTH)
> +
> +#define CMN_CALIB_CODE_POS_MASK	GENMASK(CMN_CALIB_CODE_WIDTH - 1, 0)
> +#define CMN_CALIB_CODE_POS(x)	\
> +	(((x) >> CMN_CALIB_CODE_OFFSET) & CMN_CALIB_CODE_POS_MASK)
> +
> +#define CMN_DIAG_PLL0_FBH_OVRD		(0x1c0 << 2)
> +#define CMN_DIAG_PLL0_FBL_OVRD		(0x1c1 << 2)
> +#define CMN_DIAG_PLL0_OVRD		(0x1c2 << 2)
> +#define CMN_DIAG_PLL0_V2I_TUNE		(0x1c5 << 2)
> +#define CMN_DIAG_PLL0_CP_TUNE		(0x1c6 << 2)
> +#define CMN_DIAG_PLL0_LF_PROG		(0x1c7 << 2)
> +#define CMN_DIAG_PLL1_FBH_OVRD		(0x1d0 << 2)
> +#define CMN_DIAG_PLL1_FBL_OVRD		(0x1d1 << 2)
> +#define CMN_DIAG_PLL1_OVRD		(0x1d2 << 2)
> +#define CMN_DIAG_PLL1_V2I_TUNE		(0x1d5 << 2)
> +#define CMN_DIAG_PLL1_CP_TUNE		(0x1d6 << 2)
> +#define CMN_DIAG_PLL1_LF_PROG		(0x1d7 << 2)
> +#define CMN_DIAG_PLL1_PTATIS_TUNE1	(0x1d8 << 2)
> +#define CMN_DIAG_PLL1_PTATIS_TUNE2	(0x1d9 << 2)
> +#define CMN_DIAG_PLL1_INCLK_CTRL	(0x1da << 2)
> +#define CMN_DIAG_HSCLK_SEL		(0x1e0 << 2)
> +
> +#define XCVR_PSM_RCTRL(n)		((0x4001 | ((n) << 9)) << 2)
> +#define XCVR_PSM_CAL_TMR(n)		((0x4002 | ((n) << 9)) << 2)
> +#define XCVR_PSM_A0IN_TMR(n)		((0x4003 | ((n) << 9)) << 2)
> +#define TX_TXCC_CAL_SCLR_MULT(n)	((0x4047 | ((n) << 9)) << 2)
> +#define TX_TXCC_CPOST_MULT_00(n)	((0x404c | ((n) << 9)) << 2)
> +#define TX_TXCC_CPOST_MULT_01(n)	((0x404d | ((n) << 9)) << 2)
> +#define TX_TXCC_CPOST_MULT_10(n)	((0x404e | ((n) << 9)) << 2)
> +#define TX_TXCC_CPOST_MULT_11(n)	((0x404f | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_000(n)	((0x4050 | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_001(n)	((0x4051 | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_010(n)	((0x4052 | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_011(n)	((0x4053 | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_100(n)	((0x4054 | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_101(n)	((0x4055 | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_110(n)	((0x4056 | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_111(n)	((0x4057 | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNLS_MULT_000(n)	((0x4058 | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNLS_MULT_001(n)	((0x4059 | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNLS_MULT_010(n)	((0x405a | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNLS_MULT_011(n)	((0x405b | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNLS_MULT_100(n)	((0x405c | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNLS_MULT_101(n)	((0x405d | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNLS_MULT_110(n)	((0x405e | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNLS_MULT_111(n)	((0x405f | ((n) << 9)) << 2)
> +
> +#define XCVR_DIAG_PLLDRC_CTRL(n)	((0x40e0 | ((n) << 9)) << 2)
> +#define XCVR_DIAG_BIDI_CTRL(n)		((0x40e8 | ((n) << 9)) << 2)
> +#define XCVR_DIAG_LANE_FCM_EN_MGN(n)	((0x40f2 | ((n) << 9)) << 2)
> +#define TX_PSC_A0(n)			((0x4100 | ((n) << 9)) << 2)
> +#define TX_PSC_A1(n)			((0x4101 | ((n) << 9)) << 2)
> +#define TX_PSC_A2(n)			((0x4102 | ((n) << 9)) << 2)
> +#define TX_PSC_A3(n)			((0x4103 | ((n) << 9)) << 2)
> +#define TX_RCVDET_CTRL(n)		((0x4120 | ((n) << 9)) << 2)
> +#define TX_RCVDET_EN_TMR(n)		((0x4122 | ((n) << 9)) << 2)
> +#define TX_RCVDET_ST_TMR(n)		((0x4123 | ((n) << 9)) << 2)
> +#define TX_DIAG_TX_DRV(n)		((0x41e1 | ((n) << 9)) << 2)
> +#define TX_DIAG_BGREF_PREDRV_DELAY	(0x41e7 << 2)
> +
> +/* Use this for "n" in macros like "_MULT_XXX" to target the aux channel */
> +#define AUX_CH_LANE			8
> +
> +#define TX_ANA_CTRL_REG_1		(0x5020 << 2)
> +
> +#define TXDA_DP_AUX_EN			BIT(15)
> +#define AUXDA_SE_EN			BIT(14)
> +#define TXDA_CAL_LATCH_EN		BIT(13)
> +#define AUXDA_POLARITY			BIT(12)
> +#define TXDA_DRV_POWER_ISOLATION_EN	BIT(11)
> +#define TXDA_DRV_POWER_EN_PH_2_N	BIT(10)
> +#define TXDA_DRV_POWER_EN_PH_1_N	BIT(9)
> +#define TXDA_BGREF_EN			BIT(8)
> +#define TXDA_DRV_LDO_EN			BIT(7)
> +#define TXDA_DECAP_EN_DEL		BIT(6)
> +#define TXDA_DECAP_EN			BIT(5)
> +#define TXDA_UPHY_SUPPLY_EN_DEL		BIT(4)
> +#define TXDA_UPHY_SUPPLY_EN		BIT(3)
> +#define TXDA_LOW_LEAKAGE_EN		BIT(2)
> +#define TXDA_DRV_IDLE_LOWI_EN		BIT(1)
> +#define TXDA_DRV_CMN_MODE_EN		BIT(0)
> +
> +#define TX_ANA_CTRL_REG_2		(0x5021 << 2)
> +
> +#define AUXDA_DEBOUNCING_CLK		BIT(15)
> +#define TXDA_LPBK_RECOVERED_CLK_EN	BIT(14)
> +#define TXDA_LPBK_ISI_GEN_EN		BIT(13)
> +#define TXDA_LPBK_SERIAL_EN		BIT(12)
> +#define TXDA_LPBK_LINE_EN		BIT(11)
> +#define TXDA_DRV_LDO_REDC_SINKIQ	BIT(10)
> +#define XCVR_DECAP_EN_DEL		BIT(9)
> +#define XCVR_DECAP_EN			BIT(8)
> +#define TXDA_MPHY_ENABLE_HS_NT		BIT(7)
> +#define TXDA_MPHY_SA_MODE		BIT(6)
> +#define TXDA_DRV_LDO_RBYR_FB_EN		BIT(5)
> +#define TXDA_DRV_RST_PULL_DOWN		BIT(4)
> +#define TXDA_DRV_LDO_BG_FB_EN		BIT(3)
> +#define TXDA_DRV_LDO_BG_REF_EN		BIT(2)
> +#define TXDA_DRV_PREDRV_EN_DEL		BIT(1)
> +#define TXDA_DRV_PREDRV_EN		BIT(0)
> +
> +#define TXDA_COEFF_CALC_CTRL		(0x5022 << 2)
> +
> +#define TX_HIGH_Z			BIT(6)
> +#define TX_VMARGIN_OFFSET		3
> +#define TX_VMARGIN_MASK			0x7
> +#define LOW_POWER_SWING_EN		BIT(2)
> +#define TX_FCM_DRV_MAIN_EN		BIT(1)
> +#define TX_FCM_FULL_MARGIN		BIT(0)
> +
> +#define TX_DIG_CTRL_REG_2		(0x5024 << 2)
> +
> +#define TX_HIGH_Z_TM_EN			BIT(15)
> +#define TX_RESCAL_CODE_OFFSET		0
> +#define TX_RESCAL_CODE_MASK		0x3f
> +
> +#define TXDA_CYA_AUXDA_CYA		(0x5025 << 2)
> +#define TX_ANA_CTRL_REG_3		(0x5026 << 2)
> +#define TX_ANA_CTRL_REG_4		(0x5027 << 2)
> +#define TX_ANA_CTRL_REG_5		(0x5029 << 2)
> +
> +#define RX_PSC_A0(n)			((0x8000 | ((n) << 9)) << 2)
> +#define RX_PSC_A1(n)			((0x8001 | ((n) << 9)) << 2)
> +#define RX_PSC_A2(n)			((0x8002 | ((n) << 9)) << 2)
> +#define RX_PSC_A3(n)			((0x8003 | ((n) << 9)) << 2)
> +#define RX_PSC_CAL(n)			((0x8006 | ((n) << 9)) << 2)
> +#define RX_PSC_RDY(n)			((0x8007 | ((n) << 9)) << 2)
> +#define RX_IQPI_ILL_CAL_OVRD		(0x8023 << 2)
> +#define RX_EPI_ILL_CAL_OVRD		(0x8033 << 2)
> +#define RX_SDCAL0_OVRD			(0x8041 << 2)
> +#define RX_SDCAL1_OVRD			(0x8049 << 2)
> +#define RX_SLC_INIT			(0x806d << 2)
> +#define RX_SLC_RUN			(0x806e << 2)
> +#define RX_CDRLF_CNFG2			(0x8081 << 2)
> +#define RX_SIGDET_HL_FILT_TMR(n)	((0x8090 | ((n) << 9)) << 2)
> +#define RX_SLC_IOP0_OVRD		(0x8101 << 2)
> +#define RX_SLC_IOP1_OVRD		(0x8105 << 2)
> +#define RX_SLC_QOP0_OVRD		(0x8109 << 2)
> +#define RX_SLC_QOP1_OVRD		(0x810d << 2)
> +#define RX_SLC_EOP0_OVRD		(0x8111 << 2)
> +#define RX_SLC_EOP1_OVRD		(0x8115 << 2)
> +#define RX_SLC_ION0_OVRD		(0x8119 << 2)
> +#define RX_SLC_ION1_OVRD		(0x811d << 2)
> +#define RX_SLC_QON0_OVRD		(0x8121 << 2)
> +#define RX_SLC_QON1_OVRD		(0x8125 << 2)
> +#define RX_SLC_EON0_OVRD		(0x8129 << 2)
> +#define RX_SLC_EON1_OVRD		(0x812d << 2)
> +#define RX_SLC_IEP0_OVRD		(0x8131 << 2)
> +#define RX_SLC_IEP1_OVRD		(0x8135 << 2)
> +#define RX_SLC_QEP0_OVRD		(0x8139 << 2)
> +#define RX_SLC_QEP1_OVRD		(0x813d << 2)
> +#define RX_SLC_EEP0_OVRD		(0x8141 << 2)
> +#define RX_SLC_EEP1_OVRD		(0x8145 << 2)
> +#define RX_SLC_IEN0_OVRD		(0x8149 << 2)
> +#define RX_SLC_IEN1_OVRD		(0x814d << 2)
> +#define RX_SLC_QEN0_OVRD		(0x8151 << 2)
> +#define RX_SLC_QEN1_OVRD		(0x8155 << 2)
> +#define RX_SLC_EEN0_OVRD		(0x8159 << 2)
> +#define RX_SLC_EEN1_OVRD		(0x815d << 2)
> +#define RX_REE_CTRL_DATA_MASK(n)	((0x81bb | ((n) << 9)) << 2)
> +#define RX_DIAG_SIGDET_TUNE(n)		((0x81dc | ((n) << 9)) << 2)
> +#define RX_DIAG_SC2C_DELAY		(0x81e1 << 2)
> +
> +#define PMA_LANE_CFG			(0xc000 << 2)
> +#define PIPE_CMN_CTRL1			(0xc001 << 2)
> +#define PIPE_CMN_CTRL2			(0xc002 << 2)
> +#define PIPE_COM_LOCK_CFG1		(0xc003 << 2)
> +#define PIPE_COM_LOCK_CFG2		(0xc004 << 2)
> +#define PIPE_RCV_DET_INH		(0xc005 << 2)
> +#define DP_MODE_CTL			(0xc008 << 2)
> +#define DP_CLK_CTL			(0xc009 << 2)
> +#define STS				(0xc00F << 2)
> +#define PHY_ISO_CMN_CTRL		(0xc010 << 2)
> +#define PHY_DP_TX_CTL			(0xc408 << 2)
> +#define PMA_CMN_CTRL1			(0xc800 << 2)
> +#define PHY_PMA_ISO_CMN_CTRL		(0xc810 << 2)
> +#define PHY_ISOLATION_CTRL		(0xc81f << 2)
> +#define PHY_PMA_ISO_XCVR_CTRL(n)	((0xcc11 | ((n) << 6)) << 2)
> +#define PHY_PMA_ISO_LINK_MODE(n)	((0xcc12 | ((n) << 6)) << 2)
> +#define PHY_PMA_ISO_PWRST_CTRL(n)	((0xcc13 | ((n) << 6)) << 2)
> +#define PHY_PMA_ISO_TX_DATA_LO(n)	((0xcc14 | ((n) << 6)) << 2)
> +#define PHY_PMA_ISO_TX_DATA_HI(n)	((0xcc15 | ((n) << 6)) << 2)
> +#define PHY_PMA_ISO_RX_DATA_LO(n)	((0xcc16 | ((n) << 6)) << 2)
> +#define PHY_PMA_ISO_RX_DATA_HI(n)	((0xcc17 | ((n) << 6)) << 2)
> +#define TX_BIST_CTRL(n)			((0x4140 | ((n) << 9)) << 2)
> +#define TX_BIST_UDDWR(n)		((0x4141 | ((n) << 9)) << 2)
> +
> +/*
> + * Selects which PLL clock will be driven on the analog high speed
> + * clock 0: PLL 0 div 1
> + * clock 1: PLL 1 div 2
> + */
> +#define CLK_PLL_CONFIG			0X30
> +#define CLK_PLL_MASK			0x33
> +
> +#define CMN_READY			BIT(0)
> +
> +#define DP_PLL_CLOCK_ENABLE		BIT(2)
> +#define DP_PLL_ENABLE			BIT(0)
> +#define DP_PLL_DATA_RATE_RBR		((2 << 12) | (4 << 8))
> +#define DP_PLL_DATA_RATE_HBR		((2 << 12) | (4 << 8))
> +#define DP_PLL_DATA_RATE_HBR2		((1 << 12) | (2 << 8))
> +
> +#define DP_MODE_A0			BIT(4)
> +#define DP_MODE_A2			BIT(6)
> +#define DP_MODE_ENTER_A0		0xc101
> +#define DP_MODE_ENTER_A2		0xc104
> +
> +#define PHY_MODE_SET_TIMEOUT		100000
> +
> +#define PIN_ASSIGN_C_E			0x51d9
> +#define PIN_ASSIGN_D_F			0x5100
> +
> +#define MODE_DISCONNECT			0
> +#define MODE_UFP_USB			BIT(0)
> +#define MODE_DFP_USB			BIT(1)
> +#define MODE_DFP_DP			BIT(2)
> +
> +struct usb3phy_reg {
> +	u32 offset;
> +	u32 enable_bit;
> +	u32 write_enable;
> +};
> +
> +/**
> + * struct rockchip_usb3phy_port_cfg: usb3-phy port configuration.
> + * @reg: the base address for usb3-phy config.
> + * @typec_conn_dir: the register of type-c connector direction.
> + * @usb3tousb2_en: the register of type-c force usb2 to usb2 enable.
> + * @external_psm: the register of type-c phy external psm clock.
> + * @pipe_status: the register of type-c phy pipe status.
> + * @usb3_host_disable: the register of type-c usb3 host disable.
> + * @usb3_host_port: the register of type-c usb3 host port.
> + * @uphy_dp_sel: the register of type-c phy DP select control.
> + */
> +struct rockchip_usb3phy_port_cfg {
> +	unsigned int reg;
> +	struct usb3phy_reg typec_conn_dir;
> +	struct usb3phy_reg usb3tousb2_en;
> +	struct usb3phy_reg external_psm;
> +	struct usb3phy_reg pipe_status;
> +	struct usb3phy_reg usb3_host_disable;
> +	struct usb3phy_reg usb3_host_port;
> +	struct usb3phy_reg uphy_dp_sel;
> +};
> +
> +struct rockchip_tcphy {
> +	void __iomem *reg_base;
> +	void __iomem *grf_base;
> +	struct clk clk_core;
> +	struct clk clk_ref;
> +	struct reset_ctl uphy_rst;
> +	struct reset_ctl pipe_rst;
> +	struct reset_ctl tcphy_rst;
> +	const struct rockchip_usb3phy_port_cfg *port_cfgs;
> +	u8 mode;
> +};
> +
> +struct phy_reg {
> +	u16 value;
> +	u32 addr;
> +};
> +
> +static struct phy_reg usb3_pll_cfg[] = {
> +	{ 0xf0,		CMN_PLL0_VCOCAL_INIT },
> +	{ 0x18,		CMN_PLL0_VCOCAL_ITER },
> +	{ 0xd0,		CMN_PLL0_INTDIV },
> +	{ 0x4a4a,	CMN_PLL0_FRACDIV },
> +	{ 0x34,		CMN_PLL0_HIGH_THR },
> +	{ 0x1ee,	CMN_PLL0_SS_CTRL1 },
> +	{ 0x7f03,	CMN_PLL0_SS_CTRL2 },
> +	{ 0x20,		CMN_PLL0_DSM_DIAG },
> +	{ 0,		CMN_DIAG_PLL0_OVRD },
> +	{ 0,		CMN_DIAG_PLL0_FBH_OVRD },
> +	{ 0,		CMN_DIAG_PLL0_FBL_OVRD },
> +	{ 0x7,		CMN_DIAG_PLL0_V2I_TUNE },
> +	{ 0x45,		CMN_DIAG_PLL0_CP_TUNE },
> +	{ 0x8,		CMN_DIAG_PLL0_LF_PROG },
> +};
> +
> +static inline int property_enable(struct rockchip_tcphy *priv,
> +				  const struct usb3phy_reg *reg, bool en)
> +{
> +	u32 mask = 1 << reg->write_enable;
> +	u32 val = en << reg->enable_bit;
> +
> +	return writel(val | mask, priv->grf_base + reg->offset);
> +}
> +
> +static int rockchip_tcphy_get_mode(struct rockchip_tcphy *priv)
> +{
> +	/* TODO: Add proper logic to find DP or USB3 mode */
> +	return MODE_DFP_USB | MODE_UFP_USB;
> +}
> +
> +static void rockchip_tcphy_cfg_24m(struct rockchip_tcphy *priv)
> +{
> +	u32 i, rdata;
> +
> +	/*
> +	 * cmn_ref_clk_sel = 3, select the 24Mhz for clk parent
> +	 * cmn_psm_clk_dig_div = 2, set the clk division to 2
> +	 */
> +	writel(0x830, priv->reg_base + PMA_CMN_CTRL1);
> +	for (i = 0; i < 4; i++) {
> +		/*
> +		 * The following PHY configuration assumes a 24 MHz reference
> +		 * clock.
> +		 */
> +		writel(0x90, priv->reg_base + XCVR_DIAG_LANE_FCM_EN_MGN(i));
> +		writel(0x960, priv->reg_base + TX_RCVDET_EN_TMR(i));
> +		writel(0x30, priv->reg_base + TX_RCVDET_ST_TMR(i));
> +	}
> +
> +	rdata = readl(priv->reg_base + CMN_DIAG_HSCLK_SEL);
> +	rdata &= ~CLK_PLL_MASK;
> +	rdata |= CLK_PLL_CONFIG;
> +	writel(rdata, priv->reg_base + CMN_DIAG_HSCLK_SEL);
> +}
> +
> +static void rockchip_tcphy_cfg_usb3_pll(struct rockchip_tcphy *priv)
> +{
> +	u32 i;
> +
> +	/* load the configuration of PLL0 */
> +	for (i = 0; i < ARRAY_SIZE(usb3_pll_cfg); i++)
> +		writel(usb3_pll_cfg[i].value,
> +		       priv->reg_base + usb3_pll_cfg[i].addr);
> +}
> +
> +static void rockchip_tcphy_tx_usb3_cfg_lane(struct rockchip_tcphy *priv,
> +					    u32 lane)
> +{
> +	writel(0x7799, priv->reg_base + TX_PSC_A0(lane));
> +	writel(0x7798, priv->reg_base + TX_PSC_A1(lane));
> +	writel(0x5098, priv->reg_base + TX_PSC_A2(lane));
> +	writel(0x5098, priv->reg_base + TX_PSC_A3(lane));
> +	writel(0, priv->reg_base + TX_TXCC_MGNFS_MULT_000(lane));
> +	writel(0xbf, priv->reg_base + XCVR_DIAG_BIDI_CTRL(lane));
> +}
> +
> +static void rockchip_tcphy_rx_usb3_cfg_lane(struct rockchip_tcphy *priv,
> +					    u32 lane)
> +{
> +	writel(0xa6fd, priv->reg_base + RX_PSC_A0(lane));
> +	writel(0xa6fd, priv->reg_base + RX_PSC_A1(lane));
> +	writel(0xa410, priv->reg_base + RX_PSC_A2(lane));
> +	writel(0x2410, priv->reg_base + RX_PSC_A3(lane));
> +	writel(0x23ff, priv->reg_base + RX_PSC_CAL(lane));
> +	writel(0x13, priv->reg_base + RX_SIGDET_HL_FILT_TMR(lane));
> +	writel(0x03e7, priv->reg_base + RX_REE_CTRL_DATA_MASK(lane));
> +	writel(0x1004, priv->reg_base + RX_DIAG_SIGDET_TUNE(lane));
> +	writel(0x2010, priv->reg_base + RX_PSC_RDY(lane));
> +	writel(0xfb, priv->reg_base + XCVR_DIAG_BIDI_CTRL(lane));
> +}
> +
> +static int rockchip_tcphy_init(struct rockchip_tcphy *priv)
> +{
> +	const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
> +	u32 val;
> +	int ret;
> +
> +	ret = clk_enable(&priv->clk_core);
> +	if (ret) {
> +		dev_err(phy->dev, "failed to enable core clk (ret=%d)\n", ret);
> +		return ret;
> +	}
> +
> +	ret = clk_enable(&priv->clk_ref);
> +	if (ret) {
> +		dev_err(phy->dev, "failed to enable ref clk (ret=%d)\n", ret);
> +		goto err_clk_core;
> +	}
> +
> +	ret = reset_deassert(&priv->tcphy_rst);
> +	if (ret) {
> +		dev_err(phy->dev, "failed to deassert uphy-tcphy reset (ret=%d)\n",
> +			ret);
> +		goto err_clk_ref;
> +	}
> +
> +	property_enable(priv, &cfg->typec_conn_dir, 0);
> +
> +	rockchip_tcphy_cfg_24m(priv);
> +
> +	rockchip_tcphy_cfg_usb3_pll(priv);
> +
> +	rockchip_tcphy_tx_usb3_cfg_lane(priv, 0);
> +	rockchip_tcphy_rx_usb3_cfg_lane(priv, 1);
> +
> +	ret = reset_deassert(&priv->uphy_rst);
> +	if (ret) {
> +		dev_err(phy->dev, "failed to deassert uphy rst (ret=%d)\n",
> +			ret);
> +		goto err_tcphy_rst;
> +	}
> +
> +	ret = readl_poll_sleep_timeout(priv->reg_base + PMA_CMN_CTRL1,
> +				       val, val & CMN_READY, 10,
> +				       PHY_MODE_SET_TIMEOUT);
> +	if (ret < 0) {
> +		dev_err(phy->dev, "PMA Timeout!\n");
> +		ret = -ETIMEDOUT;
> +		goto err_uphy_rst;
> +	}
> +
> +	ret = reset_deassert(&priv->pipe_rst);
> +	if (ret) {
> +		dev_err(phy->dev, "failed to deassert pipe rst (ret=%d)\n",
> +			ret);
> +		goto err_uphy_rst;
> +	}
> +
> +	return 0;
> +
> +err_uphy_rst:
> +	reset_assert(&priv->uphy_rst);
> +err_tcphy_rst:
> +	reset_assert(&priv->tcphy_rst);
> +err_clk_ref:
> +	clk_disable(&priv->clk_ref);
> +err_clk_core:
> +	clk_disable(&priv->clk_core);
> +	return ret;
> +}
> +
> +static void rockchip_tcphy_exit(struct rockchip_tcphy *priv)
> +{
> +	reset_assert(&priv->tcphy_rst);
> +	reset_assert(&priv->uphy_rst);
> +	reset_assert(&priv->pipe_rst);
> +	clk_disable(&priv->clk_core);
> +	clk_disable(&priv->clk_ref);
> +}
> +
> +static int tcphy_cfg_usb3_to_usb2_only(struct rockchip_tcphy *priv,
> +				       bool value)
> +{
> +	const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
> +
> +	property_enable(priv, &cfg->usb3tousb2_en, value);
> +	property_enable(priv, &cfg->usb3_host_disable, value);
> +	property_enable(priv, &cfg->usb3_host_port, !value);
> +
> +	return 0;
> +}
> +
> +static int rockchip_usb3_phy_power_on(struct phy *phy)
> +{
> +	struct udevice *parent = dev_get_parent(phy->dev);
> +	struct rockchip_tcphy *priv = dev_get_priv(parent);
> +	const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
> +	const struct usb3phy_reg *reg = &cfg->pipe_status;
> +	int timeout, new_mode;
> +	u32 val;
> +	int ret;
> +
> +	new_mode = rockchip_tcphy_get_mode(priv);
> +	if (new_mode < 0) {
> +		dev_err(phy->dev, "invalid mode %d\n", new_mode);
> +		return new_mode;
> +	}
> +
> +	if (priv->mode == new_mode)
> +		return 0;
> +
> +	if (priv->mode == MODE_DISCONNECT) {
> +		ret = rockchip_tcphy_init(priv);
> +		if (ret) {
> +			dev_err(dev, "failed to init tcphy (ret=%d)\n", ret);
> +			return ret;
> +		}
> +	}
> +
> +	/* wait TCPHY for pipe ready */
> +	for (timeout = 0; timeout < 100; timeout++) {
> +		val = readl(priv->grf_base + reg->offset);
> +		if (!(val & BIT(reg->enable_bit))) {
> +			priv->mode |= new_mode & (MODE_DFP_USB | MODE_UFP_USB);
> +
> +			/* enable usb3 host */
> +			tcphy_cfg_usb3_to_usb2_only(priv, false);
> +			return 0;
> +		}
> +		usleep_range(10, 20);
> +	}
> +
> +	if (priv->mode == MODE_DISCONNECT)
> +		rockchip_tcphy_exit(priv);
> +
> +	return -ETIMEDOUT;
> +}
> +
> +static int rockchip_usb3_phy_power_off(struct phy *phy)
> +{
> +	struct udevice *parent = dev_get_parent(phy->dev);
> +	struct rockchip_tcphy *priv = dev_get_priv(parent);
> +
> +	tcphy_cfg_usb3_to_usb2_only(priv, false);
> +
> +	if (priv->mode == MODE_DISCONNECT)
> +		goto exit;
> +
> +	priv->mode &= ~(MODE_UFP_USB | MODE_DFP_USB);
> +	if (priv->mode == MODE_DISCONNECT)
> +		rockchip_tcphy_exit(priv);
> +
> +exit:
> +	return 0;
> +}
> +
> +static struct phy_ops rockchip_tcphy_usb3_ops = {
> +	.power_on = rockchip_usb3_phy_power_on,
> +	.power_off = rockchip_usb3_phy_power_off,
> +};
> +
> +static void rockchip_tcphy_pre_init(struct udevice *dev)
> +{
> +	struct rockchip_tcphy *priv = dev_get_priv(dev);
> +	const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
> +
> +	reset_assert(&priv->tcphy_rst);
> +	reset_assert(&priv->uphy_rst);
> +	reset_assert(&priv->pipe_rst);
> +
> +	/* select external psm clock */
> +	property_enable(priv, &cfg->external_psm, 1);
> +	property_enable(priv, &cfg->usb3tousb2_en, 0);
> +
> +	priv->mode = MODE_DISCONNECT;
> +}
> +
> +static int rockchip_tcphy_parse_dt(struct udevice *dev)
> +{
> +	struct rockchip_tcphy *priv = dev_get_priv(dev);
> +	int ret;
> +
> +	priv->grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +	if (IS_ERR(priv->grf_base))
> +		return PTR_ERR(priv->grf_base);
> +
> +	ret = clk_get_by_name(dev, "tcpdcore", &priv->clk_core);
> +	if (ret) {
> +		dev_err(dev, "failed to get tcpdcore clk (ret=%d)\n", ret);
> +		return ret;
> +	}
> +
> +	ret = clk_get_by_name(dev, "tcpdphy-ref", &priv->clk_ref);
> +	if (ret) {
> +		dev_err(dev, "failed to get tcpdphy-ref clk (ret=%d)\n", ret);
> +		return ret;
> +	}
> +
> +	ret = reset_get_by_name(dev, "uphy", &priv->uphy_rst);
> +	if (ret) {
> +		dev_err(dev, "failed to get uphy reset (ret=%d)\n", ret);
> +		return ret;
> +	}
> +
> +	ret = reset_get_by_name(dev, "uphy-pipe", &priv->pipe_rst);
> +	if (ret) {
> +		dev_err(dev, "failed to get uphy-pipe reset (ret=%d)\n", ret);
> +		return ret;
> +	}
> +
> +	ret = reset_get_by_name(dev, "uphy-tcphy", &priv->tcphy_rst);
> +	if (ret) {
> +		dev_err(dev, "failed to get uphy-tcphy reset (ret=%d)\n", ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int rockchip_tcphy_probe(struct udevice *dev)
> +{
> +	struct rockchip_tcphy *priv = dev_get_priv(dev);
> +	const struct rockchip_usb3phy_port_cfg *phy_cfgs;
> +	unsigned int reg;
> +	int index, ret;
> +
> +	priv->reg_base = (void __iomem *)dev_read_addr(dev);
> +	if (IS_ERR(priv->reg_base))
> +		return PTR_ERR(priv->reg_base);
> +
> +	ret = dev_read_u32_index(dev, "reg", 1, &reg);
> +	if (ret) {
> +		dev_err(dev, "failed to read reg property (ret = %d)\n", ret);
> +		return ret;
> +	}
> +
> +	phy_cfgs = (const struct rockchip_usb3phy_port_cfg *)
> +					dev_get_driver_data(dev);
> +	if (!phy_cfgs)
> +		return -EINVAL;
> +
> +	/* find out a proper config which can be matched with dt. */
> +	index = 0;
> +	while (phy_cfgs[index].reg) {
> +		if (phy_cfgs[index].reg == reg) {
> +			priv->port_cfgs = &phy_cfgs[index];
> +			break;
> +		}
> +
> +		++index;
> +	}
> +
> +	if (!priv->port_cfgs) {
> +		dev_err(dev, "failed find proper phy-cfg\n");
> +		return -EINVAL;
> +	}
> +
> +	ret = rockchip_tcphy_parse_dt(dev);
> +	if (ret)
> +		return ret;
> +
> +	rockchip_tcphy_pre_init(dev);
> +
> +	return 0;
> +}
> +
> +static int rockchip_tcphy_bind(struct udevice *dev)
> +{
> +	struct udevice *tcphy_dev;
> +	ofnode node;
> +	const char *name;
> +	int ret = 0;
> +
> +	dev_for_each_subnode(node, dev) {
> +		if (!ofnode_valid(node)) {
> +			dev_info(dev, "subnode %s not found\n", dev->name);
> +			return -ENXIO;
> +		}
> +
> +		name = ofnode_get_name(node);
> +		dev_dbg(dev, "subnode %s\n", name);
> +
> +		if (!strcasecmp(name, "dp-port")) {
> +			dev_dbg(dev, "Warning: dp-port not supported yet!\n");
> +			continue;
> +		} else if (!strcasecmp(name, "usb3-port")) {
> +			ret = device_bind_driver_to_node(dev,
> +							 "rockchip_tcphy_usb3_port",
> +							 name, node, &tcphy_dev);
> +			if (ret) {
> +				dev_err(dev,
> +					"'%s' cannot bind 'rockchip_tcphy_usb3_port'\n",
> +					name);
> +				return ret;
> +			}
> +		}
> +	}
> +
> +	return ret;
> +}
> +
> +static const struct rockchip_usb3phy_port_cfg rk3399_typec_phy_cfgs[] = {
> +	{
> +		.reg			= 0xff7c0000,
> +		.typec_conn_dir		= { 0xe580, 0, 16 },
> +		.usb3tousb2_en		= { 0xe580, 3, 19 },
> +		.external_psm		= { 0xe588, 14, 30 },
> +		.pipe_status		= { 0xe5c0, 0, 0 },
> +		.usb3_host_disable	= { 0x2434, 0, 16 },
> +		.usb3_host_port		= { 0x2434, 12, 28 },
> +		.uphy_dp_sel		= { 0x6268, 19, 19 },
> +	},
> +	{
> +		.reg			= 0xff800000,
> +		.typec_conn_dir		= { 0xe58c, 0, 16 },
> +		.usb3tousb2_en		= { 0xe58c, 3, 19 },
> +		.external_psm		= { 0xe594, 14, 30 },
> +		.pipe_status		= { 0xe5c0, 16, 16 },
> +		.usb3_host_disable	= { 0x2444, 0, 16 },
> +		.usb3_host_port		= { 0x2444, 12, 28 },
> +		.uphy_dp_sel		= { 0x6268, 3, 19 },
> +	},
> +	{ /* sentinel */ }
> +};
> +
> +static const struct udevice_id rockchip_typec_phy_ids[] = {
> +	{
> +		.compatible = "rockchip,rk3399-typec-phy",
> +		.data = (ulong)&rk3399_typec_phy_cfgs,
> +	},
> +	{ /* sentinel */ }
> +};
> +
> +U_BOOT_DRIVER(rockchip_tcphy_usb3_port) = {
> +	.name		= "rockchip_tcphy_usb3_port",
> +	.id		= UCLASS_PHY,
> +	.ops		= &rockchip_tcphy_usb3_ops,
> +};
> +
> +U_BOOT_DRIVER(rockchip_typec_phy) = {
> +	.name	= "rockchip_typec_phy",
> +	.id	= UCLASS_PHY,
> +	.of_match = rockchip_typec_phy_ids,
> +	.probe = rockchip_tcphy_probe,
> +	.bind = rockchip_tcphy_bind,
> +	.priv_auto_alloc_size = sizeof(struct rockchip_tcphy),
> +};

[PATCH v5 06/16] phy: rockchip: Add Rockchip USB TypeC PHY driver

[Kever Yang]

On 2020/5/13 ??3:15, Frank Wang wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Add USB TYPEC PHY driver for rockchip platform.
>
> Referenced from Linux TypeC PHY driver, currently
> supporting usb3-port and dp-port need to add it
> in the future.
>
> Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/phy/rockchip/Kconfig              |   7 +
>   drivers/phy/rockchip/Makefile             |   1 +
>   drivers/phy/rockchip/phy-rockchip-typec.c | 796 ++++++++++++++++++++++
>   3 files changed, 804 insertions(+)
>   create mode 100644 drivers/phy/rockchip/phy-rockchip-typec.c
>
> diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
> index d73ac695e1..84cc7c876d 100644
> --- a/drivers/phy/rockchip/Kconfig
> +++ b/drivers/phy/rockchip/Kconfig
> @@ -11,4 +11,11 @@ config PHY_ROCKCHIP_INNO_USB2
>   	help
>   	  Support for Rockchip USB2.0 PHY with Innosilicon IP block.
>   
> +config PHY_ROCKCHIP_TYPEC
> +	bool "Rockchip TYPEC PHY Driver"
> +	depends on ARCH_ROCKCHIP
> +	select PHY
> +	help
> +	  Enable this to support the Rockchip USB TYPEC PHY.
> +
>   endmenu
> diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
> index 9b0cbc6acf..95b2f8a3c0 100644
> --- a/drivers/phy/rockchip/Makefile
> +++ b/drivers/phy/rockchip/Makefile
> @@ -4,3 +4,4 @@
>   #
>   
>   obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
> +obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)	+= phy-rockchip-typec.o
> diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
> new file mode 100644
> index 0000000000..c9c8e1c542
> --- /dev/null
> +++ b/drivers/phy/rockchip/phy-rockchip-typec.c
> @@ -0,0 +1,796 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * ROCKCHIP Type-C PHY driver.
> + *
> + * Copyright (C) 2020 Amarula Solutions(India)
> + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
> + * Author: Chris Zhong <zyw@rock-chips.com>
> + *         Kever Yang <kever.yang@rock-chips.com>
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <dm/device_compat.h>
> +#include <dm/lists.h>
> +#include <generic-phy.h>
> +#include <reset.h>
> +#include <syscon.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <linux/iopoll.h>
> +#include <asm/arch-rockchip/clock.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define usleep_range(a, b) udelay((b))
> +
> +#define CMN_SSM_BANDGAP			(0x21 << 2)
> +#define CMN_SSM_BIAS			(0x22 << 2)
> +#define CMN_PLLSM0_PLLEN		(0x29 << 2)
> +#define CMN_PLLSM0_PLLPRE		(0x2a << 2)
> +#define CMN_PLLSM0_PLLVREF		(0x2b << 2)
> +#define CMN_PLLSM0_PLLLOCK		(0x2c << 2)
> +#define CMN_PLLSM1_PLLEN		(0x31 << 2)
> +#define CMN_PLLSM1_PLLPRE		(0x32 << 2)
> +#define CMN_PLLSM1_PLLVREF		(0x33 << 2)
> +#define CMN_PLLSM1_PLLLOCK		(0x34 << 2)
> +#define CMN_PLLSM1_USER_DEF_CTRL	(0x37 << 2)
> +#define CMN_ICAL_OVRD			(0xc1 << 2)
> +#define CMN_PLL0_VCOCAL_OVRD		(0x83 << 2)
> +#define CMN_PLL0_VCOCAL_INIT		(0x84 << 2)
> +#define CMN_PLL0_VCOCAL_ITER		(0x85 << 2)
> +#define CMN_PLL0_LOCK_REFCNT_START	(0x90 << 2)
> +#define CMN_PLL0_LOCK_PLLCNT_START	(0x92 << 2)
> +#define CMN_PLL0_LOCK_PLLCNT_THR	(0x93 << 2)
> +#define CMN_PLL0_INTDIV			(0x94 << 2)
> +#define CMN_PLL0_FRACDIV		(0x95 << 2)
> +#define CMN_PLL0_HIGH_THR		(0x96 << 2)
> +#define CMN_PLL0_DSM_DIAG		(0x97 << 2)
> +#define CMN_PLL0_SS_CTRL1		(0x98 << 2)
> +#define CMN_PLL0_SS_CTRL2		(0x99 << 2)
> +#define CMN_PLL1_VCOCAL_START		(0xa1 << 2)
> +#define CMN_PLL1_VCOCAL_OVRD		(0xa3 << 2)
> +#define CMN_PLL1_VCOCAL_INIT		(0xa4 << 2)
> +#define CMN_PLL1_VCOCAL_ITER		(0xa5 << 2)
> +#define CMN_PLL1_LOCK_REFCNT_START	(0xb0 << 2)
> +#define CMN_PLL1_LOCK_PLLCNT_START	(0xb2 << 2)
> +#define CMN_PLL1_LOCK_PLLCNT_THR	(0xb3 << 2)
> +#define CMN_PLL1_INTDIV			(0xb4 << 2)
> +#define CMN_PLL1_FRACDIV		(0xb5 << 2)
> +#define CMN_PLL1_HIGH_THR		(0xb6 << 2)
> +#define CMN_PLL1_DSM_DIAG		(0xb7 << 2)
> +#define CMN_PLL1_SS_CTRL1		(0xb8 << 2)
> +#define CMN_PLL1_SS_CTRL2		(0xb9 << 2)
> +#define CMN_RXCAL_OVRD			(0xd1 << 2)
> +
> +#define CMN_TXPUCAL_CTRL		(0xe0 << 2)
> +#define CMN_TXPUCAL_OVRD		(0xe1 << 2)
> +#define CMN_TXPDCAL_CTRL		(0xf0 << 2)
> +#define CMN_TXPDCAL_OVRD		(0xf1 << 2)
> +
> +/* For CMN_TXPUCAL_CTRL, CMN_TXPDCAL_CTRL */
> +#define CMN_TXPXCAL_START		BIT(15)
> +#define CMN_TXPXCAL_DONE		BIT(14)
> +#define CMN_TXPXCAL_NO_RESPONSE		BIT(13)
> +#define CMN_TXPXCAL_CURRENT_RESPONSE	BIT(12)
> +
> +#define CMN_TXPU_ADJ_CTRL		(0x108 << 2)
> +#define CMN_TXPD_ADJ_CTRL		(0x10c << 2)
> +
> +/*
> + * For CMN_TXPUCAL_CTRL, CMN_TXPDCAL_CTRL,
> + *     CMN_TXPU_ADJ_CTRL, CMN_TXPDCAL_CTRL
> + *
> + * NOTE: some of these registers are documented to be 2's complement
> + * signed numbers, but then documented to be always positive.  Weird.
> + * In such a case, using CMN_CALIB_CODE_POS() avoids the unnecessary
> + * sign extension.
> + */
> +#define CMN_CALIB_CODE_WIDTH	7
> +#define CMN_CALIB_CODE_OFFSET	0
> +#define CMN_CALIB_CODE_MASK	GENMASK(CMN_CALIB_CODE_WIDTH, 0)
> +#define CMN_CALIB_CODE(x)	\
> +	sign_extend32((x) >> CMN_CALIB_CODE_OFFSET, CMN_CALIB_CODE_WIDTH)
> +
> +#define CMN_CALIB_CODE_POS_MASK	GENMASK(CMN_CALIB_CODE_WIDTH - 1, 0)
> +#define CMN_CALIB_CODE_POS(x)	\
> +	(((x) >> CMN_CALIB_CODE_OFFSET) & CMN_CALIB_CODE_POS_MASK)
> +
> +#define CMN_DIAG_PLL0_FBH_OVRD		(0x1c0 << 2)
> +#define CMN_DIAG_PLL0_FBL_OVRD		(0x1c1 << 2)
> +#define CMN_DIAG_PLL0_OVRD		(0x1c2 << 2)
> +#define CMN_DIAG_PLL0_V2I_TUNE		(0x1c5 << 2)
> +#define CMN_DIAG_PLL0_CP_TUNE		(0x1c6 << 2)
> +#define CMN_DIAG_PLL0_LF_PROG		(0x1c7 << 2)
> +#define CMN_DIAG_PLL1_FBH_OVRD		(0x1d0 << 2)
> +#define CMN_DIAG_PLL1_FBL_OVRD		(0x1d1 << 2)
> +#define CMN_DIAG_PLL1_OVRD		(0x1d2 << 2)
> +#define CMN_DIAG_PLL1_V2I_TUNE		(0x1d5 << 2)
> +#define CMN_DIAG_PLL1_CP_TUNE		(0x1d6 << 2)
> +#define CMN_DIAG_PLL1_LF_PROG		(0x1d7 << 2)
> +#define CMN_DIAG_PLL1_PTATIS_TUNE1	(0x1d8 << 2)
> +#define CMN_DIAG_PLL1_PTATIS_TUNE2	(0x1d9 << 2)
> +#define CMN_DIAG_PLL1_INCLK_CTRL	(0x1da << 2)
> +#define CMN_DIAG_HSCLK_SEL		(0x1e0 << 2)
> +
> +#define XCVR_PSM_RCTRL(n)		((0x4001 | ((n) << 9)) << 2)
> +#define XCVR_PSM_CAL_TMR(n)		((0x4002 | ((n) << 9)) << 2)
> +#define XCVR_PSM_A0IN_TMR(n)		((0x4003 | ((n) << 9)) << 2)
> +#define TX_TXCC_CAL_SCLR_MULT(n)	((0x4047 | ((n) << 9)) << 2)
> +#define TX_TXCC_CPOST_MULT_00(n)	((0x404c | ((n) << 9)) << 2)
> +#define TX_TXCC_CPOST_MULT_01(n)	((0x404d | ((n) << 9)) << 2)
> +#define TX_TXCC_CPOST_MULT_10(n)	((0x404e | ((n) << 9)) << 2)
> +#define TX_TXCC_CPOST_MULT_11(n)	((0x404f | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_000(n)	((0x4050 | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_001(n)	((0x4051 | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_010(n)	((0x4052 | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_011(n)	((0x4053 | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_100(n)	((0x4054 | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_101(n)	((0x4055 | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_110(n)	((0x4056 | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_111(n)	((0x4057 | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNLS_MULT_000(n)	((0x4058 | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNLS_MULT_001(n)	((0x4059 | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNLS_MULT_010(n)	((0x405a | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNLS_MULT_011(n)	((0x405b | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNLS_MULT_100(n)	((0x405c | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNLS_MULT_101(n)	((0x405d | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNLS_MULT_110(n)	((0x405e | ((n) << 9)) << 2)
> +#define TX_TXCC_MGNLS_MULT_111(n)	((0x405f | ((n) << 9)) << 2)
> +
> +#define XCVR_DIAG_PLLDRC_CTRL(n)	((0x40e0 | ((n) << 9)) << 2)
> +#define XCVR_DIAG_BIDI_CTRL(n)		((0x40e8 | ((n) << 9)) << 2)
> +#define XCVR_DIAG_LANE_FCM_EN_MGN(n)	((0x40f2 | ((n) << 9)) << 2)
> +#define TX_PSC_A0(n)			((0x4100 | ((n) << 9)) << 2)
> +#define TX_PSC_A1(n)			((0x4101 | ((n) << 9)) << 2)
> +#define TX_PSC_A2(n)			((0x4102 | ((n) << 9)) << 2)
> +#define TX_PSC_A3(n)			((0x4103 | ((n) << 9)) << 2)
> +#define TX_RCVDET_CTRL(n)		((0x4120 | ((n) << 9)) << 2)
> +#define TX_RCVDET_EN_TMR(n)		((0x4122 | ((n) << 9)) << 2)
> +#define TX_RCVDET_ST_TMR(n)		((0x4123 | ((n) << 9)) << 2)
> +#define TX_DIAG_TX_DRV(n)		((0x41e1 | ((n) << 9)) << 2)
> +#define TX_DIAG_BGREF_PREDRV_DELAY	(0x41e7 << 2)
> +
> +/* Use this for "n" in macros like "_MULT_XXX" to target the aux channel */
> +#define AUX_CH_LANE			8
> +
> +#define TX_ANA_CTRL_REG_1		(0x5020 << 2)
> +
> +#define TXDA_DP_AUX_EN			BIT(15)
> +#define AUXDA_SE_EN			BIT(14)
> +#define TXDA_CAL_LATCH_EN		BIT(13)
> +#define AUXDA_POLARITY			BIT(12)
> +#define TXDA_DRV_POWER_ISOLATION_EN	BIT(11)
> +#define TXDA_DRV_POWER_EN_PH_2_N	BIT(10)
> +#define TXDA_DRV_POWER_EN_PH_1_N	BIT(9)
> +#define TXDA_BGREF_EN			BIT(8)
> +#define TXDA_DRV_LDO_EN			BIT(7)
> +#define TXDA_DECAP_EN_DEL		BIT(6)
> +#define TXDA_DECAP_EN			BIT(5)
> +#define TXDA_UPHY_SUPPLY_EN_DEL		BIT(4)
> +#define TXDA_UPHY_SUPPLY_EN		BIT(3)
> +#define TXDA_LOW_LEAKAGE_EN		BIT(2)
> +#define TXDA_DRV_IDLE_LOWI_EN		BIT(1)
> +#define TXDA_DRV_CMN_MODE_EN		BIT(0)
> +
> +#define TX_ANA_CTRL_REG_2		(0x5021 << 2)
> +
> +#define AUXDA_DEBOUNCING_CLK		BIT(15)
> +#define TXDA_LPBK_RECOVERED_CLK_EN	BIT(14)
> +#define TXDA_LPBK_ISI_GEN_EN		BIT(13)
> +#define TXDA_LPBK_SERIAL_EN		BIT(12)
> +#define TXDA_LPBK_LINE_EN		BIT(11)
> +#define TXDA_DRV_LDO_REDC_SINKIQ	BIT(10)
> +#define XCVR_DECAP_EN_DEL		BIT(9)
> +#define XCVR_DECAP_EN			BIT(8)
> +#define TXDA_MPHY_ENABLE_HS_NT		BIT(7)
> +#define TXDA_MPHY_SA_MODE		BIT(6)
> +#define TXDA_DRV_LDO_RBYR_FB_EN		BIT(5)
> +#define TXDA_DRV_RST_PULL_DOWN		BIT(4)
> +#define TXDA_DRV_LDO_BG_FB_EN		BIT(3)
> +#define TXDA_DRV_LDO_BG_REF_EN		BIT(2)
> +#define TXDA_DRV_PREDRV_EN_DEL		BIT(1)
> +#define TXDA_DRV_PREDRV_EN		BIT(0)
> +
> +#define TXDA_COEFF_CALC_CTRL		(0x5022 << 2)
> +
> +#define TX_HIGH_Z			BIT(6)
> +#define TX_VMARGIN_OFFSET		3
> +#define TX_VMARGIN_MASK			0x7
> +#define LOW_POWER_SWING_EN		BIT(2)
> +#define TX_FCM_DRV_MAIN_EN		BIT(1)
> +#define TX_FCM_FULL_MARGIN		BIT(0)
> +
> +#define TX_DIG_CTRL_REG_2		(0x5024 << 2)
> +
> +#define TX_HIGH_Z_TM_EN			BIT(15)
> +#define TX_RESCAL_CODE_OFFSET		0
> +#define TX_RESCAL_CODE_MASK		0x3f
> +
> +#define TXDA_CYA_AUXDA_CYA		(0x5025 << 2)
> +#define TX_ANA_CTRL_REG_3		(0x5026 << 2)
> +#define TX_ANA_CTRL_REG_4		(0x5027 << 2)
> +#define TX_ANA_CTRL_REG_5		(0x5029 << 2)
> +
> +#define RX_PSC_A0(n)			((0x8000 | ((n) << 9)) << 2)
> +#define RX_PSC_A1(n)			((0x8001 | ((n) << 9)) << 2)
> +#define RX_PSC_A2(n)			((0x8002 | ((n) << 9)) << 2)
> +#define RX_PSC_A3(n)			((0x8003 | ((n) << 9)) << 2)
> +#define RX_PSC_CAL(n)			((0x8006 | ((n) << 9)) << 2)
> +#define RX_PSC_RDY(n)			((0x8007 | ((n) << 9)) << 2)
> +#define RX_IQPI_ILL_CAL_OVRD		(0x8023 << 2)
> +#define RX_EPI_ILL_CAL_OVRD		(0x8033 << 2)
> +#define RX_SDCAL0_OVRD			(0x8041 << 2)
> +#define RX_SDCAL1_OVRD			(0x8049 << 2)
> +#define RX_SLC_INIT			(0x806d << 2)
> +#define RX_SLC_RUN			(0x806e << 2)
> +#define RX_CDRLF_CNFG2			(0x8081 << 2)
> +#define RX_SIGDET_HL_FILT_TMR(n)	((0x8090 | ((n) << 9)) << 2)
> +#define RX_SLC_IOP0_OVRD		(0x8101 << 2)
> +#define RX_SLC_IOP1_OVRD		(0x8105 << 2)
> +#define RX_SLC_QOP0_OVRD		(0x8109 << 2)
> +#define RX_SLC_QOP1_OVRD		(0x810d << 2)
> +#define RX_SLC_EOP0_OVRD		(0x8111 << 2)
> +#define RX_SLC_EOP1_OVRD		(0x8115 << 2)
> +#define RX_SLC_ION0_OVRD		(0x8119 << 2)
> +#define RX_SLC_ION1_OVRD		(0x811d << 2)
> +#define RX_SLC_QON0_OVRD		(0x8121 << 2)
> +#define RX_SLC_QON1_OVRD		(0x8125 << 2)
> +#define RX_SLC_EON0_OVRD		(0x8129 << 2)
> +#define RX_SLC_EON1_OVRD		(0x812d << 2)
> +#define RX_SLC_IEP0_OVRD		(0x8131 << 2)
> +#define RX_SLC_IEP1_OVRD		(0x8135 << 2)
> +#define RX_SLC_QEP0_OVRD		(0x8139 << 2)
> +#define RX_SLC_QEP1_OVRD		(0x813d << 2)
> +#define RX_SLC_EEP0_OVRD		(0x8141 << 2)
> +#define RX_SLC_EEP1_OVRD		(0x8145 << 2)
> +#define RX_SLC_IEN0_OVRD		(0x8149 << 2)
> +#define RX_SLC_IEN1_OVRD		(0x814d << 2)
> +#define RX_SLC_QEN0_OVRD		(0x8151 << 2)
> +#define RX_SLC_QEN1_OVRD		(0x8155 << 2)
> +#define RX_SLC_EEN0_OVRD		(0x8159 << 2)
> +#define RX_SLC_EEN1_OVRD		(0x815d << 2)
> +#define RX_REE_CTRL_DATA_MASK(n)	((0x81bb | ((n) << 9)) << 2)
> +#define RX_DIAG_SIGDET_TUNE(n)		((0x81dc | ((n) << 9)) << 2)
> +#define RX_DIAG_SC2C_DELAY		(0x81e1 << 2)
> +
> +#define PMA_LANE_CFG			(0xc000 << 2)
> +#define PIPE_CMN_CTRL1			(0xc001 << 2)
> +#define PIPE_CMN_CTRL2			(0xc002 << 2)
> +#define PIPE_COM_LOCK_CFG1		(0xc003 << 2)
> +#define PIPE_COM_LOCK_CFG2		(0xc004 << 2)
> +#define PIPE_RCV_DET_INH		(0xc005 << 2)
> +#define DP_MODE_CTL			(0xc008 << 2)
> +#define DP_CLK_CTL			(0xc009 << 2)
> +#define STS				(0xc00F << 2)
> +#define PHY_ISO_CMN_CTRL		(0xc010 << 2)
> +#define PHY_DP_TX_CTL			(0xc408 << 2)
> +#define PMA_CMN_CTRL1			(0xc800 << 2)
> +#define PHY_PMA_ISO_CMN_CTRL		(0xc810 << 2)
> +#define PHY_ISOLATION_CTRL		(0xc81f << 2)
> +#define PHY_PMA_ISO_XCVR_CTRL(n)	((0xcc11 | ((n) << 6)) << 2)
> +#define PHY_PMA_ISO_LINK_MODE(n)	((0xcc12 | ((n) << 6)) << 2)
> +#define PHY_PMA_ISO_PWRST_CTRL(n)	((0xcc13 | ((n) << 6)) << 2)
> +#define PHY_PMA_ISO_TX_DATA_LO(n)	((0xcc14 | ((n) << 6)) << 2)
> +#define PHY_PMA_ISO_TX_DATA_HI(n)	((0xcc15 | ((n) << 6)) << 2)
> +#define PHY_PMA_ISO_RX_DATA_LO(n)	((0xcc16 | ((n) << 6)) << 2)
> +#define PHY_PMA_ISO_RX_DATA_HI(n)	((0xcc17 | ((n) << 6)) << 2)
> +#define TX_BIST_CTRL(n)			((0x4140 | ((n) << 9)) << 2)
> +#define TX_BIST_UDDWR(n)		((0x4141 | ((n) << 9)) << 2)
> +
> +/*
> + * Selects which PLL clock will be driven on the analog high speed
> + * clock 0: PLL 0 div 1
> + * clock 1: PLL 1 div 2
> + */
> +#define CLK_PLL_CONFIG			0X30
> +#define CLK_PLL_MASK			0x33
> +
> +#define CMN_READY			BIT(0)
> +
> +#define DP_PLL_CLOCK_ENABLE		BIT(2)
> +#define DP_PLL_ENABLE			BIT(0)
> +#define DP_PLL_DATA_RATE_RBR		((2 << 12) | (4 << 8))
> +#define DP_PLL_DATA_RATE_HBR		((2 << 12) | (4 << 8))
> +#define DP_PLL_DATA_RATE_HBR2		((1 << 12) | (2 << 8))
> +
> +#define DP_MODE_A0			BIT(4)
> +#define DP_MODE_A2			BIT(6)
> +#define DP_MODE_ENTER_A0		0xc101
> +#define DP_MODE_ENTER_A2		0xc104
> +
> +#define PHY_MODE_SET_TIMEOUT		100000
> +
> +#define PIN_ASSIGN_C_E			0x51d9
> +#define PIN_ASSIGN_D_F			0x5100
> +
> +#define MODE_DISCONNECT			0
> +#define MODE_UFP_USB			BIT(0)
> +#define MODE_DFP_USB			BIT(1)
> +#define MODE_DFP_DP			BIT(2)
> +
> +struct usb3phy_reg {
> +	u32 offset;
> +	u32 enable_bit;
> +	u32 write_enable;
> +};
> +
> +/**
> + * struct rockchip_usb3phy_port_cfg: usb3-phy port configuration.
> + * @reg: the base address for usb3-phy config.
> + * @typec_conn_dir: the register of type-c connector direction.
> + * @usb3tousb2_en: the register of type-c force usb2 to usb2 enable.
> + * @external_psm: the register of type-c phy external psm clock.
> + * @pipe_status: the register of type-c phy pipe status.
> + * @usb3_host_disable: the register of type-c usb3 host disable.
> + * @usb3_host_port: the register of type-c usb3 host port.
> + * @uphy_dp_sel: the register of type-c phy DP select control.
> + */
> +struct rockchip_usb3phy_port_cfg {
> +	unsigned int reg;
> +	struct usb3phy_reg typec_conn_dir;
> +	struct usb3phy_reg usb3tousb2_en;
> +	struct usb3phy_reg external_psm;
> +	struct usb3phy_reg pipe_status;
> +	struct usb3phy_reg usb3_host_disable;
> +	struct usb3phy_reg usb3_host_port;
> +	struct usb3phy_reg uphy_dp_sel;
> +};
> +
> +struct rockchip_tcphy {
> +	void __iomem *reg_base;
> +	void __iomem *grf_base;
> +	struct clk clk_core;
> +	struct clk clk_ref;
> +	struct reset_ctl uphy_rst;
> +	struct reset_ctl pipe_rst;
> +	struct reset_ctl tcphy_rst;
> +	const struct rockchip_usb3phy_port_cfg *port_cfgs;
> +	u8 mode;
> +};
> +
> +struct phy_reg {
> +	u16 value;
> +	u32 addr;
> +};
> +
> +static struct phy_reg usb3_pll_cfg[] = {
> +	{ 0xf0,		CMN_PLL0_VCOCAL_INIT },
> +	{ 0x18,		CMN_PLL0_VCOCAL_ITER },
> +	{ 0xd0,		CMN_PLL0_INTDIV },
> +	{ 0x4a4a,	CMN_PLL0_FRACDIV },
> +	{ 0x34,		CMN_PLL0_HIGH_THR },
> +	{ 0x1ee,	CMN_PLL0_SS_CTRL1 },
> +	{ 0x7f03,	CMN_PLL0_SS_CTRL2 },
> +	{ 0x20,		CMN_PLL0_DSM_DIAG },
> +	{ 0,		CMN_DIAG_PLL0_OVRD },
> +	{ 0,		CMN_DIAG_PLL0_FBH_OVRD },
> +	{ 0,		CMN_DIAG_PLL0_FBL_OVRD },
> +	{ 0x7,		CMN_DIAG_PLL0_V2I_TUNE },
> +	{ 0x45,		CMN_DIAG_PLL0_CP_TUNE },
> +	{ 0x8,		CMN_DIAG_PLL0_LF_PROG },
> +};
> +
> +static inline int property_enable(struct rockchip_tcphy *priv,
> +				  const struct usb3phy_reg *reg, bool en)
> +{
> +	u32 mask = 1 << reg->write_enable;
> +	u32 val = en << reg->enable_bit;
> +
> +	return writel(val | mask, priv->grf_base + reg->offset);
> +}
> +
> +static int rockchip_tcphy_get_mode(struct rockchip_tcphy *priv)
> +{
> +	/* TODO: Add proper logic to find DP or USB3 mode */
> +	return MODE_DFP_USB | MODE_UFP_USB;
> +}
> +
> +static void rockchip_tcphy_cfg_24m(struct rockchip_tcphy *priv)
> +{
> +	u32 i, rdata;
> +
> +	/*
> +	 * cmn_ref_clk_sel = 3, select the 24Mhz for clk parent
> +	 * cmn_psm_clk_dig_div = 2, set the clk division to 2
> +	 */
> +	writel(0x830, priv->reg_base + PMA_CMN_CTRL1);
> +	for (i = 0; i < 4; i++) {
> +		/*
> +		 * The following PHY configuration assumes a 24 MHz reference
> +		 * clock.
> +		 */
> +		writel(0x90, priv->reg_base + XCVR_DIAG_LANE_FCM_EN_MGN(i));
> +		writel(0x960, priv->reg_base + TX_RCVDET_EN_TMR(i));
> +		writel(0x30, priv->reg_base + TX_RCVDET_ST_TMR(i));
> +	}
> +
> +	rdata = readl(priv->reg_base + CMN_DIAG_HSCLK_SEL);
> +	rdata &= ~CLK_PLL_MASK;
> +	rdata |= CLK_PLL_CONFIG;
> +	writel(rdata, priv->reg_base + CMN_DIAG_HSCLK_SEL);
> +}
> +
> +static void rockchip_tcphy_cfg_usb3_pll(struct rockchip_tcphy *priv)
> +{
> +	u32 i;
> +
> +	/* load the configuration of PLL0 */
> +	for (i = 0; i < ARRAY_SIZE(usb3_pll_cfg); i++)
> +		writel(usb3_pll_cfg[i].value,
> +		       priv->reg_base + usb3_pll_cfg[i].addr);
> +}
> +
> +static void rockchip_tcphy_tx_usb3_cfg_lane(struct rockchip_tcphy *priv,
> +					    u32 lane)
> +{
> +	writel(0x7799, priv->reg_base + TX_PSC_A0(lane));
> +	writel(0x7798, priv->reg_base + TX_PSC_A1(lane));
> +	writel(0x5098, priv->reg_base + TX_PSC_A2(lane));
> +	writel(0x5098, priv->reg_base + TX_PSC_A3(lane));
> +	writel(0, priv->reg_base + TX_TXCC_MGNFS_MULT_000(lane));
> +	writel(0xbf, priv->reg_base + XCVR_DIAG_BIDI_CTRL(lane));
> +}
> +
> +static void rockchip_tcphy_rx_usb3_cfg_lane(struct rockchip_tcphy *priv,
> +					    u32 lane)
> +{
> +	writel(0xa6fd, priv->reg_base + RX_PSC_A0(lane));
> +	writel(0xa6fd, priv->reg_base + RX_PSC_A1(lane));
> +	writel(0xa410, priv->reg_base + RX_PSC_A2(lane));
> +	writel(0x2410, priv->reg_base + RX_PSC_A3(lane));
> +	writel(0x23ff, priv->reg_base + RX_PSC_CAL(lane));
> +	writel(0x13, priv->reg_base + RX_SIGDET_HL_FILT_TMR(lane));
> +	writel(0x03e7, priv->reg_base + RX_REE_CTRL_DATA_MASK(lane));
> +	writel(0x1004, priv->reg_base + RX_DIAG_SIGDET_TUNE(lane));
> +	writel(0x2010, priv->reg_base + RX_PSC_RDY(lane));
> +	writel(0xfb, priv->reg_base + XCVR_DIAG_BIDI_CTRL(lane));
> +}
> +
> +static int rockchip_tcphy_init(struct rockchip_tcphy *priv)
> +{
> +	const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
> +	u32 val;
> +	int ret;
> +
> +	ret = clk_enable(&priv->clk_core);
> +	if (ret) {
> +		dev_err(phy->dev, "failed to enable core clk (ret=%d)\n", ret);
> +		return ret;
> +	}
> +
> +	ret = clk_enable(&priv->clk_ref);
> +	if (ret) {
> +		dev_err(phy->dev, "failed to enable ref clk (ret=%d)\n", ret);
> +		goto err_clk_core;
> +	}
> +
> +	ret = reset_deassert(&priv->tcphy_rst);
> +	if (ret) {
> +		dev_err(phy->dev, "failed to deassert uphy-tcphy reset (ret=%d)\n",
> +			ret);
> +		goto err_clk_ref;
> +	}
> +
> +	property_enable(priv, &cfg->typec_conn_dir, 0);
> +
> +	rockchip_tcphy_cfg_24m(priv);
> +
> +	rockchip_tcphy_cfg_usb3_pll(priv);
> +
> +	rockchip_tcphy_tx_usb3_cfg_lane(priv, 0);
> +	rockchip_tcphy_rx_usb3_cfg_lane(priv, 1);
> +
> +	ret = reset_deassert(&priv->uphy_rst);
> +	if (ret) {
> +		dev_err(phy->dev, "failed to deassert uphy rst (ret=%d)\n",
> +			ret);
> +		goto err_tcphy_rst;
> +	}
> +
> +	ret = readl_poll_sleep_timeout(priv->reg_base + PMA_CMN_CTRL1,
> +				       val, val & CMN_READY, 10,
> +				       PHY_MODE_SET_TIMEOUT);
> +	if (ret < 0) {
> +		dev_err(phy->dev, "PMA Timeout!\n");
> +		ret = -ETIMEDOUT;
> +		goto err_uphy_rst;
> +	}
> +
> +	ret = reset_deassert(&priv->pipe_rst);
> +	if (ret) {
> +		dev_err(phy->dev, "failed to deassert pipe rst (ret=%d)\n",
> +			ret);
> +		goto err_uphy_rst;
> +	}
> +
> +	return 0;
> +
> +err_uphy_rst:
> +	reset_assert(&priv->uphy_rst);
> +err_tcphy_rst:
> +	reset_assert(&priv->tcphy_rst);
> +err_clk_ref:
> +	clk_disable(&priv->clk_ref);
> +err_clk_core:
> +	clk_disable(&priv->clk_core);
> +	return ret;
> +}
> +
> +static void rockchip_tcphy_exit(struct rockchip_tcphy *priv)
> +{
> +	reset_assert(&priv->tcphy_rst);
> +	reset_assert(&priv->uphy_rst);
> +	reset_assert(&priv->pipe_rst);
> +	clk_disable(&priv->clk_core);
> +	clk_disable(&priv->clk_ref);
> +}
> +
> +static int tcphy_cfg_usb3_to_usb2_only(struct rockchip_tcphy *priv,
> +				       bool value)
> +{
> +	const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
> +
> +	property_enable(priv, &cfg->usb3tousb2_en, value);
> +	property_enable(priv, &cfg->usb3_host_disable, value);
> +	property_enable(priv, &cfg->usb3_host_port, !value);
> +
> +	return 0;
> +}
> +
> +static int rockchip_usb3_phy_power_on(struct phy *phy)
> +{
> +	struct udevice *parent = dev_get_parent(phy->dev);
> +	struct rockchip_tcphy *priv = dev_get_priv(parent);
> +	const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
> +	const struct usb3phy_reg *reg = &cfg->pipe_status;
> +	int timeout, new_mode;
> +	u32 val;
> +	int ret;
> +
> +	new_mode = rockchip_tcphy_get_mode(priv);
> +	if (new_mode < 0) {
> +		dev_err(phy->dev, "invalid mode %d\n", new_mode);
> +		return new_mode;
> +	}
> +
> +	if (priv->mode == new_mode)
> +		return 0;
> +
> +	if (priv->mode == MODE_DISCONNECT) {
> +		ret = rockchip_tcphy_init(priv);
> +		if (ret) {
> +			dev_err(dev, "failed to init tcphy (ret=%d)\n", ret);
> +			return ret;
> +		}
> +	}
> +
> +	/* wait TCPHY for pipe ready */
> +	for (timeout = 0; timeout < 100; timeout++) {
> +		val = readl(priv->grf_base + reg->offset);
> +		if (!(val & BIT(reg->enable_bit))) {
> +			priv->mode |= new_mode & (MODE_DFP_USB | MODE_UFP_USB);
> +
> +			/* enable usb3 host */
> +			tcphy_cfg_usb3_to_usb2_only(priv, false);
> +			return 0;
> +		}
> +		usleep_range(10, 20);
> +	}
> +
> +	if (priv->mode == MODE_DISCONNECT)
> +		rockchip_tcphy_exit(priv);
> +
> +	return -ETIMEDOUT;
> +}
> +
> +static int rockchip_usb3_phy_power_off(struct phy *phy)
> +{
> +	struct udevice *parent = dev_get_parent(phy->dev);
> +	struct rockchip_tcphy *priv = dev_get_priv(parent);
> +
> +	tcphy_cfg_usb3_to_usb2_only(priv, false);
> +
> +	if (priv->mode == MODE_DISCONNECT)
> +		goto exit;
> +
> +	priv->mode &= ~(MODE_UFP_USB | MODE_DFP_USB);
> +	if (priv->mode == MODE_DISCONNECT)
> +		rockchip_tcphy_exit(priv);
> +
> +exit:
> +	return 0;
> +}
> +
> +static struct phy_ops rockchip_tcphy_usb3_ops = {
> +	.power_on = rockchip_usb3_phy_power_on,
> +	.power_off = rockchip_usb3_phy_power_off,
> +};
> +
> +static void rockchip_tcphy_pre_init(struct udevice *dev)
> +{
> +	struct rockchip_tcphy *priv = dev_get_priv(dev);
> +	const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
> +
> +	reset_assert(&priv->tcphy_rst);
> +	reset_assert(&priv->uphy_rst);
> +	reset_assert(&priv->pipe_rst);
> +
> +	/* select external psm clock */
> +	property_enable(priv, &cfg->external_psm, 1);
> +	property_enable(priv, &cfg->usb3tousb2_en, 0);
> +
> +	priv->mode = MODE_DISCONNECT;
> +}
> +
> +static int rockchip_tcphy_parse_dt(struct udevice *dev)
> +{
> +	struct rockchip_tcphy *priv = dev_get_priv(dev);
> +	int ret;
> +
> +	priv->grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +	if (IS_ERR(priv->grf_base))
> +		return PTR_ERR(priv->grf_base);
> +
> +	ret = clk_get_by_name(dev, "tcpdcore", &priv->clk_core);
> +	if (ret) {
> +		dev_err(dev, "failed to get tcpdcore clk (ret=%d)\n", ret);
> +		return ret;
> +	}
> +
> +	ret = clk_get_by_name(dev, "tcpdphy-ref", &priv->clk_ref);
> +	if (ret) {
> +		dev_err(dev, "failed to get tcpdphy-ref clk (ret=%d)\n", ret);
> +		return ret;
> +	}
> +
> +	ret = reset_get_by_name(dev, "uphy", &priv->uphy_rst);
> +	if (ret) {
> +		dev_err(dev, "failed to get uphy reset (ret=%d)\n", ret);
> +		return ret;
> +	}
> +
> +	ret = reset_get_by_name(dev, "uphy-pipe", &priv->pipe_rst);
> +	if (ret) {
> +		dev_err(dev, "failed to get uphy-pipe reset (ret=%d)\n", ret);
> +		return ret;
> +	}
> +
> +	ret = reset_get_by_name(dev, "uphy-tcphy", &priv->tcphy_rst);
> +	if (ret) {
> +		dev_err(dev, "failed to get uphy-tcphy reset (ret=%d)\n", ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int rockchip_tcphy_probe(struct udevice *dev)
> +{
> +	struct rockchip_tcphy *priv = dev_get_priv(dev);
> +	const struct rockchip_usb3phy_port_cfg *phy_cfgs;
> +	unsigned int reg;
> +	int index, ret;
> +
> +	priv->reg_base = (void __iomem *)dev_read_addr(dev);
> +	if (IS_ERR(priv->reg_base))
> +		return PTR_ERR(priv->reg_base);
> +
> +	ret = dev_read_u32_index(dev, "reg", 1, &reg);
> +	if (ret) {
> +		dev_err(dev, "failed to read reg property (ret = %d)\n", ret);
> +		return ret;
> +	}
> +
> +	phy_cfgs = (const struct rockchip_usb3phy_port_cfg *)
> +					dev_get_driver_data(dev);
> +	if (!phy_cfgs)
> +		return -EINVAL;
> +
> +	/* find out a proper config which can be matched with dt. */
> +	index = 0;
> +	while (phy_cfgs[index].reg) {
> +		if (phy_cfgs[index].reg == reg) {
> +			priv->port_cfgs = &phy_cfgs[index];
> +			break;
> +		}
> +
> +		++index;
> +	}
> +
> +	if (!priv->port_cfgs) {
> +		dev_err(dev, "failed find proper phy-cfg\n");
> +		return -EINVAL;
> +	}
> +
> +	ret = rockchip_tcphy_parse_dt(dev);
> +	if (ret)
> +		return ret;
> +
> +	rockchip_tcphy_pre_init(dev);
> +
> +	return 0;
> +}
> +
> +static int rockchip_tcphy_bind(struct udevice *dev)
> +{
> +	struct udevice *tcphy_dev;
> +	ofnode node;
> +	const char *name;
> +	int ret = 0;
> +
> +	dev_for_each_subnode(node, dev) {
> +		if (!ofnode_valid(node)) {
> +			dev_info(dev, "subnode %s not found\n", dev->name);
> +			return -ENXIO;
> +		}
> +
> +		name = ofnode_get_name(node);
> +		dev_dbg(dev, "subnode %s\n", name);
> +
> +		if (!strcasecmp(name, "dp-port")) {
> +			dev_dbg(dev, "Warning: dp-port not supported yet!\n");
> +			continue;
> +		} else if (!strcasecmp(name, "usb3-port")) {
> +			ret = device_bind_driver_to_node(dev,
> +							 "rockchip_tcphy_usb3_port",
> +							 name, node, &tcphy_dev);
> +			if (ret) {
> +				dev_err(dev,
> +					"'%s' cannot bind 'rockchip_tcphy_usb3_port'\n",
> +					name);
> +				return ret;
> +			}
> +		}
> +	}
> +
> +	return ret;
> +}
> +
> +static const struct rockchip_usb3phy_port_cfg rk3399_typec_phy_cfgs[] = {
> +	{
> +		.reg			= 0xff7c0000,
> +		.typec_conn_dir		= { 0xe580, 0, 16 },
> +		.usb3tousb2_en		= { 0xe580, 3, 19 },
> +		.external_psm		= { 0xe588, 14, 30 },
> +		.pipe_status		= { 0xe5c0, 0, 0 },
> +		.usb3_host_disable	= { 0x2434, 0, 16 },
> +		.usb3_host_port		= { 0x2434, 12, 28 },
> +		.uphy_dp_sel		= { 0x6268, 19, 19 },
> +	},
> +	{
> +		.reg			= 0xff800000,
> +		.typec_conn_dir		= { 0xe58c, 0, 16 },
> +		.usb3tousb2_en		= { 0xe58c, 3, 19 },
> +		.external_psm		= { 0xe594, 14, 30 },
> +		.pipe_status		= { 0xe5c0, 16, 16 },
> +		.usb3_host_disable	= { 0x2444, 0, 16 },
> +		.usb3_host_port		= { 0x2444, 12, 28 },
> +		.uphy_dp_sel		= { 0x6268, 3, 19 },
> +	},
> +	{ /* sentinel */ }
> +};
> +
> +static const struct udevice_id rockchip_typec_phy_ids[] = {
> +	{
> +		.compatible = "rockchip,rk3399-typec-phy",
> +		.data = (ulong)&rk3399_typec_phy_cfgs,
> +	},
> +	{ /* sentinel */ }
> +};
> +
> +U_BOOT_DRIVER(rockchip_tcphy_usb3_port) = {
> +	.name		= "rockchip_tcphy_usb3_port",
> +	.id		= UCLASS_PHY,
> +	.ops		= &rockchip_tcphy_usb3_ops,
> +};
> +
> +U_BOOT_DRIVER(rockchip_typec_phy) = {
> +	.name	= "rockchip_typec_phy",
> +	.id	= UCLASS_PHY,
> +	.of_match = rockchip_typec_phy_ids,
> +	.probe = rockchip_tcphy_probe,
> +	.bind = rockchip_tcphy_bind,
> +	.priv_auto_alloc_size = sizeof(struct rockchip_tcphy),
> +};

[PATCH v5 07/16] usb: dwc3: add dis_enblslpm_quirk

[Frank Wang]

Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.

Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk")
in Linux Kernel.

Signed-off-by: Frank Wang <frank.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Reviewed-by: Kever Yang <kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Reviewed-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Tested-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 drivers/usb/dwc3/core.c | 6 ++++++
 drivers/usb/dwc3/core.h | 2 ++
 include/dwc3-uboot.h    | 1 +
 3 files changed, 9 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 0972e458eb..20be617fd4 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -398,6 +398,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->dis_u2_susphy_quirk)
 		reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 
+	if (dwc->dis_enblslpm_quirk)
+		reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
+
 	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 
 	mdelay(100);
@@ -719,6 +722,7 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
 	dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
 	dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
 	dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk;
+	dwc->dis_enblslpm_quirk = dwc3_dev->dis_enblslpm_quirk;
 
 	dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
 	if (dwc3_dev->tx_de_emphasis)
@@ -926,6 +930,8 @@ void dwc3_of_parse(struct dwc3 *dwc)
 				"snps,dis_u2_susphy_quirk");
 	dwc->dis_del_phy_power_chg_quirk = dev_read_bool(dev,
 				"snps,dis-del-phy-power-chg-quirk");
+	dwc->dis_enblslpm_quirk = dev_read_bool(dev,
+				"snps,dis_enblslpm_quirk");
 	dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
 				"snps,tx_de_emphasis_quirk");
 	tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 7f45a9c459..e76e357f1e 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -162,6 +162,7 @@
 /* Global USB2 PHY Configuration Register */
 #define DWC3_GUSB2PHYCFG_PHYSOFTRST	(1 << 31)
 #define DWC3_GUSB2PHYCFG_SUSPHY		(1 << 6)
+#define DWC3_GUSB2PHYCFG_ENBLSLPM	(1 << 8)
 #define DWC3_GUSB2PHYCFG_PHYIF(n)	((n) << 3)
 #define DWC3_GUSB2PHYCFG_PHYIF_MASK	DWC3_GUSB2PHYCFG_PHYIF(1)
 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n)	((n) << 10)
@@ -822,6 +823,7 @@ struct dwc3 {
 	unsigned		dis_u3_susphy_quirk:1;
 	unsigned		dis_u2_susphy_quirk:1;
 	unsigned		dis_del_phy_power_chg_quirk:1;
+	unsigned		dis_enblslpm_quirk:1;
 
 	unsigned		tx_de_emphasis_quirk:1;
 	unsigned		tx_de_emphasis:2;
diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h
index ecae34bf06..98d51e05e1 100644
--- a/include/dwc3-uboot.h
+++ b/include/dwc3-uboot.h
@@ -34,6 +34,7 @@ struct dwc3_device {
 	unsigned dis_u3_susphy_quirk;
 	unsigned dis_u2_susphy_quirk;
 	unsigned dis_del_phy_power_chg_quirk;
+	unsigned dis_enblslpm_quirk;
 	unsigned tx_de_emphasis_quirk;
 	unsigned tx_de_emphasis;
 	int index;
-- 
2.17.1

[PATCH v5 07/16] usb: dwc3: add dis_enblslpm_quirk

[Frank Wang]

Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.

Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk")
in Linux Kernel.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/usb/dwc3/core.c | 6 ++++++
 drivers/usb/dwc3/core.h | 2 ++
 include/dwc3-uboot.h    | 1 +
 3 files changed, 9 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 0972e458eb..20be617fd4 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -398,6 +398,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->dis_u2_susphy_quirk)
 		reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 
+	if (dwc->dis_enblslpm_quirk)
+		reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
+
 	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 
 	mdelay(100);
@@ -719,6 +722,7 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
 	dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
 	dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
 	dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk;
+	dwc->dis_enblslpm_quirk = dwc3_dev->dis_enblslpm_quirk;
 
 	dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
 	if (dwc3_dev->tx_de_emphasis)
@@ -926,6 +930,8 @@ void dwc3_of_parse(struct dwc3 *dwc)
 				"snps,dis_u2_susphy_quirk");
 	dwc->dis_del_phy_power_chg_quirk = dev_read_bool(dev,
 				"snps,dis-del-phy-power-chg-quirk");
+	dwc->dis_enblslpm_quirk = dev_read_bool(dev,
+				"snps,dis_enblslpm_quirk");
 	dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
 				"snps,tx_de_emphasis_quirk");
 	tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 7f45a9c459..e76e357f1e 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -162,6 +162,7 @@
 /* Global USB2 PHY Configuration Register */
 #define DWC3_GUSB2PHYCFG_PHYSOFTRST	(1 << 31)
 #define DWC3_GUSB2PHYCFG_SUSPHY		(1 << 6)
+#define DWC3_GUSB2PHYCFG_ENBLSLPM	(1 << 8)
 #define DWC3_GUSB2PHYCFG_PHYIF(n)	((n) << 3)
 #define DWC3_GUSB2PHYCFG_PHYIF_MASK	DWC3_GUSB2PHYCFG_PHYIF(1)
 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n)	((n) << 10)
@@ -822,6 +823,7 @@ struct dwc3 {
 	unsigned		dis_u3_susphy_quirk:1;
 	unsigned		dis_u2_susphy_quirk:1;
 	unsigned		dis_del_phy_power_chg_quirk:1;
+	unsigned		dis_enblslpm_quirk:1;
 
 	unsigned		tx_de_emphasis_quirk:1;
 	unsigned		tx_de_emphasis:2;
diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h
index ecae34bf06..98d51e05e1 100644
--- a/include/dwc3-uboot.h
+++ b/include/dwc3-uboot.h
@@ -34,6 +34,7 @@ struct dwc3_device {
 	unsigned dis_u3_susphy_quirk;
 	unsigned dis_u2_susphy_quirk;
 	unsigned dis_del_phy_power_chg_quirk;
+	unsigned dis_enblslpm_quirk;
 	unsigned tx_de_emphasis_quirk;
 	unsigned tx_de_emphasis;
 	int index;
-- 
2.17.1

[PATCH v5 08/16] usb: dwc3: add dis_u2_freeclk_exists_quirk

[Frank Wang]

Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.

Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk")
in Linux Rockchip Kernel.

Signed-off-by: Frank Wang <frank.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Reviewed-by: Kever Yang <kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Reviewed-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Tested-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 drivers/usb/dwc3/core.c | 6 ++++++
 drivers/usb/dwc3/core.h | 2 ++
 include/dwc3-uboot.h    | 1 +
 3 files changed, 9 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 20be617fd4..3cb66515a2 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -401,6 +401,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->dis_enblslpm_quirk)
 		reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 
+	if (dwc->dis_u2_freeclk_exists_quirk)
+		reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
+
 	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 
 	mdelay(100);
@@ -723,6 +726,7 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
 	dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
 	dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk;
 	dwc->dis_enblslpm_quirk = dwc3_dev->dis_enblslpm_quirk;
+	dwc->dis_u2_freeclk_exists_quirk = dwc3_dev->dis_u2_freeclk_exists_quirk;
 
 	dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
 	if (dwc3_dev->tx_de_emphasis)
@@ -932,6 +936,8 @@ void dwc3_of_parse(struct dwc3 *dwc)
 				"snps,dis-del-phy-power-chg-quirk");
 	dwc->dis_enblslpm_quirk = dev_read_bool(dev,
 				"snps,dis_enblslpm_quirk");
+	dwc->dis_u2_freeclk_exists_quirk = dev_read_bool(dev,
+				"snps,dis-u2-freeclk-exists-quirk");
 	dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
 				"snps,tx_de_emphasis_quirk");
 	tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index e76e357f1e..c5e656885a 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -161,6 +161,7 @@
 
 /* Global USB2 PHY Configuration Register */
 #define DWC3_GUSB2PHYCFG_PHYSOFTRST	(1 << 31)
+#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS	(1 << 30)
 #define DWC3_GUSB2PHYCFG_SUSPHY		(1 << 6)
 #define DWC3_GUSB2PHYCFG_ENBLSLPM	(1 << 8)
 #define DWC3_GUSB2PHYCFG_PHYIF(n)	((n) << 3)
@@ -824,6 +825,7 @@ struct dwc3 {
 	unsigned		dis_u2_susphy_quirk:1;
 	unsigned		dis_del_phy_power_chg_quirk:1;
 	unsigned		dis_enblslpm_quirk:1;
+	unsigned		dis_u2_freeclk_exists_quirk:1;
 
 	unsigned		tx_de_emphasis_quirk:1;
 	unsigned		tx_de_emphasis:2;
diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h
index 98d51e05e1..193d225d31 100644
--- a/include/dwc3-uboot.h
+++ b/include/dwc3-uboot.h
@@ -35,6 +35,7 @@ struct dwc3_device {
 	unsigned dis_u2_susphy_quirk;
 	unsigned dis_del_phy_power_chg_quirk;
 	unsigned dis_enblslpm_quirk;
+	unsigned dis_u2_freeclk_exists_quirk;
 	unsigned tx_de_emphasis_quirk;
 	unsigned tx_de_emphasis;
 	int index;
-- 
2.17.1

[PATCH v5 08/16] usb: dwc3: add dis_u2_freeclk_exists_quirk

[Frank Wang]

Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.

Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk")
in Linux Rockchip Kernel.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/usb/dwc3/core.c | 6 ++++++
 drivers/usb/dwc3/core.h | 2 ++
 include/dwc3-uboot.h    | 1 +
 3 files changed, 9 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 20be617fd4..3cb66515a2 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -401,6 +401,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->dis_enblslpm_quirk)
 		reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 
+	if (dwc->dis_u2_freeclk_exists_quirk)
+		reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
+
 	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 
 	mdelay(100);
@@ -723,6 +726,7 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
 	dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
 	dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk;
 	dwc->dis_enblslpm_quirk = dwc3_dev->dis_enblslpm_quirk;
+	dwc->dis_u2_freeclk_exists_quirk = dwc3_dev->dis_u2_freeclk_exists_quirk;
 
 	dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
 	if (dwc3_dev->tx_de_emphasis)
@@ -932,6 +936,8 @@ void dwc3_of_parse(struct dwc3 *dwc)
 				"snps,dis-del-phy-power-chg-quirk");
 	dwc->dis_enblslpm_quirk = dev_read_bool(dev,
 				"snps,dis_enblslpm_quirk");
+	dwc->dis_u2_freeclk_exists_quirk = dev_read_bool(dev,
+				"snps,dis-u2-freeclk-exists-quirk");
 	dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
 				"snps,tx_de_emphasis_quirk");
 	tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index e76e357f1e..c5e656885a 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -161,6 +161,7 @@
 
 /* Global USB2 PHY Configuration Register */
 #define DWC3_GUSB2PHYCFG_PHYSOFTRST	(1 << 31)
+#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS	(1 << 30)
 #define DWC3_GUSB2PHYCFG_SUSPHY		(1 << 6)
 #define DWC3_GUSB2PHYCFG_ENBLSLPM	(1 << 8)
 #define DWC3_GUSB2PHYCFG_PHYIF(n)	((n) << 3)
@@ -824,6 +825,7 @@ struct dwc3 {
 	unsigned		dis_u2_susphy_quirk:1;
 	unsigned		dis_del_phy_power_chg_quirk:1;
 	unsigned		dis_enblslpm_quirk:1;
+	unsigned		dis_u2_freeclk_exists_quirk:1;
 
 	unsigned		tx_de_emphasis_quirk:1;
 	unsigned		tx_de_emphasis:2;
diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h
index 98d51e05e1..193d225d31 100644
--- a/include/dwc3-uboot.h
+++ b/include/dwc3-uboot.h
@@ -35,6 +35,7 @@ struct dwc3_device {
 	unsigned dis_u2_susphy_quirk;
 	unsigned dis_del_phy_power_chg_quirk;
 	unsigned dis_enblslpm_quirk;
+	unsigned dis_u2_freeclk_exists_quirk;
 	unsigned tx_de_emphasis_quirk;
 	unsigned tx_de_emphasis;
 	int index;
-- 
2.17.1

[PATCH v5 09/16] usb: dwc3: Add disable u2mac linestate check quirk

[Frank Wang]

From: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>

This patch adds a quirk to disable USB 2.0 MAC linestate check
during HS transmit. Refer the dwc3 databook, we can use it for
some special platforms if the linestate not reflect the expected
line state(J) during transmission.

When use this quirk, the controller implements a fixed 40-bit
TxEndDelay after the packet is given on UTMI and ignores the
linestate during the transmit of a token (during token-to-token
and token-to-data IPGAP).

On some rockchip platforms (e.g. rk3399), it requires to disable
the u2mac linestate check to decrease the SSPLIT token to SETUP
token inter-packet delay from 566ns to 466ns, and fix the issue
that FS/LS devices not recognized if inserted through USB 3.0 HUB.

Reference from below Linux commit,

commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate
check quirk")

Cc: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 drivers/usb/dwc3/core.c | 20 ++++++++++++++++++++
 drivers/usb/dwc3/core.h |  7 +++++++
 include/dwc3-uboot.h    |  1 +
 3 files changed, 28 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 3cb66515a2..dc92f471c1 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -725,6 +725,7 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
 	dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
 	dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
 	dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk;
+	dwc->dis_tx_ipgap_linecheck_quirk = dwc3_dev->dis_tx_ipgap_linecheck_quirk;
 	dwc->dis_enblslpm_quirk = dwc3_dev->dis_enblslpm_quirk;
 	dwc->dis_u2_freeclk_exists_quirk = dwc3_dev->dis_u2_freeclk_exists_quirk;
 
@@ -934,6 +935,8 @@ void dwc3_of_parse(struct dwc3 *dwc)
 				"snps,dis_u2_susphy_quirk");
 	dwc->dis_del_phy_power_chg_quirk = dev_read_bool(dev,
 				"snps,dis-del-phy-power-chg-quirk");
+	dwc->dis_tx_ipgap_linecheck_quirk = dev_read_bool(dev,
+				"snps,dis-tx-ipgap-linecheck-quirk");
 	dwc->dis_enblslpm_quirk = dev_read_bool(dev,
 				"snps,dis_enblslpm_quirk");
 	dwc->dis_u2_freeclk_exists_quirk = dev_read_bool(dev,
@@ -954,6 +957,7 @@ void dwc3_of_parse(struct dwc3 *dwc)
 int dwc3_init(struct dwc3 *dwc)
 {
 	int ret;
+	u32 reg;
 
 	dwc3_cache_hwparams(dwc);
 
@@ -975,6 +979,22 @@ int dwc3_init(struct dwc3 *dwc)
 		goto event_fail;
 	}
 
+	if (dwc->revision >= DWC3_REVISION_250A) {
+		reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
+
+		/*
+		 * Enable hardware control of sending remote wakeup
+		 * in HS when the device is in the L1 state.
+		 */
+		if (dwc->revision >= DWC3_REVISION_290A)
+			reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
+
+		if (dwc->dis_tx_ipgap_linecheck_quirk)
+			reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
+
+		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
+	}
+
 	ret = dwc3_core_init_mode(dwc);
 	if (ret)
 		goto mode_fail;
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index c5e656885a..b510d8a983 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -73,6 +73,7 @@
 #define DWC3_GCTL		0xc110
 #define DWC3_GEVTEN		0xc114
 #define DWC3_GSTS		0xc118
+#define DWC3_GUCTL1		0xc11c
 #define DWC3_GSNPSID		0xc120
 #define DWC3_GGPIO		0xc124
 #define DWC3_GUID		0xc128
@@ -159,6 +160,10 @@
 #define DWC3_GCTL_GBLHIBERNATIONEN	(1 << 1)
 #define DWC3_GCTL_DSBLCLKGTNG		(1 << 0)
 
+/* Global User Control 1 Register */
+#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
+#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW	BIT(24)
+
 /* Global USB2 PHY Configuration Register */
 #define DWC3_GUSB2PHYCFG_PHYSOFTRST	(1 << 31)
 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS	(1 << 30)
@@ -771,6 +776,7 @@ struct dwc3 {
 #define DWC3_REVISION_260A	0x5533260a
 #define DWC3_REVISION_270A	0x5533270a
 #define DWC3_REVISION_280A	0x5533280a
+#define DWC3_REVISION_290A	0x5533290a
 
 	enum dwc3_ep0_next	ep0_next_event;
 	enum dwc3_ep0_state	ep0state;
@@ -824,6 +830,7 @@ struct dwc3 {
 	unsigned		dis_u3_susphy_quirk:1;
 	unsigned		dis_u2_susphy_quirk:1;
 	unsigned		dis_del_phy_power_chg_quirk:1;
+	unsigned		dis_tx_ipgap_linecheck_quirk:1;
 	unsigned		dis_enblslpm_quirk:1;
 	unsigned		dis_u2_freeclk_exists_quirk:1;
 
diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h
index 193d225d31..e08530ec4e 100644
--- a/include/dwc3-uboot.h
+++ b/include/dwc3-uboot.h
@@ -34,6 +34,7 @@ struct dwc3_device {
 	unsigned dis_u3_susphy_quirk;
 	unsigned dis_u2_susphy_quirk;
 	unsigned dis_del_phy_power_chg_quirk;
+	unsigned dis_tx_ipgap_linecheck_quirk;
 	unsigned dis_enblslpm_quirk;
 	unsigned dis_u2_freeclk_exists_quirk;
 	unsigned tx_de_emphasis_quirk;
-- 
2.17.1

[PATCH v5 09/16] usb: dwc3: Add disable u2mac linestate check quirk

[Frank Wang]

From: Jagan Teki <jagan@amarulasolutions.com>

This patch adds a quirk to disable USB 2.0 MAC linestate check
during HS transmit. Refer the dwc3 databook, we can use it for
some special platforms if the linestate not reflect the expected
line state(J) during transmission.

When use this quirk, the controller implements a fixed 40-bit
TxEndDelay after the packet is given on UTMI and ignores the
linestate during the transmit of a token (during token-to-token
and token-to-data IPGAP).

On some rockchip platforms (e.g. rk3399), it requires to disable
the u2mac linestate check to decrease the SSPLIT token to SETUP
token inter-packet delay from 566ns to 466ns, and fix the issue
that FS/LS devices not recognized if inserted through USB 3.0 HUB.

Reference from below Linux commit,

commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate
check quirk")

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/usb/dwc3/core.c | 20 ++++++++++++++++++++
 drivers/usb/dwc3/core.h |  7 +++++++
 include/dwc3-uboot.h    |  1 +
 3 files changed, 28 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 3cb66515a2..dc92f471c1 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -725,6 +725,7 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
 	dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
 	dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
 	dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk;
+	dwc->dis_tx_ipgap_linecheck_quirk = dwc3_dev->dis_tx_ipgap_linecheck_quirk;
 	dwc->dis_enblslpm_quirk = dwc3_dev->dis_enblslpm_quirk;
 	dwc->dis_u2_freeclk_exists_quirk = dwc3_dev->dis_u2_freeclk_exists_quirk;
 
@@ -934,6 +935,8 @@ void dwc3_of_parse(struct dwc3 *dwc)
 				"snps,dis_u2_susphy_quirk");
 	dwc->dis_del_phy_power_chg_quirk = dev_read_bool(dev,
 				"snps,dis-del-phy-power-chg-quirk");
+	dwc->dis_tx_ipgap_linecheck_quirk = dev_read_bool(dev,
+				"snps,dis-tx-ipgap-linecheck-quirk");
 	dwc->dis_enblslpm_quirk = dev_read_bool(dev,
 				"snps,dis_enblslpm_quirk");
 	dwc->dis_u2_freeclk_exists_quirk = dev_read_bool(dev,
@@ -954,6 +957,7 @@ void dwc3_of_parse(struct dwc3 *dwc)
 int dwc3_init(struct dwc3 *dwc)
 {
 	int ret;
+	u32 reg;
 
 	dwc3_cache_hwparams(dwc);
 
@@ -975,6 +979,22 @@ int dwc3_init(struct dwc3 *dwc)
 		goto event_fail;
 	}
 
+	if (dwc->revision >= DWC3_REVISION_250A) {
+		reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
+
+		/*
+		 * Enable hardware control of sending remote wakeup
+		 * in HS when the device is in the L1 state.
+		 */
+		if (dwc->revision >= DWC3_REVISION_290A)
+			reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
+
+		if (dwc->dis_tx_ipgap_linecheck_quirk)
+			reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
+
+		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
+	}
+
 	ret = dwc3_core_init_mode(dwc);
 	if (ret)
 		goto mode_fail;
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index c5e656885a..b510d8a983 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -73,6 +73,7 @@
 #define DWC3_GCTL		0xc110
 #define DWC3_GEVTEN		0xc114
 #define DWC3_GSTS		0xc118
+#define DWC3_GUCTL1		0xc11c
 #define DWC3_GSNPSID		0xc120
 #define DWC3_GGPIO		0xc124
 #define DWC3_GUID		0xc128
@@ -159,6 +160,10 @@
 #define DWC3_GCTL_GBLHIBERNATIONEN	(1 << 1)
 #define DWC3_GCTL_DSBLCLKGTNG		(1 << 0)
 
+/* Global User Control 1 Register */
+#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
+#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW	BIT(24)
+
 /* Global USB2 PHY Configuration Register */
 #define DWC3_GUSB2PHYCFG_PHYSOFTRST	(1 << 31)
 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS	(1 << 30)
@@ -771,6 +776,7 @@ struct dwc3 {
 #define DWC3_REVISION_260A	0x5533260a
 #define DWC3_REVISION_270A	0x5533270a
 #define DWC3_REVISION_280A	0x5533280a
+#define DWC3_REVISION_290A	0x5533290a
 
 	enum dwc3_ep0_next	ep0_next_event;
 	enum dwc3_ep0_state	ep0state;
@@ -824,6 +830,7 @@ struct dwc3 {
 	unsigned		dis_u3_susphy_quirk:1;
 	unsigned		dis_u2_susphy_quirk:1;
 	unsigned		dis_del_phy_power_chg_quirk:1;
+	unsigned		dis_tx_ipgap_linecheck_quirk:1;
 	unsigned		dis_enblslpm_quirk:1;
 	unsigned		dis_u2_freeclk_exists_quirk:1;
 
diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h
index 193d225d31..e08530ec4e 100644
--- a/include/dwc3-uboot.h
+++ b/include/dwc3-uboot.h
@@ -34,6 +34,7 @@ struct dwc3_device {
 	unsigned dis_u3_susphy_quirk;
 	unsigned dis_u2_susphy_quirk;
 	unsigned dis_del_phy_power_chg_quirk;
+	unsigned dis_tx_ipgap_linecheck_quirk;
 	unsigned dis_enblslpm_quirk;
 	unsigned dis_u2_freeclk_exists_quirk;
 	unsigned tx_de_emphasis_quirk;
-- 
2.17.1

Re: [PATCH v5 09/16] usb: dwc3: Add disable u2mac linestate check quirk

[Kever Yang]

On 2020/5/13 下午3:15, Frank Wang wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> This patch adds a quirk to disable USB 2.0 MAC linestate check
> during HS transmit. Refer the dwc3 databook, we can use it for
> some special platforms if the linestate not reflect the expected
> line state(J) during transmission.
>
> When use this quirk, the controller implements a fixed 40-bit
> TxEndDelay after the packet is given on UTMI and ignores the
> linestate during the transmit of a token (during token-to-token
> and token-to-data IPGAP).
>
> On some rockchip platforms (e.g. rk3399), it requires to disable
> the u2mac linestate check to decrease the SSPLIT token to SETUP
> token inter-packet delay from 566ns to 466ns, and fix the issue
> that FS/LS devices not recognized if inserted through USB 3.0 HUB.
>
> Reference from below Linux commit,
>
> commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate
> check quirk")
>
> Cc: Marek Vasut <marex@denx.de>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/usb/dwc3/core.c | 20 ++++++++++++++++++++
>   drivers/usb/dwc3/core.h |  7 +++++++
>   include/dwc3-uboot.h    |  1 +
>   3 files changed, 28 insertions(+)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 3cb66515a2..dc92f471c1 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -725,6 +725,7 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
>   	dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
>   	dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
>   	dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk;
> +	dwc->dis_tx_ipgap_linecheck_quirk = dwc3_dev->dis_tx_ipgap_linecheck_quirk;
>   	dwc->dis_enblslpm_quirk = dwc3_dev->dis_enblslpm_quirk;
>   	dwc->dis_u2_freeclk_exists_quirk = dwc3_dev->dis_u2_freeclk_exists_quirk;
>   
> @@ -934,6 +935,8 @@ void dwc3_of_parse(struct dwc3 *dwc)
>   				"snps,dis_u2_susphy_quirk");
>   	dwc->dis_del_phy_power_chg_quirk = dev_read_bool(dev,
>   				"snps,dis-del-phy-power-chg-quirk");
> +	dwc->dis_tx_ipgap_linecheck_quirk = dev_read_bool(dev,
> +				"snps,dis-tx-ipgap-linecheck-quirk");
>   	dwc->dis_enblslpm_quirk = dev_read_bool(dev,
>   				"snps,dis_enblslpm_quirk");
>   	dwc->dis_u2_freeclk_exists_quirk = dev_read_bool(dev,
> @@ -954,6 +957,7 @@ void dwc3_of_parse(struct dwc3 *dwc)
>   int dwc3_init(struct dwc3 *dwc)
>   {
>   	int ret;
> +	u32 reg;
>   
>   	dwc3_cache_hwparams(dwc);
>   
> @@ -975,6 +979,22 @@ int dwc3_init(struct dwc3 *dwc)
>   		goto event_fail;
>   	}
>   
> +	if (dwc->revision >= DWC3_REVISION_250A) {
> +		reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
> +
> +		/*
> +		 * Enable hardware control of sending remote wakeup
> +		 * in HS when the device is in the L1 state.
> +		 */
> +		if (dwc->revision >= DWC3_REVISION_290A)
> +			reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
> +
> +		if (dwc->dis_tx_ipgap_linecheck_quirk)
> +			reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
> +
> +		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
> +	}
> +
>   	ret = dwc3_core_init_mode(dwc);
>   	if (ret)
>   		goto mode_fail;
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index c5e656885a..b510d8a983 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -73,6 +73,7 @@
>   #define DWC3_GCTL		0xc110
>   #define DWC3_GEVTEN		0xc114
>   #define DWC3_GSTS		0xc118
> +#define DWC3_GUCTL1		0xc11c
>   #define DWC3_GSNPSID		0xc120
>   #define DWC3_GGPIO		0xc124
>   #define DWC3_GUID		0xc128
> @@ -159,6 +160,10 @@
>   #define DWC3_GCTL_GBLHIBERNATIONEN	(1 << 1)
>   #define DWC3_GCTL_DSBLCLKGTNG		(1 << 0)
>   
> +/* Global User Control 1 Register */
> +#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
> +#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW	BIT(24)
> +
>   /* Global USB2 PHY Configuration Register */
>   #define DWC3_GUSB2PHYCFG_PHYSOFTRST	(1 << 31)
>   #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS	(1 << 30)
> @@ -771,6 +776,7 @@ struct dwc3 {
>   #define DWC3_REVISION_260A	0x5533260a
>   #define DWC3_REVISION_270A	0x5533270a
>   #define DWC3_REVISION_280A	0x5533280a
> +#define DWC3_REVISION_290A	0x5533290a
>   
>   	enum dwc3_ep0_next	ep0_next_event;
>   	enum dwc3_ep0_state	ep0state;
> @@ -824,6 +830,7 @@ struct dwc3 {
>   	unsigned		dis_u3_susphy_quirk:1;
>   	unsigned		dis_u2_susphy_quirk:1;
>   	unsigned		dis_del_phy_power_chg_quirk:1;
> +	unsigned		dis_tx_ipgap_linecheck_quirk:1;
>   	unsigned		dis_enblslpm_quirk:1;
>   	unsigned		dis_u2_freeclk_exists_quirk:1;
>   
> diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h
> index 193d225d31..e08530ec4e 100644
> --- a/include/dwc3-uboot.h
> +++ b/include/dwc3-uboot.h
> @@ -34,6 +34,7 @@ struct dwc3_device {
>   	unsigned dis_u3_susphy_quirk;
>   	unsigned dis_u2_susphy_quirk;
>   	unsigned dis_del_phy_power_chg_quirk;
> +	unsigned dis_tx_ipgap_linecheck_quirk;
>   	unsigned dis_enblslpm_quirk;
>   	unsigned dis_u2_freeclk_exists_quirk;
>   	unsigned tx_de_emphasis_quirk;



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[PATCH v5 09/16] usb: dwc3: Add disable u2mac linestate check quirk

[Kever Yang]

On 2020/5/13 ??3:15, Frank Wang wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> This patch adds a quirk to disable USB 2.0 MAC linestate check
> during HS transmit. Refer the dwc3 databook, we can use it for
> some special platforms if the linestate not reflect the expected
> line state(J) during transmission.
>
> When use this quirk, the controller implements a fixed 40-bit
> TxEndDelay after the packet is given on UTMI and ignores the
> linestate during the transmit of a token (during token-to-token
> and token-to-data IPGAP).
>
> On some rockchip platforms (e.g. rk3399), it requires to disable
> the u2mac linestate check to decrease the SSPLIT token to SETUP
> token inter-packet delay from 566ns to 466ns, and fix the issue
> that FS/LS devices not recognized if inserted through USB 3.0 HUB.
>
> Reference from below Linux commit,
>
> commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate
> check quirk")
>
> Cc: Marek Vasut <marex@denx.de>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/usb/dwc3/core.c | 20 ++++++++++++++++++++
>   drivers/usb/dwc3/core.h |  7 +++++++
>   include/dwc3-uboot.h    |  1 +
>   3 files changed, 28 insertions(+)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 3cb66515a2..dc92f471c1 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -725,6 +725,7 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
>   	dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
>   	dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
>   	dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk;
> +	dwc->dis_tx_ipgap_linecheck_quirk = dwc3_dev->dis_tx_ipgap_linecheck_quirk;
>   	dwc->dis_enblslpm_quirk = dwc3_dev->dis_enblslpm_quirk;
>   	dwc->dis_u2_freeclk_exists_quirk = dwc3_dev->dis_u2_freeclk_exists_quirk;
>   
> @@ -934,6 +935,8 @@ void dwc3_of_parse(struct dwc3 *dwc)
>   				"snps,dis_u2_susphy_quirk");
>   	dwc->dis_del_phy_power_chg_quirk = dev_read_bool(dev,
>   				"snps,dis-del-phy-power-chg-quirk");
> +	dwc->dis_tx_ipgap_linecheck_quirk = dev_read_bool(dev,
> +				"snps,dis-tx-ipgap-linecheck-quirk");
>   	dwc->dis_enblslpm_quirk = dev_read_bool(dev,
>   				"snps,dis_enblslpm_quirk");
>   	dwc->dis_u2_freeclk_exists_quirk = dev_read_bool(dev,
> @@ -954,6 +957,7 @@ void dwc3_of_parse(struct dwc3 *dwc)
>   int dwc3_init(struct dwc3 *dwc)
>   {
>   	int ret;
> +	u32 reg;
>   
>   	dwc3_cache_hwparams(dwc);
>   
> @@ -975,6 +979,22 @@ int dwc3_init(struct dwc3 *dwc)
>   		goto event_fail;
>   	}
>   
> +	if (dwc->revision >= DWC3_REVISION_250A) {
> +		reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
> +
> +		/*
> +		 * Enable hardware control of sending remote wakeup
> +		 * in HS when the device is in the L1 state.
> +		 */
> +		if (dwc->revision >= DWC3_REVISION_290A)
> +			reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
> +
> +		if (dwc->dis_tx_ipgap_linecheck_quirk)
> +			reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
> +
> +		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
> +	}
> +
>   	ret = dwc3_core_init_mode(dwc);
>   	if (ret)
>   		goto mode_fail;
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index c5e656885a..b510d8a983 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -73,6 +73,7 @@
>   #define DWC3_GCTL		0xc110
>   #define DWC3_GEVTEN		0xc114
>   #define DWC3_GSTS		0xc118
> +#define DWC3_GUCTL1		0xc11c
>   #define DWC3_GSNPSID		0xc120
>   #define DWC3_GGPIO		0xc124
>   #define DWC3_GUID		0xc128
> @@ -159,6 +160,10 @@
>   #define DWC3_GCTL_GBLHIBERNATIONEN	(1 << 1)
>   #define DWC3_GCTL_DSBLCLKGTNG		(1 << 0)
>   
> +/* Global User Control 1 Register */
> +#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
> +#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW	BIT(24)
> +
>   /* Global USB2 PHY Configuration Register */
>   #define DWC3_GUSB2PHYCFG_PHYSOFTRST	(1 << 31)
>   #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS	(1 << 30)
> @@ -771,6 +776,7 @@ struct dwc3 {
>   #define DWC3_REVISION_260A	0x5533260a
>   #define DWC3_REVISION_270A	0x5533270a
>   #define DWC3_REVISION_280A	0x5533280a
> +#define DWC3_REVISION_290A	0x5533290a
>   
>   	enum dwc3_ep0_next	ep0_next_event;
>   	enum dwc3_ep0_state	ep0state;
> @@ -824,6 +830,7 @@ struct dwc3 {
>   	unsigned		dis_u3_susphy_quirk:1;
>   	unsigned		dis_u2_susphy_quirk:1;
>   	unsigned		dis_del_phy_power_chg_quirk:1;
> +	unsigned		dis_tx_ipgap_linecheck_quirk:1;
>   	unsigned		dis_enblslpm_quirk:1;
>   	unsigned		dis_u2_freeclk_exists_quirk:1;
>   
> diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h
> index 193d225d31..e08530ec4e 100644
> --- a/include/dwc3-uboot.h
> +++ b/include/dwc3-uboot.h
> @@ -34,6 +34,7 @@ struct dwc3_device {
>   	unsigned dis_u3_susphy_quirk;
>   	unsigned dis_u2_susphy_quirk;
>   	unsigned dis_del_phy_power_chg_quirk;
> +	unsigned dis_tx_ipgap_linecheck_quirk;
>   	unsigned dis_enblslpm_quirk;
>   	unsigned dis_u2_freeclk_exists_quirk;
>   	unsigned tx_de_emphasis_quirk;

Re: [PATCH v5 05/16] arm64: dts: rk3399: Move u2phy into root port

[Kever Yang]

Hi Jagan, Frank,

On 2020/5/13 下午3:15, Frank Wang wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Yes, This is changing the actual device tree u2phy
> structure but the problem with the current Generic
> PHY subsystem is unable to find PHY if the PHY node
> is not part of the root structure.

I don't understand for this, it should be able to bind the device when

dm scan fdt.

Rockchip code always can use this node directly without modify, could

you check again?


Thanks,

- Kever

>
> This will be reverted,
> - Once we support the PHY subsystem to get the PHY
>    even though it is not part of the root node or
> - any other relevant solution that get the phy
>    directly without traversing all nodes.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
>   arch/arm/dts/rk3399.dtsi | 108 +++++++++++++++++++--------------------
>   1 file changed, 54 insertions(+), 54 deletions(-)
>
> diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
> index 74f2c3d490..6c77f25f23 100644
> --- a/arch/arm/dts/rk3399.dtsi
> +++ b/arch/arm/dts/rk3399.dtsi
> @@ -1387,60 +1387,6 @@
>   			status = "disabled";
>   		};
>   
> -		u2phy0: usb2-phy@e450 {
> -			compatible = "rockchip,rk3399-usb2phy";
> -			reg = <0xe450 0x10>;
> -			clocks = <&cru SCLK_USB2PHY0_REF>;
> -			clock-names = "phyclk";
> -			#clock-cells = <0>;
> -			clock-output-names = "clk_usbphy0_480m";
> -			status = "disabled";
> -
> -			u2phy0_host: host-port {
> -				#phy-cells = <0>;
> -				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
> -				interrupt-names = "linestate";
> -				status = "disabled";
> -			};
> -
> -			u2phy0_otg: otg-port {
> -				#phy-cells = <0>;
> -				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
> -					     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
> -					     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
> -				interrupt-names = "otg-bvalid", "otg-id",
> -						  "linestate";
> -				status = "disabled";
> -			};
> -		};
> -
> -		u2phy1: usb2-phy@e460 {
> -			compatible = "rockchip,rk3399-usb2phy";
> -			reg = <0xe460 0x10>;
> -			clocks = <&cru SCLK_USB2PHY1_REF>;
> -			clock-names = "phyclk";
> -			#clock-cells = <0>;
> -			clock-output-names = "clk_usbphy1_480m";
> -			status = "disabled";
> -
> -			u2phy1_host: host-port {
> -				#phy-cells = <0>;
> -				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
> -				interrupt-names = "linestate";
> -				status = "disabled";
> -			};
> -
> -			u2phy1_otg: otg-port {
> -				#phy-cells = <0>;
> -				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
> -					     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
> -					     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
> -				interrupt-names = "otg-bvalid", "otg-id",
> -						  "linestate";
> -				status = "disabled";
> -			};
> -		};
> -
>   		emmc_phy: phy@f780 {
>   			compatible = "rockchip,rk3399-emmc-phy";
>   			reg = <0xf780 0x24>;
> @@ -1462,6 +1408,60 @@
>   		};
>   	};
>   
> +	u2phy0: usb2-phy@e450 {
> +		compatible = "rockchip,rk3399-usb2phy";
> +		reg = <0x0 0xe450 0x0 0x10>;
> +		clocks = <&cru SCLK_USB2PHY0_REF>;
> +		clock-names = "phyclk";
> +		#clock-cells = <0>;
> +		clock-output-names = "clk_usbphy0_480m";
> +		status = "disabled";
> +
> +		u2phy0_host: host-port {
> +			#phy-cells = <0>;
> +			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "linestate";
> +			status = "disabled";
> +		};
> +
> +		u2phy0_otg: otg-port {
> +			#phy-cells = <0>;
> +			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
> +				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
> +				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "otg-bvalid", "otg-id",
> +					  "linestate";
> +			status = "disabled";
> +		};
> +	};
> +
> +	u2phy1: usb2-phy@e460 {
> +		compatible = "rockchip,rk3399-usb2phy";
> +		reg = <0x0 0xe460 0x0 0x10>;
> +		clocks = <&cru SCLK_USB2PHY1_REF>;
> +		clock-names = "phyclk";
> +		#clock-cells = <0>;
> +		clock-output-names = "clk_usbphy1_480m";
> +		status = "disabled";
> +
> +		u2phy1_host: host-port {
> +			#phy-cells = <0>;
> +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "linestate";
> +			status = "disabled";
> +		};
> +
> +		u2phy1_otg: otg-port {
> +			#phy-cells = <0>;
> +			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
> +				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
> +				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "otg-bvalid", "otg-id",
> +					  "linestate";
> +			status = "disabled";
> +		};
> +	};
> +
>   	tcphy0: phy@ff7c0000 {
>   		compatible = "rockchip,rk3399-typec-phy";
>   		reg = <0x0 0xff7c0000 0x0 0x40000>;



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[PATCH v5 05/16] arm64: dts: rk3399: Move u2phy into root port

[Kever Yang]

Hi Jagan, Frank,

On 2020/5/13 ??3:15, Frank Wang wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Yes, This is changing the actual device tree u2phy
> structure but the problem with the current Generic
> PHY subsystem is unable to find PHY if the PHY node
> is not part of the root structure.

I don't understand for this, it should be able to bind the device when

dm scan fdt.

Rockchip code always can use this node directly without modify, could

you check again?


Thanks,

- Kever

>
> This will be reverted,
> - Once we support the PHY subsystem to get the PHY
>    even though it is not part of the root node or
> - any other relevant solution that get the phy
>    directly without traversing all nodes.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
>   arch/arm/dts/rk3399.dtsi | 108 +++++++++++++++++++--------------------
>   1 file changed, 54 insertions(+), 54 deletions(-)
>
> diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
> index 74f2c3d490..6c77f25f23 100644
> --- a/arch/arm/dts/rk3399.dtsi
> +++ b/arch/arm/dts/rk3399.dtsi
> @@ -1387,60 +1387,6 @@
>   			status = "disabled";
>   		};
>   
> -		u2phy0: usb2-phy at e450 {
> -			compatible = "rockchip,rk3399-usb2phy";
> -			reg = <0xe450 0x10>;
> -			clocks = <&cru SCLK_USB2PHY0_REF>;
> -			clock-names = "phyclk";
> -			#clock-cells = <0>;
> -			clock-output-names = "clk_usbphy0_480m";
> -			status = "disabled";
> -
> -			u2phy0_host: host-port {
> -				#phy-cells = <0>;
> -				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
> -				interrupt-names = "linestate";
> -				status = "disabled";
> -			};
> -
> -			u2phy0_otg: otg-port {
> -				#phy-cells = <0>;
> -				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
> -					     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
> -					     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
> -				interrupt-names = "otg-bvalid", "otg-id",
> -						  "linestate";
> -				status = "disabled";
> -			};
> -		};
> -
> -		u2phy1: usb2-phy at e460 {
> -			compatible = "rockchip,rk3399-usb2phy";
> -			reg = <0xe460 0x10>;
> -			clocks = <&cru SCLK_USB2PHY1_REF>;
> -			clock-names = "phyclk";
> -			#clock-cells = <0>;
> -			clock-output-names = "clk_usbphy1_480m";
> -			status = "disabled";
> -
> -			u2phy1_host: host-port {
> -				#phy-cells = <0>;
> -				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
> -				interrupt-names = "linestate";
> -				status = "disabled";
> -			};
> -
> -			u2phy1_otg: otg-port {
> -				#phy-cells = <0>;
> -				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
> -					     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
> -					     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
> -				interrupt-names = "otg-bvalid", "otg-id",
> -						  "linestate";
> -				status = "disabled";
> -			};
> -		};
> -
>   		emmc_phy: phy at f780 {
>   			compatible = "rockchip,rk3399-emmc-phy";
>   			reg = <0xf780 0x24>;
> @@ -1462,6 +1408,60 @@
>   		};
>   	};
>   
> +	u2phy0: usb2-phy at e450 {
> +		compatible = "rockchip,rk3399-usb2phy";
> +		reg = <0x0 0xe450 0x0 0x10>;
> +		clocks = <&cru SCLK_USB2PHY0_REF>;
> +		clock-names = "phyclk";
> +		#clock-cells = <0>;
> +		clock-output-names = "clk_usbphy0_480m";
> +		status = "disabled";
> +
> +		u2phy0_host: host-port {
> +			#phy-cells = <0>;
> +			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "linestate";
> +			status = "disabled";
> +		};
> +
> +		u2phy0_otg: otg-port {
> +			#phy-cells = <0>;
> +			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
> +				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
> +				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "otg-bvalid", "otg-id",
> +					  "linestate";
> +			status = "disabled";
> +		};
> +	};
> +
> +	u2phy1: usb2-phy at e460 {
> +		compatible = "rockchip,rk3399-usb2phy";
> +		reg = <0x0 0xe460 0x0 0x10>;
> +		clocks = <&cru SCLK_USB2PHY1_REF>;
> +		clock-names = "phyclk";
> +		#clock-cells = <0>;
> +		clock-output-names = "clk_usbphy1_480m";
> +		status = "disabled";
> +
> +		u2phy1_host: host-port {
> +			#phy-cells = <0>;
> +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "linestate";
> +			status = "disabled";
> +		};
> +
> +		u2phy1_otg: otg-port {
> +			#phy-cells = <0>;
> +			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
> +				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
> +				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "otg-bvalid", "otg-id",
> +					  "linestate";
> +			status = "disabled";
> +		};
> +	};
> +
>   	tcphy0: phy at ff7c0000 {
>   		compatible = "rockchip,rk3399-typec-phy";
>   		reg = <0x0 0xff7c0000 0x0 0x40000>;

Re: [PATCH v5 05/16] arm64: dts: rk3399: Move u2phy into root port

[Frank Wang]

Hi Jagan, Kever,

On 2020/5/15 10:40, Kever Yang wrote:
> Hi Jagan, Frank,
>
> On 2020/5/13 下午3:15, Frank Wang wrote:
>> From: Jagan Teki <jagan@amarulasolutions.com>
>>
>> Yes, This is changing the actual device tree u2phy
>> structure but the problem with the current Generic
>> PHY subsystem is unable to find PHY if the PHY node
>> is not part of the root structure.
>
> I don't understand for this, it should be able to bind the device when
>
> dm scan fdt.
>
> Rockchip code always can use this node directly without modify, could
>
> you check again?
>

Sub-nodes under grf were not scanned recursively since dm_scan_fdt_dev 
is not assigned to rk3399_syscon driver's bind in Upstream codes .

I have fixed it and updated all changed for patch v6, please refer to 
below links.

https://patchwork.ozlabs.org/project/uboot/cover/20200526033220.20047-1-frank.wang@rock-chips.com/


BR,
Frank

> Thanks,
>
> - Kever
>
>>
>> This will be reverted,
>> - Once we support the PHY subsystem to get the PHY
>>    even though it is not part of the root node or
>> - any other relevant solution that get the phy
>>    directly without traversing all nodes.
>>
>> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>> ---
>>   arch/arm/dts/rk3399.dtsi | 108 +++++++++++++++++++--------------------
>>   1 file changed, 54 insertions(+), 54 deletions(-)
>>
>> diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
>> index 74f2c3d490..6c77f25f23 100644
>> --- a/arch/arm/dts/rk3399.dtsi
>> +++ b/arch/arm/dts/rk3399.dtsi
>> @@ -1387,60 +1387,6 @@
>>               status = "disabled";
>>           };
>>   -        u2phy0: usb2-phy@e450 {
>> -            compatible = "rockchip,rk3399-usb2phy";
>> -            reg = <0xe450 0x10>;
>> -            clocks = <&cru SCLK_USB2PHY0_REF>;
>> -            clock-names = "phyclk";
>> -            #clock-cells = <0>;
>> -            clock-output-names = "clk_usbphy0_480m";
>> -            status = "disabled";
>> -
>> -            u2phy0_host: host-port {
>> -                #phy-cells = <0>;
>> -                interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
>> -                interrupt-names = "linestate";
>> -                status = "disabled";
>> -            };
>> -
>> -            u2phy0_otg: otg-port {
>> -                #phy-cells = <0>;
>> -                interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
>> -                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
>> -                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
>> -                interrupt-names = "otg-bvalid", "otg-id",
>> -                          "linestate";
>> -                status = "disabled";
>> -            };
>> -        };
>> -
>> -        u2phy1: usb2-phy@e460 {
>> -            compatible = "rockchip,rk3399-usb2phy";
>> -            reg = <0xe460 0x10>;
>> -            clocks = <&cru SCLK_USB2PHY1_REF>;
>> -            clock-names = "phyclk";
>> -            #clock-cells = <0>;
>> -            clock-output-names = "clk_usbphy1_480m";
>> -            status = "disabled";
>> -
>> -            u2phy1_host: host-port {
>> -                #phy-cells = <0>;
>> -                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
>> -                interrupt-names = "linestate";
>> -                status = "disabled";
>> -            };
>> -
>> -            u2phy1_otg: otg-port {
>> -                #phy-cells = <0>;
>> -                interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
>> -                         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
>> -                         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
>> -                interrupt-names = "otg-bvalid", "otg-id",
>> -                          "linestate";
>> -                status = "disabled";
>> -            };
>> -        };
>> -
>>           emmc_phy: phy@f780 {
>>               compatible = "rockchip,rk3399-emmc-phy";
>>               reg = <0xf780 0x24>;
>> @@ -1462,6 +1408,60 @@
>>           };
>>       };
>>   +    u2phy0: usb2-phy@e450 {
>> +        compatible = "rockchip,rk3399-usb2phy";
>> +        reg = <0x0 0xe450 0x0 0x10>;
>> +        clocks = <&cru SCLK_USB2PHY0_REF>;
>> +        clock-names = "phyclk";
>> +        #clock-cells = <0>;
>> +        clock-output-names = "clk_usbphy0_480m";
>> +        status = "disabled";
>> +
>> +        u2phy0_host: host-port {
>> +            #phy-cells = <0>;
>> +            interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            interrupt-names = "linestate";
>> +            status = "disabled";
>> +        };
>> +
>> +        u2phy0_otg: otg-port {
>> +            #phy-cells = <0>;
>> +            interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
>> +                     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
>> +                     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            interrupt-names = "otg-bvalid", "otg-id",
>> +                      "linestate";
>> +            status = "disabled";
>> +        };
>> +    };
>> +
>> +    u2phy1: usb2-phy@e460 {
>> +        compatible = "rockchip,rk3399-usb2phy";
>> +        reg = <0x0 0xe460 0x0 0x10>;
>> +        clocks = <&cru SCLK_USB2PHY1_REF>;
>> +        clock-names = "phyclk";
>> +        #clock-cells = <0>;
>> +        clock-output-names = "clk_usbphy1_480m";
>> +        status = "disabled";
>> +
>> +        u2phy1_host: host-port {
>> +            #phy-cells = <0>;
>> +            interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            interrupt-names = "linestate";
>> +            status = "disabled";
>> +        };
>> +
>> +        u2phy1_otg: otg-port {
>> +            #phy-cells = <0>;
>> +            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
>> +                     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
>> +                     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            interrupt-names = "otg-bvalid", "otg-id",
>> +                      "linestate";
>> +            status = "disabled";
>> +        };
>> +    };
>> +
>>       tcphy0: phy@ff7c0000 {
>>           compatible = "rockchip,rk3399-typec-phy";
>>           reg = <0x0 0xff7c0000 0x0 0x40000>;
>
>




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[PATCH v5 05/16] arm64: dts: rk3399: Move u2phy into root port

[Frank Wang]

Hi Jagan, Kever,

On 2020/5/15 10:40, Kever Yang wrote:
> Hi Jagan, Frank,
>
> On 2020/5/13 ??3:15, Frank Wang wrote:
>> From: Jagan Teki <jagan@amarulasolutions.com>
>>
>> Yes, This is changing the actual device tree u2phy
>> structure but the problem with the current Generic
>> PHY subsystem is unable to find PHY if the PHY node
>> is not part of the root structure.
>
> I don't understand for this, it should be able to bind the device when
>
> dm scan fdt.
>
> Rockchip code always can use this node directly without modify, could
>
> you check again?
>

Sub-nodes under grf were not scanned recursively since dm_scan_fdt_dev 
is not assigned to rk3399_syscon driver's bind in Upstream codes .

I have fixed it and updated all changed for patch v6, please refer to 
below links.

https://patchwork.ozlabs.org/project/uboot/cover/20200526033220.20047-1-frank.wang at rock-chips.com/


BR,
Frank

> Thanks,
>
> - Kever
>
>>
>> This will be reverted,
>> - Once we support the PHY subsystem to get the PHY
>> ?? even though it is not part of the root node or
>> - any other relevant solution that get the phy
>> ?? directly without traversing all nodes.
>>
>> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>> ---
>> ? arch/arm/dts/rk3399.dtsi | 108 +++++++++++++++++++--------------------
>> ? 1 file changed, 54 insertions(+), 54 deletions(-)
>>
>> diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
>> index 74f2c3d490..6c77f25f23 100644
>> --- a/arch/arm/dts/rk3399.dtsi
>> +++ b/arch/arm/dts/rk3399.dtsi
>> @@ -1387,60 +1387,6 @@
>> ????????????? status = "disabled";
>> ????????? };
>> ? -??????? u2phy0: usb2-phy at e450 {
>> -??????????? compatible = "rockchip,rk3399-usb2phy";
>> -??????????? reg = <0xe450 0x10>;
>> -??????????? clocks = <&cru SCLK_USB2PHY0_REF>;
>> -??????????? clock-names = "phyclk";
>> -??????????? #clock-cells = <0>;
>> -??????????? clock-output-names = "clk_usbphy0_480m";
>> -??????????? status = "disabled";
>> -
>> -??????????? u2phy0_host: host-port {
>> -??????????????? #phy-cells = <0>;
>> -??????????????? interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
>> -??????????????? interrupt-names = "linestate";
>> -??????????????? status = "disabled";
>> -??????????? };
>> -
>> -??????????? u2phy0_otg: otg-port {
>> -??????????????? #phy-cells = <0>;
>> -??????????????? interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
>> -???????????????????????? <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
>> -???????????????????????? <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
>> -??????????????? interrupt-names = "otg-bvalid", "otg-id",
>> -????????????????????????? "linestate";
>> -??????????????? status = "disabled";
>> -??????????? };
>> -??????? };
>> -
>> -??????? u2phy1: usb2-phy at e460 {
>> -??????????? compatible = "rockchip,rk3399-usb2phy";
>> -??????????? reg = <0xe460 0x10>;
>> -??????????? clocks = <&cru SCLK_USB2PHY1_REF>;
>> -??????????? clock-names = "phyclk";
>> -??????????? #clock-cells = <0>;
>> -??????????? clock-output-names = "clk_usbphy1_480m";
>> -??????????? status = "disabled";
>> -
>> -??????????? u2phy1_host: host-port {
>> -??????????????? #phy-cells = <0>;
>> -??????????????? interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
>> -??????????????? interrupt-names = "linestate";
>> -??????????????? status = "disabled";
>> -??????????? };
>> -
>> -??????????? u2phy1_otg: otg-port {
>> -??????????????? #phy-cells = <0>;
>> -??????????????? interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
>> -???????????????????????? <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
>> -???????????????????????? <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
>> -??????????????? interrupt-names = "otg-bvalid", "otg-id",
>> -????????????????????????? "linestate";
>> -??????????????? status = "disabled";
>> -??????????? };
>> -??????? };
>> -
>> ????????? emmc_phy: phy at f780 {
>> ????????????? compatible = "rockchip,rk3399-emmc-phy";
>> ????????????? reg = <0xf780 0x24>;
>> @@ -1462,6 +1408,60 @@
>> ????????? };
>> ????? };
>> ? +??? u2phy0: usb2-phy at e450 {
>> +??????? compatible = "rockchip,rk3399-usb2phy";
>> +??????? reg = <0x0 0xe450 0x0 0x10>;
>> +??????? clocks = <&cru SCLK_USB2PHY0_REF>;
>> +??????? clock-names = "phyclk";
>> +??????? #clock-cells = <0>;
>> +??????? clock-output-names = "clk_usbphy0_480m";
>> +??????? status = "disabled";
>> +
>> +??????? u2phy0_host: host-port {
>> +??????????? #phy-cells = <0>;
>> +??????????? interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
>> +??????????? interrupt-names = "linestate";
>> +??????????? status = "disabled";
>> +??????? };
>> +
>> +??????? u2phy0_otg: otg-port {
>> +??????????? #phy-cells = <0>;
>> +??????????? interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
>> +???????????????????? <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
>> +???????????????????? <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
>> +??????????? interrupt-names = "otg-bvalid", "otg-id",
>> +????????????????????? "linestate";
>> +??????????? status = "disabled";
>> +??????? };
>> +??? };
>> +
>> +??? u2phy1: usb2-phy at e460 {
>> +??????? compatible = "rockchip,rk3399-usb2phy";
>> +??????? reg = <0x0 0xe460 0x0 0x10>;
>> +??????? clocks = <&cru SCLK_USB2PHY1_REF>;
>> +??????? clock-names = "phyclk";
>> +??????? #clock-cells = <0>;
>> +??????? clock-output-names = "clk_usbphy1_480m";
>> +??????? status = "disabled";
>> +
>> +??????? u2phy1_host: host-port {
>> +??????????? #phy-cells = <0>;
>> +??????????? interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
>> +??????????? interrupt-names = "linestate";
>> +??????????? status = "disabled";
>> +??????? };
>> +
>> +??????? u2phy1_otg: otg-port {
>> +??????????? #phy-cells = <0>;
>> +??????????? interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
>> +???????????????????? <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
>> +???????????????????? <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
>> +??????????? interrupt-names = "otg-bvalid", "otg-id",
>> +????????????????????? "linestate";
>> +??????????? status = "disabled";
>> +??????? };
>> +??? };
>> +
>> ????? tcphy0: phy at ff7c0000 {
>> ????????? compatible = "rockchip,rk3399-typec-phy";
>> ????????? reg = <0x0 0xff7c0000 0x0 0x40000>;
>
>

[PATCH v5 10/16] usb: dwc3: Enable AutoRetry feature in the controller

[Frank Wang]

From: Jagan Teki <jagan@amarulasolutions.com>

By default when core sees any transaction error (CRC or overflow) it
replies with terminating retry ACK (Retry=1 and Nump == 0).

Enabling this Auto Retry feature in controller will make the core send
a non-terminanting ACK upon such transaction errors. That is, ACK TP
with Retry=1 and Nump != 0.

Doing so will give controller a chance to recover from transient error
conditions.

Reference from below Linux commit,

commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature
in the controller")

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/usb/dwc3/core.c | 9 +++++++++
 drivers/usb/dwc3/core.h | 3 +++
 2 files changed, 12 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index dc92f471c1..aab6c34c2d 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -995,6 +995,15 @@ int dwc3_init(struct dwc3 *dwc)
 		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
 	}
 
+	if (dwc->dr_mode == USB_DR_MODE_HOST ||
+	    dwc->dr_mode == USB_DR_MODE_OTG) {
+		reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
+
+		reg |= DWC3_GUCTL_HSTINAUTORETRY;
+
+		dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
+	}
+
 	ret = dwc3_core_init_mode(dwc);
 	if (ret)
 		goto mode_fail;
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index b510d8a983..2adcaf0029 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -160,6 +160,9 @@
 #define DWC3_GCTL_GBLHIBERNATIONEN	(1 << 1)
 #define DWC3_GCTL_DSBLCLKGTNG		(1 << 0)
 
+/* Global User Control Register */
+#define DWC3_GUCTL_HSTINAUTORETRY	BIT(14)
+
 /* Global User Control 1 Register */
 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW	BIT(24)
-- 
2.17.1

[PATCH v5 10/16] usb: dwc3: Enable AutoRetry feature in the controller

[Frank Wang]

From: Jagan Teki <jagan@amarulasolutions.com>

By default when core sees any transaction error (CRC or overflow) it
replies with terminating retry ACK (Retry=1 and Nump == 0).

Enabling this Auto Retry feature in controller will make the core send
a non-terminanting ACK upon such transaction errors. That is, ACK TP
with Retry=1 and Nump != 0.

Doing so will give controller a chance to recover from transient error
conditions.

Reference from below Linux commit,

commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature
in the controller")

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/usb/dwc3/core.c | 9 +++++++++
 drivers/usb/dwc3/core.h | 3 +++
 2 files changed, 12 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index dc92f471c1..aab6c34c2d 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -995,6 +995,15 @@ int dwc3_init(struct dwc3 *dwc)
 		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
 	}
 
+	if (dwc->dr_mode == USB_DR_MODE_HOST ||
+	    dwc->dr_mode == USB_DR_MODE_OTG) {
+		reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
+
+		reg |= DWC3_GUCTL_HSTINAUTORETRY;
+
+		dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
+	}
+
 	ret = dwc3_core_init_mode(dwc);
 	if (ret)
 		goto mode_fail;
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index b510d8a983..2adcaf0029 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -160,6 +160,9 @@
 #define DWC3_GCTL_GBLHIBERNATIONEN	(1 << 1)
 #define DWC3_GCTL_DSBLCLKGTNG		(1 << 0)
 
+/* Global User Control Register */
+#define DWC3_GUCTL_HSTINAUTORETRY	BIT(14)
+
 /* Global User Control 1 Register */
 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW	BIT(24)
-- 
2.17.1

[PATCH v5 11/16] usb: dwc3: amend UTMI/UTMIW phy interface setup

[Frank Wang]

Let move 8/16-bit UTMI+ interface initialization into DWC3 core init
that is convenient for both DM_USB and u-boot traditional process.

Signed-off-by: Frank Wang <frank.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Reviewed-by: Kever Yang <kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
 drivers/usb/common/common.c | 25 ++++++++++++++
 drivers/usb/dwc3/core.c     | 65 +++++++++++++++++++------------------
 drivers/usb/dwc3/core.h     |  5 +++
 include/linux/usb/phy.h     | 18 ++++++++++
 4 files changed, 82 insertions(+), 31 deletions(-)

diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c
index 0db281b970..d4ae18693c 100644
--- a/drivers/usb/common/common.c
+++ b/drivers/usb/common/common.c
@@ -10,6 +10,7 @@
 #include <dm.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ch9.h>
+#include <linux/usb/phy.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -64,3 +65,27 @@ enum usb_device_speed usb_get_maximum_speed(ofnode node)
 
 	return USB_SPEED_UNKNOWN;
 }
+
+#if CONFIG_IS_ENABLED(DM_USB)
+static const char *const usbphy_modes[] = {
+	[USBPHY_INTERFACE_MODE_UNKNOWN]	= "",
+	[USBPHY_INTERFACE_MODE_UTMI]	= "utmi",
+	[USBPHY_INTERFACE_MODE_UTMIW]	= "utmi_wide",
+};
+
+enum usb_phy_interface usb_get_phy_mode(ofnode node)
+{
+	const char *phy_type;
+	int i;
+
+	phy_type = ofnode_get_property(node, "phy_type", NULL);
+	if (!phy_type)
+		return USBPHY_INTERFACE_MODE_UNKNOWN;
+
+	for (i = 0; i < ARRAY_SIZE(usbphy_modes); i++)
+		if (!strcmp(phy_type, usbphy_modes[i]))
+			return i;
+
+	return USBPHY_INTERFACE_MODE_UNKNOWN;
+}
+#endif
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index aab6c34c2d..c8cb9e13b2 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -334,6 +334,34 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc)
 	parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 }
 
+static void dwc3_hsphy_mode_setup(struct dwc3 *dwc)
+{
+	enum usb_phy_interface hsphy_mode = dwc->hsphy_mode;
+	u32 reg;
+
+	/* Set dwc3 usb2 phy config */
+	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
+
+	switch (hsphy_mode) {
+	case USBPHY_INTERFACE_MODE_UTMI:
+		reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
+			DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
+		reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
+			DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
+		break;
+	case USBPHY_INTERFACE_MODE_UTMIW:
+		reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
+			DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
+		reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
+			DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
+		break;
+	default:
+		break;
+	}
+
+	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+}
+
 /**
  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
  * @dwc: Pointer to our controller context structure
@@ -382,6 +410,8 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
 
 	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 
+	dwc3_hsphy_mode_setup(dwc);
+
 	mdelay(100);
 
 	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
@@ -626,35 +656,6 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc)
 	dwc3_gadget_run(dwc);
 }
 
-static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev,
-				  struct dwc3 *dwc)
-{
-	enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode;
-	u32 reg;
-
-	/* Set dwc3 usb2 phy config */
-	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
-
-	switch (hsphy_mode) {
-	case USBPHY_INTERFACE_MODE_UTMI:
-		reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
-			DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
-		reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
-			DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
-		break;
-	case USBPHY_INTERFACE_MODE_UTMIW:
-		reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
-			DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
-		reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
-			DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
-		break;
-	default:
-		break;
-	}
-
-	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
-}
-
 #define DWC3_ALIGN_MASK		(16 - 1)
 
 /**
@@ -743,6 +744,8 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
 	dwc->hird_threshold = hird_threshold
 		| (dwc->is_utmi_l1_suspend << 4);
 
+	dwc->hsphy_mode = dwc3_dev->hsphy_mode;
+
 	dwc->index = dwc3_dev->index;
 
 	dwc3_cache_hwparams(dwc);
@@ -767,8 +770,6 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
 		goto err0;
 	}
 
-	dwc3_uboot_hsphy_mode(dwc3_dev, dwc);
-
 	ret = dwc3_event_buffers_setup(dwc);
 	if (ret) {
 		dev_err(dwc->dev, "failed to setup event buffers\n");
@@ -901,6 +902,8 @@ void dwc3_of_parse(struct dwc3 *dwc)
 	 */
 	hird_threshold = 12;
 
+	dwc->hsphy_mode = usb_get_phy_mode(dev->node);
+
 	dwc->has_lpm_erratum = dev_read_bool(dev,
 				"snps,has-lpm-erratum");
 	tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 2adcaf0029..8e562ae6c4 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -21,6 +21,7 @@
 
 #include <linux/usb/ch9.h>
 #include <linux/usb/otg.h>
+#include <linux/usb/phy.h>
 
 #define DWC3_MSG_MAX	500
 
@@ -658,6 +659,9 @@ struct dwc3_scratchpad_array {
  * @maximum_speed: maximum speed requested (mainly for testing purposes)
  * @revision: revision register contents
  * @dr_mode: requested mode of operation
+ * @hsphy_mode: UTMI phy mode, one of following:
+ *		- USBPHY_INTERFACE_MODE_UTMI
+ *		- USBPHY_INTERFACE_MODE_UTMIW
  * @dcfg: saved contents of DCFG register
  * @gctl: saved contents of GCTL register
  * @isoch_delay: wValue from Set Isochronous Delay request;
@@ -749,6 +753,7 @@ struct dwc3 {
 	size_t			regs_size;
 
 	enum usb_dr_mode	dr_mode;
+	enum usb_phy_interface	hsphy_mode;
 
 	/* used for suspend/resume */
 	u32			dcfg;
diff --git a/include/linux/usb/phy.h b/include/linux/usb/phy.h
index 158ca9cd85..1e1217a958 100644
--- a/include/linux/usb/phy.h
+++ b/include/linux/usb/phy.h
@@ -10,10 +10,28 @@
 #ifndef __LINUX_USB_PHY_H
 #define __LINUX_USB_PHY_H
 
+#include <dm/ofnode.h>
+
 enum usb_phy_interface {
 	USBPHY_INTERFACE_MODE_UNKNOWN,
 	USBPHY_INTERFACE_MODE_UTMI,
 	USBPHY_INTERFACE_MODE_UTMIW,
 };
 
+#if CONFIG_IS_ENABLED(DM_USB)
+/**
+ * usb_get_phy_mode - Get phy mode for given device_node
+ * @np:	Pointer to the given device_node
+ *
+ * The function gets phy interface string from property 'phy_type',
+ * and returns the corresponding enum usb_phy_interface
+ */
+enum usb_phy_interface usb_get_phy_mode(ofnode node);
+#else
+static inline enum usb_phy_interface usb_get_phy_mode(ofnode node)
+{
+	return USBPHY_INTERFACE_MODE_UNKNOWN;
+}
+#endif
+
 #endif /* __LINUX_USB_PHY_H */
-- 
2.17.1

[PATCH v5 11/16] usb: dwc3: amend UTMI/UTMIW phy interface setup

[Frank Wang]

Let move 8/16-bit UTMI+ interface initialization into DWC3 core init
that is convenient for both DM_USB and u-boot traditional process.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
 drivers/usb/common/common.c | 25 ++++++++++++++
 drivers/usb/dwc3/core.c     | 65 +++++++++++++++++++------------------
 drivers/usb/dwc3/core.h     |  5 +++
 include/linux/usb/phy.h     | 18 ++++++++++
 4 files changed, 82 insertions(+), 31 deletions(-)

diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c
index 0db281b970..d4ae18693c 100644
--- a/drivers/usb/common/common.c
+++ b/drivers/usb/common/common.c
@@ -10,6 +10,7 @@
 #include <dm.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ch9.h>
+#include <linux/usb/phy.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -64,3 +65,27 @@ enum usb_device_speed usb_get_maximum_speed(ofnode node)
 
 	return USB_SPEED_UNKNOWN;
 }
+
+#if CONFIG_IS_ENABLED(DM_USB)
+static const char *const usbphy_modes[] = {
+	[USBPHY_INTERFACE_MODE_UNKNOWN]	= "",
+	[USBPHY_INTERFACE_MODE_UTMI]	= "utmi",
+	[USBPHY_INTERFACE_MODE_UTMIW]	= "utmi_wide",
+};
+
+enum usb_phy_interface usb_get_phy_mode(ofnode node)
+{
+	const char *phy_type;
+	int i;
+
+	phy_type = ofnode_get_property(node, "phy_type", NULL);
+	if (!phy_type)
+		return USBPHY_INTERFACE_MODE_UNKNOWN;
+
+	for (i = 0; i < ARRAY_SIZE(usbphy_modes); i++)
+		if (!strcmp(phy_type, usbphy_modes[i]))
+			return i;
+
+	return USBPHY_INTERFACE_MODE_UNKNOWN;
+}
+#endif
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index aab6c34c2d..c8cb9e13b2 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -334,6 +334,34 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc)
 	parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 }
 
+static void dwc3_hsphy_mode_setup(struct dwc3 *dwc)
+{
+	enum usb_phy_interface hsphy_mode = dwc->hsphy_mode;
+	u32 reg;
+
+	/* Set dwc3 usb2 phy config */
+	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
+
+	switch (hsphy_mode) {
+	case USBPHY_INTERFACE_MODE_UTMI:
+		reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
+			DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
+		reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
+			DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
+		break;
+	case USBPHY_INTERFACE_MODE_UTMIW:
+		reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
+			DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
+		reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
+			DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
+		break;
+	default:
+		break;
+	}
+
+	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+}
+
 /**
  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
  * @dwc: Pointer to our controller context structure
@@ -382,6 +410,8 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
 
 	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 
+	dwc3_hsphy_mode_setup(dwc);
+
 	mdelay(100);
 
 	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
@@ -626,35 +656,6 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc)
 	dwc3_gadget_run(dwc);
 }
 
-static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev,
-				  struct dwc3 *dwc)
-{
-	enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode;
-	u32 reg;
-
-	/* Set dwc3 usb2 phy config */
-	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
-
-	switch (hsphy_mode) {
-	case USBPHY_INTERFACE_MODE_UTMI:
-		reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
-			DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
-		reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
-			DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
-		break;
-	case USBPHY_INTERFACE_MODE_UTMIW:
-		reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
-			DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
-		reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
-			DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
-		break;
-	default:
-		break;
-	}
-
-	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
-}
-
 #define DWC3_ALIGN_MASK		(16 - 1)
 
 /**
@@ -743,6 +744,8 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
 	dwc->hird_threshold = hird_threshold
 		| (dwc->is_utmi_l1_suspend << 4);
 
+	dwc->hsphy_mode = dwc3_dev->hsphy_mode;
+
 	dwc->index = dwc3_dev->index;
 
 	dwc3_cache_hwparams(dwc);
@@ -767,8 +770,6 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
 		goto err0;
 	}
 
-	dwc3_uboot_hsphy_mode(dwc3_dev, dwc);
-
 	ret = dwc3_event_buffers_setup(dwc);
 	if (ret) {
 		dev_err(dwc->dev, "failed to setup event buffers\n");
@@ -901,6 +902,8 @@ void dwc3_of_parse(struct dwc3 *dwc)
 	 */
 	hird_threshold = 12;
 
+	dwc->hsphy_mode = usb_get_phy_mode(dev->node);
+
 	dwc->has_lpm_erratum = dev_read_bool(dev,
 				"snps,has-lpm-erratum");
 	tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 2adcaf0029..8e562ae6c4 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -21,6 +21,7 @@
 
 #include <linux/usb/ch9.h>
 #include <linux/usb/otg.h>
+#include <linux/usb/phy.h>
 
 #define DWC3_MSG_MAX	500
 
@@ -658,6 +659,9 @@ struct dwc3_scratchpad_array {
  * @maximum_speed: maximum speed requested (mainly for testing purposes)
  * @revision: revision register contents
  * @dr_mode: requested mode of operation
+ * @hsphy_mode: UTMI phy mode, one of following:
+ *		- USBPHY_INTERFACE_MODE_UTMI
+ *		- USBPHY_INTERFACE_MODE_UTMIW
  * @dcfg: saved contents of DCFG register
  * @gctl: saved contents of GCTL register
  * @isoch_delay: wValue from Set Isochronous Delay request;
@@ -749,6 +753,7 @@ struct dwc3 {
 	size_t			regs_size;
 
 	enum usb_dr_mode	dr_mode;
+	enum usb_phy_interface	hsphy_mode;
 
 	/* used for suspend/resume */
 	u32			dcfg;
diff --git a/include/linux/usb/phy.h b/include/linux/usb/phy.h
index 158ca9cd85..1e1217a958 100644
--- a/include/linux/usb/phy.h
+++ b/include/linux/usb/phy.h
@@ -10,10 +10,28 @@
 #ifndef __LINUX_USB_PHY_H
 #define __LINUX_USB_PHY_H
 
+#include <dm/ofnode.h>
+
 enum usb_phy_interface {
 	USBPHY_INTERFACE_MODE_UNKNOWN,
 	USBPHY_INTERFACE_MODE_UTMI,
 	USBPHY_INTERFACE_MODE_UTMIW,
 };
 
+#if CONFIG_IS_ENABLED(DM_USB)
+/**
+ * usb_get_phy_mode - Get phy mode for given device_node
+ * @np:	Pointer to the given device_node
+ *
+ * The function gets phy interface string from property 'phy_type',
+ * and returns the corresponding enum usb_phy_interface
+ */
+enum usb_phy_interface usb_get_phy_mode(ofnode node);
+#else
+static inline enum usb_phy_interface usb_get_phy_mode(ofnode node)
+{
+	return USBPHY_INTERFACE_MODE_UNKNOWN;
+}
+#endif
+
 #endif /* __LINUX_USB_PHY_H */
-- 
2.17.1

[PATCH v5 12/16] usb: dwc3: add make compatible for rockchip platform

[Frank Wang]

RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller
in resetting to hold pipe power state in P2 before initializing the PHY.
This commit fixed it and added device compatible for rockchip platform.

Signed-off-by: Frank Wang <frank.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 drivers/usb/dwc3/dwc3-generic.c | 33 +++++++++++++++++++++++++++------
 1 file changed, 27 insertions(+), 6 deletions(-)

diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index eabd53a36d..421e0be135 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -24,6 +24,12 @@
 #include <clk.h>
 #include <usb/xhci.h>
 
+struct dwc3_glue_data {
+	struct clk_bulk		clks;
+	struct reset_ctl_bulk	resets;
+	fdt_addr_t regs;
+};
+
 struct dwc3_generic_plat {
 	fdt_addr_t base;
 	u32 maximum_speed;
@@ -47,6 +53,7 @@ static int dwc3_generic_probe(struct udevice *dev,
 	int rc;
 	struct dwc3_generic_plat *plat = dev_get_platdata(dev);
 	struct dwc3 *dwc3 = &priv->dwc3;
+	struct dwc3_glue_data *glue = dev_get_platdata(dev->parent);
 
 	dwc3->dev = dev;
 	dwc3->maximum_speed = plat->maximum_speed;
@@ -55,10 +62,22 @@ static int dwc3_generic_probe(struct udevice *dev,
 	dwc3_of_parse(dwc3);
 #endif
 
+	/*
+	 * It must hold whole USB3.0 OTG controller in resetting to hold pipe
+	 * power state in P2 before initializing TypeC PHY on RK3399 platform.
+	 */
+	if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) {
+		reset_assert_bulk(&glue->resets);
+		udelay(1);
+	}
+
 	rc = dwc3_setup_phy(dev, &priv->phys);
 	if (rc)
 		return rc;
 
+	if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3"))
+		reset_deassert_bulk(&glue->resets);
+
 	priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
 	dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
 
@@ -186,12 +205,6 @@ U_BOOT_DRIVER(dwc3_generic_host) = {
 };
 #endif
 
-struct dwc3_glue_data {
-	struct clk_bulk		clks;
-	struct reset_ctl_bulk	resets;
-	fdt_addr_t regs;
-};
-
 struct dwc3_glue_ops {
 	void (*select_dr_mode)(struct udevice *dev, int index,
 			       enum usb_dr_mode mode);
@@ -394,6 +407,12 @@ static int dwc3_glue_probe(struct udevice *dev)
 	if (ret)
 		return ret;
 
+	if (glue->resets.count == 0) {
+		ret = dwc3_glue_reset_init(child, glue);
+		if (ret)
+			return ret;
+	}
+
 	while (child) {
 		enum usb_dr_mode dr_mode;
 
@@ -424,6 +443,8 @@ static const struct udevice_id dwc3_glue_ids[] = {
 	{ .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
 	{ .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
 	{ .compatible = "ti,am654-dwc3" },
+	{ .compatible = "rockchip,rk3328-dwc3" },
+	{ .compatible = "rockchip,rk3399-dwc3" },
 	{ }
 };
 
-- 
2.17.1

[PATCH v5 12/16] usb: dwc3: add make compatible for rockchip platform

[Frank Wang]

RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller
in resetting to hold pipe power state in P2 before initializing the PHY.
This commit fixed it and added device compatible for rockchip platform.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/usb/dwc3/dwc3-generic.c | 33 +++++++++++++++++++++++++++------
 1 file changed, 27 insertions(+), 6 deletions(-)

diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index eabd53a36d..421e0be135 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -24,6 +24,12 @@
 #include <clk.h>
 #include <usb/xhci.h>
 
+struct dwc3_glue_data {
+	struct clk_bulk		clks;
+	struct reset_ctl_bulk	resets;
+	fdt_addr_t regs;
+};
+
 struct dwc3_generic_plat {
 	fdt_addr_t base;
 	u32 maximum_speed;
@@ -47,6 +53,7 @@ static int dwc3_generic_probe(struct udevice *dev,
 	int rc;
 	struct dwc3_generic_plat *plat = dev_get_platdata(dev);
 	struct dwc3 *dwc3 = &priv->dwc3;
+	struct dwc3_glue_data *glue = dev_get_platdata(dev->parent);
 
 	dwc3->dev = dev;
 	dwc3->maximum_speed = plat->maximum_speed;
@@ -55,10 +62,22 @@ static int dwc3_generic_probe(struct udevice *dev,
 	dwc3_of_parse(dwc3);
 #endif
 
+	/*
+	 * It must hold whole USB3.0 OTG controller in resetting to hold pipe
+	 * power state in P2 before initializing TypeC PHY on RK3399 platform.
+	 */
+	if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) {
+		reset_assert_bulk(&glue->resets);
+		udelay(1);
+	}
+
 	rc = dwc3_setup_phy(dev, &priv->phys);
 	if (rc)
 		return rc;
 
+	if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3"))
+		reset_deassert_bulk(&glue->resets);
+
 	priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
 	dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
 
@@ -186,12 +205,6 @@ U_BOOT_DRIVER(dwc3_generic_host) = {
 };
 #endif
 
-struct dwc3_glue_data {
-	struct clk_bulk		clks;
-	struct reset_ctl_bulk	resets;
-	fdt_addr_t regs;
-};
-
 struct dwc3_glue_ops {
 	void (*select_dr_mode)(struct udevice *dev, int index,
 			       enum usb_dr_mode mode);
@@ -394,6 +407,12 @@ static int dwc3_glue_probe(struct udevice *dev)
 	if (ret)
 		return ret;
 
+	if (glue->resets.count == 0) {
+		ret = dwc3_glue_reset_init(child, glue);
+		if (ret)
+			return ret;
+	}
+
 	while (child) {
 		enum usb_dr_mode dr_mode;
 
@@ -424,6 +443,8 @@ static const struct udevice_id dwc3_glue_ids[] = {
 	{ .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
 	{ .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
 	{ .compatible = "ti,am654-dwc3" },
+	{ .compatible = "rockchip,rk3328-dwc3" },
+	{ .compatible = "rockchip,rk3399-dwc3" },
 	{ }
 };
 
-- 
2.17.1

Re: [PATCH v5 12/16] usb: dwc3: add make compatible for rockchip platform

[Kever Yang]

On 2020/5/13 下午3:17, Frank Wang wrote:
> RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller
> in resetting to hold pipe power state in P2 before initializing the PHY.
> This commit fixed it and added device compatible for rockchip platform.
>
> Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/usb/dwc3/dwc3-generic.c | 33 +++++++++++++++++++++++++++------
>   1 file changed, 27 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
> index eabd53a36d..421e0be135 100644
> --- a/drivers/usb/dwc3/dwc3-generic.c
> +++ b/drivers/usb/dwc3/dwc3-generic.c
> @@ -24,6 +24,12 @@
>   #include <clk.h>
>   #include <usb/xhci.h>
>   
> +struct dwc3_glue_data {
> +	struct clk_bulk		clks;
> +	struct reset_ctl_bulk	resets;
> +	fdt_addr_t regs;
> +};
> +
>   struct dwc3_generic_plat {
>   	fdt_addr_t base;
>   	u32 maximum_speed;
> @@ -47,6 +53,7 @@ static int dwc3_generic_probe(struct udevice *dev,
>   	int rc;
>   	struct dwc3_generic_plat *plat = dev_get_platdata(dev);
>   	struct dwc3 *dwc3 = &priv->dwc3;
> +	struct dwc3_glue_data *glue = dev_get_platdata(dev->parent);
>   
>   	dwc3->dev = dev;
>   	dwc3->maximum_speed = plat->maximum_speed;
> @@ -55,10 +62,22 @@ static int dwc3_generic_probe(struct udevice *dev,
>   	dwc3_of_parse(dwc3);
>   #endif
>   
> +	/*
> +	 * It must hold whole USB3.0 OTG controller in resetting to hold pipe
> +	 * power state in P2 before initializing TypeC PHY on RK3399 platform.
> +	 */
> +	if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) {
> +		reset_assert_bulk(&glue->resets);
> +		udelay(1);
> +	}
> +
>   	rc = dwc3_setup_phy(dev, &priv->phys);
>   	if (rc)
>   		return rc;
>   
> +	if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3"))
> +		reset_deassert_bulk(&glue->resets);
> +
>   	priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
>   	dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
>   
> @@ -186,12 +205,6 @@ U_BOOT_DRIVER(dwc3_generic_host) = {
>   };
>   #endif
>   
> -struct dwc3_glue_data {
> -	struct clk_bulk		clks;
> -	struct reset_ctl_bulk	resets;
> -	fdt_addr_t regs;
> -};
> -
>   struct dwc3_glue_ops {
>   	void (*select_dr_mode)(struct udevice *dev, int index,
>   			       enum usb_dr_mode mode);
> @@ -394,6 +407,12 @@ static int dwc3_glue_probe(struct udevice *dev)
>   	if (ret)
>   		return ret;
>   
> +	if (glue->resets.count == 0) {
> +		ret = dwc3_glue_reset_init(child, glue);
> +		if (ret)
> +			return ret;
> +	}
> +
>   	while (child) {
>   		enum usb_dr_mode dr_mode;
>   
> @@ -424,6 +443,8 @@ static const struct udevice_id dwc3_glue_ids[] = {
>   	{ .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
>   	{ .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
>   	{ .compatible = "ti,am654-dwc3" },
> +	{ .compatible = "rockchip,rk3328-dwc3" },
> +	{ .compatible = "rockchip,rk3399-dwc3" },
>   	{ }
>   };
>   

[PATCH v5 12/16] usb: dwc3: add make compatible for rockchip platform

[Kever Yang]

On 2020/5/13 ??3:17, Frank Wang wrote:
> RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller
> in resetting to hold pipe power state in P2 before initializing the PHY.
> This commit fixed it and added device compatible for rockchip platform.
>
> Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/usb/dwc3/dwc3-generic.c | 33 +++++++++++++++++++++++++++------
>   1 file changed, 27 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
> index eabd53a36d..421e0be135 100644
> --- a/drivers/usb/dwc3/dwc3-generic.c
> +++ b/drivers/usb/dwc3/dwc3-generic.c
> @@ -24,6 +24,12 @@
>   #include <clk.h>
>   #include <usb/xhci.h>
>   
> +struct dwc3_glue_data {
> +	struct clk_bulk		clks;
> +	struct reset_ctl_bulk	resets;
> +	fdt_addr_t regs;
> +};
> +
>   struct dwc3_generic_plat {
>   	fdt_addr_t base;
>   	u32 maximum_speed;
> @@ -47,6 +53,7 @@ static int dwc3_generic_probe(struct udevice *dev,
>   	int rc;
>   	struct dwc3_generic_plat *plat = dev_get_platdata(dev);
>   	struct dwc3 *dwc3 = &priv->dwc3;
> +	struct dwc3_glue_data *glue = dev_get_platdata(dev->parent);
>   
>   	dwc3->dev = dev;
>   	dwc3->maximum_speed = plat->maximum_speed;
> @@ -55,10 +62,22 @@ static int dwc3_generic_probe(struct udevice *dev,
>   	dwc3_of_parse(dwc3);
>   #endif
>   
> +	/*
> +	 * It must hold whole USB3.0 OTG controller in resetting to hold pipe
> +	 * power state in P2 before initializing TypeC PHY on RK3399 platform.
> +	 */
> +	if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) {
> +		reset_assert_bulk(&glue->resets);
> +		udelay(1);
> +	}
> +
>   	rc = dwc3_setup_phy(dev, &priv->phys);
>   	if (rc)
>   		return rc;
>   
> +	if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3"))
> +		reset_deassert_bulk(&glue->resets);
> +
>   	priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
>   	dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
>   
> @@ -186,12 +205,6 @@ U_BOOT_DRIVER(dwc3_generic_host) = {
>   };
>   #endif
>   
> -struct dwc3_glue_data {
> -	struct clk_bulk		clks;
> -	struct reset_ctl_bulk	resets;
> -	fdt_addr_t regs;
> -};
> -
>   struct dwc3_glue_ops {
>   	void (*select_dr_mode)(struct udevice *dev, int index,
>   			       enum usb_dr_mode mode);
> @@ -394,6 +407,12 @@ static int dwc3_glue_probe(struct udevice *dev)
>   	if (ret)
>   		return ret;
>   
> +	if (glue->resets.count == 0) {
> +		ret = dwc3_glue_reset_init(child, glue);
> +		if (ret)
> +			return ret;
> +	}
> +
>   	while (child) {
>   		enum usb_dr_mode dr_mode;
>   
> @@ -424,6 +443,8 @@ static const struct udevice_id dwc3_glue_ids[] = {
>   	{ .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
>   	{ .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
>   	{ .compatible = "ti,am654-dwc3" },
> +	{ .compatible = "rockchip,rk3328-dwc3" },
> +	{ .compatible = "rockchip,rk3399-dwc3" },
>   	{ }
>   };
>   

[PATCH v5 13/16] driver: usb: drop legacy rockchip xhci driver

[Frank Wang]

We have changed to use dwc3 generic driver for usb3.0 host, so the
legacy Rockchip's xHCI driver is not needed, and drop it.

Signed-off-by: Frank Wang <frank.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Reviewed-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 drivers/usb/host/Kconfig         |   9 --
 drivers/usb/host/Makefile        |   1 -
 drivers/usb/host/xhci-rockchip.c | 196 -------------------------------
 3 files changed, 206 deletions(-)
 delete mode 100644 drivers/usb/host/xhci-rockchip.c

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 2f381dc958..088931a6b9 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -53,15 +53,6 @@ config USB_XHCI_PCI
 	help
 	  Enables support for the PCI-based xHCI controller.
 
-config USB_XHCI_ROCKCHIP
-	bool "Support for Rockchip on-chip xHCI USB controller"
-	depends on ARCH_ROCKCHIP
-	depends on DM_REGULATOR
-	depends on DM_USB
-	default y
-	help
-	  Enables support for the on-chip xHCI controller on Rockchip SoCs.
-
 config USB_XHCI_RCAR
 	bool "Renesas RCar USB 3.0 support"
 	default y
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index e8e3b17e42..29d4f87e38 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -48,7 +48,6 @@ obj-$(CONFIG_USB_XHCI_BRCM) += xhci-brcm.o
 obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
 obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
 obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o
-obj-$(CONFIG_USB_XHCI_ROCKCHIP) += xhci-rockchip.o
 obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
 obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
 obj-$(CONFIG_USB_XHCI_MTK) += xhci-mtk.o
diff --git a/drivers/usb/host/xhci-rockchip.c b/drivers/usb/host/xhci-rockchip.c
deleted file mode 100644
index b67722fe45..0000000000
--- a/drivers/usb/host/xhci-rockchip.c
+++ /dev/null
@@ -1,196 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2016 Rockchip, Inc.
- * Authors: Daniel Meng <daniel.meng-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
- */
-#include <common.h>
-#include <dm.h>
-#include <malloc.h>
-#include <usb.h>
-#include <watchdog.h>
-#include <linux/errno.h>
-#include <linux/compat.h>
-#include <linux/usb/dwc3.h>
-#include <power/regulator.h>
-
-#include <usb/xhci.h>
-
-struct rockchip_xhci_platdata {
-	fdt_addr_t hcd_base;
-	struct udevice *vbus_supply;
-};
-
-/*
- * Contains pointers to register base addresses
- * for the usb controller.
- */
-struct rockchip_xhci {
-	struct usb_platdata usb_plat;
-	struct xhci_ctrl ctrl;
-	struct xhci_hccr *hcd;
-	struct dwc3 *dwc3_reg;
-};
-
-static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
-{
-	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
-	int ret = 0;
-
-	/*
-	 * Get the base address for XHCI controller from the device node
-	 */
-	plat->hcd_base = dev_read_addr(dev);
-	if (plat->hcd_base == FDT_ADDR_T_NONE) {
-		pr_err("Can't get the XHCI register base address\n");
-		return -ENXIO;
-	}
-
-	/* Vbus regulator */
-	ret = device_get_supply_regulator(dev, "vbus-supply",
-					  &plat->vbus_supply);
-	if (ret)
-		debug("Can't get VBus regulator!\n");
-
-	return 0;
-}
-
-/*
- * rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core
- * @dwc: Pointer to our controller context structure
- * @dev: Pointer to ulcass device
- */
-static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg,
-				    struct udevice *dev)
-{
-	u32 reg;
-	u32 utmi_bits;
-
-	/* Set dwc3 usb2 phy config */
-	reg = readl(&dwc3_reg->g_usb2phycfg[0]);
-
-	if (dev_read_bool(dev, "snps,dis-enblslpm-quirk"))
-		reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
-
-	utmi_bits = dev_read_u32_default(dev, "snps,phyif-utmi-bits", -1);
-	if (utmi_bits == 16) {
-		reg |= DWC3_GUSB2PHYCFG_PHYIF;
-		reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
-		reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
-	} else if (utmi_bits == 8) {
-		reg &= ~DWC3_GUSB2PHYCFG_PHYIF;
-		reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
-		reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
-	}
-
-	if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
-		reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
-
-	if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk"))
-		reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
-
-	writel(reg, &dwc3_reg->g_usb2phycfg[0]);
-}
-
-static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci,
-				   struct udevice *dev)
-{
-	int ret;
-
-	ret = dwc3_core_init(rkxhci->dwc3_reg);
-	if (ret) {
-		pr_err("failed to initialize core\n");
-		return ret;
-	}
-
-	rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev);
-
-	/* We are hard-coding DWC3 core to Host Mode */
-	dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
-
-	return 0;
-}
-
-static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci)
-{
-	return 0;
-}
-
-static int xhci_usb_probe(struct udevice *dev)
-{
-	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
-	struct rockchip_xhci *ctx = dev_get_priv(dev);
-	struct xhci_hcor *hcor;
-	int ret;
-
-	ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
-	ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
-	hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd +
-			HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));
-
-	if (plat->vbus_supply) {
-		ret = regulator_set_enable(plat->vbus_supply, true);
-		if (ret) {
-			pr_err("XHCI: failed to set VBus supply\n");
-			return ret;
-		}
-	}
-
-	ret = rockchip_xhci_core_init(ctx, dev);
-	if (ret) {
-		pr_err("XHCI: failed to initialize controller\n");
-		return ret;
-	}
-
-	return xhci_register(dev, ctx->hcd, hcor);
-}
-
-static int xhci_usb_remove(struct udevice *dev)
-{
-	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
-	struct rockchip_xhci *ctx = dev_get_priv(dev);
-	int ret;
-
-	ret = xhci_deregister(dev);
-	if (ret)
-		return ret;
-	ret = rockchip_xhci_core_exit(ctx);
-	if (ret)
-		return ret;
-
-	if (plat->vbus_supply) {
-		ret = regulator_set_enable(plat->vbus_supply, false);
-		if (ret)
-			pr_err("XHCI: failed to set VBus supply\n");
-	}
-
-	return ret;
-}
-
-static const struct udevice_id xhci_usb_ids[] = {
-	{ .compatible = "rockchip,rk3328-xhci" },
-	{ }
-};
-
-U_BOOT_DRIVER(usb_xhci) = {
-	.name	= "xhci_rockchip",
-	.id	= UCLASS_USB,
-	.of_match = xhci_usb_ids,
-	.ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
-	.probe = xhci_usb_probe,
-	.remove = xhci_usb_remove,
-	.ops	= &xhci_usb_ops,
-	.bind	= dm_scan_fdt_dev,
-	.platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata),
-	.priv_auto_alloc_size = sizeof(struct rockchip_xhci),
-	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
-};
-
-static const struct udevice_id usb_phy_ids[] = {
-	{ .compatible = "rockchip,rk3328-usb3-phy" },
-	{ }
-};
-
-U_BOOT_DRIVER(usb_phy) = {
-	.name = "usb_phy_rockchip",
-	.of_match = usb_phy_ids,
-};
-- 
2.17.1

[PATCH v5 13/16] driver: usb: drop legacy rockchip xhci driver

[Frank Wang]

We have changed to use dwc3 generic driver for usb3.0 host, so the
legacy Rockchip's xHCI driver is not needed, and drop it.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/usb/host/Kconfig         |   9 --
 drivers/usb/host/Makefile        |   1 -
 drivers/usb/host/xhci-rockchip.c | 196 -------------------------------
 3 files changed, 206 deletions(-)
 delete mode 100644 drivers/usb/host/xhci-rockchip.c

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 2f381dc958..088931a6b9 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -53,15 +53,6 @@ config USB_XHCI_PCI
 	help
 	  Enables support for the PCI-based xHCI controller.
 
-config USB_XHCI_ROCKCHIP
-	bool "Support for Rockchip on-chip xHCI USB controller"
-	depends on ARCH_ROCKCHIP
-	depends on DM_REGULATOR
-	depends on DM_USB
-	default y
-	help
-	  Enables support for the on-chip xHCI controller on Rockchip SoCs.
-
 config USB_XHCI_RCAR
 	bool "Renesas RCar USB 3.0 support"
 	default y
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index e8e3b17e42..29d4f87e38 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -48,7 +48,6 @@ obj-$(CONFIG_USB_XHCI_BRCM) += xhci-brcm.o
 obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
 obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
 obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o
-obj-$(CONFIG_USB_XHCI_ROCKCHIP) += xhci-rockchip.o
 obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
 obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
 obj-$(CONFIG_USB_XHCI_MTK) += xhci-mtk.o
diff --git a/drivers/usb/host/xhci-rockchip.c b/drivers/usb/host/xhci-rockchip.c
deleted file mode 100644
index b67722fe45..0000000000
--- a/drivers/usb/host/xhci-rockchip.c
+++ /dev/null
@@ -1,196 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2016 Rockchip, Inc.
- * Authors: Daniel Meng <daniel.meng@rock-chips.com>
- */
-#include <common.h>
-#include <dm.h>
-#include <malloc.h>
-#include <usb.h>
-#include <watchdog.h>
-#include <linux/errno.h>
-#include <linux/compat.h>
-#include <linux/usb/dwc3.h>
-#include <power/regulator.h>
-
-#include <usb/xhci.h>
-
-struct rockchip_xhci_platdata {
-	fdt_addr_t hcd_base;
-	struct udevice *vbus_supply;
-};
-
-/*
- * Contains pointers to register base addresses
- * for the usb controller.
- */
-struct rockchip_xhci {
-	struct usb_platdata usb_plat;
-	struct xhci_ctrl ctrl;
-	struct xhci_hccr *hcd;
-	struct dwc3 *dwc3_reg;
-};
-
-static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
-{
-	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
-	int ret = 0;
-
-	/*
-	 * Get the base address for XHCI controller from the device node
-	 */
-	plat->hcd_base = dev_read_addr(dev);
-	if (plat->hcd_base == FDT_ADDR_T_NONE) {
-		pr_err("Can't get the XHCI register base address\n");
-		return -ENXIO;
-	}
-
-	/* Vbus regulator */
-	ret = device_get_supply_regulator(dev, "vbus-supply",
-					  &plat->vbus_supply);
-	if (ret)
-		debug("Can't get VBus regulator!\n");
-
-	return 0;
-}
-
-/*
- * rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core
- * @dwc: Pointer to our controller context structure
- * @dev: Pointer to ulcass device
- */
-static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg,
-				    struct udevice *dev)
-{
-	u32 reg;
-	u32 utmi_bits;
-
-	/* Set dwc3 usb2 phy config */
-	reg = readl(&dwc3_reg->g_usb2phycfg[0]);
-
-	if (dev_read_bool(dev, "snps,dis-enblslpm-quirk"))
-		reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
-
-	utmi_bits = dev_read_u32_default(dev, "snps,phyif-utmi-bits", -1);
-	if (utmi_bits == 16) {
-		reg |= DWC3_GUSB2PHYCFG_PHYIF;
-		reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
-		reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
-	} else if (utmi_bits == 8) {
-		reg &= ~DWC3_GUSB2PHYCFG_PHYIF;
-		reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
-		reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
-	}
-
-	if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
-		reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
-
-	if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk"))
-		reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
-
-	writel(reg, &dwc3_reg->g_usb2phycfg[0]);
-}
-
-static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci,
-				   struct udevice *dev)
-{
-	int ret;
-
-	ret = dwc3_core_init(rkxhci->dwc3_reg);
-	if (ret) {
-		pr_err("failed to initialize core\n");
-		return ret;
-	}
-
-	rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev);
-
-	/* We are hard-coding DWC3 core to Host Mode */
-	dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
-
-	return 0;
-}
-
-static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci)
-{
-	return 0;
-}
-
-static int xhci_usb_probe(struct udevice *dev)
-{
-	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
-	struct rockchip_xhci *ctx = dev_get_priv(dev);
-	struct xhci_hcor *hcor;
-	int ret;
-
-	ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
-	ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
-	hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd +
-			HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));
-
-	if (plat->vbus_supply) {
-		ret = regulator_set_enable(plat->vbus_supply, true);
-		if (ret) {
-			pr_err("XHCI: failed to set VBus supply\n");
-			return ret;
-		}
-	}
-
-	ret = rockchip_xhci_core_init(ctx, dev);
-	if (ret) {
-		pr_err("XHCI: failed to initialize controller\n");
-		return ret;
-	}
-
-	return xhci_register(dev, ctx->hcd, hcor);
-}
-
-static int xhci_usb_remove(struct udevice *dev)
-{
-	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
-	struct rockchip_xhci *ctx = dev_get_priv(dev);
-	int ret;
-
-	ret = xhci_deregister(dev);
-	if (ret)
-		return ret;
-	ret = rockchip_xhci_core_exit(ctx);
-	if (ret)
-		return ret;
-
-	if (plat->vbus_supply) {
-		ret = regulator_set_enable(plat->vbus_supply, false);
-		if (ret)
-			pr_err("XHCI: failed to set VBus supply\n");
-	}
-
-	return ret;
-}
-
-static const struct udevice_id xhci_usb_ids[] = {
-	{ .compatible = "rockchip,rk3328-xhci" },
-	{ }
-};
-
-U_BOOT_DRIVER(usb_xhci) = {
-	.name	= "xhci_rockchip",
-	.id	= UCLASS_USB,
-	.of_match = xhci_usb_ids,
-	.ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
-	.probe = xhci_usb_probe,
-	.remove = xhci_usb_remove,
-	.ops	= &xhci_usb_ops,
-	.bind	= dm_scan_fdt_dev,
-	.platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata),
-	.priv_auto_alloc_size = sizeof(struct rockchip_xhci),
-	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
-};
-
-static const struct udevice_id usb_phy_ids[] = {
-	{ .compatible = "rockchip,rk3328-usb3-phy" },
-	{ }
-};
-
-U_BOOT_DRIVER(usb_phy) = {
-	.name = "usb_phy_rockchip",
-	.of_match = usb_phy_ids,
-};
-- 
2.17.1

Re: [PATCH v5 13/16] driver: usb: drop legacy rockchip xhci driver

[Kever Yang]

On 2020/5/13 下午3:17, Frank Wang wrote:
> We have changed to use dwc3 generic driver for usb3.0 host, so the
> legacy Rockchip's xHCI driver is not needed, and drop it.
>
> Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/usb/host/Kconfig         |   9 --
>   drivers/usb/host/Makefile        |   1 -
>   drivers/usb/host/xhci-rockchip.c | 196 -------------------------------
>   3 files changed, 206 deletions(-)
>   delete mode 100644 drivers/usb/host/xhci-rockchip.c
>
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index 2f381dc958..088931a6b9 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -53,15 +53,6 @@ config USB_XHCI_PCI
>   	help
>   	  Enables support for the PCI-based xHCI controller.
>   
> -config USB_XHCI_ROCKCHIP
> -	bool "Support for Rockchip on-chip xHCI USB controller"
> -	depends on ARCH_ROCKCHIP
> -	depends on DM_REGULATOR
> -	depends on DM_USB
> -	default y
> -	help
> -	  Enables support for the on-chip xHCI controller on Rockchip SoCs.
> -
>   config USB_XHCI_RCAR
>   	bool "Renesas RCar USB 3.0 support"
>   	default y
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index e8e3b17e42..29d4f87e38 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -48,7 +48,6 @@ obj-$(CONFIG_USB_XHCI_BRCM) += xhci-brcm.o
>   obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
>   obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
>   obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o
> -obj-$(CONFIG_USB_XHCI_ROCKCHIP) += xhci-rockchip.o
>   obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
>   obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
>   obj-$(CONFIG_USB_XHCI_MTK) += xhci-mtk.o
> diff --git a/drivers/usb/host/xhci-rockchip.c b/drivers/usb/host/xhci-rockchip.c
> deleted file mode 100644
> index b67722fe45..0000000000
> --- a/drivers/usb/host/xhci-rockchip.c
> +++ /dev/null
> @@ -1,196 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright (c) 2016 Rockchip, Inc.
> - * Authors: Daniel Meng <daniel.meng@rock-chips.com>
> - */
> -#include <common.h>
> -#include <dm.h>
> -#include <malloc.h>
> -#include <usb.h>
> -#include <watchdog.h>
> -#include <linux/errno.h>
> -#include <linux/compat.h>
> -#include <linux/usb/dwc3.h>
> -#include <power/regulator.h>
> -
> -#include <usb/xhci.h>
> -
> -struct rockchip_xhci_platdata {
> -	fdt_addr_t hcd_base;
> -	struct udevice *vbus_supply;
> -};
> -
> -/*
> - * Contains pointers to register base addresses
> - * for the usb controller.
> - */
> -struct rockchip_xhci {
> -	struct usb_platdata usb_plat;
> -	struct xhci_ctrl ctrl;
> -	struct xhci_hccr *hcd;
> -	struct dwc3 *dwc3_reg;
> -};
> -
> -static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
> -{
> -	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
> -	int ret = 0;
> -
> -	/*
> -	 * Get the base address for XHCI controller from the device node
> -	 */
> -	plat->hcd_base = dev_read_addr(dev);
> -	if (plat->hcd_base == FDT_ADDR_T_NONE) {
> -		pr_err("Can't get the XHCI register base address\n");
> -		return -ENXIO;
> -	}
> -
> -	/* Vbus regulator */
> -	ret = device_get_supply_regulator(dev, "vbus-supply",
> -					  &plat->vbus_supply);
> -	if (ret)
> -		debug("Can't get VBus regulator!\n");
> -
> -	return 0;
> -}
> -
> -/*
> - * rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core
> - * @dwc: Pointer to our controller context structure
> - * @dev: Pointer to ulcass device
> - */
> -static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg,
> -				    struct udevice *dev)
> -{
> -	u32 reg;
> -	u32 utmi_bits;
> -
> -	/* Set dwc3 usb2 phy config */
> -	reg = readl(&dwc3_reg->g_usb2phycfg[0]);
> -
> -	if (dev_read_bool(dev, "snps,dis-enblslpm-quirk"))
> -		reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
> -
> -	utmi_bits = dev_read_u32_default(dev, "snps,phyif-utmi-bits", -1);
> -	if (utmi_bits == 16) {
> -		reg |= DWC3_GUSB2PHYCFG_PHYIF;
> -		reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
> -		reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
> -	} else if (utmi_bits == 8) {
> -		reg &= ~DWC3_GUSB2PHYCFG_PHYIF;
> -		reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
> -		reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
> -	}
> -
> -	if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
> -		reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
> -
> -	if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk"))
> -		reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
> -
> -	writel(reg, &dwc3_reg->g_usb2phycfg[0]);
> -}
> -
> -static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci,
> -				   struct udevice *dev)
> -{
> -	int ret;
> -
> -	ret = dwc3_core_init(rkxhci->dwc3_reg);
> -	if (ret) {
> -		pr_err("failed to initialize core\n");
> -		return ret;
> -	}
> -
> -	rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev);
> -
> -	/* We are hard-coding DWC3 core to Host Mode */
> -	dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
> -
> -	return 0;
> -}
> -
> -static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci)
> -{
> -	return 0;
> -}
> -
> -static int xhci_usb_probe(struct udevice *dev)
> -{
> -	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
> -	struct rockchip_xhci *ctx = dev_get_priv(dev);
> -	struct xhci_hcor *hcor;
> -	int ret;
> -
> -	ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
> -	ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
> -	hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd +
> -			HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));
> -
> -	if (plat->vbus_supply) {
> -		ret = regulator_set_enable(plat->vbus_supply, true);
> -		if (ret) {
> -			pr_err("XHCI: failed to set VBus supply\n");
> -			return ret;
> -		}
> -	}
> -
> -	ret = rockchip_xhci_core_init(ctx, dev);
> -	if (ret) {
> -		pr_err("XHCI: failed to initialize controller\n");
> -		return ret;
> -	}
> -
> -	return xhci_register(dev, ctx->hcd, hcor);
> -}
> -
> -static int xhci_usb_remove(struct udevice *dev)
> -{
> -	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
> -	struct rockchip_xhci *ctx = dev_get_priv(dev);
> -	int ret;
> -
> -	ret = xhci_deregister(dev);
> -	if (ret)
> -		return ret;
> -	ret = rockchip_xhci_core_exit(ctx);
> -	if (ret)
> -		return ret;
> -
> -	if (plat->vbus_supply) {
> -		ret = regulator_set_enable(plat->vbus_supply, false);
> -		if (ret)
> -			pr_err("XHCI: failed to set VBus supply\n");
> -	}
> -
> -	return ret;
> -}
> -
> -static const struct udevice_id xhci_usb_ids[] = {
> -	{ .compatible = "rockchip,rk3328-xhci" },
> -	{ }
> -};
> -
> -U_BOOT_DRIVER(usb_xhci) = {
> -	.name	= "xhci_rockchip",
> -	.id	= UCLASS_USB,
> -	.of_match = xhci_usb_ids,
> -	.ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
> -	.probe = xhci_usb_probe,
> -	.remove = xhci_usb_remove,
> -	.ops	= &xhci_usb_ops,
> -	.bind	= dm_scan_fdt_dev,
> -	.platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata),
> -	.priv_auto_alloc_size = sizeof(struct rockchip_xhci),
> -	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
> -};
> -
> -static const struct udevice_id usb_phy_ids[] = {
> -	{ .compatible = "rockchip,rk3328-usb3-phy" },
> -	{ }
> -};
> -
> -U_BOOT_DRIVER(usb_phy) = {
> -	.name = "usb_phy_rockchip",
> -	.of_match = usb_phy_ids,
> -};

[PATCH v5 13/16] driver: usb: drop legacy rockchip xhci driver

[Kever Yang]

On 2020/5/13 ??3:17, Frank Wang wrote:
> We have changed to use dwc3 generic driver for usb3.0 host, so the
> legacy Rockchip's xHCI driver is not needed, and drop it.
>
> Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/usb/host/Kconfig         |   9 --
>   drivers/usb/host/Makefile        |   1 -
>   drivers/usb/host/xhci-rockchip.c | 196 -------------------------------
>   3 files changed, 206 deletions(-)
>   delete mode 100644 drivers/usb/host/xhci-rockchip.c
>
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index 2f381dc958..088931a6b9 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -53,15 +53,6 @@ config USB_XHCI_PCI
>   	help
>   	  Enables support for the PCI-based xHCI controller.
>   
> -config USB_XHCI_ROCKCHIP
> -	bool "Support for Rockchip on-chip xHCI USB controller"
> -	depends on ARCH_ROCKCHIP
> -	depends on DM_REGULATOR
> -	depends on DM_USB
> -	default y
> -	help
> -	  Enables support for the on-chip xHCI controller on Rockchip SoCs.
> -
>   config USB_XHCI_RCAR
>   	bool "Renesas RCar USB 3.0 support"
>   	default y
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index e8e3b17e42..29d4f87e38 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -48,7 +48,6 @@ obj-$(CONFIG_USB_XHCI_BRCM) += xhci-brcm.o
>   obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
>   obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
>   obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o
> -obj-$(CONFIG_USB_XHCI_ROCKCHIP) += xhci-rockchip.o
>   obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
>   obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
>   obj-$(CONFIG_USB_XHCI_MTK) += xhci-mtk.o
> diff --git a/drivers/usb/host/xhci-rockchip.c b/drivers/usb/host/xhci-rockchip.c
> deleted file mode 100644
> index b67722fe45..0000000000
> --- a/drivers/usb/host/xhci-rockchip.c
> +++ /dev/null
> @@ -1,196 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright (c) 2016 Rockchip, Inc.
> - * Authors: Daniel Meng <daniel.meng@rock-chips.com>
> - */
> -#include <common.h>
> -#include <dm.h>
> -#include <malloc.h>
> -#include <usb.h>
> -#include <watchdog.h>
> -#include <linux/errno.h>
> -#include <linux/compat.h>
> -#include <linux/usb/dwc3.h>
> -#include <power/regulator.h>
> -
> -#include <usb/xhci.h>
> -
> -struct rockchip_xhci_platdata {
> -	fdt_addr_t hcd_base;
> -	struct udevice *vbus_supply;
> -};
> -
> -/*
> - * Contains pointers to register base addresses
> - * for the usb controller.
> - */
> -struct rockchip_xhci {
> -	struct usb_platdata usb_plat;
> -	struct xhci_ctrl ctrl;
> -	struct xhci_hccr *hcd;
> -	struct dwc3 *dwc3_reg;
> -};
> -
> -static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
> -{
> -	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
> -	int ret = 0;
> -
> -	/*
> -	 * Get the base address for XHCI controller from the device node
> -	 */
> -	plat->hcd_base = dev_read_addr(dev);
> -	if (plat->hcd_base == FDT_ADDR_T_NONE) {
> -		pr_err("Can't get the XHCI register base address\n");
> -		return -ENXIO;
> -	}
> -
> -	/* Vbus regulator */
> -	ret = device_get_supply_regulator(dev, "vbus-supply",
> -					  &plat->vbus_supply);
> -	if (ret)
> -		debug("Can't get VBus regulator!\n");
> -
> -	return 0;
> -}
> -
> -/*
> - * rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core
> - * @dwc: Pointer to our controller context structure
> - * @dev: Pointer to ulcass device
> - */
> -static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg,
> -				    struct udevice *dev)
> -{
> -	u32 reg;
> -	u32 utmi_bits;
> -
> -	/* Set dwc3 usb2 phy config */
> -	reg = readl(&dwc3_reg->g_usb2phycfg[0]);
> -
> -	if (dev_read_bool(dev, "snps,dis-enblslpm-quirk"))
> -		reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
> -
> -	utmi_bits = dev_read_u32_default(dev, "snps,phyif-utmi-bits", -1);
> -	if (utmi_bits == 16) {
> -		reg |= DWC3_GUSB2PHYCFG_PHYIF;
> -		reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
> -		reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
> -	} else if (utmi_bits == 8) {
> -		reg &= ~DWC3_GUSB2PHYCFG_PHYIF;
> -		reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
> -		reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
> -	}
> -
> -	if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
> -		reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
> -
> -	if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk"))
> -		reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
> -
> -	writel(reg, &dwc3_reg->g_usb2phycfg[0]);
> -}
> -
> -static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci,
> -				   struct udevice *dev)
> -{
> -	int ret;
> -
> -	ret = dwc3_core_init(rkxhci->dwc3_reg);
> -	if (ret) {
> -		pr_err("failed to initialize core\n");
> -		return ret;
> -	}
> -
> -	rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev);
> -
> -	/* We are hard-coding DWC3 core to Host Mode */
> -	dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
> -
> -	return 0;
> -}
> -
> -static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci)
> -{
> -	return 0;
> -}
> -
> -static int xhci_usb_probe(struct udevice *dev)
> -{
> -	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
> -	struct rockchip_xhci *ctx = dev_get_priv(dev);
> -	struct xhci_hcor *hcor;
> -	int ret;
> -
> -	ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
> -	ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
> -	hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd +
> -			HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));
> -
> -	if (plat->vbus_supply) {
> -		ret = regulator_set_enable(plat->vbus_supply, true);
> -		if (ret) {
> -			pr_err("XHCI: failed to set VBus supply\n");
> -			return ret;
> -		}
> -	}
> -
> -	ret = rockchip_xhci_core_init(ctx, dev);
> -	if (ret) {
> -		pr_err("XHCI: failed to initialize controller\n");
> -		return ret;
> -	}
> -
> -	return xhci_register(dev, ctx->hcd, hcor);
> -}
> -
> -static int xhci_usb_remove(struct udevice *dev)
> -{
> -	struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
> -	struct rockchip_xhci *ctx = dev_get_priv(dev);
> -	int ret;
> -
> -	ret = xhci_deregister(dev);
> -	if (ret)
> -		return ret;
> -	ret = rockchip_xhci_core_exit(ctx);
> -	if (ret)
> -		return ret;
> -
> -	if (plat->vbus_supply) {
> -		ret = regulator_set_enable(plat->vbus_supply, false);
> -		if (ret)
> -			pr_err("XHCI: failed to set VBus supply\n");
> -	}
> -
> -	return ret;
> -}
> -
> -static const struct udevice_id xhci_usb_ids[] = {
> -	{ .compatible = "rockchip,rk3328-xhci" },
> -	{ }
> -};
> -
> -U_BOOT_DRIVER(usb_xhci) = {
> -	.name	= "xhci_rockchip",
> -	.id	= UCLASS_USB,
> -	.of_match = xhci_usb_ids,
> -	.ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
> -	.probe = xhci_usb_probe,
> -	.remove = xhci_usb_remove,
> -	.ops	= &xhci_usb_ops,
> -	.bind	= dm_scan_fdt_dev,
> -	.platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata),
> -	.priv_auto_alloc_size = sizeof(struct rockchip_xhci),
> -	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
> -};
> -
> -static const struct udevice_id usb_phy_ids[] = {
> -	{ .compatible = "rockchip,rk3328-usb3-phy" },
> -	{ }
> -};
> -
> -U_BOOT_DRIVER(usb_phy) = {
> -	.name = "usb_phy_rockchip",
> -	.of_match = usb_phy_ids,
> -};

[PATCH v5 14/16] ARM: dts: rk3399-evb: usb3.0 host support

[Frank Wang]

Configure 'tcphy1' and 'usbdrd_dwc3_1' nodes to support USB3.0 host
for Rockchip RK3399 Evaluation Board.

Signed-off-by: Frank Wang <frank.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Reviewed-by: Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 arch/arm/dts/rk3399-evb-u-boot.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi
index e5659d7999..1bebe258f0 100644
--- a/arch/arm/dts/rk3399-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi
@@ -23,3 +23,16 @@
 &rk808 {
 	u-boot,dm-pre-reloc;
 };
+
+&tcphy1 {
+	status = "okay";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
-- 
2.17.1

[PATCH v5 14/16] ARM: dts: rk3399-evb: usb3.0 host support

[Frank Wang]

Configure 'tcphy1' and 'usbdrd_dwc3_1' nodes to support USB3.0 host
for Rockchip RK3399 Evaluation Board.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
---
 arch/arm/dts/rk3399-evb-u-boot.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi
index e5659d7999..1bebe258f0 100644
--- a/arch/arm/dts/rk3399-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi
@@ -23,3 +23,16 @@
 &rk808 {
 	u-boot,dm-pre-reloc;
 };
+
+&tcphy1 {
+	status = "okay";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
-- 
2.17.1

Re: [PATCH v5 14/16] ARM: dts: rk3399-evb: usb3.0 host support【请注意，邮件由linux-rockchip-bounces+kever.yang=rock-chips.com@lists.infradead.org代发】

[Kever Yang]

On 2020/5/13 下午3:17, Frank Wang wrote:
> Configure 'tcphy1' and 'usbdrd_dwc3_1' nodes to support USB3.0 host
> for Rockchip RK3399 Evaluation Board.
>
> Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   arch/arm/dts/rk3399-evb-u-boot.dtsi | 13 +++++++++++++
>   1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi
> index e5659d7999..1bebe258f0 100644
> --- a/arch/arm/dts/rk3399-evb-u-boot.dtsi
> +++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi
> @@ -23,3 +23,16 @@
>   &rk808 {
>   	u-boot,dm-pre-reloc;
>   };
> +
> +&tcphy1 {
> +	status = "okay";
> +};
> +
> +&usbdrd3_1 {
> +	status = "okay";
> +};
> +
> +&usbdrd_dwc3_1 {
> +	dr_mode = "host";
> +	status = "okay";
> +};



_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
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Re: [PATCH v5 14/16] ARM: dts: rk3399-evb: usb3.0 host support【请注意，邮件由linux-rockchip-bounces+kever.yang=rock-chips.com@lists.infradead.org代发】

[Kever Yang]

On 2020/5/13 ??3:17, Frank Wang wrote:
> Configure 'tcphy1' and 'usbdrd_dwc3_1' nodes to support USB3.0 host
> for Rockchip RK3399 Evaluation Board.
>
> Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   arch/arm/dts/rk3399-evb-u-boot.dtsi | 13 +++++++++++++
>   1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi
> index e5659d7999..1bebe258f0 100644
> --- a/arch/arm/dts/rk3399-evb-u-boot.dtsi
> +++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi
> @@ -23,3 +23,16 @@
>   &rk808 {
>   	u-boot,dm-pre-reloc;
>   };
> +
> +&tcphy1 {
> +	status = "okay";
> +};
> +
> +&usbdrd3_1 {
> +	status = "okay";
> +};
> +
> +&usbdrd_dwc3_1 {
> +	dr_mode = "host";
> +	status = "okay";
> +};

Re: [PATCH v5 10/16] usb: dwc3: Enable AutoRetry feature in the controller

[Kever Yang]

On 2020/5/13 下午3:17, Frank Wang wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> By default when core sees any transaction error (CRC or overflow) it
> replies with terminating retry ACK (Retry=1 and Nump == 0).
>
> Enabling this Auto Retry feature in controller will make the core send
> a non-terminanting ACK upon such transaction errors. That is, ACK TP
> with Retry=1 and Nump != 0.
>
> Doing so will give controller a chance to recover from transient error
> conditions.
>
> Reference from below Linux commit,
>
> commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature
> in the controller")
>
> Cc: Marek Vasut <marex@denx.de>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/usb/dwc3/core.c | 9 +++++++++
>   drivers/usb/dwc3/core.h | 3 +++
>   2 files changed, 12 insertions(+)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index dc92f471c1..aab6c34c2d 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -995,6 +995,15 @@ int dwc3_init(struct dwc3 *dwc)
>   		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
>   	}
>   
> +	if (dwc->dr_mode == USB_DR_MODE_HOST ||
> +	    dwc->dr_mode == USB_DR_MODE_OTG) {
> +		reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
> +
> +		reg |= DWC3_GUCTL_HSTINAUTORETRY;
> +
> +		dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
> +	}
> +
>   	ret = dwc3_core_init_mode(dwc);
>   	if (ret)
>   		goto mode_fail;
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index b510d8a983..2adcaf0029 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -160,6 +160,9 @@
>   #define DWC3_GCTL_GBLHIBERNATIONEN	(1 << 1)
>   #define DWC3_GCTL_DSBLCLKGTNG		(1 << 0)
>   
> +/* Global User Control Register */
> +#define DWC3_GUCTL_HSTINAUTORETRY	BIT(14)
> +
>   /* Global User Control 1 Register */
>   #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
>   #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW	BIT(24)



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[PATCH v5 10/16] usb: dwc3: Enable AutoRetry feature in the controller

[Kever Yang]

On 2020/5/13 ??3:17, Frank Wang wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> By default when core sees any transaction error (CRC or overflow) it
> replies with terminating retry ACK (Retry=1 and Nump == 0).
>
> Enabling this Auto Retry feature in controller will make the core send
> a non-terminanting ACK upon such transaction errors. That is, ACK TP
> with Retry=1 and Nump != 0.
>
> Doing so will give controller a chance to recover from transient error
> conditions.
>
> Reference from below Linux commit,
>
> commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature
> in the controller")
>
> Cc: Marek Vasut <marex@denx.de>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/usb/dwc3/core.c | 9 +++++++++
>   drivers/usb/dwc3/core.h | 3 +++
>   2 files changed, 12 insertions(+)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index dc92f471c1..aab6c34c2d 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -995,6 +995,15 @@ int dwc3_init(struct dwc3 *dwc)
>   		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
>   	}
>   
> +	if (dwc->dr_mode == USB_DR_MODE_HOST ||
> +	    dwc->dr_mode == USB_DR_MODE_OTG) {
> +		reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
> +
> +		reg |= DWC3_GUCTL_HSTINAUTORETRY;
> +
> +		dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
> +	}
> +
>   	ret = dwc3_core_init_mode(dwc);
>   	if (ret)
>   		goto mode_fail;
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index b510d8a983..2adcaf0029 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -160,6 +160,9 @@
>   #define DWC3_GCTL_GBLHIBERNATIONEN	(1 << 1)
>   #define DWC3_GCTL_DSBLCLKGTNG		(1 << 0)
>   
> +/* Global User Control Register */
> +#define DWC3_GUCTL_HSTINAUTORETRY	BIT(14)
> +
>   /* Global User Control 1 Register */
>   #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
>   #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW	BIT(24)

[PATCH v5 00/16] Add Rockchip RK3399 USB3.0 Host support

[Marcin Juszkiewicz]

W dniu 13.05.2020 o 09:13, frank.wang at rock-chips.com (Frank Wang) pisze:
> This series add quirks for DWC3 and add Rockchip RK3399 USB3.0 host support.
> 
> The function has been tested pass on rk3399-evb and roc-rk3399-pc board.
> 
> For V5 update:
>  - Fix dwc3-generic driver followed Marek's comments for [PATCH v4 12/16].
>  - Add 'Reviewed-by' and 'Tested-by' tag for [PATCH v4 07/16] and [PATCH v4 08/16].

I imported patchset and started it on RockPro64. Enabled same config
options as on evb-rk3399. DeviceTree entries were already setup.

Pendrive in USB3 (type A) port gets recognized as SuperSpeed one (was
HighSpeed before). Type C port is not working - nevermind is it empty,
with usb-c pendrive plugged or with usb-c to usb-a/c/hdmi dongle with
usb-a pendrive.

=> usb start 
starting USB...
Bus usb at fe380000: USB EHCI 1.00
Bus usb at fe3c0000: USB EHCI 1.00
Bus dwc3: usb maximum-speed not found
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
scanning bus usb at fe380000 for devices... 1 USB Device(s) found
scanning bus usb at fe3c0000 for devices... 1 USB Device(s) found
scanning bus dwc3 for devices... cannot reset port 1!?
2 USB Device(s) found
       scanning usb for storage devices... 1 Storage Device(s) found

=> usb tree
USB device tree:
  1  Hub (480 Mb/s, 0mA)
     u-boot EHCI Host Controller 
   
  1  Hub (480 Mb/s, 0mA)
     u-boot EHCI Host Controller 
   
  1  Hub (5 Gb/s, 0mA)
  |  U-Boot XHCI Host Controller 
  |
  +-2  Mass Storage (5 Gb/s, 76mA)
       ADATA ADATA USB Flash Drive 1520405012240002

[PATCH v5 00/16] Add Rockchip RK3399 USB3.0 Host support

[Jagan Teki]

On Mon, May 25, 2020 at 2:36 PM Marcin Juszkiewicz
<marcin@juszkiewicz.com.pl> wrote:
>
> W dniu 13.05.2020 o 09:13, frank.wang at rock-chips.com (Frank Wang) pisze:
> > This series add quirks for DWC3 and add Rockchip RK3399 USB3.0 host support.
> >
> > The function has been tested pass on rk3399-evb and roc-rk3399-pc board.
> >
> > For V5 update:
> >  - Fix dwc3-generic driver followed Marek's comments for [PATCH v4 12/16].
> >  - Add 'Reviewed-by' and 'Tested-by' tag for [PATCH v4 07/16] and [PATCH v4 08/16].
>
> I imported patchset and started it on RockPro64. Enabled same config
> options as on evb-rk3399. DeviceTree entries were already setup.
>
> Pendrive in USB3 (type A) port gets recognized as SuperSpeed one (was
> HighSpeed before). Type C port is not working - nevermind is it empty,
> with usb-c pendrive plugged or with usb-c to usb-a/c/hdmi dongle with
> usb-a pendrive.

Does that mean usb-c pendrive is also detected?

Jagan.

[PATCH v5 00/16] Add Rockchip RK3399 USB3.0 Host support

[Marcin Juszkiewicz]

W dniu 25.05.2020 o?11:24, Jagan Teki pisze:
> On Mon, May 25, 2020 at 2:36 PM Marcin Juszkiewicz
> <marcin@juszkiewicz.com.pl> wrote:
>>
>> W dniu 13.05.2020 o 09:13, frank.wang at rock-chips.com (Frank Wang) pisze:
>>> This series add quirks for DWC3 and add Rockchip RK3399 USB3.0 host support.
>>>
>>> The function has been tested pass on rk3399-evb and roc-rk3399-pc board.
>>>
>>> For V5 update:
>>>  - Fix dwc3-generic driver followed Marek's comments for [PATCH v4 12/16].
>>>  - Add 'Reviewed-by' and 'Tested-by' tag for [PATCH v4 07/16] and [PATCH v4 08/16].
>>
>> I imported patchset and started it on RockPro64. Enabled same config
>> options as on evb-rk3399. DeviceTree entries were already setup.
>>
>> Pendrive in USB3 (type A) port gets recognized as SuperSpeed one (was
>> HighSpeed before). Type C port is not working - nevermind is it empty,
>> with usb-c pendrive plugged or with usb-c to usb-a/c/hdmi dongle with
>> usb-a pendrive.
> 
> Does that mean usb-c pendrive is also detected?

No - "scanning bus dwc3 for devices... cannot reset port 1!?" every time
and devices plugged into usb-c are ignored.

[PATCH v5 00/16] Add Rockchip RK3399 USB3.0 Host support

[Jagan Teki]

On Mon, May 25, 2020 at 2:57 PM Marcin Juszkiewicz
<marcin@juszkiewicz.com.pl> wrote:
>
> W dniu 25.05.2020 o 11:24, Jagan Teki pisze:
> > On Mon, May 25, 2020 at 2:36 PM Marcin Juszkiewicz
> > <marcin@juszkiewicz.com.pl> wrote:
> >>
> >> W dniu 13.05.2020 o 09:13, frank.wang at rock-chips.com (Frank Wang) pisze:
> >>> This series add quirks for DWC3 and add Rockchip RK3399 USB3.0 host support.
> >>>
> >>> The function has been tested pass on rk3399-evb and roc-rk3399-pc board.
> >>>
> >>> For V5 update:
> >>>  - Fix dwc3-generic driver followed Marek's comments for [PATCH v4 12/16].
> >>>  - Add 'Reviewed-by' and 'Tested-by' tag for [PATCH v4 07/16] and [PATCH v4 08/16].
> >>
> >> I imported patchset and started it on RockPro64. Enabled same config
> >> options as on evb-rk3399. DeviceTree entries were already setup.
> >>
> >> Pendrive in USB3 (type A) port gets recognized as SuperSpeed one (was
> >> HighSpeed before). Type C port is not working - nevermind is it empty,
> >> with usb-c pendrive plugged or with usb-c to usb-a/c/hdmi dongle with
> >> usb-a pendrive.
> >
> > Does that mean usb-c pendrive is also detected?
>
> No - "scanning bus dwc3 for devices... cannot reset port 1!?" every time
> and devices plugged into usb-c are ignored.

Can you check 'usb reset' after 'usb start'

[PATCH v5 00/16] Add Rockchip RK3399 USB3.0 Host support

[Marcin Juszkiewicz]

W dniu 25.05.2020 o?11:32, Jagan Teki pisze:
> On Mon, May 25, 2020 at 2:57 PM Marcin Juszkiewicz

>> No - "scanning bus dwc3 for devices... cannot reset port 1!?" every time
>> and devices plugged into usb-c are ignored.
> 
> Can you check 'usb reset' after 'usb start'

Same situation after each 'usb reset' command.
 

[PATCH v5 00/16] Add Rockchip RK3399 USB3.0 Host support

[Jagan Teki]

On Mon, May 25, 2020 at 3:06 PM Marcin Juszkiewicz
<marcin@juszkiewicz.com.pl> wrote:
>
> W dniu 25.05.2020 o 11:32, Jagan Teki pisze:
> > On Mon, May 25, 2020 at 2:57 PM Marcin Juszkiewicz
>
> >> No - "scanning bus dwc3 for devices... cannot reset port 1!?" every time
> >> and devices plugged into usb-c are ignored.
> >
> > Can you check 'usb reset' after 'usb start'
>
> Same situation after each 'usb reset' command.

Can you check v6, I have marked you CC. I've a Sandisk Type C disk
which got worked with rock-rk3399-pc.

Jagan.